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TARGET_K82F/core_cmFunc.h@140:97feb9bacc10, 2017-04-12 (annotated)
- Committer:
- <>
- Date:
- Wed Apr 12 16:07:08 2017 +0100
- Revision:
- 140:97feb9bacc10
- Parent:
- 129:0ab6a29f35bf
Release 140 of the mbed library
Ports for Upcoming Targets
3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841
3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992
Fixes and Changes
3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951
4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021
3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979
3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990
4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003
4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012
4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020
4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065
4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014
4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030
4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109
3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 129:0ab6a29f35bf | 1 | /**************************************************************************//** |
<> | 129:0ab6a29f35bf | 2 | * @file core_cmFunc.h |
<> | 129:0ab6a29f35bf | 3 | * @brief CMSIS Cortex-M Core Function Access Header File |
<> | 129:0ab6a29f35bf | 4 | * @version V4.10 |
<> | 129:0ab6a29f35bf | 5 | * @date 18. March 2015 |
<> | 129:0ab6a29f35bf | 6 | * |
<> | 129:0ab6a29f35bf | 7 | * @note |
<> | 129:0ab6a29f35bf | 8 | * |
<> | 129:0ab6a29f35bf | 9 | ******************************************************************************/ |
<> | 129:0ab6a29f35bf | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
<> | 129:0ab6a29f35bf | 11 | |
<> | 129:0ab6a29f35bf | 12 | All rights reserved. |
<> | 129:0ab6a29f35bf | 13 | Redistribution and use in source and binary forms, with or without |
<> | 129:0ab6a29f35bf | 14 | modification, are permitted provided that the following conditions are met: |
<> | 129:0ab6a29f35bf | 15 | - Redistributions of source code must retain the above copyright |
<> | 129:0ab6a29f35bf | 16 | notice, this list of conditions and the following disclaimer. |
<> | 129:0ab6a29f35bf | 17 | - Redistributions in binary form must reproduce the above copyright |
<> | 129:0ab6a29f35bf | 18 | notice, this list of conditions and the following disclaimer in the |
<> | 129:0ab6a29f35bf | 19 | documentation and/or other materials provided with the distribution. |
<> | 129:0ab6a29f35bf | 20 | - Neither the name of ARM nor the names of its contributors may be used |
<> | 129:0ab6a29f35bf | 21 | to endorse or promote products derived from this software without |
<> | 129:0ab6a29f35bf | 22 | specific prior written permission. |
<> | 129:0ab6a29f35bf | 23 | * |
<> | 129:0ab6a29f35bf | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 129:0ab6a29f35bf | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 129:0ab6a29f35bf | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
<> | 129:0ab6a29f35bf | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
<> | 129:0ab6a29f35bf | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
<> | 129:0ab6a29f35bf | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
<> | 129:0ab6a29f35bf | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
<> | 129:0ab6a29f35bf | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
<> | 129:0ab6a29f35bf | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
<> | 129:0ab6a29f35bf | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
<> | 129:0ab6a29f35bf | 34 | POSSIBILITY OF SUCH DAMAGE. |
<> | 129:0ab6a29f35bf | 35 | ---------------------------------------------------------------------------*/ |
<> | 129:0ab6a29f35bf | 36 | |
<> | 129:0ab6a29f35bf | 37 | |
<> | 129:0ab6a29f35bf | 38 | #ifndef __CORE_CMFUNC_H |
<> | 129:0ab6a29f35bf | 39 | #define __CORE_CMFUNC_H |
<> | 129:0ab6a29f35bf | 40 | |
<> | 129:0ab6a29f35bf | 41 | |
<> | 129:0ab6a29f35bf | 42 | /* ########################### Core Function Access ########################### */ |
<> | 129:0ab6a29f35bf | 43 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 129:0ab6a29f35bf | 44 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
<> | 129:0ab6a29f35bf | 45 | @{ |
<> | 129:0ab6a29f35bf | 46 | */ |
<> | 129:0ab6a29f35bf | 47 | |
<> | 129:0ab6a29f35bf | 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
<> | 129:0ab6a29f35bf | 49 | /* ARM armcc specific functions */ |
<> | 129:0ab6a29f35bf | 50 | |
<> | 129:0ab6a29f35bf | 51 | #if (__ARMCC_VERSION < 400677) |
<> | 129:0ab6a29f35bf | 52 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
<> | 129:0ab6a29f35bf | 53 | #endif |
<> | 129:0ab6a29f35bf | 54 | |
<> | 129:0ab6a29f35bf | 55 | /* intrinsic void __enable_irq(); */ |
<> | 129:0ab6a29f35bf | 56 | /* intrinsic void __disable_irq(); */ |
<> | 129:0ab6a29f35bf | 57 | |
<> | 129:0ab6a29f35bf | 58 | /** \brief Get Control Register |
<> | 129:0ab6a29f35bf | 59 | |
<> | 129:0ab6a29f35bf | 60 | This function returns the content of the Control Register. |
<> | 129:0ab6a29f35bf | 61 | |
<> | 129:0ab6a29f35bf | 62 | \return Control Register value |
<> | 129:0ab6a29f35bf | 63 | */ |
<> | 129:0ab6a29f35bf | 64 | __STATIC_INLINE uint32_t __get_CONTROL(void) |
<> | 129:0ab6a29f35bf | 65 | { |
<> | 129:0ab6a29f35bf | 66 | register uint32_t __regControl __ASM("control"); |
<> | 129:0ab6a29f35bf | 67 | return(__regControl); |
<> | 129:0ab6a29f35bf | 68 | } |
<> | 129:0ab6a29f35bf | 69 | |
<> | 129:0ab6a29f35bf | 70 | |
<> | 129:0ab6a29f35bf | 71 | /** \brief Set Control Register |
<> | 129:0ab6a29f35bf | 72 | |
<> | 129:0ab6a29f35bf | 73 | This function writes the given value to the Control Register. |
<> | 129:0ab6a29f35bf | 74 | |
<> | 129:0ab6a29f35bf | 75 | \param [in] control Control Register value to set |
<> | 129:0ab6a29f35bf | 76 | */ |
<> | 129:0ab6a29f35bf | 77 | __STATIC_INLINE void __set_CONTROL(uint32_t control) |
<> | 129:0ab6a29f35bf | 78 | { |
<> | 129:0ab6a29f35bf | 79 | register uint32_t __regControl __ASM("control"); |
<> | 129:0ab6a29f35bf | 80 | __regControl = control; |
<> | 129:0ab6a29f35bf | 81 | } |
<> | 129:0ab6a29f35bf | 82 | |
<> | 129:0ab6a29f35bf | 83 | |
<> | 129:0ab6a29f35bf | 84 | /** \brief Get IPSR Register |
<> | 129:0ab6a29f35bf | 85 | |
<> | 129:0ab6a29f35bf | 86 | This function returns the content of the IPSR Register. |
<> | 129:0ab6a29f35bf | 87 | |
<> | 129:0ab6a29f35bf | 88 | \return IPSR Register value |
<> | 129:0ab6a29f35bf | 89 | */ |
<> | 129:0ab6a29f35bf | 90 | __STATIC_INLINE uint32_t __get_IPSR(void) |
<> | 129:0ab6a29f35bf | 91 | { |
<> | 129:0ab6a29f35bf | 92 | register uint32_t __regIPSR __ASM("ipsr"); |
<> | 129:0ab6a29f35bf | 93 | return(__regIPSR); |
<> | 129:0ab6a29f35bf | 94 | } |
<> | 129:0ab6a29f35bf | 95 | |
<> | 129:0ab6a29f35bf | 96 | |
<> | 129:0ab6a29f35bf | 97 | /** \brief Get APSR Register |
<> | 129:0ab6a29f35bf | 98 | |
<> | 129:0ab6a29f35bf | 99 | This function returns the content of the APSR Register. |
<> | 129:0ab6a29f35bf | 100 | |
<> | 129:0ab6a29f35bf | 101 | \return APSR Register value |
<> | 129:0ab6a29f35bf | 102 | */ |
<> | 129:0ab6a29f35bf | 103 | __STATIC_INLINE uint32_t __get_APSR(void) |
<> | 129:0ab6a29f35bf | 104 | { |
<> | 129:0ab6a29f35bf | 105 | register uint32_t __regAPSR __ASM("apsr"); |
<> | 129:0ab6a29f35bf | 106 | return(__regAPSR); |
<> | 129:0ab6a29f35bf | 107 | } |
<> | 129:0ab6a29f35bf | 108 | |
<> | 129:0ab6a29f35bf | 109 | |
<> | 129:0ab6a29f35bf | 110 | /** \brief Get xPSR Register |
<> | 129:0ab6a29f35bf | 111 | |
<> | 129:0ab6a29f35bf | 112 | This function returns the content of the xPSR Register. |
<> | 129:0ab6a29f35bf | 113 | |
<> | 129:0ab6a29f35bf | 114 | \return xPSR Register value |
<> | 129:0ab6a29f35bf | 115 | */ |
<> | 129:0ab6a29f35bf | 116 | __STATIC_INLINE uint32_t __get_xPSR(void) |
<> | 129:0ab6a29f35bf | 117 | { |
<> | 129:0ab6a29f35bf | 118 | register uint32_t __regXPSR __ASM("xpsr"); |
<> | 129:0ab6a29f35bf | 119 | return(__regXPSR); |
<> | 129:0ab6a29f35bf | 120 | } |
<> | 129:0ab6a29f35bf | 121 | |
<> | 129:0ab6a29f35bf | 122 | |
<> | 129:0ab6a29f35bf | 123 | /** \brief Get Process Stack Pointer |
<> | 129:0ab6a29f35bf | 124 | |
<> | 129:0ab6a29f35bf | 125 | This function returns the current value of the Process Stack Pointer (PSP). |
<> | 129:0ab6a29f35bf | 126 | |
<> | 129:0ab6a29f35bf | 127 | \return PSP Register value |
<> | 129:0ab6a29f35bf | 128 | */ |
<> | 129:0ab6a29f35bf | 129 | __STATIC_INLINE uint32_t __get_PSP(void) |
<> | 129:0ab6a29f35bf | 130 | { |
<> | 129:0ab6a29f35bf | 131 | register uint32_t __regProcessStackPointer __ASM("psp"); |
<> | 129:0ab6a29f35bf | 132 | return(__regProcessStackPointer); |
<> | 129:0ab6a29f35bf | 133 | } |
<> | 129:0ab6a29f35bf | 134 | |
<> | 129:0ab6a29f35bf | 135 | |
<> | 129:0ab6a29f35bf | 136 | /** \brief Set Process Stack Pointer |
<> | 129:0ab6a29f35bf | 137 | |
<> | 129:0ab6a29f35bf | 138 | This function assigns the given value to the Process Stack Pointer (PSP). |
<> | 129:0ab6a29f35bf | 139 | |
<> | 129:0ab6a29f35bf | 140 | \param [in] topOfProcStack Process Stack Pointer value to set |
<> | 129:0ab6a29f35bf | 141 | */ |
<> | 129:0ab6a29f35bf | 142 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
<> | 129:0ab6a29f35bf | 143 | { |
<> | 129:0ab6a29f35bf | 144 | register uint32_t __regProcessStackPointer __ASM("psp"); |
<> | 129:0ab6a29f35bf | 145 | __regProcessStackPointer = topOfProcStack; |
<> | 129:0ab6a29f35bf | 146 | } |
<> | 129:0ab6a29f35bf | 147 | |
<> | 129:0ab6a29f35bf | 148 | |
<> | 129:0ab6a29f35bf | 149 | /** \brief Get Main Stack Pointer |
<> | 129:0ab6a29f35bf | 150 | |
<> | 129:0ab6a29f35bf | 151 | This function returns the current value of the Main Stack Pointer (MSP). |
<> | 129:0ab6a29f35bf | 152 | |
<> | 129:0ab6a29f35bf | 153 | \return MSP Register value |
<> | 129:0ab6a29f35bf | 154 | */ |
<> | 129:0ab6a29f35bf | 155 | __STATIC_INLINE uint32_t __get_MSP(void) |
<> | 129:0ab6a29f35bf | 156 | { |
<> | 129:0ab6a29f35bf | 157 | register uint32_t __regMainStackPointer __ASM("msp"); |
<> | 129:0ab6a29f35bf | 158 | return(__regMainStackPointer); |
<> | 129:0ab6a29f35bf | 159 | } |
<> | 129:0ab6a29f35bf | 160 | |
<> | 129:0ab6a29f35bf | 161 | |
<> | 129:0ab6a29f35bf | 162 | /** \brief Set Main Stack Pointer |
<> | 129:0ab6a29f35bf | 163 | |
<> | 129:0ab6a29f35bf | 164 | This function assigns the given value to the Main Stack Pointer (MSP). |
<> | 129:0ab6a29f35bf | 165 | |
<> | 129:0ab6a29f35bf | 166 | \param [in] topOfMainStack Main Stack Pointer value to set |
<> | 129:0ab6a29f35bf | 167 | */ |
<> | 129:0ab6a29f35bf | 168 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
<> | 129:0ab6a29f35bf | 169 | { |
<> | 129:0ab6a29f35bf | 170 | register uint32_t __regMainStackPointer __ASM("msp"); |
<> | 129:0ab6a29f35bf | 171 | __regMainStackPointer = topOfMainStack; |
<> | 129:0ab6a29f35bf | 172 | } |
<> | 129:0ab6a29f35bf | 173 | |
<> | 129:0ab6a29f35bf | 174 | |
<> | 129:0ab6a29f35bf | 175 | /** \brief Get Priority Mask |
<> | 129:0ab6a29f35bf | 176 | |
<> | 129:0ab6a29f35bf | 177 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
<> | 129:0ab6a29f35bf | 178 | |
<> | 129:0ab6a29f35bf | 179 | \return Priority Mask value |
<> | 129:0ab6a29f35bf | 180 | */ |
<> | 129:0ab6a29f35bf | 181 | __STATIC_INLINE uint32_t __get_PRIMASK(void) |
<> | 129:0ab6a29f35bf | 182 | { |
<> | 129:0ab6a29f35bf | 183 | register uint32_t __regPriMask __ASM("primask"); |
<> | 129:0ab6a29f35bf | 184 | return(__regPriMask); |
<> | 129:0ab6a29f35bf | 185 | } |
<> | 129:0ab6a29f35bf | 186 | |
<> | 129:0ab6a29f35bf | 187 | |
<> | 129:0ab6a29f35bf | 188 | /** \brief Set Priority Mask |
<> | 129:0ab6a29f35bf | 189 | |
<> | 129:0ab6a29f35bf | 190 | This function assigns the given value to the Priority Mask Register. |
<> | 129:0ab6a29f35bf | 191 | |
<> | 129:0ab6a29f35bf | 192 | \param [in] priMask Priority Mask |
<> | 129:0ab6a29f35bf | 193 | */ |
<> | 129:0ab6a29f35bf | 194 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
<> | 129:0ab6a29f35bf | 195 | { |
<> | 129:0ab6a29f35bf | 196 | register uint32_t __regPriMask __ASM("primask"); |
<> | 129:0ab6a29f35bf | 197 | __regPriMask = (priMask); |
<> | 129:0ab6a29f35bf | 198 | } |
<> | 129:0ab6a29f35bf | 199 | |
<> | 129:0ab6a29f35bf | 200 | |
<> | 129:0ab6a29f35bf | 201 | #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) |
<> | 129:0ab6a29f35bf | 202 | |
<> | 129:0ab6a29f35bf | 203 | /** \brief Enable FIQ |
<> | 129:0ab6a29f35bf | 204 | |
<> | 129:0ab6a29f35bf | 205 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
<> | 129:0ab6a29f35bf | 206 | Can only be executed in Privileged modes. |
<> | 129:0ab6a29f35bf | 207 | */ |
<> | 129:0ab6a29f35bf | 208 | #define __enable_fault_irq __enable_fiq |
<> | 129:0ab6a29f35bf | 209 | |
<> | 129:0ab6a29f35bf | 210 | |
<> | 129:0ab6a29f35bf | 211 | /** \brief Disable FIQ |
<> | 129:0ab6a29f35bf | 212 | |
<> | 129:0ab6a29f35bf | 213 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
<> | 129:0ab6a29f35bf | 214 | Can only be executed in Privileged modes. |
<> | 129:0ab6a29f35bf | 215 | */ |
<> | 129:0ab6a29f35bf | 216 | #define __disable_fault_irq __disable_fiq |
<> | 129:0ab6a29f35bf | 217 | |
<> | 129:0ab6a29f35bf | 218 | |
<> | 129:0ab6a29f35bf | 219 | /** \brief Get Base Priority |
<> | 129:0ab6a29f35bf | 220 | |
<> | 129:0ab6a29f35bf | 221 | This function returns the current value of the Base Priority register. |
<> | 129:0ab6a29f35bf | 222 | |
<> | 129:0ab6a29f35bf | 223 | \return Base Priority register value |
<> | 129:0ab6a29f35bf | 224 | */ |
<> | 129:0ab6a29f35bf | 225 | __STATIC_INLINE uint32_t __get_BASEPRI(void) |
<> | 129:0ab6a29f35bf | 226 | { |
<> | 129:0ab6a29f35bf | 227 | register uint32_t __regBasePri __ASM("basepri"); |
<> | 129:0ab6a29f35bf | 228 | return(__regBasePri); |
<> | 129:0ab6a29f35bf | 229 | } |
<> | 129:0ab6a29f35bf | 230 | |
<> | 129:0ab6a29f35bf | 231 | |
<> | 129:0ab6a29f35bf | 232 | /** \brief Set Base Priority |
<> | 129:0ab6a29f35bf | 233 | |
<> | 129:0ab6a29f35bf | 234 | This function assigns the given value to the Base Priority register. |
<> | 129:0ab6a29f35bf | 235 | |
<> | 129:0ab6a29f35bf | 236 | \param [in] basePri Base Priority value to set |
<> | 129:0ab6a29f35bf | 237 | */ |
<> | 129:0ab6a29f35bf | 238 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
<> | 129:0ab6a29f35bf | 239 | { |
<> | 129:0ab6a29f35bf | 240 | register uint32_t __regBasePri __ASM("basepri"); |
<> | 129:0ab6a29f35bf | 241 | __regBasePri = (basePri & 0xff); |
<> | 129:0ab6a29f35bf | 242 | } |
<> | 129:0ab6a29f35bf | 243 | |
<> | 129:0ab6a29f35bf | 244 | |
<> | 129:0ab6a29f35bf | 245 | /** \brief Set Base Priority with condition |
<> | 129:0ab6a29f35bf | 246 | |
<> | 129:0ab6a29f35bf | 247 | This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
<> | 129:0ab6a29f35bf | 248 | or the new value increases the BASEPRI priority level. |
<> | 129:0ab6a29f35bf | 249 | |
<> | 129:0ab6a29f35bf | 250 | \param [in] basePri Base Priority value to set |
<> | 129:0ab6a29f35bf | 251 | */ |
<> | 129:0ab6a29f35bf | 252 | __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
<> | 129:0ab6a29f35bf | 253 | { |
<> | 129:0ab6a29f35bf | 254 | register uint32_t __regBasePriMax __ASM("basepri_max"); |
<> | 129:0ab6a29f35bf | 255 | __regBasePriMax = (basePri & 0xff); |
<> | 129:0ab6a29f35bf | 256 | } |
<> | 129:0ab6a29f35bf | 257 | |
<> | 129:0ab6a29f35bf | 258 | |
<> | 129:0ab6a29f35bf | 259 | /** \brief Get Fault Mask |
<> | 129:0ab6a29f35bf | 260 | |
<> | 129:0ab6a29f35bf | 261 | This function returns the current value of the Fault Mask register. |
<> | 129:0ab6a29f35bf | 262 | |
<> | 129:0ab6a29f35bf | 263 | \return Fault Mask register value |
<> | 129:0ab6a29f35bf | 264 | */ |
<> | 129:0ab6a29f35bf | 265 | __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
<> | 129:0ab6a29f35bf | 266 | { |
<> | 129:0ab6a29f35bf | 267 | register uint32_t __regFaultMask __ASM("faultmask"); |
<> | 129:0ab6a29f35bf | 268 | return(__regFaultMask); |
<> | 129:0ab6a29f35bf | 269 | } |
<> | 129:0ab6a29f35bf | 270 | |
<> | 129:0ab6a29f35bf | 271 | |
<> | 129:0ab6a29f35bf | 272 | /** \brief Set Fault Mask |
<> | 129:0ab6a29f35bf | 273 | |
<> | 129:0ab6a29f35bf | 274 | This function assigns the given value to the Fault Mask register. |
<> | 129:0ab6a29f35bf | 275 | |
<> | 129:0ab6a29f35bf | 276 | \param [in] faultMask Fault Mask value to set |
<> | 129:0ab6a29f35bf | 277 | */ |
<> | 129:0ab6a29f35bf | 278 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
<> | 129:0ab6a29f35bf | 279 | { |
<> | 129:0ab6a29f35bf | 280 | register uint32_t __regFaultMask __ASM("faultmask"); |
<> | 129:0ab6a29f35bf | 281 | __regFaultMask = (faultMask & (uint32_t)1); |
<> | 129:0ab6a29f35bf | 282 | } |
<> | 129:0ab6a29f35bf | 283 | |
<> | 129:0ab6a29f35bf | 284 | #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ |
<> | 129:0ab6a29f35bf | 285 | |
<> | 129:0ab6a29f35bf | 286 | |
<> | 129:0ab6a29f35bf | 287 | #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) |
<> | 129:0ab6a29f35bf | 288 | |
<> | 129:0ab6a29f35bf | 289 | /** \brief Get FPSCR |
<> | 129:0ab6a29f35bf | 290 | |
<> | 129:0ab6a29f35bf | 291 | This function returns the current value of the Floating Point Status/Control register. |
<> | 129:0ab6a29f35bf | 292 | |
<> | 129:0ab6a29f35bf | 293 | \return Floating Point Status/Control register value |
<> | 129:0ab6a29f35bf | 294 | */ |
<> | 129:0ab6a29f35bf | 295 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
<> | 129:0ab6a29f35bf | 296 | { |
<> | 129:0ab6a29f35bf | 297 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
<> | 129:0ab6a29f35bf | 298 | register uint32_t __regfpscr __ASM("fpscr"); |
<> | 129:0ab6a29f35bf | 299 | return(__regfpscr); |
<> | 129:0ab6a29f35bf | 300 | #else |
<> | 129:0ab6a29f35bf | 301 | return(0); |
<> | 129:0ab6a29f35bf | 302 | #endif |
<> | 129:0ab6a29f35bf | 303 | } |
<> | 129:0ab6a29f35bf | 304 | |
<> | 129:0ab6a29f35bf | 305 | |
<> | 129:0ab6a29f35bf | 306 | /** \brief Set FPSCR |
<> | 129:0ab6a29f35bf | 307 | |
<> | 129:0ab6a29f35bf | 308 | This function assigns the given value to the Floating Point Status/Control register. |
<> | 129:0ab6a29f35bf | 309 | |
<> | 129:0ab6a29f35bf | 310 | \param [in] fpscr Floating Point Status/Control value to set |
<> | 129:0ab6a29f35bf | 311 | */ |
<> | 129:0ab6a29f35bf | 312 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
<> | 129:0ab6a29f35bf | 313 | { |
<> | 129:0ab6a29f35bf | 314 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
<> | 129:0ab6a29f35bf | 315 | register uint32_t __regfpscr __ASM("fpscr"); |
<> | 129:0ab6a29f35bf | 316 | __regfpscr = (fpscr); |
<> | 129:0ab6a29f35bf | 317 | #endif |
<> | 129:0ab6a29f35bf | 318 | } |
<> | 129:0ab6a29f35bf | 319 | |
<> | 129:0ab6a29f35bf | 320 | #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ |
<> | 129:0ab6a29f35bf | 321 | |
<> | 129:0ab6a29f35bf | 322 | |
<> | 129:0ab6a29f35bf | 323 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
<> | 129:0ab6a29f35bf | 324 | /* GNU gcc specific functions */ |
<> | 129:0ab6a29f35bf | 325 | |
<> | 129:0ab6a29f35bf | 326 | /** \brief Enable IRQ Interrupts |
<> | 129:0ab6a29f35bf | 327 | |
<> | 129:0ab6a29f35bf | 328 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. |
<> | 129:0ab6a29f35bf | 329 | Can only be executed in Privileged modes. |
<> | 129:0ab6a29f35bf | 330 | */ |
<> | 129:0ab6a29f35bf | 331 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) |
<> | 129:0ab6a29f35bf | 332 | { |
<> | 129:0ab6a29f35bf | 333 | __ASM volatile ("cpsie i" : : : "memory"); |
<> | 129:0ab6a29f35bf | 334 | } |
<> | 129:0ab6a29f35bf | 335 | |
<> | 129:0ab6a29f35bf | 336 | |
<> | 129:0ab6a29f35bf | 337 | /** \brief Disable IRQ Interrupts |
<> | 129:0ab6a29f35bf | 338 | |
<> | 129:0ab6a29f35bf | 339 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
<> | 129:0ab6a29f35bf | 340 | Can only be executed in Privileged modes. |
<> | 129:0ab6a29f35bf | 341 | */ |
<> | 129:0ab6a29f35bf | 342 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) |
<> | 129:0ab6a29f35bf | 343 | { |
<> | 129:0ab6a29f35bf | 344 | __ASM volatile ("cpsid i" : : : "memory"); |
<> | 129:0ab6a29f35bf | 345 | } |
<> | 129:0ab6a29f35bf | 346 | |
<> | 129:0ab6a29f35bf | 347 | |
<> | 129:0ab6a29f35bf | 348 | /** \brief Get Control Register |
<> | 129:0ab6a29f35bf | 349 | |
<> | 129:0ab6a29f35bf | 350 | This function returns the content of the Control Register. |
<> | 129:0ab6a29f35bf | 351 | |
<> | 129:0ab6a29f35bf | 352 | \return Control Register value |
<> | 129:0ab6a29f35bf | 353 | */ |
<> | 129:0ab6a29f35bf | 354 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) |
<> | 129:0ab6a29f35bf | 355 | { |
<> | 129:0ab6a29f35bf | 356 | uint32_t result; |
<> | 129:0ab6a29f35bf | 357 | |
<> | 129:0ab6a29f35bf | 358 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 359 | return(result); |
<> | 129:0ab6a29f35bf | 360 | } |
<> | 129:0ab6a29f35bf | 361 | |
<> | 129:0ab6a29f35bf | 362 | |
<> | 129:0ab6a29f35bf | 363 | /** \brief Set Control Register |
<> | 129:0ab6a29f35bf | 364 | |
<> | 129:0ab6a29f35bf | 365 | This function writes the given value to the Control Register. |
<> | 129:0ab6a29f35bf | 366 | |
<> | 129:0ab6a29f35bf | 367 | \param [in] control Control Register value to set |
<> | 129:0ab6a29f35bf | 368 | */ |
<> | 129:0ab6a29f35bf | 369 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) |
<> | 129:0ab6a29f35bf | 370 | { |
<> | 129:0ab6a29f35bf | 371 | __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); |
<> | 129:0ab6a29f35bf | 372 | } |
<> | 129:0ab6a29f35bf | 373 | |
<> | 129:0ab6a29f35bf | 374 | |
<> | 129:0ab6a29f35bf | 375 | /** \brief Get IPSR Register |
<> | 129:0ab6a29f35bf | 376 | |
<> | 129:0ab6a29f35bf | 377 | This function returns the content of the IPSR Register. |
<> | 129:0ab6a29f35bf | 378 | |
<> | 129:0ab6a29f35bf | 379 | \return IPSR Register value |
<> | 129:0ab6a29f35bf | 380 | */ |
<> | 129:0ab6a29f35bf | 381 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) |
<> | 129:0ab6a29f35bf | 382 | { |
<> | 129:0ab6a29f35bf | 383 | uint32_t result; |
<> | 129:0ab6a29f35bf | 384 | |
<> | 129:0ab6a29f35bf | 385 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 386 | return(result); |
<> | 129:0ab6a29f35bf | 387 | } |
<> | 129:0ab6a29f35bf | 388 | |
<> | 129:0ab6a29f35bf | 389 | |
<> | 129:0ab6a29f35bf | 390 | /** \brief Get APSR Register |
<> | 129:0ab6a29f35bf | 391 | |
<> | 129:0ab6a29f35bf | 392 | This function returns the content of the APSR Register. |
<> | 129:0ab6a29f35bf | 393 | |
<> | 129:0ab6a29f35bf | 394 | \return APSR Register value |
<> | 129:0ab6a29f35bf | 395 | */ |
<> | 129:0ab6a29f35bf | 396 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) |
<> | 129:0ab6a29f35bf | 397 | { |
<> | 129:0ab6a29f35bf | 398 | uint32_t result; |
<> | 129:0ab6a29f35bf | 399 | |
<> | 129:0ab6a29f35bf | 400 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 401 | return(result); |
<> | 129:0ab6a29f35bf | 402 | } |
<> | 129:0ab6a29f35bf | 403 | |
<> | 129:0ab6a29f35bf | 404 | |
<> | 129:0ab6a29f35bf | 405 | /** \brief Get xPSR Register |
<> | 129:0ab6a29f35bf | 406 | |
<> | 129:0ab6a29f35bf | 407 | This function returns the content of the xPSR Register. |
<> | 129:0ab6a29f35bf | 408 | |
<> | 129:0ab6a29f35bf | 409 | \return xPSR Register value |
<> | 129:0ab6a29f35bf | 410 | */ |
<> | 129:0ab6a29f35bf | 411 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) |
<> | 129:0ab6a29f35bf | 412 | { |
<> | 129:0ab6a29f35bf | 413 | uint32_t result; |
<> | 129:0ab6a29f35bf | 414 | |
<> | 129:0ab6a29f35bf | 415 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 416 | return(result); |
<> | 129:0ab6a29f35bf | 417 | } |
<> | 129:0ab6a29f35bf | 418 | |
<> | 129:0ab6a29f35bf | 419 | |
<> | 129:0ab6a29f35bf | 420 | /** \brief Get Process Stack Pointer |
<> | 129:0ab6a29f35bf | 421 | |
<> | 129:0ab6a29f35bf | 422 | This function returns the current value of the Process Stack Pointer (PSP). |
<> | 129:0ab6a29f35bf | 423 | |
<> | 129:0ab6a29f35bf | 424 | \return PSP Register value |
<> | 129:0ab6a29f35bf | 425 | */ |
<> | 129:0ab6a29f35bf | 426 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) |
<> | 129:0ab6a29f35bf | 427 | { |
<> | 129:0ab6a29f35bf | 428 | register uint32_t result; |
<> | 129:0ab6a29f35bf | 429 | |
<> | 129:0ab6a29f35bf | 430 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 431 | return(result); |
<> | 129:0ab6a29f35bf | 432 | } |
<> | 129:0ab6a29f35bf | 433 | |
<> | 129:0ab6a29f35bf | 434 | |
<> | 129:0ab6a29f35bf | 435 | /** \brief Set Process Stack Pointer |
<> | 129:0ab6a29f35bf | 436 | |
<> | 129:0ab6a29f35bf | 437 | This function assigns the given value to the Process Stack Pointer (PSP). |
<> | 129:0ab6a29f35bf | 438 | |
<> | 129:0ab6a29f35bf | 439 | \param [in] topOfProcStack Process Stack Pointer value to set |
<> | 129:0ab6a29f35bf | 440 | */ |
<> | 129:0ab6a29f35bf | 441 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
<> | 129:0ab6a29f35bf | 442 | { |
<> | 129:0ab6a29f35bf | 443 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); |
<> | 129:0ab6a29f35bf | 444 | } |
<> | 129:0ab6a29f35bf | 445 | |
<> | 129:0ab6a29f35bf | 446 | |
<> | 129:0ab6a29f35bf | 447 | /** \brief Get Main Stack Pointer |
<> | 129:0ab6a29f35bf | 448 | |
<> | 129:0ab6a29f35bf | 449 | This function returns the current value of the Main Stack Pointer (MSP). |
<> | 129:0ab6a29f35bf | 450 | |
<> | 129:0ab6a29f35bf | 451 | \return MSP Register value |
<> | 129:0ab6a29f35bf | 452 | */ |
<> | 129:0ab6a29f35bf | 453 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) |
<> | 129:0ab6a29f35bf | 454 | { |
<> | 129:0ab6a29f35bf | 455 | register uint32_t result; |
<> | 129:0ab6a29f35bf | 456 | |
<> | 129:0ab6a29f35bf | 457 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 458 | return(result); |
<> | 129:0ab6a29f35bf | 459 | } |
<> | 129:0ab6a29f35bf | 460 | |
<> | 129:0ab6a29f35bf | 461 | |
<> | 129:0ab6a29f35bf | 462 | /** \brief Set Main Stack Pointer |
<> | 129:0ab6a29f35bf | 463 | |
<> | 129:0ab6a29f35bf | 464 | This function assigns the given value to the Main Stack Pointer (MSP). |
<> | 129:0ab6a29f35bf | 465 | |
<> | 129:0ab6a29f35bf | 466 | \param [in] topOfMainStack Main Stack Pointer value to set |
<> | 129:0ab6a29f35bf | 467 | */ |
<> | 129:0ab6a29f35bf | 468 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
<> | 129:0ab6a29f35bf | 469 | { |
<> | 129:0ab6a29f35bf | 470 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); |
<> | 129:0ab6a29f35bf | 471 | } |
<> | 129:0ab6a29f35bf | 472 | |
<> | 129:0ab6a29f35bf | 473 | |
<> | 129:0ab6a29f35bf | 474 | /** \brief Get Priority Mask |
<> | 129:0ab6a29f35bf | 475 | |
<> | 129:0ab6a29f35bf | 476 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
<> | 129:0ab6a29f35bf | 477 | |
<> | 129:0ab6a29f35bf | 478 | \return Priority Mask value |
<> | 129:0ab6a29f35bf | 479 | */ |
<> | 129:0ab6a29f35bf | 480 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) |
<> | 129:0ab6a29f35bf | 481 | { |
<> | 129:0ab6a29f35bf | 482 | uint32_t result; |
<> | 129:0ab6a29f35bf | 483 | |
<> | 129:0ab6a29f35bf | 484 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 485 | return(result); |
<> | 129:0ab6a29f35bf | 486 | } |
<> | 129:0ab6a29f35bf | 487 | |
<> | 129:0ab6a29f35bf | 488 | |
<> | 129:0ab6a29f35bf | 489 | /** \brief Set Priority Mask |
<> | 129:0ab6a29f35bf | 490 | |
<> | 129:0ab6a29f35bf | 491 | This function assigns the given value to the Priority Mask Register. |
<> | 129:0ab6a29f35bf | 492 | |
<> | 129:0ab6a29f35bf | 493 | \param [in] priMask Priority Mask |
<> | 129:0ab6a29f35bf | 494 | */ |
<> | 129:0ab6a29f35bf | 495 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
<> | 129:0ab6a29f35bf | 496 | { |
<> | 129:0ab6a29f35bf | 497 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); |
<> | 129:0ab6a29f35bf | 498 | } |
<> | 129:0ab6a29f35bf | 499 | |
<> | 129:0ab6a29f35bf | 500 | |
<> | 129:0ab6a29f35bf | 501 | #if (__CORTEX_M >= 0x03) |
<> | 129:0ab6a29f35bf | 502 | |
<> | 129:0ab6a29f35bf | 503 | /** \brief Enable FIQ |
<> | 129:0ab6a29f35bf | 504 | |
<> | 129:0ab6a29f35bf | 505 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
<> | 129:0ab6a29f35bf | 506 | Can only be executed in Privileged modes. |
<> | 129:0ab6a29f35bf | 507 | */ |
<> | 129:0ab6a29f35bf | 508 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) |
<> | 129:0ab6a29f35bf | 509 | { |
<> | 129:0ab6a29f35bf | 510 | __ASM volatile ("cpsie f" : : : "memory"); |
<> | 129:0ab6a29f35bf | 511 | } |
<> | 129:0ab6a29f35bf | 512 | |
<> | 129:0ab6a29f35bf | 513 | |
<> | 129:0ab6a29f35bf | 514 | /** \brief Disable FIQ |
<> | 129:0ab6a29f35bf | 515 | |
<> | 129:0ab6a29f35bf | 516 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
<> | 129:0ab6a29f35bf | 517 | Can only be executed in Privileged modes. |
<> | 129:0ab6a29f35bf | 518 | */ |
<> | 129:0ab6a29f35bf | 519 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) |
<> | 129:0ab6a29f35bf | 520 | { |
<> | 129:0ab6a29f35bf | 521 | __ASM volatile ("cpsid f" : : : "memory"); |
<> | 129:0ab6a29f35bf | 522 | } |
<> | 129:0ab6a29f35bf | 523 | |
<> | 129:0ab6a29f35bf | 524 | |
<> | 129:0ab6a29f35bf | 525 | /** \brief Get Base Priority |
<> | 129:0ab6a29f35bf | 526 | |
<> | 129:0ab6a29f35bf | 527 | This function returns the current value of the Base Priority register. |
<> | 129:0ab6a29f35bf | 528 | |
<> | 129:0ab6a29f35bf | 529 | \return Base Priority register value |
<> | 129:0ab6a29f35bf | 530 | */ |
<> | 129:0ab6a29f35bf | 531 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) |
<> | 129:0ab6a29f35bf | 532 | { |
<> | 129:0ab6a29f35bf | 533 | uint32_t result; |
<> | 129:0ab6a29f35bf | 534 | |
<> | 129:0ab6a29f35bf | 535 | __ASM volatile ("MRS %0, basepri" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 536 | return(result); |
<> | 129:0ab6a29f35bf | 537 | } |
<> | 129:0ab6a29f35bf | 538 | |
<> | 129:0ab6a29f35bf | 539 | |
<> | 129:0ab6a29f35bf | 540 | /** \brief Set Base Priority |
<> | 129:0ab6a29f35bf | 541 | |
<> | 129:0ab6a29f35bf | 542 | This function assigns the given value to the Base Priority register. |
<> | 129:0ab6a29f35bf | 543 | |
<> | 129:0ab6a29f35bf | 544 | \param [in] basePri Base Priority value to set |
<> | 129:0ab6a29f35bf | 545 | */ |
<> | 129:0ab6a29f35bf | 546 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) |
<> | 129:0ab6a29f35bf | 547 | { |
<> | 129:0ab6a29f35bf | 548 | __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); |
<> | 129:0ab6a29f35bf | 549 | } |
<> | 129:0ab6a29f35bf | 550 | |
<> | 129:0ab6a29f35bf | 551 | |
<> | 129:0ab6a29f35bf | 552 | /** \brief Set Base Priority with condition |
<> | 129:0ab6a29f35bf | 553 | |
<> | 129:0ab6a29f35bf | 554 | This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
<> | 129:0ab6a29f35bf | 555 | or the new value increases the BASEPRI priority level. |
<> | 129:0ab6a29f35bf | 556 | |
<> | 129:0ab6a29f35bf | 557 | \param [in] basePri Base Priority value to set |
<> | 129:0ab6a29f35bf | 558 | */ |
<> | 129:0ab6a29f35bf | 559 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) |
<> | 129:0ab6a29f35bf | 560 | { |
<> | 129:0ab6a29f35bf | 561 | __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); |
<> | 129:0ab6a29f35bf | 562 | } |
<> | 129:0ab6a29f35bf | 563 | |
<> | 129:0ab6a29f35bf | 564 | |
<> | 129:0ab6a29f35bf | 565 | /** \brief Get Fault Mask |
<> | 129:0ab6a29f35bf | 566 | |
<> | 129:0ab6a29f35bf | 567 | This function returns the current value of the Fault Mask register. |
<> | 129:0ab6a29f35bf | 568 | |
<> | 129:0ab6a29f35bf | 569 | \return Fault Mask register value |
<> | 129:0ab6a29f35bf | 570 | */ |
<> | 129:0ab6a29f35bf | 571 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
<> | 129:0ab6a29f35bf | 572 | { |
<> | 129:0ab6a29f35bf | 573 | uint32_t result; |
<> | 129:0ab6a29f35bf | 574 | |
<> | 129:0ab6a29f35bf | 575 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 576 | return(result); |
<> | 129:0ab6a29f35bf | 577 | } |
<> | 129:0ab6a29f35bf | 578 | |
<> | 129:0ab6a29f35bf | 579 | |
<> | 129:0ab6a29f35bf | 580 | /** \brief Set Fault Mask |
<> | 129:0ab6a29f35bf | 581 | |
<> | 129:0ab6a29f35bf | 582 | This function assigns the given value to the Fault Mask register. |
<> | 129:0ab6a29f35bf | 583 | |
<> | 129:0ab6a29f35bf | 584 | \param [in] faultMask Fault Mask value to set |
<> | 129:0ab6a29f35bf | 585 | */ |
<> | 129:0ab6a29f35bf | 586 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
<> | 129:0ab6a29f35bf | 587 | { |
<> | 129:0ab6a29f35bf | 588 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); |
<> | 129:0ab6a29f35bf | 589 | } |
<> | 129:0ab6a29f35bf | 590 | |
<> | 129:0ab6a29f35bf | 591 | #endif /* (__CORTEX_M >= 0x03) */ |
<> | 129:0ab6a29f35bf | 592 | |
<> | 129:0ab6a29f35bf | 593 | |
<> | 129:0ab6a29f35bf | 594 | #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) |
<> | 129:0ab6a29f35bf | 595 | |
<> | 129:0ab6a29f35bf | 596 | /** \brief Get FPSCR |
<> | 129:0ab6a29f35bf | 597 | |
<> | 129:0ab6a29f35bf | 598 | This function returns the current value of the Floating Point Status/Control register. |
<> | 129:0ab6a29f35bf | 599 | |
<> | 129:0ab6a29f35bf | 600 | \return Floating Point Status/Control register value |
<> | 129:0ab6a29f35bf | 601 | */ |
<> | 129:0ab6a29f35bf | 602 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) |
<> | 129:0ab6a29f35bf | 603 | { |
<> | 129:0ab6a29f35bf | 604 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
<> | 129:0ab6a29f35bf | 605 | uint32_t result; |
<> | 129:0ab6a29f35bf | 606 | |
<> | 129:0ab6a29f35bf | 607 | /* Empty asm statement works as a scheduling barrier */ |
<> | 129:0ab6a29f35bf | 608 | __ASM volatile (""); |
<> | 129:0ab6a29f35bf | 609 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
<> | 129:0ab6a29f35bf | 610 | __ASM volatile (""); |
<> | 129:0ab6a29f35bf | 611 | return(result); |
<> | 129:0ab6a29f35bf | 612 | #else |
<> | 129:0ab6a29f35bf | 613 | return(0); |
<> | 129:0ab6a29f35bf | 614 | #endif |
<> | 129:0ab6a29f35bf | 615 | } |
<> | 129:0ab6a29f35bf | 616 | |
<> | 129:0ab6a29f35bf | 617 | |
<> | 129:0ab6a29f35bf | 618 | /** \brief Set FPSCR |
<> | 129:0ab6a29f35bf | 619 | |
<> | 129:0ab6a29f35bf | 620 | This function assigns the given value to the Floating Point Status/Control register. |
<> | 129:0ab6a29f35bf | 621 | |
<> | 129:0ab6a29f35bf | 622 | \param [in] fpscr Floating Point Status/Control value to set |
<> | 129:0ab6a29f35bf | 623 | */ |
<> | 129:0ab6a29f35bf | 624 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
<> | 129:0ab6a29f35bf | 625 | { |
<> | 129:0ab6a29f35bf | 626 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
<> | 129:0ab6a29f35bf | 627 | /* Empty asm statement works as a scheduling barrier */ |
<> | 129:0ab6a29f35bf | 628 | __ASM volatile (""); |
<> | 129:0ab6a29f35bf | 629 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); |
<> | 129:0ab6a29f35bf | 630 | __ASM volatile (""); |
<> | 129:0ab6a29f35bf | 631 | #endif |
<> | 129:0ab6a29f35bf | 632 | } |
<> | 129:0ab6a29f35bf | 633 | |
<> | 129:0ab6a29f35bf | 634 | #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ |
<> | 129:0ab6a29f35bf | 635 | |
<> | 129:0ab6a29f35bf | 636 | |
<> | 129:0ab6a29f35bf | 637 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
<> | 129:0ab6a29f35bf | 638 | /* IAR iccarm specific functions */ |
<> | 129:0ab6a29f35bf | 639 | #include <cmsis_iar.h> |
<> | 129:0ab6a29f35bf | 640 | |
<> | 129:0ab6a29f35bf | 641 | |
<> | 129:0ab6a29f35bf | 642 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ |
<> | 129:0ab6a29f35bf | 643 | /* TI CCS specific functions */ |
<> | 129:0ab6a29f35bf | 644 | #include <cmsis_ccs.h> |
<> | 129:0ab6a29f35bf | 645 | |
<> | 129:0ab6a29f35bf | 646 | |
<> | 129:0ab6a29f35bf | 647 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
<> | 129:0ab6a29f35bf | 648 | /* TASKING carm specific functions */ |
<> | 129:0ab6a29f35bf | 649 | /* |
<> | 129:0ab6a29f35bf | 650 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
<> | 129:0ab6a29f35bf | 651 | * Please use "carm -?i" to get an up to date list of all intrinsics, |
<> | 129:0ab6a29f35bf | 652 | * Including the CMSIS ones. |
<> | 129:0ab6a29f35bf | 653 | */ |
<> | 129:0ab6a29f35bf | 654 | |
<> | 129:0ab6a29f35bf | 655 | |
<> | 129:0ab6a29f35bf | 656 | #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ |
<> | 129:0ab6a29f35bf | 657 | /* Cosmic specific functions */ |
<> | 129:0ab6a29f35bf | 658 | #include <cmsis_csm.h> |
<> | 129:0ab6a29f35bf | 659 | |
<> | 129:0ab6a29f35bf | 660 | #endif |
<> | 129:0ab6a29f35bf | 661 | |
<> | 129:0ab6a29f35bf | 662 | /*@} end of CMSIS_Core_RegAccFunctions */ |
<> | 129:0ab6a29f35bf | 663 | |
<> | 129:0ab6a29f35bf | 664 | #endif /* __CORE_CMFUNC_H */ |