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TARGET_NUCLEO_F031K6/core_cm0plus.h@109:9296ab0bfc11, 2015-10-29 (annotated)

Committer:
Kojto
Date:
Thu Oct 29 08:40:18 2015 +0000
Revision:
109:9296ab0bfc11
Child:
110:165afa46840b
Release 109  of the mbed library



Changes:

- new platforms - NUCLEO_F042K6, WIZNWIKI_W7500ECO

- MTS targets - bootloaders update to 0.1.1

- STM F7 - RTC enable fixes

- STM F4 - i2c pending stop before start fix

- STM all targets - analogout normalization fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**************************************************************************//**
Kojto 109:9296ab0bfc11 2 * @file core_cm0plus.h
Kojto 109:9296ab0bfc11 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 109:9296ab0bfc11 4 * @version V3.20
Kojto 109:9296ab0bfc11 5 * @date 25. February 2013
Kojto 109:9296ab0bfc11 6 *
Kojto 109:9296ab0bfc11 7 * @note
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 ******************************************************************************/
Kojto 109:9296ab0bfc11 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 109:9296ab0bfc11 11
Kojto 109:9296ab0bfc11 12 All rights reserved.
Kojto 109:9296ab0bfc11 13 Redistribution and use in source and binary forms, with or without
Kojto 109:9296ab0bfc11 14 modification, are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 - Redistributions of source code must retain the above copyright
Kojto 109:9296ab0bfc11 16 notice, this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 - Redistributions in binary form must reproduce the above copyright
Kojto 109:9296ab0bfc11 18 notice, this list of conditions and the following disclaimer in the
Kojto 109:9296ab0bfc11 19 documentation and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 109:9296ab0bfc11 21 to endorse or promote products derived from this software without
Kojto 109:9296ab0bfc11 22 specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 109:9296ab0bfc11 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 109:9296ab0bfc11 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 109:9296ab0bfc11 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 109:9296ab0bfc11 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 109:9296ab0bfc11 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 109:9296ab0bfc11 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 109:9296ab0bfc11 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 109:9296ab0bfc11 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 35 ---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 36
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 #if defined ( __ICCARM__ )
Kojto 109:9296ab0bfc11 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 109:9296ab0bfc11 40 #endif
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 43 extern "C" {
Kojto 109:9296ab0bfc11 44 #endif
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 109:9296ab0bfc11 47 #define __CORE_CM0PLUS_H_GENERIC
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 109:9296ab0bfc11 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 109:9296ab0bfc11 51
Kojto 109:9296ab0bfc11 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 109:9296ab0bfc11 53 Function definitions in header files are used to allow 'inlining'.
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 109:9296ab0bfc11 56 Unions are used for effective representation of core registers.
Kojto 109:9296ab0bfc11 57
Kojto 109:9296ab0bfc11 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 109:9296ab0bfc11 59 Function-like macros are used to allow more efficient code.
Kojto 109:9296ab0bfc11 60 */
Kojto 109:9296ab0bfc11 61
Kojto 109:9296ab0bfc11 62
Kojto 109:9296ab0bfc11 63 /*******************************************************************************
Kojto 109:9296ab0bfc11 64 * CMSIS definitions
Kojto 109:9296ab0bfc11 65 ******************************************************************************/
Kojto 109:9296ab0bfc11 66 /** \ingroup Cortex-M0+
Kojto 109:9296ab0bfc11 67 @{
Kojto 109:9296ab0bfc11 68 */
Kojto 109:9296ab0bfc11 69
Kojto 109:9296ab0bfc11 70 /* CMSIS CM0P definitions */
Kojto 109:9296ab0bfc11 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 109:9296ab0bfc11 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 109:9296ab0bfc11 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 109:9296ab0bfc11 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 109:9296ab0bfc11 75
Kojto 109:9296ab0bfc11 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78
Kojto 109:9296ab0bfc11 79 #if defined ( __CC_ARM )
Kojto 109:9296ab0bfc11 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 109:9296ab0bfc11 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 109:9296ab0bfc11 82 #define __STATIC_INLINE static __inline
Kojto 109:9296ab0bfc11 83
Kojto 109:9296ab0bfc11 84 #elif defined ( __ICCARM__ )
Kojto 109:9296ab0bfc11 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 109:9296ab0bfc11 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 109:9296ab0bfc11 87 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 88
Kojto 109:9296ab0bfc11 89 #elif defined ( __GNUC__ )
Kojto 109:9296ab0bfc11 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 109:9296ab0bfc11 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 109:9296ab0bfc11 92 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 93
Kojto 109:9296ab0bfc11 94 #elif defined ( __TASKING__ )
Kojto 109:9296ab0bfc11 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 109:9296ab0bfc11 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 109:9296ab0bfc11 97 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 98
Kojto 109:9296ab0bfc11 99 #endif
Kojto 109:9296ab0bfc11 100
Kojto 109:9296ab0bfc11 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 109:9296ab0bfc11 102 */
Kojto 109:9296ab0bfc11 103 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 104
Kojto 109:9296ab0bfc11 105 #if defined ( __CC_ARM )
Kojto 109:9296ab0bfc11 106 #if defined __TARGET_FPU_VFP
Kojto 109:9296ab0bfc11 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 108 #endif
Kojto 109:9296ab0bfc11 109
Kojto 109:9296ab0bfc11 110 #elif defined ( __ICCARM__ )
Kojto 109:9296ab0bfc11 111 #if defined __ARMVFP__
Kojto 109:9296ab0bfc11 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 113 #endif
Kojto 109:9296ab0bfc11 114
Kojto 109:9296ab0bfc11 115 #elif defined ( __GNUC__ )
Kojto 109:9296ab0bfc11 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 109:9296ab0bfc11 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 118 #endif
Kojto 109:9296ab0bfc11 119
Kojto 109:9296ab0bfc11 120 #elif defined ( __TASKING__ )
Kojto 109:9296ab0bfc11 121 #if defined __FPU_VFP__
Kojto 109:9296ab0bfc11 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 123 #endif
Kojto 109:9296ab0bfc11 124 #endif
Kojto 109:9296ab0bfc11 125
Kojto 109:9296ab0bfc11 126 #include <stdint.h> /* standard types definitions */
Kojto 109:9296ab0bfc11 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 109:9296ab0bfc11 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 109:9296ab0bfc11 129
Kojto 109:9296ab0bfc11 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 109:9296ab0bfc11 131
Kojto 109:9296ab0bfc11 132 #ifndef __CMSIS_GENERIC
Kojto 109:9296ab0bfc11 133
Kojto 109:9296ab0bfc11 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 109:9296ab0bfc11 135 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 109:9296ab0bfc11 136
Kojto 109:9296ab0bfc11 137 /* check device defines and use defaults */
Kojto 109:9296ab0bfc11 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 109:9296ab0bfc11 139 #ifndef __CM0PLUS_REV
Kojto 109:9296ab0bfc11 140 #define __CM0PLUS_REV 0x0000
Kojto 109:9296ab0bfc11 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 142 #endif
Kojto 109:9296ab0bfc11 143
Kojto 109:9296ab0bfc11 144 #ifndef __MPU_PRESENT
Kojto 109:9296ab0bfc11 145 #define __MPU_PRESENT 0
Kojto 109:9296ab0bfc11 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 147 #endif
Kojto 109:9296ab0bfc11 148
Kojto 109:9296ab0bfc11 149 #ifndef __VTOR_PRESENT
Kojto 109:9296ab0bfc11 150 #define __VTOR_PRESENT 0
Kojto 109:9296ab0bfc11 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 152 #endif
Kojto 109:9296ab0bfc11 153
Kojto 109:9296ab0bfc11 154 #ifndef __NVIC_PRIO_BITS
Kojto 109:9296ab0bfc11 155 #define __NVIC_PRIO_BITS 2
Kojto 109:9296ab0bfc11 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 157 #endif
Kojto 109:9296ab0bfc11 158
Kojto 109:9296ab0bfc11 159 #ifndef __Vendor_SysTickConfig
Kojto 109:9296ab0bfc11 160 #define __Vendor_SysTickConfig 0
Kojto 109:9296ab0bfc11 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 162 #endif
Kojto 109:9296ab0bfc11 163 #endif
Kojto 109:9296ab0bfc11 164
Kojto 109:9296ab0bfc11 165 /* IO definitions (access restrictions to peripheral registers) */
Kojto 109:9296ab0bfc11 166 /**
Kojto 109:9296ab0bfc11 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 109:9296ab0bfc11 168
Kojto 109:9296ab0bfc11 169 <strong>IO Type Qualifiers</strong> are used
Kojto 109:9296ab0bfc11 170 \li to specify the access to peripheral variables.
Kojto 109:9296ab0bfc11 171 \li for automatic generation of peripheral register debug information.
Kojto 109:9296ab0bfc11 172 */
Kojto 109:9296ab0bfc11 173 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 174 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 109:9296ab0bfc11 175 #else
Kojto 109:9296ab0bfc11 176 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 109:9296ab0bfc11 177 #endif
Kojto 109:9296ab0bfc11 178 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 109:9296ab0bfc11 179 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 109:9296ab0bfc11 180
Kojto 109:9296ab0bfc11 181 /*@} end of group Cortex-M0+ */
Kojto 109:9296ab0bfc11 182
Kojto 109:9296ab0bfc11 183
Kojto 109:9296ab0bfc11 184
Kojto 109:9296ab0bfc11 185 /*******************************************************************************
Kojto 109:9296ab0bfc11 186 * Register Abstraction
Kojto 109:9296ab0bfc11 187 Core Register contain:
Kojto 109:9296ab0bfc11 188 - Core Register
Kojto 109:9296ab0bfc11 189 - Core NVIC Register
Kojto 109:9296ab0bfc11 190 - Core SCB Register
Kojto 109:9296ab0bfc11 191 - Core SysTick Register
Kojto 109:9296ab0bfc11 192 - Core MPU Register
Kojto 109:9296ab0bfc11 193 ******************************************************************************/
Kojto 109:9296ab0bfc11 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 109:9296ab0bfc11 195 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 109:9296ab0bfc11 196 */
Kojto 109:9296ab0bfc11 197
Kojto 109:9296ab0bfc11 198 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 199 \defgroup CMSIS_CORE Status and Control Registers
Kojto 109:9296ab0bfc11 200 \brief Core Register type definitions.
Kojto 109:9296ab0bfc11 201 @{
Kojto 109:9296ab0bfc11 202 */
Kojto 109:9296ab0bfc11 203
Kojto 109:9296ab0bfc11 204 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 109:9296ab0bfc11 205 */
Kojto 109:9296ab0bfc11 206 typedef union
Kojto 109:9296ab0bfc11 207 {
Kojto 109:9296ab0bfc11 208 struct
Kojto 109:9296ab0bfc11 209 {
Kojto 109:9296ab0bfc11 210 #if (__CORTEX_M != 0x04)
Kojto 109:9296ab0bfc11 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 109:9296ab0bfc11 212 #else
Kojto 109:9296ab0bfc11 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 109:9296ab0bfc11 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 109:9296ab0bfc11 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 109:9296ab0bfc11 216 #endif
Kojto 109:9296ab0bfc11 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 109:9296ab0bfc11 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 109:9296ab0bfc11 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 109:9296ab0bfc11 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 109:9296ab0bfc11 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 109:9296ab0bfc11 222 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 223 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 224 } APSR_Type;
Kojto 109:9296ab0bfc11 225
Kojto 109:9296ab0bfc11 226
Kojto 109:9296ab0bfc11 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 109:9296ab0bfc11 228 */
Kojto 109:9296ab0bfc11 229 typedef union
Kojto 109:9296ab0bfc11 230 {
Kojto 109:9296ab0bfc11 231 struct
Kojto 109:9296ab0bfc11 232 {
Kojto 109:9296ab0bfc11 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 109:9296ab0bfc11 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 109:9296ab0bfc11 235 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 236 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 237 } IPSR_Type;
Kojto 109:9296ab0bfc11 238
Kojto 109:9296ab0bfc11 239
Kojto 109:9296ab0bfc11 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 109:9296ab0bfc11 241 */
Kojto 109:9296ab0bfc11 242 typedef union
Kojto 109:9296ab0bfc11 243 {
Kojto 109:9296ab0bfc11 244 struct
Kojto 109:9296ab0bfc11 245 {
Kojto 109:9296ab0bfc11 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 109:9296ab0bfc11 247 #if (__CORTEX_M != 0x04)
Kojto 109:9296ab0bfc11 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 109:9296ab0bfc11 249 #else
Kojto 109:9296ab0bfc11 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 109:9296ab0bfc11 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 109:9296ab0bfc11 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 109:9296ab0bfc11 253 #endif
Kojto 109:9296ab0bfc11 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 109:9296ab0bfc11 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 109:9296ab0bfc11 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 109:9296ab0bfc11 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 109:9296ab0bfc11 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 109:9296ab0bfc11 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 109:9296ab0bfc11 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 109:9296ab0bfc11 261 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 262 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 263 } xPSR_Type;
Kojto 109:9296ab0bfc11 264
Kojto 109:9296ab0bfc11 265
Kojto 109:9296ab0bfc11 266 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 109:9296ab0bfc11 267 */
Kojto 109:9296ab0bfc11 268 typedef union
Kojto 109:9296ab0bfc11 269 {
Kojto 109:9296ab0bfc11 270 struct
Kojto 109:9296ab0bfc11 271 {
Kojto 109:9296ab0bfc11 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 109:9296ab0bfc11 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 109:9296ab0bfc11 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 109:9296ab0bfc11 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 109:9296ab0bfc11 276 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 277 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 278 } CONTROL_Type;
Kojto 109:9296ab0bfc11 279
Kojto 109:9296ab0bfc11 280 /*@} end of group CMSIS_CORE */
Kojto 109:9296ab0bfc11 281
Kojto 109:9296ab0bfc11 282
Kojto 109:9296ab0bfc11 283 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 109:9296ab0bfc11 285 \brief Type definitions for the NVIC Registers
Kojto 109:9296ab0bfc11 286 @{
Kojto 109:9296ab0bfc11 287 */
Kojto 109:9296ab0bfc11 288
Kojto 109:9296ab0bfc11 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 109:9296ab0bfc11 290 */
Kojto 109:9296ab0bfc11 291 typedef struct
Kojto 109:9296ab0bfc11 292 {
Kojto 109:9296ab0bfc11 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 109:9296ab0bfc11 294 uint32_t RESERVED0[31];
Kojto 109:9296ab0bfc11 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 109:9296ab0bfc11 296 uint32_t RSERVED1[31];
Kojto 109:9296ab0bfc11 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 109:9296ab0bfc11 298 uint32_t RESERVED2[31];
Kojto 109:9296ab0bfc11 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 109:9296ab0bfc11 300 uint32_t RESERVED3[31];
Kojto 109:9296ab0bfc11 301 uint32_t RESERVED4[64];
Kojto 109:9296ab0bfc11 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 109:9296ab0bfc11 303 } NVIC_Type;
Kojto 109:9296ab0bfc11 304
Kojto 109:9296ab0bfc11 305 /*@} end of group CMSIS_NVIC */
Kojto 109:9296ab0bfc11 306
Kojto 109:9296ab0bfc11 307
Kojto 109:9296ab0bfc11 308 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 309 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 109:9296ab0bfc11 310 \brief Type definitions for the System Control Block Registers
Kojto 109:9296ab0bfc11 311 @{
Kojto 109:9296ab0bfc11 312 */
Kojto 109:9296ab0bfc11 313
Kojto 109:9296ab0bfc11 314 /** \brief Structure type to access the System Control Block (SCB).
Kojto 109:9296ab0bfc11 315 */
Kojto 109:9296ab0bfc11 316 typedef struct
Kojto 109:9296ab0bfc11 317 {
Kojto 109:9296ab0bfc11 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 109:9296ab0bfc11 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 109:9296ab0bfc11 320 #if (__VTOR_PRESENT == 1)
Kojto 109:9296ab0bfc11 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 109:9296ab0bfc11 322 #else
Kojto 109:9296ab0bfc11 323 uint32_t RESERVED0;
Kojto 109:9296ab0bfc11 324 #endif
Kojto 109:9296ab0bfc11 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 109:9296ab0bfc11 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 109:9296ab0bfc11 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 109:9296ab0bfc11 328 uint32_t RESERVED1;
Kojto 109:9296ab0bfc11 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 109:9296ab0bfc11 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 109:9296ab0bfc11 331 } SCB_Type;
Kojto 109:9296ab0bfc11 332
Kojto 109:9296ab0bfc11 333 /* SCB CPUID Register Definitions */
Kojto 109:9296ab0bfc11 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 109:9296ab0bfc11 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 109:9296ab0bfc11 336
Kojto 109:9296ab0bfc11 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 109:9296ab0bfc11 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 109:9296ab0bfc11 339
Kojto 109:9296ab0bfc11 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 109:9296ab0bfc11 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 109:9296ab0bfc11 342
Kojto 109:9296ab0bfc11 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 109:9296ab0bfc11 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 109:9296ab0bfc11 345
Kojto 109:9296ab0bfc11 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 109:9296ab0bfc11 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 109:9296ab0bfc11 348
Kojto 109:9296ab0bfc11 349 /* SCB Interrupt Control State Register Definitions */
Kojto 109:9296ab0bfc11 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 109:9296ab0bfc11 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 109:9296ab0bfc11 352
Kojto 109:9296ab0bfc11 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 109:9296ab0bfc11 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 109:9296ab0bfc11 355
Kojto 109:9296ab0bfc11 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 109:9296ab0bfc11 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 109:9296ab0bfc11 358
Kojto 109:9296ab0bfc11 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 109:9296ab0bfc11 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 109:9296ab0bfc11 361
Kojto 109:9296ab0bfc11 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 109:9296ab0bfc11 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 109:9296ab0bfc11 364
Kojto 109:9296ab0bfc11 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 109:9296ab0bfc11 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 109:9296ab0bfc11 367
Kojto 109:9296ab0bfc11 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 109:9296ab0bfc11 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 109:9296ab0bfc11 370
Kojto 109:9296ab0bfc11 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 109:9296ab0bfc11 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 109:9296ab0bfc11 373
Kojto 109:9296ab0bfc11 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 109:9296ab0bfc11 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 109:9296ab0bfc11 376
Kojto 109:9296ab0bfc11 377 #if (__VTOR_PRESENT == 1)
Kojto 109:9296ab0bfc11 378 /* SCB Interrupt Control State Register Definitions */
Kojto 109:9296ab0bfc11 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 109:9296ab0bfc11 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 109:9296ab0bfc11 381 #endif
Kojto 109:9296ab0bfc11 382
Kojto 109:9296ab0bfc11 383 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 109:9296ab0bfc11 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 109:9296ab0bfc11 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 109:9296ab0bfc11 386
Kojto 109:9296ab0bfc11 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 109:9296ab0bfc11 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 109:9296ab0bfc11 389
Kojto 109:9296ab0bfc11 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 109:9296ab0bfc11 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 109:9296ab0bfc11 392
Kojto 109:9296ab0bfc11 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 109:9296ab0bfc11 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 109:9296ab0bfc11 395
Kojto 109:9296ab0bfc11 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 109:9296ab0bfc11 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 109:9296ab0bfc11 398
Kojto 109:9296ab0bfc11 399 /* SCB System Control Register Definitions */
Kojto 109:9296ab0bfc11 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 109:9296ab0bfc11 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 109:9296ab0bfc11 402
Kojto 109:9296ab0bfc11 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 109:9296ab0bfc11 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 109:9296ab0bfc11 405
Kojto 109:9296ab0bfc11 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 109:9296ab0bfc11 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 109:9296ab0bfc11 408
Kojto 109:9296ab0bfc11 409 /* SCB Configuration Control Register Definitions */
Kojto 109:9296ab0bfc11 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 109:9296ab0bfc11 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 109:9296ab0bfc11 412
Kojto 109:9296ab0bfc11 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 109:9296ab0bfc11 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 109:9296ab0bfc11 415
Kojto 109:9296ab0bfc11 416 /* SCB System Handler Control and State Register Definitions */
Kojto 109:9296ab0bfc11 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 109:9296ab0bfc11 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 109:9296ab0bfc11 419
Kojto 109:9296ab0bfc11 420 /*@} end of group CMSIS_SCB */
Kojto 109:9296ab0bfc11 421
Kojto 109:9296ab0bfc11 422
Kojto 109:9296ab0bfc11 423 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 109:9296ab0bfc11 425 \brief Type definitions for the System Timer Registers.
Kojto 109:9296ab0bfc11 426 @{
Kojto 109:9296ab0bfc11 427 */
Kojto 109:9296ab0bfc11 428
Kojto 109:9296ab0bfc11 429 /** \brief Structure type to access the System Timer (SysTick).
Kojto 109:9296ab0bfc11 430 */
Kojto 109:9296ab0bfc11 431 typedef struct
Kojto 109:9296ab0bfc11 432 {
Kojto 109:9296ab0bfc11 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 109:9296ab0bfc11 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 109:9296ab0bfc11 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 109:9296ab0bfc11 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 109:9296ab0bfc11 437 } SysTick_Type;
Kojto 109:9296ab0bfc11 438
Kojto 109:9296ab0bfc11 439 /* SysTick Control / Status Register Definitions */
Kojto 109:9296ab0bfc11 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 109:9296ab0bfc11 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 109:9296ab0bfc11 442
Kojto 109:9296ab0bfc11 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 109:9296ab0bfc11 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 109:9296ab0bfc11 445
Kojto 109:9296ab0bfc11 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 109:9296ab0bfc11 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 109:9296ab0bfc11 448
Kojto 109:9296ab0bfc11 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 109:9296ab0bfc11 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 109:9296ab0bfc11 451
Kojto 109:9296ab0bfc11 452 /* SysTick Reload Register Definitions */
Kojto 109:9296ab0bfc11 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 109:9296ab0bfc11 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 109:9296ab0bfc11 455
Kojto 109:9296ab0bfc11 456 /* SysTick Current Register Definitions */
Kojto 109:9296ab0bfc11 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 109:9296ab0bfc11 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 109:9296ab0bfc11 459
Kojto 109:9296ab0bfc11 460 /* SysTick Calibration Register Definitions */
Kojto 109:9296ab0bfc11 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 109:9296ab0bfc11 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 109:9296ab0bfc11 463
Kojto 109:9296ab0bfc11 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 109:9296ab0bfc11 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 109:9296ab0bfc11 466
Kojto 109:9296ab0bfc11 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 109:9296ab0bfc11 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 109:9296ab0bfc11 469
Kojto 109:9296ab0bfc11 470 /*@} end of group CMSIS_SysTick */
Kojto 109:9296ab0bfc11 471
Kojto 109:9296ab0bfc11 472 #if (__MPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 473 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 109:9296ab0bfc11 475 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 109:9296ab0bfc11 476 @{
Kojto 109:9296ab0bfc11 477 */
Kojto 109:9296ab0bfc11 478
Kojto 109:9296ab0bfc11 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 109:9296ab0bfc11 480 */
Kojto 109:9296ab0bfc11 481 typedef struct
Kojto 109:9296ab0bfc11 482 {
Kojto 109:9296ab0bfc11 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 109:9296ab0bfc11 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 109:9296ab0bfc11 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 109:9296ab0bfc11 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 109:9296ab0bfc11 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 488 } MPU_Type;
Kojto 109:9296ab0bfc11 489
Kojto 109:9296ab0bfc11 490 /* MPU Type Register */
Kojto 109:9296ab0bfc11 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 109:9296ab0bfc11 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 109:9296ab0bfc11 493
Kojto 109:9296ab0bfc11 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 109:9296ab0bfc11 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 109:9296ab0bfc11 496
Kojto 109:9296ab0bfc11 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 109:9296ab0bfc11 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kojto 109:9296ab0bfc11 499
Kojto 109:9296ab0bfc11 500 /* MPU Control Register */
Kojto 109:9296ab0bfc11 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 109:9296ab0bfc11 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 109:9296ab0bfc11 503
Kojto 109:9296ab0bfc11 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 109:9296ab0bfc11 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 109:9296ab0bfc11 506
Kojto 109:9296ab0bfc11 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 109:9296ab0bfc11 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kojto 109:9296ab0bfc11 509
Kojto 109:9296ab0bfc11 510 /* MPU Region Number Register */
Kojto 109:9296ab0bfc11 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 109:9296ab0bfc11 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kojto 109:9296ab0bfc11 513
Kojto 109:9296ab0bfc11 514 /* MPU Region Base Address Register */
Kojto 109:9296ab0bfc11 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 109:9296ab0bfc11 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 109:9296ab0bfc11 517
Kojto 109:9296ab0bfc11 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 109:9296ab0bfc11 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 109:9296ab0bfc11 520
Kojto 109:9296ab0bfc11 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 109:9296ab0bfc11 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kojto 109:9296ab0bfc11 523
Kojto 109:9296ab0bfc11 524 /* MPU Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 109:9296ab0bfc11 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 109:9296ab0bfc11 527
Kojto 109:9296ab0bfc11 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 109:9296ab0bfc11 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 109:9296ab0bfc11 530
Kojto 109:9296ab0bfc11 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 109:9296ab0bfc11 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 109:9296ab0bfc11 533
Kojto 109:9296ab0bfc11 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 109:9296ab0bfc11 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 109:9296ab0bfc11 536
Kojto 109:9296ab0bfc11 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 109:9296ab0bfc11 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 109:9296ab0bfc11 539
Kojto 109:9296ab0bfc11 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 109:9296ab0bfc11 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 109:9296ab0bfc11 542
Kojto 109:9296ab0bfc11 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 109:9296ab0bfc11 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 109:9296ab0bfc11 545
Kojto 109:9296ab0bfc11 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 109:9296ab0bfc11 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 109:9296ab0bfc11 548
Kojto 109:9296ab0bfc11 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 109:9296ab0bfc11 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 109:9296ab0bfc11 551
Kojto 109:9296ab0bfc11 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 109:9296ab0bfc11 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 109:9296ab0bfc11 554
Kojto 109:9296ab0bfc11 555 /*@} end of group CMSIS_MPU */
Kojto 109:9296ab0bfc11 556 #endif
Kojto 109:9296ab0bfc11 557
Kojto 109:9296ab0bfc11 558
Kojto 109:9296ab0bfc11 559 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 109:9296ab0bfc11 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 109:9296ab0bfc11 562 are only accessible over DAP and not via processor. Therefore
Kojto 109:9296ab0bfc11 563 they are not covered by the Cortex-M0 header file.
Kojto 109:9296ab0bfc11 564 @{
Kojto 109:9296ab0bfc11 565 */
Kojto 109:9296ab0bfc11 566 /*@} end of group CMSIS_CoreDebug */
Kojto 109:9296ab0bfc11 567
Kojto 109:9296ab0bfc11 568
Kojto 109:9296ab0bfc11 569 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 570 \defgroup CMSIS_core_base Core Definitions
Kojto 109:9296ab0bfc11 571 \brief Definitions for base addresses, unions, and structures.
Kojto 109:9296ab0bfc11 572 @{
Kojto 109:9296ab0bfc11 573 */
Kojto 109:9296ab0bfc11 574
Kojto 109:9296ab0bfc11 575 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 109:9296ab0bfc11 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 109:9296ab0bfc11 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 109:9296ab0bfc11 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 109:9296ab0bfc11 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 109:9296ab0bfc11 580
Kojto 109:9296ab0bfc11 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 109:9296ab0bfc11 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 109:9296ab0bfc11 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 109:9296ab0bfc11 584
Kojto 109:9296ab0bfc11 585 #if (__MPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 109:9296ab0bfc11 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 109:9296ab0bfc11 588 #endif
Kojto 109:9296ab0bfc11 589
Kojto 109:9296ab0bfc11 590 /*@} */
Kojto 109:9296ab0bfc11 591
Kojto 109:9296ab0bfc11 592
Kojto 109:9296ab0bfc11 593
Kojto 109:9296ab0bfc11 594 /*******************************************************************************
Kojto 109:9296ab0bfc11 595 * Hardware Abstraction Layer
Kojto 109:9296ab0bfc11 596 Core Function Interface contains:
Kojto 109:9296ab0bfc11 597 - Core NVIC Functions
Kojto 109:9296ab0bfc11 598 - Core SysTick Functions
Kojto 109:9296ab0bfc11 599 - Core Register Access Functions
Kojto 109:9296ab0bfc11 600 ******************************************************************************/
Kojto 109:9296ab0bfc11 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 109:9296ab0bfc11 602 */
Kojto 109:9296ab0bfc11 603
Kojto 109:9296ab0bfc11 604
Kojto 109:9296ab0bfc11 605
Kojto 109:9296ab0bfc11 606 /* ########################## NVIC functions #################################### */
Kojto 109:9296ab0bfc11 607 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 109:9296ab0bfc11 609 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 109:9296ab0bfc11 610 @{
Kojto 109:9296ab0bfc11 611 */
Kojto 109:9296ab0bfc11 612
Kojto 109:9296ab0bfc11 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 109:9296ab0bfc11 614 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 109:9296ab0bfc11 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 109:9296ab0bfc11 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 109:9296ab0bfc11 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 109:9296ab0bfc11 618
Kojto 109:9296ab0bfc11 619
Kojto 109:9296ab0bfc11 620 /** \brief Enable External Interrupt
Kojto 109:9296ab0bfc11 621
Kojto 109:9296ab0bfc11 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 109:9296ab0bfc11 623
Kojto 109:9296ab0bfc11 624 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 625 */
Kojto 109:9296ab0bfc11 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 627 {
Kojto 109:9296ab0bfc11 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 109:9296ab0bfc11 629 }
Kojto 109:9296ab0bfc11 630
Kojto 109:9296ab0bfc11 631
Kojto 109:9296ab0bfc11 632 /** \brief Disable External Interrupt
Kojto 109:9296ab0bfc11 633
Kojto 109:9296ab0bfc11 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 109:9296ab0bfc11 635
Kojto 109:9296ab0bfc11 636 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 637 */
Kojto 109:9296ab0bfc11 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 639 {
Kojto 109:9296ab0bfc11 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 109:9296ab0bfc11 641 }
Kojto 109:9296ab0bfc11 642
Kojto 109:9296ab0bfc11 643
Kojto 109:9296ab0bfc11 644 /** \brief Get Pending Interrupt
Kojto 109:9296ab0bfc11 645
Kojto 109:9296ab0bfc11 646 The function reads the pending register in the NVIC and returns the pending bit
Kojto 109:9296ab0bfc11 647 for the specified interrupt.
Kojto 109:9296ab0bfc11 648
Kojto 109:9296ab0bfc11 649 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 650
Kojto 109:9296ab0bfc11 651 \return 0 Interrupt status is not pending.
Kojto 109:9296ab0bfc11 652 \return 1 Interrupt status is pending.
Kojto 109:9296ab0bfc11 653 */
Kojto 109:9296ab0bfc11 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 655 {
Kojto 109:9296ab0bfc11 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 109:9296ab0bfc11 657 }
Kojto 109:9296ab0bfc11 658
Kojto 109:9296ab0bfc11 659
Kojto 109:9296ab0bfc11 660 /** \brief Set Pending Interrupt
Kojto 109:9296ab0bfc11 661
Kojto 109:9296ab0bfc11 662 The function sets the pending bit of an external interrupt.
Kojto 109:9296ab0bfc11 663
Kojto 109:9296ab0bfc11 664 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 665 */
Kojto 109:9296ab0bfc11 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 667 {
Kojto 109:9296ab0bfc11 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 109:9296ab0bfc11 669 }
Kojto 109:9296ab0bfc11 670
Kojto 109:9296ab0bfc11 671
Kojto 109:9296ab0bfc11 672 /** \brief Clear Pending Interrupt
Kojto 109:9296ab0bfc11 673
Kojto 109:9296ab0bfc11 674 The function clears the pending bit of an external interrupt.
Kojto 109:9296ab0bfc11 675
Kojto 109:9296ab0bfc11 676 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 677 */
Kojto 109:9296ab0bfc11 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 679 {
Kojto 109:9296ab0bfc11 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 109:9296ab0bfc11 681 }
Kojto 109:9296ab0bfc11 682
Kojto 109:9296ab0bfc11 683
Kojto 109:9296ab0bfc11 684 /** \brief Set Interrupt Priority
Kojto 109:9296ab0bfc11 685
Kojto 109:9296ab0bfc11 686 The function sets the priority of an interrupt.
Kojto 109:9296ab0bfc11 687
Kojto 109:9296ab0bfc11 688 \note The priority cannot be set for every core interrupt.
Kojto 109:9296ab0bfc11 689
Kojto 109:9296ab0bfc11 690 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 691 \param [in] priority Priority to set.
Kojto 109:9296ab0bfc11 692 */
Kojto 109:9296ab0bfc11 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 109:9296ab0bfc11 694 {
Kojto 109:9296ab0bfc11 695 if(IRQn < 0) {
Kojto 109:9296ab0bfc11 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 109:9296ab0bfc11 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 109:9296ab0bfc11 698 else {
Kojto 109:9296ab0bfc11 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 109:9296ab0bfc11 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 109:9296ab0bfc11 701 }
Kojto 109:9296ab0bfc11 702
Kojto 109:9296ab0bfc11 703
Kojto 109:9296ab0bfc11 704 /** \brief Get Interrupt Priority
Kojto 109:9296ab0bfc11 705
Kojto 109:9296ab0bfc11 706 The function reads the priority of an interrupt. The interrupt
Kojto 109:9296ab0bfc11 707 number can be positive to specify an external (device specific)
Kojto 109:9296ab0bfc11 708 interrupt, or negative to specify an internal (core) interrupt.
Kojto 109:9296ab0bfc11 709
Kojto 109:9296ab0bfc11 710
Kojto 109:9296ab0bfc11 711 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 712 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 109:9296ab0bfc11 713 priority bits of the microcontroller.
Kojto 109:9296ab0bfc11 714 */
Kojto 109:9296ab0bfc11 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 716 {
Kojto 109:9296ab0bfc11 717
Kojto 109:9296ab0bfc11 718 if(IRQn < 0) {
Kojto 109:9296ab0bfc11 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 109:9296ab0bfc11 720 else {
Kojto 109:9296ab0bfc11 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 109:9296ab0bfc11 722 }
Kojto 109:9296ab0bfc11 723
Kojto 109:9296ab0bfc11 724
Kojto 109:9296ab0bfc11 725 /** \brief System Reset
Kojto 109:9296ab0bfc11 726
Kojto 109:9296ab0bfc11 727 The function initiates a system reset request to reset the MCU.
Kojto 109:9296ab0bfc11 728 */
Kojto 109:9296ab0bfc11 729 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 109:9296ab0bfc11 730 {
Kojto 109:9296ab0bfc11 731 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 109:9296ab0bfc11 732 buffered write are completed before reset */
Kojto 109:9296ab0bfc11 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 109:9296ab0bfc11 734 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 109:9296ab0bfc11 735 __DSB(); /* Ensure completion of memory access */
Kojto 109:9296ab0bfc11 736 while(1); /* wait until reset */
Kojto 109:9296ab0bfc11 737 }
Kojto 109:9296ab0bfc11 738
Kojto 109:9296ab0bfc11 739 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 109:9296ab0bfc11 740
Kojto 109:9296ab0bfc11 741
Kojto 109:9296ab0bfc11 742
Kojto 109:9296ab0bfc11 743 /* ################################## SysTick function ############################################ */
Kojto 109:9296ab0bfc11 744 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 109:9296ab0bfc11 746 \brief Functions that configure the System.
Kojto 109:9296ab0bfc11 747 @{
Kojto 109:9296ab0bfc11 748 */
Kojto 109:9296ab0bfc11 749
Kojto 109:9296ab0bfc11 750 #if (__Vendor_SysTickConfig == 0)
Kojto 109:9296ab0bfc11 751
Kojto 109:9296ab0bfc11 752 /** \brief System Tick Configuration
Kojto 109:9296ab0bfc11 753
Kojto 109:9296ab0bfc11 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 109:9296ab0bfc11 755 Counter is in free running mode to generate periodic interrupts.
Kojto 109:9296ab0bfc11 756
Kojto 109:9296ab0bfc11 757 \param [in] ticks Number of ticks between two interrupts.
Kojto 109:9296ab0bfc11 758
Kojto 109:9296ab0bfc11 759 \return 0 Function succeeded.
Kojto 109:9296ab0bfc11 760 \return 1 Function failed.
Kojto 109:9296ab0bfc11 761
Kojto 109:9296ab0bfc11 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 109:9296ab0bfc11 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 109:9296ab0bfc11 764 must contain a vendor-specific implementation of this function.
Kojto 109:9296ab0bfc11 765
Kojto 109:9296ab0bfc11 766 */
Kojto 109:9296ab0bfc11 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 109:9296ab0bfc11 768 {
Kojto 109:9296ab0bfc11 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 109:9296ab0bfc11 770
Kojto 109:9296ab0bfc11 771 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 109:9296ab0bfc11 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 109:9296ab0bfc11 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 109:9296ab0bfc11 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 109:9296ab0bfc11 775 SysTick_CTRL_TICKINT_Msk |
Kojto 109:9296ab0bfc11 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 109:9296ab0bfc11 777 return (0); /* Function successful */
Kojto 109:9296ab0bfc11 778 }
Kojto 109:9296ab0bfc11 779
Kojto 109:9296ab0bfc11 780 #endif
Kojto 109:9296ab0bfc11 781
Kojto 109:9296ab0bfc11 782 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 109:9296ab0bfc11 783
Kojto 109:9296ab0bfc11 784
Kojto 109:9296ab0bfc11 785
Kojto 109:9296ab0bfc11 786
Kojto 109:9296ab0bfc11 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 109:9296ab0bfc11 788
Kojto 109:9296ab0bfc11 789 #endif /* __CMSIS_GENERIC */
Kojto 109:9296ab0bfc11 790
Kojto 109:9296ab0bfc11 791 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 792 }
Kojto 109:9296ab0bfc11 793 #endif