mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F446RE/core_caFunc.h@115:87f2f5183dfb, 2016-03-02 (annotated)

Committer:
Kojto
Date:
Wed Mar 02 09:58:28 2016 +0100
Revision:
115:87f2f5183dfb
Parent:
108:34e6b704fe68
Child:
121:6c34061e7c34
Release 115 of the mbed library



Changes:

- new targets - NUCLEO_F746ZG

- Bugfix - STM32F7 + STM32L4 - RTC init fix

- Bugfix - STM32L4 Set NVIC_RAM_VECTOR_ADDRESS to 0x10000000

- B96B_F446VE - CAN addition

- Changed target name from NZ32SC151 to NZ32_SC151

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 106:ba1f97679dad 1 /**************************************************************************//**
Kojto 106:ba1f97679dad 2 * @file core_caFunc.h
Kojto 106:ba1f97679dad 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 106:ba1f97679dad 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 106:ba1f97679dad 6 *
Kojto 106:ba1f97679dad 7 * @note
Kojto 106:ba1f97679dad 8 *
Kojto 106:ba1f97679dad 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 106:ba1f97679dad 11
Kojto 106:ba1f97679dad 12 All rights reserved.
Kojto 106:ba1f97679dad 13 Redistribution and use in source and binary forms, with or without
Kojto 106:ba1f97679dad 14 modification, are permitted provided that the following conditions are met:
Kojto 106:ba1f97679dad 15 - Redistributions of source code must retain the above copyright
Kojto 106:ba1f97679dad 16 notice, this list of conditions and the following disclaimer.
Kojto 106:ba1f97679dad 17 - Redistributions in binary form must reproduce the above copyright
Kojto 106:ba1f97679dad 18 notice, this list of conditions and the following disclaimer in the
Kojto 106:ba1f97679dad 19 documentation and/or other materials provided with the distribution.
Kojto 106:ba1f97679dad 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 106:ba1f97679dad 21 to endorse or promote products derived from this software without
Kojto 106:ba1f97679dad 22 specific prior written permission.
Kojto 106:ba1f97679dad 23 *
Kojto 106:ba1f97679dad 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 106:ba1f97679dad 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 106:ba1f97679dad 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 106:ba1f97679dad 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 106:ba1f97679dad 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 106:ba1f97679dad 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 106:ba1f97679dad 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 106:ba1f97679dad 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 106:ba1f97679dad 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 106:ba1f97679dad 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 106:ba1f97679dad 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 106:ba1f97679dad 35 ---------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 36
Kojto 106:ba1f97679dad 37
Kojto 106:ba1f97679dad 38 #ifndef __CORE_CAFUNC_H__
Kojto 106:ba1f97679dad 39 #define __CORE_CAFUNC_H__
Kojto 106:ba1f97679dad 40
Kojto 106:ba1f97679dad 41
Kojto 106:ba1f97679dad 42 /* ########################### Core Function Access ########################### */
Kojto 106:ba1f97679dad 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 106:ba1f97679dad 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 106:ba1f97679dad 45 @{
Kojto 106:ba1f97679dad 46 */
Kojto 106:ba1f97679dad 47
Kojto 106:ba1f97679dad 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 106:ba1f97679dad 49 /* ARM armcc specific functions */
Kojto 106:ba1f97679dad 50
Kojto 106:ba1f97679dad 51 #if (__ARMCC_VERSION < 400677)
Kojto 106:ba1f97679dad 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 106:ba1f97679dad 53 #endif
Kojto 106:ba1f97679dad 54
Kojto 106:ba1f97679dad 55 #define MODE_USR 0x10
Kojto 106:ba1f97679dad 56 #define MODE_FIQ 0x11
Kojto 106:ba1f97679dad 57 #define MODE_IRQ 0x12
Kojto 106:ba1f97679dad 58 #define MODE_SVC 0x13
Kojto 106:ba1f97679dad 59 #define MODE_MON 0x16
Kojto 106:ba1f97679dad 60 #define MODE_ABT 0x17
Kojto 106:ba1f97679dad 61 #define MODE_HYP 0x1A
Kojto 106:ba1f97679dad 62 #define MODE_UND 0x1B
Kojto 106:ba1f97679dad 63 #define MODE_SYS 0x1F
Kojto 106:ba1f97679dad 64
Kojto 106:ba1f97679dad 65 /** \brief Get APSR Register
Kojto 106:ba1f97679dad 66
Kojto 106:ba1f97679dad 67 This function returns the content of the APSR Register.
Kojto 106:ba1f97679dad 68
Kojto 106:ba1f97679dad 69 \return APSR Register value
Kojto 106:ba1f97679dad 70 */
Kojto 106:ba1f97679dad 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 106:ba1f97679dad 72 {
Kojto 106:ba1f97679dad 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 106:ba1f97679dad 74 return(__regAPSR);
Kojto 106:ba1f97679dad 75 }
Kojto 106:ba1f97679dad 76
Kojto 106:ba1f97679dad 77
Kojto 106:ba1f97679dad 78 /** \brief Get CPSR Register
Kojto 106:ba1f97679dad 79
Kojto 106:ba1f97679dad 80 This function returns the content of the CPSR Register.
Kojto 106:ba1f97679dad 81
Kojto 106:ba1f97679dad 82 \return CPSR Register value
Kojto 106:ba1f97679dad 83 */
Kojto 106:ba1f97679dad 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 106:ba1f97679dad 85 {
Kojto 106:ba1f97679dad 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 106:ba1f97679dad 87 return(__regCPSR);
Kojto 106:ba1f97679dad 88 }
Kojto 106:ba1f97679dad 89
Kojto 106:ba1f97679dad 90 /** \brief Set Stack Pointer
Kojto 106:ba1f97679dad 91
Kojto 106:ba1f97679dad 92 This function assigns the given value to the current stack pointer.
Kojto 106:ba1f97679dad 93
Kojto 106:ba1f97679dad 94 \param [in] topOfStack Stack Pointer value to set
Kojto 106:ba1f97679dad 95 */
Kojto 106:ba1f97679dad 96 register uint32_t __regSP __ASM("sp");
Kojto 106:ba1f97679dad 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 106:ba1f97679dad 98 {
Kojto 106:ba1f97679dad 99 __regSP = topOfStack;
Kojto 106:ba1f97679dad 100 }
Kojto 106:ba1f97679dad 101
Kojto 106:ba1f97679dad 102
Kojto 106:ba1f97679dad 103 /** \brief Get link register
Kojto 106:ba1f97679dad 104
Kojto 106:ba1f97679dad 105 This function returns the value of the link register
Kojto 106:ba1f97679dad 106
Kojto 106:ba1f97679dad 107 \return Value of link register
Kojto 106:ba1f97679dad 108 */
Kojto 106:ba1f97679dad 109 register uint32_t __reglr __ASM("lr");
Kojto 106:ba1f97679dad 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 106:ba1f97679dad 111 {
Kojto 106:ba1f97679dad 112 return(__reglr);
Kojto 106:ba1f97679dad 113 }
Kojto 106:ba1f97679dad 114
Kojto 106:ba1f97679dad 115 /** \brief Set link register
Kojto 106:ba1f97679dad 116
Kojto 106:ba1f97679dad 117 This function sets the value of the link register
Kojto 106:ba1f97679dad 118
Kojto 106:ba1f97679dad 119 \param [in] lr LR value to set
Kojto 106:ba1f97679dad 120 */
Kojto 106:ba1f97679dad 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 106:ba1f97679dad 122 {
Kojto 106:ba1f97679dad 123 __reglr = lr;
Kojto 106:ba1f97679dad 124 }
Kojto 106:ba1f97679dad 125
Kojto 106:ba1f97679dad 126 /** \brief Set Process Stack Pointer
Kojto 106:ba1f97679dad 127
Kojto 106:ba1f97679dad 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 106:ba1f97679dad 129
Kojto 106:ba1f97679dad 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 106:ba1f97679dad 131 */
Kojto 106:ba1f97679dad 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 106:ba1f97679dad 133 {
Kojto 106:ba1f97679dad 134 ARM
Kojto 106:ba1f97679dad 135 PRESERVE8
Kojto 106:ba1f97679dad 136
Kojto 106:ba1f97679dad 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 106:ba1f97679dad 138 MRS R1, CPSR
Kojto 106:ba1f97679dad 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 106:ba1f97679dad 140 MOV SP, R0
Kojto 106:ba1f97679dad 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 106:ba1f97679dad 142 ISB
Kojto 106:ba1f97679dad 143 BX LR
Kojto 106:ba1f97679dad 144
Kojto 106:ba1f97679dad 145 }
Kojto 106:ba1f97679dad 146
Kojto 106:ba1f97679dad 147 /** \brief Set User Mode
Kojto 106:ba1f97679dad 148
Kojto 106:ba1f97679dad 149 This function changes the processor state to User Mode
Kojto 106:ba1f97679dad 150 */
Kojto 106:ba1f97679dad 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 106:ba1f97679dad 152 {
Kojto 106:ba1f97679dad 153 ARM
Kojto 106:ba1f97679dad 154
Kojto 106:ba1f97679dad 155 CPS #MODE_USR
Kojto 106:ba1f97679dad 156 BX LR
Kojto 106:ba1f97679dad 157 }
Kojto 106:ba1f97679dad 158
Kojto 106:ba1f97679dad 159
Kojto 106:ba1f97679dad 160 /** \brief Enable FIQ
Kojto 106:ba1f97679dad 161
Kojto 106:ba1f97679dad 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 106:ba1f97679dad 163 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 164 */
Kojto 106:ba1f97679dad 165 #define __enable_fault_irq __enable_fiq
Kojto 106:ba1f97679dad 166
Kojto 106:ba1f97679dad 167
Kojto 106:ba1f97679dad 168 /** \brief Disable FIQ
Kojto 106:ba1f97679dad 169
Kojto 106:ba1f97679dad 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 106:ba1f97679dad 171 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 172 */
Kojto 106:ba1f97679dad 173 #define __disable_fault_irq __disable_fiq
Kojto 106:ba1f97679dad 174
Kojto 106:ba1f97679dad 175
Kojto 106:ba1f97679dad 176 /** \brief Get FPSCR
Kojto 106:ba1f97679dad 177
Kojto 106:ba1f97679dad 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 179
Kojto 106:ba1f97679dad 180 \return Floating Point Status/Control register value
Kojto 106:ba1f97679dad 181 */
Kojto 106:ba1f97679dad 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 106:ba1f97679dad 183 {
Kojto 106:ba1f97679dad 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 186 return(__regfpscr);
Kojto 106:ba1f97679dad 187 #else
Kojto 106:ba1f97679dad 188 return(0);
Kojto 106:ba1f97679dad 189 #endif
Kojto 106:ba1f97679dad 190 }
Kojto 106:ba1f97679dad 191
Kojto 106:ba1f97679dad 192
Kojto 106:ba1f97679dad 193 /** \brief Set FPSCR
Kojto 106:ba1f97679dad 194
Kojto 106:ba1f97679dad 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 196
Kojto 106:ba1f97679dad 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 106:ba1f97679dad 198 */
Kojto 106:ba1f97679dad 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 106:ba1f97679dad 200 {
Kojto 106:ba1f97679dad 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 203 __regfpscr = (fpscr);
Kojto 106:ba1f97679dad 204 #endif
Kojto 106:ba1f97679dad 205 }
Kojto 106:ba1f97679dad 206
Kojto 106:ba1f97679dad 207 /** \brief Get FPEXC
Kojto 106:ba1f97679dad 208
Kojto 106:ba1f97679dad 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 210
Kojto 106:ba1f97679dad 211 \return Floating Point Exception Control register value
Kojto 106:ba1f97679dad 212 */
Kojto 106:ba1f97679dad 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 106:ba1f97679dad 214 {
Kojto 106:ba1f97679dad 215 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 217 return(__regfpexc);
Kojto 106:ba1f97679dad 218 #else
Kojto 106:ba1f97679dad 219 return(0);
Kojto 106:ba1f97679dad 220 #endif
Kojto 106:ba1f97679dad 221 }
Kojto 106:ba1f97679dad 222
Kojto 106:ba1f97679dad 223
Kojto 106:ba1f97679dad 224 /** \brief Set FPEXC
Kojto 106:ba1f97679dad 225
Kojto 106:ba1f97679dad 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 227
Kojto 106:ba1f97679dad 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 106:ba1f97679dad 229 */
Kojto 106:ba1f97679dad 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 106:ba1f97679dad 231 {
Kojto 106:ba1f97679dad 232 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 234 __regfpexc = (fpexc);
Kojto 106:ba1f97679dad 235 #endif
Kojto 106:ba1f97679dad 236 }
Kojto 106:ba1f97679dad 237
Kojto 106:ba1f97679dad 238 /** \brief Get CPACR
Kojto 106:ba1f97679dad 239
Kojto 106:ba1f97679dad 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 241
Kojto 106:ba1f97679dad 242 \return Coprocessor Access Control register value
Kojto 106:ba1f97679dad 243 */
Kojto 106:ba1f97679dad 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 106:ba1f97679dad 245 {
Kojto 106:ba1f97679dad 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 247 return __regCPACR;
Kojto 106:ba1f97679dad 248 }
Kojto 106:ba1f97679dad 249
Kojto 106:ba1f97679dad 250 /** \brief Set CPACR
Kojto 106:ba1f97679dad 251
Kojto 106:ba1f97679dad 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 106:ba1f97679dad 255 */
Kojto 106:ba1f97679dad 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 106:ba1f97679dad 257 {
Kojto 106:ba1f97679dad 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 259 __regCPACR = cpacr;
Kojto 106:ba1f97679dad 260 __ISB();
Kojto 106:ba1f97679dad 261 }
Kojto 106:ba1f97679dad 262
Kojto 106:ba1f97679dad 263 /** \brief Get CBAR
Kojto 106:ba1f97679dad 264
Kojto 106:ba1f97679dad 265 This function returns the value of the Configuration Base Address register.
Kojto 106:ba1f97679dad 266
Kojto 106:ba1f97679dad 267 \return Configuration Base Address register value
Kojto 106:ba1f97679dad 268 */
Kojto 106:ba1f97679dad 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 106:ba1f97679dad 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 106:ba1f97679dad 271 return(__regCBAR);
Kojto 106:ba1f97679dad 272 }
Kojto 106:ba1f97679dad 273
Kojto 106:ba1f97679dad 274 /** \brief Get TTBR0
Kojto 106:ba1f97679dad 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 106:ba1f97679dad 277
Kojto 106:ba1f97679dad 278 \return Translation Table Base Register 0 value
Kojto 106:ba1f97679dad 279 */
Kojto 106:ba1f97679dad 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 106:ba1f97679dad 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 282 return(__regTTBR0);
Kojto 106:ba1f97679dad 283 }
Kojto 106:ba1f97679dad 284
Kojto 106:ba1f97679dad 285 /** \brief Set TTBR0
Kojto 106:ba1f97679dad 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 106:ba1f97679dad 288
Kojto 106:ba1f97679dad 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 106:ba1f97679dad 290 */
Kojto 106:ba1f97679dad 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 106:ba1f97679dad 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 293 __regTTBR0 = ttbr0;
Kojto 106:ba1f97679dad 294 __ISB();
Kojto 106:ba1f97679dad 295 }
Kojto 106:ba1f97679dad 296
Kojto 106:ba1f97679dad 297 /** \brief Get DACR
Kojto 106:ba1f97679dad 298
Kojto 106:ba1f97679dad 299 This function returns the value of the Domain Access Control Register.
Kojto 106:ba1f97679dad 300
Kojto 106:ba1f97679dad 301 \return Domain Access Control Register value
Kojto 106:ba1f97679dad 302 */
Kojto 106:ba1f97679dad 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 106:ba1f97679dad 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 305 return(__regDACR);
Kojto 106:ba1f97679dad 306 }
Kojto 106:ba1f97679dad 307
Kojto 106:ba1f97679dad 308 /** \brief Set DACR
Kojto 106:ba1f97679dad 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 106:ba1f97679dad 311
Kojto 106:ba1f97679dad 312 \param [in] dacr Domain Access Control Register value to set
Kojto 106:ba1f97679dad 313 */
Kojto 106:ba1f97679dad 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 106:ba1f97679dad 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 316 __regDACR = dacr;
Kojto 106:ba1f97679dad 317 __ISB();
Kojto 106:ba1f97679dad 318 }
Kojto 106:ba1f97679dad 319
Kojto 106:ba1f97679dad 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 106:ba1f97679dad 321
Kojto 106:ba1f97679dad 322 /** \brief Set SCTLR
Kojto 106:ba1f97679dad 323
Kojto 106:ba1f97679dad 324 This function assigns the given value to the System Control Register.
Kojto 106:ba1f97679dad 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 106:ba1f97679dad 327 */
Kojto 106:ba1f97679dad 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 106:ba1f97679dad 329 {
Kojto 106:ba1f97679dad 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 331 __regSCTLR = sctlr;
Kojto 106:ba1f97679dad 332 }
Kojto 106:ba1f97679dad 333
Kojto 106:ba1f97679dad 334 /** \brief Get SCTLR
Kojto 106:ba1f97679dad 335
Kojto 106:ba1f97679dad 336 This function returns the value of the System Control Register.
Kojto 106:ba1f97679dad 337
Kojto 106:ba1f97679dad 338 \return System Control Register value
Kojto 106:ba1f97679dad 339 */
Kojto 106:ba1f97679dad 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 106:ba1f97679dad 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 342 return(__regSCTLR);
Kojto 106:ba1f97679dad 343 }
Kojto 106:ba1f97679dad 344
Kojto 106:ba1f97679dad 345 /** \brief Enable Caches
Kojto 106:ba1f97679dad 346
Kojto 106:ba1f97679dad 347 Enable Caches
Kojto 106:ba1f97679dad 348 */
Kojto 106:ba1f97679dad 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 106:ba1f97679dad 350 // Set I bit 12 to enable I Cache
Kojto 106:ba1f97679dad 351 // Set C bit 2 to enable D Cache
Kojto 106:ba1f97679dad 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 106:ba1f97679dad 353 }
Kojto 106:ba1f97679dad 354
Kojto 106:ba1f97679dad 355 /** \brief Disable Caches
Kojto 106:ba1f97679dad 356
Kojto 106:ba1f97679dad 357 Disable Caches
Kojto 106:ba1f97679dad 358 */
Kojto 106:ba1f97679dad 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 106:ba1f97679dad 360 // Clear I bit 12 to disable I Cache
Kojto 106:ba1f97679dad 361 // Clear C bit 2 to disable D Cache
Kojto 106:ba1f97679dad 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 106:ba1f97679dad 363 __ISB();
Kojto 106:ba1f97679dad 364 }
Kojto 106:ba1f97679dad 365
Kojto 106:ba1f97679dad 366 /** \brief Enable BTAC
Kojto 106:ba1f97679dad 367
Kojto 106:ba1f97679dad 368 Enable BTAC
Kojto 106:ba1f97679dad 369 */
Kojto 106:ba1f97679dad 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 106:ba1f97679dad 371 // Set Z bit 11 to enable branch prediction
Kojto 106:ba1f97679dad 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 106:ba1f97679dad 373 __ISB();
Kojto 106:ba1f97679dad 374 }
Kojto 106:ba1f97679dad 375
Kojto 106:ba1f97679dad 376 /** \brief Disable BTAC
Kojto 106:ba1f97679dad 377
Kojto 106:ba1f97679dad 378 Disable BTAC
Kojto 106:ba1f97679dad 379 */
Kojto 106:ba1f97679dad 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 106:ba1f97679dad 381 // Clear Z bit 11 to disable branch prediction
Kojto 106:ba1f97679dad 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 106:ba1f97679dad 383 }
Kojto 106:ba1f97679dad 384
Kojto 106:ba1f97679dad 385
Kojto 106:ba1f97679dad 386 /** \brief Enable MMU
Kojto 106:ba1f97679dad 387
Kojto 106:ba1f97679dad 388 Enable MMU
Kojto 106:ba1f97679dad 389 */
Kojto 106:ba1f97679dad 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 106:ba1f97679dad 391 // Set M bit 0 to enable the MMU
Kojto 106:ba1f97679dad 392 // Set AFE bit to enable simplified access permissions model
Kojto 106:ba1f97679dad 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 106:ba1f97679dad 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 106:ba1f97679dad 395 __ISB();
Kojto 106:ba1f97679dad 396 }
Kojto 106:ba1f97679dad 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 106:ba1f97679dad 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 106:ba1f97679dad 401 */
Kojto 106:ba1f97679dad 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 106:ba1f97679dad 403 // Clear M bit 0 to disable the MMU
Kojto 106:ba1f97679dad 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 106:ba1f97679dad 405 __ISB();
Kojto 106:ba1f97679dad 406 }
Kojto 106:ba1f97679dad 407
Kojto 106:ba1f97679dad 408 /******************************** TLB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 409 /** \brief Invalidate the whole tlb
Kojto 106:ba1f97679dad 410
Kojto 106:ba1f97679dad 411 TLBIALL. Invalidate the whole tlb
Kojto 106:ba1f97679dad 412 */
Kojto 106:ba1f97679dad 413
Kojto 106:ba1f97679dad 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 106:ba1f97679dad 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 106:ba1f97679dad 416 __TLBIALL = 0;
Kojto 106:ba1f97679dad 417 __DSB();
Kojto 106:ba1f97679dad 418 __ISB();
Kojto 106:ba1f97679dad 419 }
Kojto 106:ba1f97679dad 420
Kojto 106:ba1f97679dad 421 /******************************** BTB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 422 /** \brief Invalidate entire branch predictor array
Kojto 106:ba1f97679dad 423
Kojto 106:ba1f97679dad 424 BPIALL. Branch Predictor Invalidate All.
Kojto 106:ba1f97679dad 425 */
Kojto 106:ba1f97679dad 426
Kojto 106:ba1f97679dad 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 106:ba1f97679dad 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 106:ba1f97679dad 429 __BPIALL = 0;
Kojto 106:ba1f97679dad 430 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 106:ba1f97679dad 432 }
Kojto 106:ba1f97679dad 433
Kojto 106:ba1f97679dad 434
Kojto 106:ba1f97679dad 435 /******************************** L1 cache operations ******************************************************/
Kojto 106:ba1f97679dad 436
Kojto 106:ba1f97679dad 437 /** \brief Invalidate the whole I$
Kojto 106:ba1f97679dad 438
Kojto 106:ba1f97679dad 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 106:ba1f97679dad 440 */
Kojto 106:ba1f97679dad 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 106:ba1f97679dad 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 106:ba1f97679dad 443 __ICIALLU = 0;
Kojto 106:ba1f97679dad 444 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 106:ba1f97679dad 446 }
Kojto 106:ba1f97679dad 447
Kojto 106:ba1f97679dad 448 /** \brief Clean D$ by MVA
Kojto 106:ba1f97679dad 449
Kojto 106:ba1f97679dad 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 106:ba1f97679dad 451 */
Kojto 106:ba1f97679dad 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 106:ba1f97679dad 454 __DCCMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 456 }
Kojto 106:ba1f97679dad 457
Kojto 106:ba1f97679dad 458 /** \brief Invalidate D$ by MVA
Kojto 106:ba1f97679dad 459
Kojto 106:ba1f97679dad 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 106:ba1f97679dad 461 */
Kojto 106:ba1f97679dad 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 106:ba1f97679dad 464 __DCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 466 }
Kojto 106:ba1f97679dad 467
Kojto 106:ba1f97679dad 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 106:ba1f97679dad 469
Kojto 106:ba1f97679dad 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 106:ba1f97679dad 471 */
Kojto 106:ba1f97679dad 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 106:ba1f97679dad 474 __DCCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 476 }
Kojto 106:ba1f97679dad 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 106:ba1f97679dad 481 */
Kojto 106:ba1f97679dad 482 #pragma push
Kojto 106:ba1f97679dad 483 #pragma arm
Kojto 106:ba1f97679dad 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 106:ba1f97679dad 485 ARM
Kojto 106:ba1f97679dad 486
Kojto 106:ba1f97679dad 487 PUSH {R4-R11}
Kojto 106:ba1f97679dad 488
Kojto 106:ba1f97679dad 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 106:ba1f97679dad 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 106:ba1f97679dad 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 106:ba1f97679dad 492 BEQ Finished // If 0, no need to clean
Kojto 106:ba1f97679dad 493
Kojto 106:ba1f97679dad 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 106:ba1f97679dad 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 106:ba1f97679dad 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 106:ba1f97679dad 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 106:ba1f97679dad 498 CMP R1, #2
Kojto 106:ba1f97679dad 499 BLT Skip // No cache or only instruction cache at this level
Kojto 106:ba1f97679dad 500
Kojto 106:ba1f97679dad 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 106:ba1f97679dad 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 106:ba1f97679dad 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 106:ba1f97679dad 504 AND R2, R1, #7 // Extract the line length field
Kojto 106:ba1f97679dad 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 106:ba1f97679dad 506 LDR R4, =0x3FF
Kojto 106:ba1f97679dad 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 106:ba1f97679dad 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 106:ba1f97679dad 509 LDR R7, =0x7FFF
Kojto 106:ba1f97679dad 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 106:ba1f97679dad 511
Kojto 106:ba1f97679dad 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 106:ba1f97679dad 513
Kojto 106:ba1f97679dad 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 106:ba1f97679dad 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 106:ba1f97679dad 516 CMP R0, #0
Kojto 106:ba1f97679dad 517 BNE Dccsw
Kojto 106:ba1f97679dad 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 106:ba1f97679dad 519 B cont
Kojto 106:ba1f97679dad 520 Dccsw CMP R0, #1
Kojto 106:ba1f97679dad 521 BNE Dccisw
Kojto 106:ba1f97679dad 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 106:ba1f97679dad 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 106:ba1f97679dad 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 106:ba1f97679dad 526 BGE Loop3
Kojto 106:ba1f97679dad 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 106:ba1f97679dad 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 106:ba1f97679dad 530 CMP R3, R10
Kojto 106:ba1f97679dad 531 BGT Loop1
Kojto 106:ba1f97679dad 532
Kojto 106:ba1f97679dad 533 Finished
Kojto 106:ba1f97679dad 534 DSB
Kojto 106:ba1f97679dad 535 POP {R4-R11}
Kojto 106:ba1f97679dad 536 BX lr
Kojto 106:ba1f97679dad 537
Kojto 106:ba1f97679dad 538 }
Kojto 106:ba1f97679dad 539 #pragma pop
Kojto 106:ba1f97679dad 540
Kojto 106:ba1f97679dad 541
Kojto 106:ba1f97679dad 542 /** \brief Invalidate the whole D$
Kojto 106:ba1f97679dad 543
Kojto 106:ba1f97679dad 544 DCISW. Invalidate by Set/Way
Kojto 106:ba1f97679dad 545 */
Kojto 106:ba1f97679dad 546
Kojto 106:ba1f97679dad 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 548 __v7_all_cache(0);
Kojto 106:ba1f97679dad 549 }
Kojto 106:ba1f97679dad 550
Kojto 106:ba1f97679dad 551 /** \brief Clean the whole D$
Kojto 106:ba1f97679dad 552
Kojto 106:ba1f97679dad 553 DCCSW. Clean by Set/Way
Kojto 106:ba1f97679dad 554 */
Kojto 106:ba1f97679dad 555
Kojto 106:ba1f97679dad 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 106:ba1f97679dad 557 __v7_all_cache(1);
Kojto 106:ba1f97679dad 558 }
Kojto 106:ba1f97679dad 559
Kojto 106:ba1f97679dad 560 /** \brief Clean and invalidate the whole D$
Kojto 106:ba1f97679dad 561
Kojto 106:ba1f97679dad 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 106:ba1f97679dad 563 */
Kojto 106:ba1f97679dad 564
Kojto 106:ba1f97679dad 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 566 __v7_all_cache(2);
Kojto 106:ba1f97679dad 567 }
Kojto 106:ba1f97679dad 568
Kojto 106:ba1f97679dad 569 #include "core_ca_mmu.h"
Kojto 106:ba1f97679dad 570
Kojto 106:ba1f97679dad 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 106:ba1f97679dad 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
Kojto 115:87f2f5183dfb 814 #include "core_ca_mmu.h"
Kojto 106:ba1f97679dad 815
Kojto 106:ba1f97679dad 816 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 106:ba1f97679dad 817 /* GNU gcc specific functions */
Kojto 106:ba1f97679dad 818
Kojto 106:ba1f97679dad 819 #define MODE_USR 0x10
Kojto 106:ba1f97679dad 820 #define MODE_FIQ 0x11
Kojto 106:ba1f97679dad 821 #define MODE_IRQ 0x12
Kojto 106:ba1f97679dad 822 #define MODE_SVC 0x13
Kojto 106:ba1f97679dad 823 #define MODE_MON 0x16
Kojto 106:ba1f97679dad 824 #define MODE_ABT 0x17
Kojto 106:ba1f97679dad 825 #define MODE_HYP 0x1A
Kojto 106:ba1f97679dad 826 #define MODE_UND 0x1B
Kojto 106:ba1f97679dad 827 #define MODE_SYS 0x1F
Kojto 106:ba1f97679dad 828
Kojto 106:ba1f97679dad 829
Kojto 106:ba1f97679dad 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 106:ba1f97679dad 831 {
Kojto 106:ba1f97679dad 832 __ASM volatile ("cpsie i");
Kojto 106:ba1f97679dad 833 }
Kojto 106:ba1f97679dad 834
Kojto 106:ba1f97679dad 835 /** \brief Disable IRQ Interrupts
Kojto 106:ba1f97679dad 836
Kojto 106:ba1f97679dad 837 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 106:ba1f97679dad 838 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 839 */
Kojto 106:ba1f97679dad 840 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 106:ba1f97679dad 841 {
Kojto 106:ba1f97679dad 842 uint32_t result;
Kojto 106:ba1f97679dad 843
Kojto 106:ba1f97679dad 844 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 106:ba1f97679dad 845 __ASM volatile ("cpsid i");
Kojto 106:ba1f97679dad 846 return(result & 0x80);
Kojto 106:ba1f97679dad 847 }
Kojto 106:ba1f97679dad 848
Kojto 106:ba1f97679dad 849
Kojto 106:ba1f97679dad 850 /** \brief Get APSR Register
Kojto 106:ba1f97679dad 851
Kojto 106:ba1f97679dad 852 This function returns the content of the APSR Register.
Kojto 106:ba1f97679dad 853
Kojto 106:ba1f97679dad 854 \return APSR Register value
Kojto 106:ba1f97679dad 855 */
Kojto 106:ba1f97679dad 856 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 106:ba1f97679dad 857 {
Kojto 106:ba1f97679dad 858 #if 1
Kojto 108:34e6b704fe68 859 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 860 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 106:ba1f97679dad 861 #else
Kojto 106:ba1f97679dad 862 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 863 #endif
Kojto 106:ba1f97679dad 864 return(__regAPSR);
Kojto 106:ba1f97679dad 865 }
Kojto 106:ba1f97679dad 866
Kojto 106:ba1f97679dad 867
Kojto 106:ba1f97679dad 868 /** \brief Get CPSR Register
Kojto 106:ba1f97679dad 869
Kojto 106:ba1f97679dad 870 This function returns the content of the CPSR Register.
Kojto 106:ba1f97679dad 871
Kojto 106:ba1f97679dad 872 \return CPSR Register value
Kojto 106:ba1f97679dad 873 */
Kojto 106:ba1f97679dad 874 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 106:ba1f97679dad 875 {
Kojto 106:ba1f97679dad 876 #if 1
Kojto 106:ba1f97679dad 877 register uint32_t __regCPSR;
Kojto 106:ba1f97679dad 878 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 106:ba1f97679dad 879 #else
Kojto 106:ba1f97679dad 880 register uint32_t __regCPSR __ASM("cpsr");
Kojto 106:ba1f97679dad 881 #endif
Kojto 106:ba1f97679dad 882 return(__regCPSR);
Kojto 106:ba1f97679dad 883 }
Kojto 106:ba1f97679dad 884
Kojto 106:ba1f97679dad 885 #if 0
Kojto 106:ba1f97679dad 886 /** \brief Set Stack Pointer
Kojto 106:ba1f97679dad 887
Kojto 106:ba1f97679dad 888 This function assigns the given value to the current stack pointer.
Kojto 106:ba1f97679dad 889
Kojto 106:ba1f97679dad 890 \param [in] topOfStack Stack Pointer value to set
Kojto 106:ba1f97679dad 891 */
Kojto 106:ba1f97679dad 892 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 106:ba1f97679dad 893 {
Kojto 106:ba1f97679dad 894 register uint32_t __regSP __ASM("sp");
Kojto 106:ba1f97679dad 895 __regSP = topOfStack;
Kojto 106:ba1f97679dad 896 }
Kojto 106:ba1f97679dad 897 #endif
Kojto 106:ba1f97679dad 898
Kojto 106:ba1f97679dad 899 /** \brief Get link register
Kojto 106:ba1f97679dad 900
Kojto 106:ba1f97679dad 901 This function returns the value of the link register
Kojto 106:ba1f97679dad 902
Kojto 106:ba1f97679dad 903 \return Value of link register
Kojto 106:ba1f97679dad 904 */
Kojto 106:ba1f97679dad 905 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 106:ba1f97679dad 906 {
Kojto 106:ba1f97679dad 907 register uint32_t __reglr __ASM("lr");
Kojto 106:ba1f97679dad 908 return(__reglr);
Kojto 106:ba1f97679dad 909 }
Kojto 106:ba1f97679dad 910
Kojto 106:ba1f97679dad 911 #if 0
Kojto 106:ba1f97679dad 912 /** \brief Set link register
Kojto 106:ba1f97679dad 913
Kojto 106:ba1f97679dad 914 This function sets the value of the link register
Kojto 106:ba1f97679dad 915
Kojto 106:ba1f97679dad 916 \param [in] lr LR value to set
Kojto 106:ba1f97679dad 917 */
Kojto 106:ba1f97679dad 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 106:ba1f97679dad 919 {
Kojto 106:ba1f97679dad 920 register uint32_t __reglr __ASM("lr");
Kojto 106:ba1f97679dad 921 __reglr = lr;
Kojto 106:ba1f97679dad 922 }
Kojto 106:ba1f97679dad 923 #endif
Kojto 106:ba1f97679dad 924
Kojto 106:ba1f97679dad 925 /** \brief Set Process Stack Pointer
Kojto 106:ba1f97679dad 926
Kojto 106:ba1f97679dad 927 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 106:ba1f97679dad 928
Kojto 106:ba1f97679dad 929 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 106:ba1f97679dad 930 */
Kojto 108:34e6b704fe68 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 932 {
Kojto 108:34e6b704fe68 933 __asm__ volatile (
Kojto 108:34e6b704fe68 934 ".ARM;"
Kojto 108:34e6b704fe68 935 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 936
Kojto 108:34e6b704fe68 937 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 938 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 939 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 940 "MOV SP, R0;"
Kojto 108:34e6b704fe68 941 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 942 "ISB;"
Kojto 108:34e6b704fe68 943 //"BX LR;"
Kojto 108:34e6b704fe68 944 :
Kojto 108:34e6b704fe68 945 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 946 : "r0", "r1");
Kojto 108:34e6b704fe68 947 return;
Kojto 108:34e6b704fe68 948 }
Kojto 106:ba1f97679dad 949
Kojto 106:ba1f97679dad 950 /** \brief Set User Mode
Kojto 106:ba1f97679dad 951
Kojto 106:ba1f97679dad 952 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 953 */
Kojto 108:34e6b704fe68 954 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 955 {
Kojto 108:34e6b704fe68 956 __asm__ volatile (
Kojto 108:34e6b704fe68 957 ".ARM;"
Kojto 106:ba1f97679dad 958
Kojto 108:34e6b704fe68 959 "CPS %0;"
Kojto 108:34e6b704fe68 960 //"BX LR;"
Kojto 108:34e6b704fe68 961 :
Kojto 108:34e6b704fe68 962 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 963 : );
Kojto 108:34e6b704fe68 964 return;
Kojto 108:34e6b704fe68 965 }
Kojto 108:34e6b704fe68 966
Kojto 106:ba1f97679dad 967
Kojto 106:ba1f97679dad 968 /** \brief Enable FIQ
Kojto 106:ba1f97679dad 969
Kojto 106:ba1f97679dad 970 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 106:ba1f97679dad 971 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 972 */
Kojto 108:34e6b704fe68 973 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 106:ba1f97679dad 974
Kojto 106:ba1f97679dad 975
Kojto 106:ba1f97679dad 976 /** \brief Disable FIQ
Kojto 106:ba1f97679dad 977
Kojto 106:ba1f97679dad 978 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 106:ba1f97679dad 979 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 980 */
Kojto 108:34e6b704fe68 981 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 106:ba1f97679dad 982
Kojto 106:ba1f97679dad 983
Kojto 106:ba1f97679dad 984 /** \brief Get FPSCR
Kojto 106:ba1f97679dad 985
Kojto 106:ba1f97679dad 986 This function returns the current value of the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 987
Kojto 106:ba1f97679dad 988 \return Floating Point Status/Control register value
Kojto 106:ba1f97679dad 989 */
Kojto 106:ba1f97679dad 990 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 106:ba1f97679dad 991 {
Kojto 106:ba1f97679dad 992 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 993 #if 1
Kojto 106:ba1f97679dad 994 uint32_t result;
Kojto 106:ba1f97679dad 995
Kojto 106:ba1f97679dad 996 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 106:ba1f97679dad 997 return (result);
Kojto 106:ba1f97679dad 998 #else
Kojto 106:ba1f97679dad 999 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 1000 return(__regfpscr);
Kojto 106:ba1f97679dad 1001 #endif
Kojto 106:ba1f97679dad 1002 #else
Kojto 106:ba1f97679dad 1003 return(0);
Kojto 106:ba1f97679dad 1004 #endif
Kojto 106:ba1f97679dad 1005 }
Kojto 106:ba1f97679dad 1006
Kojto 106:ba1f97679dad 1007
Kojto 106:ba1f97679dad 1008 /** \brief Set FPSCR
Kojto 106:ba1f97679dad 1009
Kojto 106:ba1f97679dad 1010 This function assigns the given value to the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 1011
Kojto 106:ba1f97679dad 1012 \param [in] fpscr Floating Point Status/Control value to set
Kojto 106:ba1f97679dad 1013 */
Kojto 106:ba1f97679dad 1014 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 106:ba1f97679dad 1015 {
Kojto 106:ba1f97679dad 1016 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 1017 #if 1
Kojto 106:ba1f97679dad 1018 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 106:ba1f97679dad 1019 #else
Kojto 106:ba1f97679dad 1020 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 1021 __regfpscr = (fpscr);
Kojto 106:ba1f97679dad 1022 #endif
Kojto 106:ba1f97679dad 1023 #endif
Kojto 106:ba1f97679dad 1024 }
Kojto 106:ba1f97679dad 1025
Kojto 106:ba1f97679dad 1026 /** \brief Get FPEXC
Kojto 106:ba1f97679dad 1027
Kojto 106:ba1f97679dad 1028 This function returns the current value of the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 1029
Kojto 106:ba1f97679dad 1030 \return Floating Point Exception Control register value
Kojto 106:ba1f97679dad 1031 */
Kojto 106:ba1f97679dad 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 106:ba1f97679dad 1033 {
Kojto 106:ba1f97679dad 1034 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 1035 #if 1
Kojto 106:ba1f97679dad 1036 uint32_t result;
Kojto 106:ba1f97679dad 1037
Kojto 106:ba1f97679dad 1038 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 106:ba1f97679dad 1039 return (result);
Kojto 106:ba1f97679dad 1040 #else
Kojto 106:ba1f97679dad 1041 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 1042 return(__regfpexc);
Kojto 106:ba1f97679dad 1043 #endif
Kojto 106:ba1f97679dad 1044 #else
Kojto 106:ba1f97679dad 1045 return(0);
Kojto 106:ba1f97679dad 1046 #endif
Kojto 106:ba1f97679dad 1047 }
Kojto 106:ba1f97679dad 1048
Kojto 106:ba1f97679dad 1049
Kojto 106:ba1f97679dad 1050 /** \brief Set FPEXC
Kojto 106:ba1f97679dad 1051
Kojto 106:ba1f97679dad 1052 This function assigns the given value to the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 1053
Kojto 106:ba1f97679dad 1054 \param [in] fpscr Floating Point Exception Control value to set
Kojto 106:ba1f97679dad 1055 */
Kojto 106:ba1f97679dad 1056 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 106:ba1f97679dad 1057 {
Kojto 106:ba1f97679dad 1058 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 1059 #if 1
Kojto 106:ba1f97679dad 1060 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 106:ba1f97679dad 1061 #else
Kojto 106:ba1f97679dad 1062 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 1063 __regfpexc = (fpexc);
Kojto 106:ba1f97679dad 1064 #endif
Kojto 106:ba1f97679dad 1065 #endif
Kojto 106:ba1f97679dad 1066 }
Kojto 106:ba1f97679dad 1067
Kojto 106:ba1f97679dad 1068 /** \brief Get CPACR
Kojto 106:ba1f97679dad 1069
Kojto 106:ba1f97679dad 1070 This function returns the current value of the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 1071
Kojto 106:ba1f97679dad 1072 \return Coprocessor Access Control register value
Kojto 106:ba1f97679dad 1073 */
Kojto 106:ba1f97679dad 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 106:ba1f97679dad 1075 {
Kojto 106:ba1f97679dad 1076 #if 1
Kojto 106:ba1f97679dad 1077 register uint32_t __regCPACR;
Kojto 106:ba1f97679dad 1078 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 106:ba1f97679dad 1079 #else
Kojto 106:ba1f97679dad 1080 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 1081 #endif
Kojto 106:ba1f97679dad 1082 return __regCPACR;
Kojto 106:ba1f97679dad 1083 }
Kojto 106:ba1f97679dad 1084
Kojto 106:ba1f97679dad 1085 /** \brief Set CPACR
Kojto 106:ba1f97679dad 1086
Kojto 106:ba1f97679dad 1087 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 1088
Kojto 108:34e6b704fe68 1089 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 106:ba1f97679dad 1090 */
Kojto 106:ba1f97679dad 1091 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 106:ba1f97679dad 1092 {
Kojto 106:ba1f97679dad 1093 #if 1
Kojto 106:ba1f97679dad 1094 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 106:ba1f97679dad 1095 #else
Kojto 106:ba1f97679dad 1096 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 1097 __regCPACR = cpacr;
Kojto 106:ba1f97679dad 1098 #endif
Kojto 106:ba1f97679dad 1099 __ISB();
Kojto 106:ba1f97679dad 1100 }
Kojto 106:ba1f97679dad 1101
Kojto 106:ba1f97679dad 1102 /** \brief Get CBAR
Kojto 106:ba1f97679dad 1103
Kojto 106:ba1f97679dad 1104 This function returns the value of the Configuration Base Address register.
Kojto 106:ba1f97679dad 1105
Kojto 106:ba1f97679dad 1106 \return Configuration Base Address register value
Kojto 106:ba1f97679dad 1107 */
Kojto 106:ba1f97679dad 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 106:ba1f97679dad 1109 #if 1
Kojto 106:ba1f97679dad 1110 register uint32_t __regCBAR;
Kojto 106:ba1f97679dad 1111 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 106:ba1f97679dad 1112 #else
Kojto 106:ba1f97679dad 1113 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 106:ba1f97679dad 1114 #endif
Kojto 106:ba1f97679dad 1115 return(__regCBAR);
Kojto 106:ba1f97679dad 1116 }
Kojto 106:ba1f97679dad 1117
Kojto 106:ba1f97679dad 1118 /** \brief Get TTBR0
Kojto 106:ba1f97679dad 1119
Kojto 108:34e6b704fe68 1120 This function returns the value of the Translation Table Base Register 0.
Kojto 106:ba1f97679dad 1121
Kojto 106:ba1f97679dad 1122 \return Translation Table Base Register 0 value
Kojto 106:ba1f97679dad 1123 */
Kojto 106:ba1f97679dad 1124 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 106:ba1f97679dad 1125 #if 1
Kojto 106:ba1f97679dad 1126 register uint32_t __regTTBR0;
Kojto 106:ba1f97679dad 1127 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 106:ba1f97679dad 1128 #else
Kojto 106:ba1f97679dad 1129 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 1130 #endif
Kojto 106:ba1f97679dad 1131 return(__regTTBR0);
Kojto 106:ba1f97679dad 1132 }
Kojto 106:ba1f97679dad 1133
Kojto 106:ba1f97679dad 1134 /** \brief Set TTBR0
Kojto 106:ba1f97679dad 1135
Kojto 108:34e6b704fe68 1136 This function assigns the given value to the Translation Table Base Register 0.
Kojto 106:ba1f97679dad 1137
Kojto 106:ba1f97679dad 1138 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 106:ba1f97679dad 1139 */
Kojto 106:ba1f97679dad 1140 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 106:ba1f97679dad 1141 #if 1
Kojto 106:ba1f97679dad 1142 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 106:ba1f97679dad 1143 #else
Kojto 106:ba1f97679dad 1144 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 1145 __regTTBR0 = ttbr0;
Kojto 106:ba1f97679dad 1146 #endif
Kojto 106:ba1f97679dad 1147 __ISB();
Kojto 106:ba1f97679dad 1148 }
Kojto 106:ba1f97679dad 1149
Kojto 106:ba1f97679dad 1150 /** \brief Get DACR
Kojto 106:ba1f97679dad 1151
Kojto 106:ba1f97679dad 1152 This function returns the value of the Domain Access Control Register.
Kojto 106:ba1f97679dad 1153
Kojto 106:ba1f97679dad 1154 \return Domain Access Control Register value
Kojto 106:ba1f97679dad 1155 */
Kojto 106:ba1f97679dad 1156 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 106:ba1f97679dad 1157 #if 1
Kojto 106:ba1f97679dad 1158 register uint32_t __regDACR;
Kojto 106:ba1f97679dad 1159 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 106:ba1f97679dad 1160 #else
Kojto 106:ba1f97679dad 1161 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 1162 #endif
Kojto 106:ba1f97679dad 1163 return(__regDACR);
Kojto 106:ba1f97679dad 1164 }
Kojto 106:ba1f97679dad 1165
Kojto 106:ba1f97679dad 1166 /** \brief Set DACR
Kojto 106:ba1f97679dad 1167
Kojto 108:34e6b704fe68 1168 This function assigns the given value to the Domain Access Control Register.
Kojto 106:ba1f97679dad 1169
Kojto 106:ba1f97679dad 1170 \param [in] dacr Domain Access Control Register value to set
Kojto 106:ba1f97679dad 1171 */
Kojto 106:ba1f97679dad 1172 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 106:ba1f97679dad 1173 #if 1
Kojto 106:ba1f97679dad 1174 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 106:ba1f97679dad 1175 #else
Kojto 106:ba1f97679dad 1176 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 1177 __regDACR = dacr;
Kojto 106:ba1f97679dad 1178 #endif
Kojto 106:ba1f97679dad 1179 __ISB();
Kojto 106:ba1f97679dad 1180 }
Kojto 106:ba1f97679dad 1181
Kojto 106:ba1f97679dad 1182 /******************************** Cache and BTAC enable ****************************************************/
Kojto 106:ba1f97679dad 1183
Kojto 106:ba1f97679dad 1184 /** \brief Set SCTLR
Kojto 106:ba1f97679dad 1185
Kojto 106:ba1f97679dad 1186 This function assigns the given value to the System Control Register.
Kojto 106:ba1f97679dad 1187
Kojto 108:34e6b704fe68 1188 \param [in] sctlr System Control Register value to set
Kojto 106:ba1f97679dad 1189 */
Kojto 106:ba1f97679dad 1190 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 106:ba1f97679dad 1191 {
Kojto 106:ba1f97679dad 1192 #if 1
Kojto 106:ba1f97679dad 1193 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 106:ba1f97679dad 1194 #else
Kojto 106:ba1f97679dad 1195 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 1196 __regSCTLR = sctlr;
Kojto 106:ba1f97679dad 1197 #endif
Kojto 106:ba1f97679dad 1198 }
Kojto 106:ba1f97679dad 1199
Kojto 106:ba1f97679dad 1200 /** \brief Get SCTLR
Kojto 106:ba1f97679dad 1201
Kojto 106:ba1f97679dad 1202 This function returns the value of the System Control Register.
Kojto 106:ba1f97679dad 1203
Kojto 106:ba1f97679dad 1204 \return System Control Register value
Kojto 106:ba1f97679dad 1205 */
Kojto 106:ba1f97679dad 1206 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 106:ba1f97679dad 1207 #if 1
Kojto 106:ba1f97679dad 1208 register uint32_t __regSCTLR;
Kojto 106:ba1f97679dad 1209 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 106:ba1f97679dad 1210 #else
Kojto 106:ba1f97679dad 1211 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 1212 #endif
Kojto 106:ba1f97679dad 1213 return(__regSCTLR);
Kojto 106:ba1f97679dad 1214 }
Kojto 106:ba1f97679dad 1215
Kojto 106:ba1f97679dad 1216 /** \brief Enable Caches
Kojto 106:ba1f97679dad 1217
Kojto 106:ba1f97679dad 1218 Enable Caches
Kojto 106:ba1f97679dad 1219 */
Kojto 106:ba1f97679dad 1220 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 106:ba1f97679dad 1221 // Set I bit 12 to enable I Cache
Kojto 106:ba1f97679dad 1222 // Set C bit 2 to enable D Cache
Kojto 106:ba1f97679dad 1223 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 106:ba1f97679dad 1224 }
Kojto 106:ba1f97679dad 1225
Kojto 106:ba1f97679dad 1226 /** \brief Disable Caches
Kojto 106:ba1f97679dad 1227
Kojto 106:ba1f97679dad 1228 Disable Caches
Kojto 106:ba1f97679dad 1229 */
Kojto 106:ba1f97679dad 1230 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 106:ba1f97679dad 1231 // Clear I bit 12 to disable I Cache
Kojto 106:ba1f97679dad 1232 // Clear C bit 2 to disable D Cache
Kojto 106:ba1f97679dad 1233 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 106:ba1f97679dad 1234 __ISB();
Kojto 106:ba1f97679dad 1235 }
Kojto 106:ba1f97679dad 1236
Kojto 106:ba1f97679dad 1237 /** \brief Enable BTAC
Kojto 106:ba1f97679dad 1238
Kojto 106:ba1f97679dad 1239 Enable BTAC
Kojto 106:ba1f97679dad 1240 */
Kojto 106:ba1f97679dad 1241 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 106:ba1f97679dad 1242 // Set Z bit 11 to enable branch prediction
Kojto 106:ba1f97679dad 1243 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 106:ba1f97679dad 1244 __ISB();
Kojto 106:ba1f97679dad 1245 }
Kojto 106:ba1f97679dad 1246
Kojto 106:ba1f97679dad 1247 /** \brief Disable BTAC
Kojto 106:ba1f97679dad 1248
Kojto 106:ba1f97679dad 1249 Disable BTAC
Kojto 106:ba1f97679dad 1250 */
Kojto 106:ba1f97679dad 1251 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 106:ba1f97679dad 1252 // Clear Z bit 11 to disable branch prediction
Kojto 106:ba1f97679dad 1253 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 106:ba1f97679dad 1254 }
Kojto 106:ba1f97679dad 1255
Kojto 106:ba1f97679dad 1256
Kojto 106:ba1f97679dad 1257 /** \brief Enable MMU
Kojto 106:ba1f97679dad 1258
Kojto 106:ba1f97679dad 1259 Enable MMU
Kojto 106:ba1f97679dad 1260 */
Kojto 106:ba1f97679dad 1261 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 106:ba1f97679dad 1262 // Set M bit 0 to enable the MMU
Kojto 106:ba1f97679dad 1263 // Set AFE bit to enable simplified access permissions model
Kojto 106:ba1f97679dad 1264 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 106:ba1f97679dad 1265 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 106:ba1f97679dad 1266 __ISB();
Kojto 106:ba1f97679dad 1267 }
Kojto 106:ba1f97679dad 1268
Kojto 108:34e6b704fe68 1269 /** \brief Disable MMU
Kojto 106:ba1f97679dad 1270
Kojto 108:34e6b704fe68 1271 Disable MMU
Kojto 106:ba1f97679dad 1272 */
Kojto 106:ba1f97679dad 1273 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 106:ba1f97679dad 1274 // Clear M bit 0 to disable the MMU
Kojto 106:ba1f97679dad 1275 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 106:ba1f97679dad 1276 __ISB();
Kojto 106:ba1f97679dad 1277 }
Kojto 106:ba1f97679dad 1278
Kojto 106:ba1f97679dad 1279 /******************************** TLB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 1280 /** \brief Invalidate the whole tlb
Kojto 106:ba1f97679dad 1281
Kojto 106:ba1f97679dad 1282 TLBIALL. Invalidate the whole tlb
Kojto 106:ba1f97679dad 1283 */
Kojto 106:ba1f97679dad 1284
Kojto 106:ba1f97679dad 1285 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 106:ba1f97679dad 1286 #if 1
Kojto 106:ba1f97679dad 1287 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 106:ba1f97679dad 1288 #else
Kojto 106:ba1f97679dad 1289 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 106:ba1f97679dad 1290 __TLBIALL = 0;
Kojto 106:ba1f97679dad 1291 #endif
Kojto 106:ba1f97679dad 1292 __DSB();
Kojto 106:ba1f97679dad 1293 __ISB();
Kojto 106:ba1f97679dad 1294 }
Kojto 106:ba1f97679dad 1295
Kojto 106:ba1f97679dad 1296 /******************************** BTB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 1297 /** \brief Invalidate entire branch predictor array
Kojto 106:ba1f97679dad 1298
Kojto 106:ba1f97679dad 1299 BPIALL. Branch Predictor Invalidate All.
Kojto 106:ba1f97679dad 1300 */
Kojto 106:ba1f97679dad 1301
Kojto 106:ba1f97679dad 1302 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 106:ba1f97679dad 1303 #if 1
Kojto 106:ba1f97679dad 1304 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 106:ba1f97679dad 1305 #else
Kojto 106:ba1f97679dad 1306 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 106:ba1f97679dad 1307 __BPIALL = 0;
Kojto 106:ba1f97679dad 1308 #endif
Kojto 106:ba1f97679dad 1309 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 1310 __ISB(); //ensure instruction fetch path sees new state
Kojto 106:ba1f97679dad 1311 }
Kojto 106:ba1f97679dad 1312
Kojto 106:ba1f97679dad 1313
Kojto 106:ba1f97679dad 1314 /******************************** L1 cache operations ******************************************************/
Kojto 106:ba1f97679dad 1315
Kojto 106:ba1f97679dad 1316 /** \brief Invalidate the whole I$
Kojto 106:ba1f97679dad 1317
Kojto 106:ba1f97679dad 1318 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 106:ba1f97679dad 1319 */
Kojto 106:ba1f97679dad 1320 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 106:ba1f97679dad 1321 #if 1
Kojto 106:ba1f97679dad 1322 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 106:ba1f97679dad 1323 #else
Kojto 106:ba1f97679dad 1324 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 106:ba1f97679dad 1325 __ICIALLU = 0;
Kojto 106:ba1f97679dad 1326 #endif
Kojto 106:ba1f97679dad 1327 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 1328 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 106:ba1f97679dad 1329 }
Kojto 106:ba1f97679dad 1330
Kojto 106:ba1f97679dad 1331 /** \brief Clean D$ by MVA
Kojto 106:ba1f97679dad 1332
Kojto 106:ba1f97679dad 1333 DCCMVAC. Data cache clean by MVA to PoC
Kojto 106:ba1f97679dad 1334 */
Kojto 106:ba1f97679dad 1335 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 1336 #if 1
Kojto 106:ba1f97679dad 1337 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 106:ba1f97679dad 1338 #else
Kojto 106:ba1f97679dad 1339 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 106:ba1f97679dad 1340 __DCCMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 1341 #endif
Kojto 106:ba1f97679dad 1342 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 1343 }
Kojto 106:ba1f97679dad 1344
Kojto 106:ba1f97679dad 1345 /** \brief Invalidate D$ by MVA
Kojto 106:ba1f97679dad 1346
Kojto 106:ba1f97679dad 1347 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 106:ba1f97679dad 1348 */
Kojto 106:ba1f97679dad 1349 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 1350 #if 1
Kojto 106:ba1f97679dad 1351 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 106:ba1f97679dad 1352 #else
Kojto 106:ba1f97679dad 1353 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 106:ba1f97679dad 1354 __DCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 1355 #endif
Kojto 106:ba1f97679dad 1356 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 1357 }
Kojto 106:ba1f97679dad 1358
Kojto 106:ba1f97679dad 1359 /** \brief Clean and Invalidate D$ by MVA
Kojto 106:ba1f97679dad 1360
Kojto 106:ba1f97679dad 1361 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 106:ba1f97679dad 1362 */
Kojto 106:ba1f97679dad 1363 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 1364 #if 1
Kojto 106:ba1f97679dad 1365 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 106:ba1f97679dad 1366 #else
Kojto 106:ba1f97679dad 1367 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 106:ba1f97679dad 1368 __DCCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 1369 #endif
Kojto 106:ba1f97679dad 1370 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 1371 }
Kojto 106:ba1f97679dad 1372
Kojto 108:34e6b704fe68 1373 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 106:ba1f97679dad 1374
Kojto 108:34e6b704fe68 1375 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 106:ba1f97679dad 1376 */
Kojto 106:ba1f97679dad 1377 extern void __v7_all_cache(uint32_t op);
Kojto 106:ba1f97679dad 1378
Kojto 106:ba1f97679dad 1379
Kojto 106:ba1f97679dad 1380 /** \brief Invalidate the whole D$
Kojto 106:ba1f97679dad 1381
Kojto 106:ba1f97679dad 1382 DCISW. Invalidate by Set/Way
Kojto 106:ba1f97679dad 1383 */
Kojto 106:ba1f97679dad 1384
Kojto 106:ba1f97679dad 1385 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 1386 __v7_all_cache(0);
Kojto 106:ba1f97679dad 1387 }
Kojto 106:ba1f97679dad 1388
Kojto 106:ba1f97679dad 1389 /** \brief Clean the whole D$
Kojto 106:ba1f97679dad 1390
Kojto 106:ba1f97679dad 1391 DCCSW. Clean by Set/Way
Kojto 106:ba1f97679dad 1392 */
Kojto 106:ba1f97679dad 1393
Kojto 106:ba1f97679dad 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 106:ba1f97679dad 1395 __v7_all_cache(1);
Kojto 106:ba1f97679dad 1396 }
Kojto 106:ba1f97679dad 1397
Kojto 106:ba1f97679dad 1398 /** \brief Clean and invalidate the whole D$
Kojto 106:ba1f97679dad 1399
Kojto 106:ba1f97679dad 1400 DCCISW. Clean and Invalidate by Set/Way
Kojto 106:ba1f97679dad 1401 */
Kojto 106:ba1f97679dad 1402
Kojto 106:ba1f97679dad 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 1404 __v7_all_cache(2);
Kojto 106:ba1f97679dad 1405 }
Kojto 106:ba1f97679dad 1406
Kojto 106:ba1f97679dad 1407 #include "core_ca_mmu.h"
Kojto 106:ba1f97679dad 1408
Kojto 106:ba1f97679dad 1409 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 106:ba1f97679dad 1410
Kojto 106:ba1f97679dad 1411 #error TASKING Compiler support not implemented for Cortex-A
Kojto 106:ba1f97679dad 1412
Kojto 106:ba1f97679dad 1413 #endif
Kojto 106:ba1f97679dad 1414
Kojto 106:ba1f97679dad 1415 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 106:ba1f97679dad 1416
Kojto 106:ba1f97679dad 1417
Kojto 106:ba1f97679dad 1418 #endif /* __CORE_CAFUNC_H__ */