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TARGET_TB_SENSE_12/core_cm0plus.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
142:4eea097334d6
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file core_cm0plus.h
Anna Bridge 142:4eea097334d6 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Anna Bridge 142:4eea097334d6 4 * @version V4.10
Anna Bridge 142:4eea097334d6 5 * @date 18. March 2015
Anna Bridge 142:4eea097334d6 6 *
Anna Bridge 142:4eea097334d6 7 * @note
Anna Bridge 142:4eea097334d6 8 *
Anna Bridge 142:4eea097334d6 9 ******************************************************************************/
Anna Bridge 142:4eea097334d6 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Anna Bridge 142:4eea097334d6 11
Anna Bridge 142:4eea097334d6 12 All rights reserved.
Anna Bridge 142:4eea097334d6 13 Redistribution and use in source and binary forms, with or without
Anna Bridge 142:4eea097334d6 14 modification, are permitted provided that the following conditions are met:
Anna Bridge 142:4eea097334d6 15 - Redistributions of source code must retain the above copyright
Anna Bridge 142:4eea097334d6 16 notice, this list of conditions and the following disclaimer.
Anna Bridge 142:4eea097334d6 17 - Redistributions in binary form must reproduce the above copyright
Anna Bridge 142:4eea097334d6 18 notice, this list of conditions and the following disclaimer in the
Anna Bridge 142:4eea097334d6 19 documentation and/or other materials provided with the distribution.
Anna Bridge 142:4eea097334d6 20 - Neither the name of ARM nor the names of its contributors may be used
Anna Bridge 142:4eea097334d6 21 to endorse or promote products derived from this software without
Anna Bridge 142:4eea097334d6 22 specific prior written permission.
Anna Bridge 142:4eea097334d6 23 *
Anna Bridge 142:4eea097334d6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Anna Bridge 142:4eea097334d6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Anna Bridge 142:4eea097334d6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Anna Bridge 142:4eea097334d6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Anna Bridge 142:4eea097334d6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Anna Bridge 142:4eea097334d6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Anna Bridge 142:4eea097334d6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Anna Bridge 142:4eea097334d6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Anna Bridge 142:4eea097334d6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Anna Bridge 142:4eea097334d6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Anna Bridge 142:4eea097334d6 34 POSSIBILITY OF SUCH DAMAGE.
Anna Bridge 142:4eea097334d6 35 ---------------------------------------------------------------------------*/
Anna Bridge 142:4eea097334d6 36
Anna Bridge 142:4eea097334d6 37
Anna Bridge 142:4eea097334d6 38 #if defined ( __ICCARM__ )
Anna Bridge 142:4eea097334d6 39 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 142:4eea097334d6 40 #endif
Anna Bridge 142:4eea097334d6 41
Anna Bridge 142:4eea097334d6 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Anna Bridge 142:4eea097334d6 43 #define __CORE_CM0PLUS_H_GENERIC
Anna Bridge 142:4eea097334d6 44
Anna Bridge 142:4eea097334d6 45 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 46 extern "C" {
Anna Bridge 142:4eea097334d6 47 #endif
Anna Bridge 142:4eea097334d6 48
Anna Bridge 142:4eea097334d6 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 142:4eea097334d6 50 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 142:4eea097334d6 51
Anna Bridge 142:4eea097334d6 52 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 142:4eea097334d6 53 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 142:4eea097334d6 54
Anna Bridge 142:4eea097334d6 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 142:4eea097334d6 56 Unions are used for effective representation of core registers.
Anna Bridge 142:4eea097334d6 57
Anna Bridge 142:4eea097334d6 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 142:4eea097334d6 59 Function-like macros are used to allow more efficient code.
Anna Bridge 142:4eea097334d6 60 */
Anna Bridge 142:4eea097334d6 61
Anna Bridge 142:4eea097334d6 62
Anna Bridge 142:4eea097334d6 63 /*******************************************************************************
Anna Bridge 142:4eea097334d6 64 * CMSIS definitions
Anna Bridge 142:4eea097334d6 65 ******************************************************************************/
Anna Bridge 142:4eea097334d6 66 /** \ingroup Cortex-M0+
Anna Bridge 142:4eea097334d6 67 @{
Anna Bridge 142:4eea097334d6 68 */
Anna Bridge 142:4eea097334d6 69
Anna Bridge 142:4eea097334d6 70 /* CMSIS CM0P definitions */
Anna Bridge 142:4eea097334d6 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Anna Bridge 142:4eea097334d6 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Anna Bridge 142:4eea097334d6 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Anna Bridge 142:4eea097334d6 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Anna Bridge 142:4eea097334d6 75
Anna Bridge 142:4eea097334d6 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Anna Bridge 142:4eea097334d6 77
Anna Bridge 142:4eea097334d6 78
Anna Bridge 142:4eea097334d6 79 #if defined ( __CC_ARM )
Anna Bridge 142:4eea097334d6 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Anna Bridge 142:4eea097334d6 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Anna Bridge 142:4eea097334d6 82 #define __STATIC_INLINE static __inline
Anna Bridge 142:4eea097334d6 83
Anna Bridge 142:4eea097334d6 84 #elif defined ( __GNUC__ )
Anna Bridge 142:4eea097334d6 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Anna Bridge 142:4eea097334d6 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Anna Bridge 142:4eea097334d6 87 #define __STATIC_INLINE static inline
Anna Bridge 142:4eea097334d6 88
Anna Bridge 142:4eea097334d6 89 #elif defined ( __ICCARM__ )
Anna Bridge 142:4eea097334d6 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Anna Bridge 142:4eea097334d6 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Anna Bridge 142:4eea097334d6 92 #define __STATIC_INLINE static inline
Anna Bridge 142:4eea097334d6 93
Anna Bridge 142:4eea097334d6 94 #elif defined ( __TMS470__ )
Anna Bridge 142:4eea097334d6 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Anna Bridge 142:4eea097334d6 96 #define __STATIC_INLINE static inline
Anna Bridge 142:4eea097334d6 97
Anna Bridge 142:4eea097334d6 98 #elif defined ( __TASKING__ )
Anna Bridge 142:4eea097334d6 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Anna Bridge 142:4eea097334d6 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Anna Bridge 142:4eea097334d6 101 #define __STATIC_INLINE static inline
Anna Bridge 142:4eea097334d6 102
Anna Bridge 142:4eea097334d6 103 #elif defined ( __CSMC__ )
Anna Bridge 142:4eea097334d6 104 #define __packed
Anna Bridge 142:4eea097334d6 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Anna Bridge 142:4eea097334d6 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Anna Bridge 142:4eea097334d6 107 #define __STATIC_INLINE static inline
Anna Bridge 142:4eea097334d6 108
Anna Bridge 142:4eea097334d6 109 #endif
Anna Bridge 142:4eea097334d6 110
Anna Bridge 142:4eea097334d6 111 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 142:4eea097334d6 112 This core does not support an FPU at all
Anna Bridge 142:4eea097334d6 113 */
Anna Bridge 142:4eea097334d6 114 #define __FPU_USED 0
Anna Bridge 142:4eea097334d6 115
Anna Bridge 142:4eea097334d6 116 #if defined ( __CC_ARM )
Anna Bridge 142:4eea097334d6 117 #if defined __TARGET_FPU_VFP
Anna Bridge 142:4eea097334d6 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 119 #endif
Anna Bridge 142:4eea097334d6 120
Anna Bridge 142:4eea097334d6 121 #elif defined ( __GNUC__ )
Anna Bridge 142:4eea097334d6 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 142:4eea097334d6 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 124 #endif
Anna Bridge 142:4eea097334d6 125
Anna Bridge 142:4eea097334d6 126 #elif defined ( __ICCARM__ )
Anna Bridge 142:4eea097334d6 127 #if defined __ARMVFP__
Anna Bridge 142:4eea097334d6 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 129 #endif
Anna Bridge 142:4eea097334d6 130
Anna Bridge 142:4eea097334d6 131 #elif defined ( __TMS470__ )
Anna Bridge 142:4eea097334d6 132 #if defined __TI__VFP_SUPPORT____
Anna Bridge 142:4eea097334d6 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 134 #endif
Anna Bridge 142:4eea097334d6 135
Anna Bridge 142:4eea097334d6 136 #elif defined ( __TASKING__ )
Anna Bridge 142:4eea097334d6 137 #if defined __FPU_VFP__
Anna Bridge 142:4eea097334d6 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 139 #endif
Anna Bridge 142:4eea097334d6 140
Anna Bridge 142:4eea097334d6 141 #elif defined ( __CSMC__ ) /* Cosmic */
Anna Bridge 142:4eea097334d6 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Anna Bridge 142:4eea097334d6 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 144 #endif
Anna Bridge 142:4eea097334d6 145 #endif
Anna Bridge 142:4eea097334d6 146
Anna Bridge 142:4eea097334d6 147 #include <stdint.h> /* standard types definitions */
Anna Bridge 142:4eea097334d6 148 #include <core_cmInstr.h> /* Core Instruction Access */
Anna Bridge 142:4eea097334d6 149 #include <core_cmFunc.h> /* Core Function Access */
Anna Bridge 142:4eea097334d6 150
Anna Bridge 142:4eea097334d6 151 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 152 }
Anna Bridge 142:4eea097334d6 153 #endif
Anna Bridge 142:4eea097334d6 154
Anna Bridge 142:4eea097334d6 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Anna Bridge 142:4eea097334d6 156
Anna Bridge 142:4eea097334d6 157 #ifndef __CMSIS_GENERIC
Anna Bridge 142:4eea097334d6 158
Anna Bridge 142:4eea097334d6 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 142:4eea097334d6 160 #define __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 142:4eea097334d6 161
Anna Bridge 142:4eea097334d6 162 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 163 extern "C" {
Anna Bridge 142:4eea097334d6 164 #endif
Anna Bridge 142:4eea097334d6 165
Anna Bridge 142:4eea097334d6 166 /* check device defines and use defaults */
Anna Bridge 142:4eea097334d6 167 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 142:4eea097334d6 168 #ifndef __CM0PLUS_REV
Anna Bridge 142:4eea097334d6 169 #define __CM0PLUS_REV 0x0000
Anna Bridge 142:4eea097334d6 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 171 #endif
Anna Bridge 142:4eea097334d6 172
Anna Bridge 142:4eea097334d6 173 #ifndef __MPU_PRESENT
Anna Bridge 142:4eea097334d6 174 #define __MPU_PRESENT 0
Anna Bridge 142:4eea097334d6 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 176 #endif
Anna Bridge 142:4eea097334d6 177
Anna Bridge 142:4eea097334d6 178 #ifndef __VTOR_PRESENT
Anna Bridge 142:4eea097334d6 179 #define __VTOR_PRESENT 0
Anna Bridge 142:4eea097334d6 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 181 #endif
Anna Bridge 142:4eea097334d6 182
Anna Bridge 142:4eea097334d6 183 #ifndef __NVIC_PRIO_BITS
Anna Bridge 142:4eea097334d6 184 #define __NVIC_PRIO_BITS 2
Anna Bridge 142:4eea097334d6 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 186 #endif
Anna Bridge 142:4eea097334d6 187
Anna Bridge 142:4eea097334d6 188 #ifndef __Vendor_SysTickConfig
Anna Bridge 142:4eea097334d6 189 #define __Vendor_SysTickConfig 0
Anna Bridge 142:4eea097334d6 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 191 #endif
Anna Bridge 142:4eea097334d6 192 #endif
Anna Bridge 142:4eea097334d6 193
Anna Bridge 142:4eea097334d6 194 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 142:4eea097334d6 195 /**
Anna Bridge 142:4eea097334d6 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 142:4eea097334d6 197
Anna Bridge 142:4eea097334d6 198 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 142:4eea097334d6 199 \li to specify the access to peripheral variables.
Anna Bridge 142:4eea097334d6 200 \li for automatic generation of peripheral register debug information.
Anna Bridge 142:4eea097334d6 201 */
Anna Bridge 142:4eea097334d6 202 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 203 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 142:4eea097334d6 204 #else
Anna Bridge 142:4eea097334d6 205 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 142:4eea097334d6 206 #endif
Anna Bridge 142:4eea097334d6 207 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 142:4eea097334d6 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 142:4eea097334d6 209
Anna Bridge 142:4eea097334d6 210 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 211 #define __IM volatile /*!< Defines 'read only' permissions */
Anna Bridge 142:4eea097334d6 212 #else
Anna Bridge 142:4eea097334d6 213 #define __IM volatile const /*!< Defines 'read only' permissions */
Anna Bridge 142:4eea097334d6 214 #endif
Anna Bridge 142:4eea097334d6 215 #define __OM volatile /*!< Defines 'write only' permissions */
Anna Bridge 142:4eea097334d6 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
Anna Bridge 142:4eea097334d6 217
Anna Bridge 142:4eea097334d6 218 /*@} end of group Cortex-M0+ */
Anna Bridge 142:4eea097334d6 219
Anna Bridge 142:4eea097334d6 220
Anna Bridge 142:4eea097334d6 221
Anna Bridge 142:4eea097334d6 222 /*******************************************************************************
Anna Bridge 142:4eea097334d6 223 * Register Abstraction
Anna Bridge 142:4eea097334d6 224 Core Register contain:
Anna Bridge 142:4eea097334d6 225 - Core Register
Anna Bridge 142:4eea097334d6 226 - Core NVIC Register
Anna Bridge 142:4eea097334d6 227 - Core SCB Register
Anna Bridge 142:4eea097334d6 228 - Core SysTick Register
Anna Bridge 142:4eea097334d6 229 - Core MPU Register
Anna Bridge 142:4eea097334d6 230 ******************************************************************************/
Anna Bridge 142:4eea097334d6 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 142:4eea097334d6 232 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 142:4eea097334d6 233 */
Anna Bridge 142:4eea097334d6 234
Anna Bridge 142:4eea097334d6 235 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 236 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 142:4eea097334d6 237 \brief Core Register type definitions.
Anna Bridge 142:4eea097334d6 238 @{
Anna Bridge 142:4eea097334d6 239 */
Anna Bridge 142:4eea097334d6 240
Anna Bridge 142:4eea097334d6 241 /** \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 142:4eea097334d6 242 */
Anna Bridge 142:4eea097334d6 243 typedef union
Anna Bridge 142:4eea097334d6 244 {
Anna Bridge 142:4eea097334d6 245 struct
Anna Bridge 142:4eea097334d6 246 {
Anna Bridge 142:4eea097334d6 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 142:4eea097334d6 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 142:4eea097334d6 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 142:4eea097334d6 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 142:4eea097334d6 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 142:4eea097334d6 252 } b; /*!< Structure used for bit access */
Anna Bridge 142:4eea097334d6 253 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 254 } APSR_Type;
Anna Bridge 142:4eea097334d6 255
Anna Bridge 142:4eea097334d6 256 /* APSR Register Definitions */
Anna Bridge 142:4eea097334d6 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Anna Bridge 142:4eea097334d6 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 142:4eea097334d6 259
Anna Bridge 142:4eea097334d6 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Anna Bridge 142:4eea097334d6 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 142:4eea097334d6 262
Anna Bridge 142:4eea097334d6 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Anna Bridge 142:4eea097334d6 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 142:4eea097334d6 265
Anna Bridge 142:4eea097334d6 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Anna Bridge 142:4eea097334d6 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 142:4eea097334d6 268
Anna Bridge 142:4eea097334d6 269
Anna Bridge 142:4eea097334d6 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 142:4eea097334d6 271 */
Anna Bridge 142:4eea097334d6 272 typedef union
Anna Bridge 142:4eea097334d6 273 {
Anna Bridge 142:4eea097334d6 274 struct
Anna Bridge 142:4eea097334d6 275 {
Anna Bridge 142:4eea097334d6 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 142:4eea097334d6 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 142:4eea097334d6 278 } b; /*!< Structure used for bit access */
Anna Bridge 142:4eea097334d6 279 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 280 } IPSR_Type;
Anna Bridge 142:4eea097334d6 281
Anna Bridge 142:4eea097334d6 282 /* IPSR Register Definitions */
Anna Bridge 142:4eea097334d6 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Anna Bridge 142:4eea097334d6 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 142:4eea097334d6 285
Anna Bridge 142:4eea097334d6 286
Anna Bridge 142:4eea097334d6 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 142:4eea097334d6 288 */
Anna Bridge 142:4eea097334d6 289 typedef union
Anna Bridge 142:4eea097334d6 290 {
Anna Bridge 142:4eea097334d6 291 struct
Anna Bridge 142:4eea097334d6 292 {
Anna Bridge 142:4eea097334d6 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 142:4eea097334d6 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 142:4eea097334d6 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 142:4eea097334d6 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 142:4eea097334d6 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 142:4eea097334d6 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 142:4eea097334d6 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 142:4eea097334d6 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 142:4eea097334d6 301 } b; /*!< Structure used for bit access */
Anna Bridge 142:4eea097334d6 302 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 303 } xPSR_Type;
Anna Bridge 142:4eea097334d6 304
Anna Bridge 142:4eea097334d6 305 /* xPSR Register Definitions */
Anna Bridge 142:4eea097334d6 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Anna Bridge 142:4eea097334d6 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 142:4eea097334d6 308
Anna Bridge 142:4eea097334d6 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Anna Bridge 142:4eea097334d6 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 142:4eea097334d6 311
Anna Bridge 142:4eea097334d6 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Anna Bridge 142:4eea097334d6 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 142:4eea097334d6 314
Anna Bridge 142:4eea097334d6 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Anna Bridge 142:4eea097334d6 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 142:4eea097334d6 317
Anna Bridge 142:4eea097334d6 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Anna Bridge 142:4eea097334d6 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 142:4eea097334d6 320
Anna Bridge 142:4eea097334d6 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Anna Bridge 142:4eea097334d6 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 142:4eea097334d6 323
Anna Bridge 142:4eea097334d6 324
Anna Bridge 142:4eea097334d6 325 /** \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 142:4eea097334d6 326 */
Anna Bridge 142:4eea097334d6 327 typedef union
Anna Bridge 142:4eea097334d6 328 {
Anna Bridge 142:4eea097334d6 329 struct
Anna Bridge 142:4eea097334d6 330 {
Anna Bridge 142:4eea097334d6 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 142:4eea097334d6 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Anna Bridge 142:4eea097334d6 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 142:4eea097334d6 334 } b; /*!< Structure used for bit access */
Anna Bridge 142:4eea097334d6 335 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 336 } CONTROL_Type;
Anna Bridge 142:4eea097334d6 337
Anna Bridge 142:4eea097334d6 338 /* CONTROL Register Definitions */
Anna Bridge 142:4eea097334d6 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Anna Bridge 142:4eea097334d6 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 142:4eea097334d6 341
Anna Bridge 142:4eea097334d6 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Anna Bridge 142:4eea097334d6 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 142:4eea097334d6 344
Anna Bridge 142:4eea097334d6 345 /*@} end of group CMSIS_CORE */
Anna Bridge 142:4eea097334d6 346
Anna Bridge 142:4eea097334d6 347
Anna Bridge 142:4eea097334d6 348 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 142:4eea097334d6 350 \brief Type definitions for the NVIC Registers
Anna Bridge 142:4eea097334d6 351 @{
Anna Bridge 142:4eea097334d6 352 */
Anna Bridge 142:4eea097334d6 353
Anna Bridge 142:4eea097334d6 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 142:4eea097334d6 355 */
Anna Bridge 142:4eea097334d6 356 typedef struct
Anna Bridge 142:4eea097334d6 357 {
Anna Bridge 142:4eea097334d6 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 142:4eea097334d6 359 uint32_t RESERVED0[31];
Anna Bridge 142:4eea097334d6 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 142:4eea097334d6 361 uint32_t RSERVED1[31];
Anna Bridge 142:4eea097334d6 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 142:4eea097334d6 363 uint32_t RESERVED2[31];
Anna Bridge 142:4eea097334d6 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 142:4eea097334d6 365 uint32_t RESERVED3[31];
Anna Bridge 142:4eea097334d6 366 uint32_t RESERVED4[64];
Anna Bridge 142:4eea097334d6 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 142:4eea097334d6 368 } NVIC_Type;
Anna Bridge 142:4eea097334d6 369
Anna Bridge 142:4eea097334d6 370 /*@} end of group CMSIS_NVIC */
Anna Bridge 142:4eea097334d6 371
Anna Bridge 142:4eea097334d6 372
Anna Bridge 142:4eea097334d6 373 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 374 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 142:4eea097334d6 375 \brief Type definitions for the System Control Block Registers
Anna Bridge 142:4eea097334d6 376 @{
Anna Bridge 142:4eea097334d6 377 */
Anna Bridge 142:4eea097334d6 378
Anna Bridge 142:4eea097334d6 379 /** \brief Structure type to access the System Control Block (SCB).
Anna Bridge 142:4eea097334d6 380 */
Anna Bridge 142:4eea097334d6 381 typedef struct
Anna Bridge 142:4eea097334d6 382 {
Anna Bridge 142:4eea097334d6 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 142:4eea097334d6 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 142:4eea097334d6 385 #if (__VTOR_PRESENT == 1)
Anna Bridge 142:4eea097334d6 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 142:4eea097334d6 387 #else
Anna Bridge 142:4eea097334d6 388 uint32_t RESERVED0;
Anna Bridge 142:4eea097334d6 389 #endif
Anna Bridge 142:4eea097334d6 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 142:4eea097334d6 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 142:4eea097334d6 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 142:4eea097334d6 393 uint32_t RESERVED1;
Anna Bridge 142:4eea097334d6 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 142:4eea097334d6 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 142:4eea097334d6 396 } SCB_Type;
Anna Bridge 142:4eea097334d6 397
Anna Bridge 142:4eea097334d6 398 /* SCB CPUID Register Definitions */
Anna Bridge 142:4eea097334d6 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 142:4eea097334d6 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 142:4eea097334d6 401
Anna Bridge 142:4eea097334d6 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Anna Bridge 142:4eea097334d6 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 142:4eea097334d6 404
Anna Bridge 142:4eea097334d6 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 142:4eea097334d6 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 142:4eea097334d6 407
Anna Bridge 142:4eea097334d6 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Anna Bridge 142:4eea097334d6 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 142:4eea097334d6 410
Anna Bridge 142:4eea097334d6 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Anna Bridge 142:4eea097334d6 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 142:4eea097334d6 413
Anna Bridge 142:4eea097334d6 414 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 142:4eea097334d6 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 142:4eea097334d6 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 142:4eea097334d6 417
Anna Bridge 142:4eea097334d6 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 142:4eea097334d6 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 142:4eea097334d6 420
Anna Bridge 142:4eea097334d6 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 142:4eea097334d6 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 142:4eea097334d6 423
Anna Bridge 142:4eea097334d6 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 142:4eea097334d6 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 142:4eea097334d6 426
Anna Bridge 142:4eea097334d6 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 142:4eea097334d6 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 142:4eea097334d6 429
Anna Bridge 142:4eea097334d6 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 142:4eea097334d6 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 142:4eea097334d6 432
Anna Bridge 142:4eea097334d6 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 142:4eea097334d6 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 142:4eea097334d6 435
Anna Bridge 142:4eea097334d6 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 142:4eea097334d6 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 142:4eea097334d6 438
Anna Bridge 142:4eea097334d6 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 142:4eea097334d6 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 142:4eea097334d6 441
Anna Bridge 142:4eea097334d6 442 #if (__VTOR_PRESENT == 1)
Anna Bridge 142:4eea097334d6 443 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 142:4eea097334d6 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 142:4eea097334d6 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 142:4eea097334d6 446 #endif
Anna Bridge 142:4eea097334d6 447
Anna Bridge 142:4eea097334d6 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 142:4eea097334d6 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 142:4eea097334d6 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 142:4eea097334d6 451
Anna Bridge 142:4eea097334d6 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 142:4eea097334d6 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 142:4eea097334d6 454
Anna Bridge 142:4eea097334d6 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 142:4eea097334d6 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 142:4eea097334d6 457
Anna Bridge 142:4eea097334d6 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 142:4eea097334d6 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 142:4eea097334d6 460
Anna Bridge 142:4eea097334d6 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 142:4eea097334d6 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 142:4eea097334d6 463
Anna Bridge 142:4eea097334d6 464 /* SCB System Control Register Definitions */
Anna Bridge 142:4eea097334d6 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 142:4eea097334d6 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 142:4eea097334d6 467
Anna Bridge 142:4eea097334d6 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 142:4eea097334d6 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 142:4eea097334d6 470
Anna Bridge 142:4eea097334d6 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 142:4eea097334d6 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 142:4eea097334d6 473
Anna Bridge 142:4eea097334d6 474 /* SCB Configuration Control Register Definitions */
Anna Bridge 142:4eea097334d6 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Anna Bridge 142:4eea097334d6 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 142:4eea097334d6 477
Anna Bridge 142:4eea097334d6 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 142:4eea097334d6 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 142:4eea097334d6 480
Anna Bridge 142:4eea097334d6 481 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 142:4eea097334d6 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 142:4eea097334d6 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 142:4eea097334d6 484
Anna Bridge 142:4eea097334d6 485 /*@} end of group CMSIS_SCB */
Anna Bridge 142:4eea097334d6 486
Anna Bridge 142:4eea097334d6 487
Anna Bridge 142:4eea097334d6 488 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 142:4eea097334d6 490 \brief Type definitions for the System Timer Registers.
Anna Bridge 142:4eea097334d6 491 @{
Anna Bridge 142:4eea097334d6 492 */
Anna Bridge 142:4eea097334d6 493
Anna Bridge 142:4eea097334d6 494 /** \brief Structure type to access the System Timer (SysTick).
Anna Bridge 142:4eea097334d6 495 */
Anna Bridge 142:4eea097334d6 496 typedef struct
Anna Bridge 142:4eea097334d6 497 {
Anna Bridge 142:4eea097334d6 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 142:4eea097334d6 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 142:4eea097334d6 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 142:4eea097334d6 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 142:4eea097334d6 502 } SysTick_Type;
Anna Bridge 142:4eea097334d6 503
Anna Bridge 142:4eea097334d6 504 /* SysTick Control / Status Register Definitions */
Anna Bridge 142:4eea097334d6 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 142:4eea097334d6 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 142:4eea097334d6 507
Anna Bridge 142:4eea097334d6 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 142:4eea097334d6 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 142:4eea097334d6 510
Anna Bridge 142:4eea097334d6 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 142:4eea097334d6 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 142:4eea097334d6 513
Anna Bridge 142:4eea097334d6 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 142:4eea097334d6 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 142:4eea097334d6 516
Anna Bridge 142:4eea097334d6 517 /* SysTick Reload Register Definitions */
Anna Bridge 142:4eea097334d6 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 142:4eea097334d6 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 142:4eea097334d6 520
Anna Bridge 142:4eea097334d6 521 /* SysTick Current Register Definitions */
Anna Bridge 142:4eea097334d6 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Anna Bridge 142:4eea097334d6 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 142:4eea097334d6 524
Anna Bridge 142:4eea097334d6 525 /* SysTick Calibration Register Definitions */
Anna Bridge 142:4eea097334d6 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Anna Bridge 142:4eea097334d6 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 142:4eea097334d6 528
Anna Bridge 142:4eea097334d6 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Anna Bridge 142:4eea097334d6 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 142:4eea097334d6 531
Anna Bridge 142:4eea097334d6 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Anna Bridge 142:4eea097334d6 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 142:4eea097334d6 534
Anna Bridge 142:4eea097334d6 535 /*@} end of group CMSIS_SysTick */
Anna Bridge 142:4eea097334d6 536
Anna Bridge 142:4eea097334d6 537 #if (__MPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 538 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 142:4eea097334d6 540 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 142:4eea097334d6 541 @{
Anna Bridge 142:4eea097334d6 542 */
Anna Bridge 142:4eea097334d6 543
Anna Bridge 142:4eea097334d6 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 142:4eea097334d6 545 */
Anna Bridge 142:4eea097334d6 546 typedef struct
Anna Bridge 142:4eea097334d6 547 {
Anna Bridge 142:4eea097334d6 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 142:4eea097334d6 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 142:4eea097334d6 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Anna Bridge 142:4eea097334d6 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 142:4eea097334d6 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 142:4eea097334d6 553 } MPU_Type;
Anna Bridge 142:4eea097334d6 554
Anna Bridge 142:4eea097334d6 555 /* MPU Type Register */
Anna Bridge 142:4eea097334d6 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Anna Bridge 142:4eea097334d6 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 142:4eea097334d6 558
Anna Bridge 142:4eea097334d6 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Anna Bridge 142:4eea097334d6 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 142:4eea097334d6 561
Anna Bridge 142:4eea097334d6 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 142:4eea097334d6 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 142:4eea097334d6 564
Anna Bridge 142:4eea097334d6 565 /* MPU Control Register */
Anna Bridge 142:4eea097334d6 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 142:4eea097334d6 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 142:4eea097334d6 568
Anna Bridge 142:4eea097334d6 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 142:4eea097334d6 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 142:4eea097334d6 571
Anna Bridge 142:4eea097334d6 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Anna Bridge 142:4eea097334d6 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 142:4eea097334d6 574
Anna Bridge 142:4eea097334d6 575 /* MPU Region Number Register */
Anna Bridge 142:4eea097334d6 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Anna Bridge 142:4eea097334d6 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 142:4eea097334d6 578
Anna Bridge 142:4eea097334d6 579 /* MPU Region Base Address Register */
Anna Bridge 142:4eea097334d6 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Anna Bridge 142:4eea097334d6 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 142:4eea097334d6 582
Anna Bridge 142:4eea097334d6 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Anna Bridge 142:4eea097334d6 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 142:4eea097334d6 585
Anna Bridge 142:4eea097334d6 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Anna Bridge 142:4eea097334d6 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 142:4eea097334d6 588
Anna Bridge 142:4eea097334d6 589 /* MPU Region Attribute and Size Register */
Anna Bridge 142:4eea097334d6 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 142:4eea097334d6 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 142:4eea097334d6 592
Anna Bridge 142:4eea097334d6 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 142:4eea097334d6 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 142:4eea097334d6 595
Anna Bridge 142:4eea097334d6 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 142:4eea097334d6 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 142:4eea097334d6 598
Anna Bridge 142:4eea097334d6 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 142:4eea097334d6 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 142:4eea097334d6 601
Anna Bridge 142:4eea097334d6 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 142:4eea097334d6 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 142:4eea097334d6 604
Anna Bridge 142:4eea097334d6 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 142:4eea097334d6 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 142:4eea097334d6 607
Anna Bridge 142:4eea097334d6 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 142:4eea097334d6 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 142:4eea097334d6 610
Anna Bridge 142:4eea097334d6 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 142:4eea097334d6 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 142:4eea097334d6 613
Anna Bridge 142:4eea097334d6 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Anna Bridge 142:4eea097334d6 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 142:4eea097334d6 616
Anna Bridge 142:4eea097334d6 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Anna Bridge 142:4eea097334d6 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 142:4eea097334d6 619
Anna Bridge 142:4eea097334d6 620 /*@} end of group CMSIS_MPU */
Anna Bridge 142:4eea097334d6 621 #endif
Anna Bridge 142:4eea097334d6 622
Anna Bridge 142:4eea097334d6 623
Anna Bridge 142:4eea097334d6 624 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 142:4eea097334d6 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Anna Bridge 142:4eea097334d6 627 are only accessible over DAP and not via processor. Therefore
Anna Bridge 142:4eea097334d6 628 they are not covered by the Cortex-M0 header file.
Anna Bridge 142:4eea097334d6 629 @{
Anna Bridge 142:4eea097334d6 630 */
Anna Bridge 142:4eea097334d6 631 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 142:4eea097334d6 632
Anna Bridge 142:4eea097334d6 633
Anna Bridge 142:4eea097334d6 634 /** \ingroup CMSIS_core_register
Anna Bridge 142:4eea097334d6 635 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 142:4eea097334d6 636 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 142:4eea097334d6 637 @{
Anna Bridge 142:4eea097334d6 638 */
Anna Bridge 142:4eea097334d6 639
Anna Bridge 142:4eea097334d6 640 /* Memory mapping of Cortex-M0+ Hardware */
Anna Bridge 142:4eea097334d6 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 142:4eea097334d6 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 142:4eea097334d6 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 142:4eea097334d6 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 142:4eea097334d6 645
Anna Bridge 142:4eea097334d6 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 142:4eea097334d6 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 142:4eea097334d6 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 142:4eea097334d6 649
Anna Bridge 142:4eea097334d6 650 #if (__MPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 142:4eea097334d6 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 142:4eea097334d6 653 #endif
Anna Bridge 142:4eea097334d6 654
Anna Bridge 142:4eea097334d6 655 /*@} */
Anna Bridge 142:4eea097334d6 656
Anna Bridge 142:4eea097334d6 657
Anna Bridge 142:4eea097334d6 658
Anna Bridge 142:4eea097334d6 659 /*******************************************************************************
Anna Bridge 142:4eea097334d6 660 * Hardware Abstraction Layer
Anna Bridge 142:4eea097334d6 661 Core Function Interface contains:
Anna Bridge 142:4eea097334d6 662 - Core NVIC Functions
Anna Bridge 142:4eea097334d6 663 - Core SysTick Functions
Anna Bridge 142:4eea097334d6 664 - Core Register Access Functions
Anna Bridge 142:4eea097334d6 665 ******************************************************************************/
Anna Bridge 142:4eea097334d6 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 142:4eea097334d6 667 */
Anna Bridge 142:4eea097334d6 668
Anna Bridge 142:4eea097334d6 669
Anna Bridge 142:4eea097334d6 670
Anna Bridge 142:4eea097334d6 671 /* ########################## NVIC functions #################################### */
Anna Bridge 142:4eea097334d6 672 /** \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 142:4eea097334d6 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 142:4eea097334d6 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 142:4eea097334d6 675 @{
Anna Bridge 142:4eea097334d6 676 */
Anna Bridge 142:4eea097334d6 677
Anna Bridge 142:4eea097334d6 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Anna Bridge 142:4eea097334d6 679 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 142:4eea097334d6 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 142:4eea097334d6 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 142:4eea097334d6 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 142:4eea097334d6 683
Anna Bridge 142:4eea097334d6 684
Anna Bridge 142:4eea097334d6 685 /** \brief Enable External Interrupt
Anna Bridge 142:4eea097334d6 686
Anna Bridge 142:4eea097334d6 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Anna Bridge 142:4eea097334d6 688
Anna Bridge 142:4eea097334d6 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Anna Bridge 142:4eea097334d6 690 */
Anna Bridge 142:4eea097334d6 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 692 {
Anna Bridge 142:4eea097334d6 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge 142:4eea097334d6 694 }
Anna Bridge 142:4eea097334d6 695
Anna Bridge 142:4eea097334d6 696
Anna Bridge 142:4eea097334d6 697 /** \brief Disable External Interrupt
Anna Bridge 142:4eea097334d6 698
Anna Bridge 142:4eea097334d6 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Anna Bridge 142:4eea097334d6 700
Anna Bridge 142:4eea097334d6 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Anna Bridge 142:4eea097334d6 702 */
Anna Bridge 142:4eea097334d6 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 704 {
Anna Bridge 142:4eea097334d6 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge 142:4eea097334d6 706 __DSB();
Anna Bridge 142:4eea097334d6 707 __ISB();
Anna Bridge 142:4eea097334d6 708 }
Anna Bridge 142:4eea097334d6 709
Anna Bridge 142:4eea097334d6 710
Anna Bridge 142:4eea097334d6 711 /** \brief Get Pending Interrupt
Anna Bridge 142:4eea097334d6 712
Anna Bridge 142:4eea097334d6 713 The function reads the pending register in the NVIC and returns the pending bit
Anna Bridge 142:4eea097334d6 714 for the specified interrupt.
Anna Bridge 142:4eea097334d6 715
Anna Bridge 142:4eea097334d6 716 \param [in] IRQn Interrupt number.
Anna Bridge 142:4eea097334d6 717
Anna Bridge 142:4eea097334d6 718 \return 0 Interrupt status is not pending.
Anna Bridge 142:4eea097334d6 719 \return 1 Interrupt status is pending.
Anna Bridge 142:4eea097334d6 720 */
Anna Bridge 142:4eea097334d6 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 722 {
Anna Bridge 142:4eea097334d6 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 142:4eea097334d6 724 }
Anna Bridge 142:4eea097334d6 725
Anna Bridge 142:4eea097334d6 726
Anna Bridge 142:4eea097334d6 727 /** \brief Set Pending Interrupt
Anna Bridge 142:4eea097334d6 728
Anna Bridge 142:4eea097334d6 729 The function sets the pending bit of an external interrupt.
Anna Bridge 142:4eea097334d6 730
Anna Bridge 142:4eea097334d6 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Anna Bridge 142:4eea097334d6 732 */
Anna Bridge 142:4eea097334d6 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 734 {
Anna Bridge 142:4eea097334d6 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge 142:4eea097334d6 736 }
Anna Bridge 142:4eea097334d6 737
Anna Bridge 142:4eea097334d6 738
Anna Bridge 142:4eea097334d6 739 /** \brief Clear Pending Interrupt
Anna Bridge 142:4eea097334d6 740
Anna Bridge 142:4eea097334d6 741 The function clears the pending bit of an external interrupt.
Anna Bridge 142:4eea097334d6 742
Anna Bridge 142:4eea097334d6 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Anna Bridge 142:4eea097334d6 744 */
Anna Bridge 142:4eea097334d6 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 746 {
Anna Bridge 142:4eea097334d6 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge 142:4eea097334d6 748 }
Anna Bridge 142:4eea097334d6 749
Anna Bridge 142:4eea097334d6 750
Anna Bridge 142:4eea097334d6 751 /** \brief Set Interrupt Priority
Anna Bridge 142:4eea097334d6 752
Anna Bridge 142:4eea097334d6 753 The function sets the priority of an interrupt.
Anna Bridge 142:4eea097334d6 754
Anna Bridge 142:4eea097334d6 755 \note The priority cannot be set for every core interrupt.
Anna Bridge 142:4eea097334d6 756
Anna Bridge 142:4eea097334d6 757 \param [in] IRQn Interrupt number.
Anna Bridge 142:4eea097334d6 758 \param [in] priority Priority to set.
Anna Bridge 142:4eea097334d6 759 */
Anna Bridge 142:4eea097334d6 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 142:4eea097334d6 761 {
Anna Bridge 142:4eea097334d6 762 if((int32_t)(IRQn) < 0) {
Anna Bridge 142:4eea097334d6 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 142:4eea097334d6 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 142:4eea097334d6 765 }
Anna Bridge 142:4eea097334d6 766 else {
Anna Bridge 142:4eea097334d6 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 142:4eea097334d6 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 142:4eea097334d6 769 }
Anna Bridge 142:4eea097334d6 770 }
Anna Bridge 142:4eea097334d6 771
Anna Bridge 142:4eea097334d6 772
Anna Bridge 142:4eea097334d6 773 /** \brief Get Interrupt Priority
Anna Bridge 142:4eea097334d6 774
Anna Bridge 142:4eea097334d6 775 The function reads the priority of an interrupt. The interrupt
Anna Bridge 142:4eea097334d6 776 number can be positive to specify an external (device specific)
Anna Bridge 142:4eea097334d6 777 interrupt, or negative to specify an internal (core) interrupt.
Anna Bridge 142:4eea097334d6 778
Anna Bridge 142:4eea097334d6 779
Anna Bridge 142:4eea097334d6 780 \param [in] IRQn Interrupt number.
Anna Bridge 142:4eea097334d6 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Anna Bridge 142:4eea097334d6 782 priority bits of the microcontroller.
Anna Bridge 142:4eea097334d6 783 */
Anna Bridge 142:4eea097334d6 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 785 {
Anna Bridge 142:4eea097334d6 786
Anna Bridge 142:4eea097334d6 787 if((int32_t)(IRQn) < 0) {
Anna Bridge 142:4eea097334d6 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Anna Bridge 142:4eea097334d6 789 }
Anna Bridge 142:4eea097334d6 790 else {
Anna Bridge 142:4eea097334d6 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Anna Bridge 142:4eea097334d6 792 }
Anna Bridge 142:4eea097334d6 793 }
Anna Bridge 142:4eea097334d6 794
Anna Bridge 142:4eea097334d6 795
Anna Bridge 142:4eea097334d6 796 /** \brief System Reset
Anna Bridge 142:4eea097334d6 797
Anna Bridge 142:4eea097334d6 798 The function initiates a system reset request to reset the MCU.
Anna Bridge 142:4eea097334d6 799 */
Anna Bridge 142:4eea097334d6 800 __STATIC_INLINE void NVIC_SystemReset(void)
Anna Bridge 142:4eea097334d6 801 {
Anna Bridge 142:4eea097334d6 802 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 142:4eea097334d6 803 buffered write are completed before reset */
Anna Bridge 142:4eea097334d6 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 142:4eea097334d6 805 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 142:4eea097334d6 806 __DSB(); /* Ensure completion of memory access */
Anna Bridge 142:4eea097334d6 807 while(1) { __NOP(); } /* wait until reset */
Anna Bridge 142:4eea097334d6 808 }
Anna Bridge 142:4eea097334d6 809
Anna Bridge 142:4eea097334d6 810 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 142:4eea097334d6 811
Anna Bridge 142:4eea097334d6 812
Anna Bridge 142:4eea097334d6 813
Anna Bridge 142:4eea097334d6 814 /* ################################## SysTick function ############################################ */
Anna Bridge 142:4eea097334d6 815 /** \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 142:4eea097334d6 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 142:4eea097334d6 817 \brief Functions that configure the System.
Anna Bridge 142:4eea097334d6 818 @{
Anna Bridge 142:4eea097334d6 819 */
Anna Bridge 142:4eea097334d6 820
Anna Bridge 142:4eea097334d6 821 #if (__Vendor_SysTickConfig == 0)
Anna Bridge 142:4eea097334d6 822
Anna Bridge 142:4eea097334d6 823 /** \brief System Tick Configuration
Anna Bridge 142:4eea097334d6 824
Anna Bridge 142:4eea097334d6 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 142:4eea097334d6 826 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 142:4eea097334d6 827
Anna Bridge 142:4eea097334d6 828 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 142:4eea097334d6 829
Anna Bridge 142:4eea097334d6 830 \return 0 Function succeeded.
Anna Bridge 142:4eea097334d6 831 \return 1 Function failed.
Anna Bridge 142:4eea097334d6 832
Anna Bridge 142:4eea097334d6 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 142:4eea097334d6 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 142:4eea097334d6 835 must contain a vendor-specific implementation of this function.
Anna Bridge 142:4eea097334d6 836
Anna Bridge 142:4eea097334d6 837 */
Anna Bridge 142:4eea097334d6 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 142:4eea097334d6 839 {
Anna Bridge 142:4eea097334d6 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Anna Bridge 142:4eea097334d6 841
Anna Bridge 142:4eea097334d6 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 142:4eea097334d6 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 142:4eea097334d6 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 142:4eea097334d6 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 142:4eea097334d6 846 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 142:4eea097334d6 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 142:4eea097334d6 848 return (0UL); /* Function successful */
Anna Bridge 142:4eea097334d6 849 }
Anna Bridge 142:4eea097334d6 850
Anna Bridge 142:4eea097334d6 851 #endif
Anna Bridge 142:4eea097334d6 852
Anna Bridge 142:4eea097334d6 853 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 142:4eea097334d6 854
Anna Bridge 142:4eea097334d6 855
Anna Bridge 142:4eea097334d6 856
Anna Bridge 142:4eea097334d6 857
Anna Bridge 142:4eea097334d6 858 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 859 }
Anna Bridge 142:4eea097334d6 860 #endif
Anna Bridge 142:4eea097334d6 861
Anna Bridge 142:4eea097334d6 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Anna Bridge 142:4eea097334d6 863
Anna Bridge 142:4eea097334d6 864 #endif /* __CMSIS_GENERIC */