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TARGET_TB_SENSE_1/core_cm4.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 142:4eea097334d6
Child:: 145:64910690c574

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Anna Bridge	142:4eea097334d6	1	/************************************************************************//
Anna Bridge	142:4eea097334d6	2	* @file core_cm4.h
Anna Bridge	142:4eea097334d6	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Anna Bridge	142:4eea097334d6	4	* @version V4.10
Anna Bridge	142:4eea097334d6	5	* @date 18. March 2015
Anna Bridge	142:4eea097334d6	6	*
Anna Bridge	142:4eea097334d6	7	* @note
Anna Bridge	142:4eea097334d6	8	*
Anna Bridge	142:4eea097334d6	9	******************************************************************************/
Anna Bridge	142:4eea097334d6	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Anna Bridge	142:4eea097334d6	11
Anna Bridge	142:4eea097334d6	12	All rights reserved.
Anna Bridge	142:4eea097334d6	13	Redistribution and use in source and binary forms, with or without
Anna Bridge	142:4eea097334d6	14	modification, are permitted provided that the following conditions are met:
Anna Bridge	142:4eea097334d6	15	- Redistributions of source code must retain the above copyright
Anna Bridge	142:4eea097334d6	16	notice, this list of conditions and the following disclaimer.
Anna Bridge	142:4eea097334d6	17	- Redistributions in binary form must reproduce the above copyright
Anna Bridge	142:4eea097334d6	18	notice, this list of conditions and the following disclaimer in the
Anna Bridge	142:4eea097334d6	19	documentation and/or other materials provided with the distribution.
Anna Bridge	142:4eea097334d6	20	- Neither the name of ARM nor the names of its contributors may be used
Anna Bridge	142:4eea097334d6	21	to endorse or promote products derived from this software without
Anna Bridge	142:4eea097334d6	22	specific prior written permission.
Anna Bridge	142:4eea097334d6	23	*
Anna Bridge	142:4eea097334d6	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Anna Bridge	142:4eea097334d6	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Anna Bridge	142:4eea097334d6	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Anna Bridge	142:4eea097334d6	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Anna Bridge	142:4eea097334d6	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Anna Bridge	142:4eea097334d6	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Anna Bridge	142:4eea097334d6	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Anna Bridge	142:4eea097334d6	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Anna Bridge	142:4eea097334d6	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Anna Bridge	142:4eea097334d6	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Anna Bridge	142:4eea097334d6	34	POSSIBILITY OF SUCH DAMAGE.
Anna Bridge	142:4eea097334d6	35	---------------------------------------------------------------------------*/
Anna Bridge	142:4eea097334d6	36
Anna Bridge	142:4eea097334d6	37
Anna Bridge	142:4eea097334d6	38	#if defined ( __ICCARM__ )
Anna Bridge	142:4eea097334d6	39	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	142:4eea097334d6	40	#endif
Anna Bridge	142:4eea097334d6	41
Anna Bridge	142:4eea097334d6	42	#ifndef __CORE_CM4_H_GENERIC
Anna Bridge	142:4eea097334d6	43	#define __CORE_CM4_H_GENERIC
Anna Bridge	142:4eea097334d6	44
Anna Bridge	142:4eea097334d6	45	#ifdef __cplusplus
Anna Bridge	142:4eea097334d6	46	extern "C" {
Anna Bridge	142:4eea097334d6	47	#endif
Anna Bridge	142:4eea097334d6	48
Anna Bridge	142:4eea097334d6	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge	142:4eea097334d6	50	CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge	142:4eea097334d6	51
Anna Bridge	142:4eea097334d6	52	\li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge	142:4eea097334d6	53	Function definitions in header files are used to allow 'inlining'.
Anna Bridge	142:4eea097334d6	54
Anna Bridge	142:4eea097334d6	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge	142:4eea097334d6	56	Unions are used for effective representation of core registers.
Anna Bridge	142:4eea097334d6	57
Anna Bridge	142:4eea097334d6	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge	142:4eea097334d6	59	Function-like macros are used to allow more efficient code.
Anna Bridge	142:4eea097334d6	60	*/
Anna Bridge	142:4eea097334d6	61
Anna Bridge	142:4eea097334d6	62
Anna Bridge	142:4eea097334d6	63	/*******************************************************************************
Anna Bridge	142:4eea097334d6	64	* CMSIS definitions
Anna Bridge	142:4eea097334d6	65	******************************************************************************/
Anna Bridge	142:4eea097334d6	66	/** \ingroup Cortex_M4
Anna Bridge	142:4eea097334d6	67	@{
Anna Bridge	142:4eea097334d6	68	*/
Anna Bridge	142:4eea097334d6	69
Anna Bridge	142:4eea097334d6	70	/* CMSIS CM4 definitions */
Anna Bridge	142:4eea097334d6	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Anna Bridge	142:4eea097334d6	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Anna Bridge	142:4eea097334d6	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
Anna Bridge	142:4eea097334d6	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Anna Bridge	142:4eea097334d6	75
Anna Bridge	142:4eea097334d6	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
Anna Bridge	142:4eea097334d6	77
Anna Bridge	142:4eea097334d6	78
Anna Bridge	142:4eea097334d6	79	#if defined ( __CC_ARM )
Anna Bridge	142:4eea097334d6	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Anna Bridge	142:4eea097334d6	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Anna Bridge	142:4eea097334d6	82	#define __STATIC_INLINE static __inline
Anna Bridge	142:4eea097334d6	83
Anna Bridge	142:4eea097334d6	84	#elif defined ( __GNUC__ )
Anna Bridge	142:4eea097334d6	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Anna Bridge	142:4eea097334d6	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Anna Bridge	142:4eea097334d6	87	#define __STATIC_INLINE static inline
Anna Bridge	142:4eea097334d6	88
Anna Bridge	142:4eea097334d6	89	#elif defined ( __ICCARM__ )
Anna Bridge	142:4eea097334d6	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Anna Bridge	142:4eea097334d6	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Anna Bridge	142:4eea097334d6	92	#define __STATIC_INLINE static inline
Anna Bridge	142:4eea097334d6	93
Anna Bridge	142:4eea097334d6	94	#elif defined ( __TMS470__ )
Anna Bridge	142:4eea097334d6	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Anna Bridge	142:4eea097334d6	96	#define __STATIC_INLINE static inline
Anna Bridge	142:4eea097334d6	97
Anna Bridge	142:4eea097334d6	98	#elif defined ( __TASKING__ )
Anna Bridge	142:4eea097334d6	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Anna Bridge	142:4eea097334d6	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Anna Bridge	142:4eea097334d6	101	#define __STATIC_INLINE static inline
Anna Bridge	142:4eea097334d6	102
Anna Bridge	142:4eea097334d6	103	#elif defined ( __CSMC__ )
Anna Bridge	142:4eea097334d6	104	#define __packed
Anna Bridge	142:4eea097334d6	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Anna Bridge	142:4eea097334d6	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Anna Bridge	142:4eea097334d6	107	#define __STATIC_INLINE static inline
Anna Bridge	142:4eea097334d6	108
Anna Bridge	142:4eea097334d6	109	#endif
Anna Bridge	142:4eea097334d6	110
Anna Bridge	142:4eea097334d6	111	/** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge	142:4eea097334d6	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Anna Bridge	142:4eea097334d6	113	*/
Anna Bridge	142:4eea097334d6	114	#if defined ( __CC_ARM )
Anna Bridge	142:4eea097334d6	115	#if defined __TARGET_FPU_VFP
Anna Bridge	142:4eea097334d6	116	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	117	#define __FPU_USED 1
Anna Bridge	142:4eea097334d6	118	#else
Anna Bridge	142:4eea097334d6	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	142:4eea097334d6	120	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	121	#endif
Anna Bridge	142:4eea097334d6	122	#else
Anna Bridge	142:4eea097334d6	123	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	124	#endif
Anna Bridge	142:4eea097334d6	125
Anna Bridge	142:4eea097334d6	126	#elif defined ( __GNUC__ )
Anna Bridge	142:4eea097334d6	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge	142:4eea097334d6	128	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	129	#define __FPU_USED 1
Anna Bridge	142:4eea097334d6	130	#else
Anna Bridge	142:4eea097334d6	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	142:4eea097334d6	132	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	133	#endif
Anna Bridge	142:4eea097334d6	134	#else
Anna Bridge	142:4eea097334d6	135	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	136	#endif
Anna Bridge	142:4eea097334d6	137
Anna Bridge	142:4eea097334d6	138	#elif defined ( __ICCARM__ )
Anna Bridge	142:4eea097334d6	139	#if defined __ARMVFP__
Anna Bridge	142:4eea097334d6	140	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	141	#define __FPU_USED 1
Anna Bridge	142:4eea097334d6	142	#else
Anna Bridge	142:4eea097334d6	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	142:4eea097334d6	144	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	145	#endif
Anna Bridge	142:4eea097334d6	146	#else
Anna Bridge	142:4eea097334d6	147	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	148	#endif
Anna Bridge	142:4eea097334d6	149
Anna Bridge	142:4eea097334d6	150	#elif defined ( __TMS470__ )
Anna Bridge	142:4eea097334d6	151	#if defined __TI_VFP_SUPPORT__
Anna Bridge	142:4eea097334d6	152	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	153	#define __FPU_USED 1
Anna Bridge	142:4eea097334d6	154	#else
Anna Bridge	142:4eea097334d6	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	142:4eea097334d6	156	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	157	#endif
Anna Bridge	142:4eea097334d6	158	#else
Anna Bridge	142:4eea097334d6	159	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	160	#endif
Anna Bridge	142:4eea097334d6	161
Anna Bridge	142:4eea097334d6	162	#elif defined ( __TASKING__ )
Anna Bridge	142:4eea097334d6	163	#if defined __FPU_VFP__
Anna Bridge	142:4eea097334d6	164	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	165	#define __FPU_USED 1
Anna Bridge	142:4eea097334d6	166	#else
Anna Bridge	142:4eea097334d6	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	142:4eea097334d6	168	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	169	#endif
Anna Bridge	142:4eea097334d6	170	#else
Anna Bridge	142:4eea097334d6	171	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	172	#endif
Anna Bridge	142:4eea097334d6	173
Anna Bridge	142:4eea097334d6	174	#elif defined ( __CSMC__ ) /* Cosmic */
Anna Bridge	142:4eea097334d6	175	#if ( __CSMC__ & 0x400) // FPU present for parser
Anna Bridge	142:4eea097334d6	176	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	177	#define __FPU_USED 1
Anna Bridge	142:4eea097334d6	178	#else
Anna Bridge	142:4eea097334d6	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	142:4eea097334d6	180	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	181	#endif
Anna Bridge	142:4eea097334d6	182	#else
Anna Bridge	142:4eea097334d6	183	#define __FPU_USED 0
Anna Bridge	142:4eea097334d6	184	#endif
Anna Bridge	142:4eea097334d6	185	#endif
Anna Bridge	142:4eea097334d6	186
Anna Bridge	142:4eea097334d6	187	#include <stdint.h> /* standard types definitions */
Anna Bridge	142:4eea097334d6	188	#include <core_cmInstr.h> /* Core Instruction Access */
Anna Bridge	142:4eea097334d6	189	#include <core_cmFunc.h> /* Core Function Access */
Anna Bridge	142:4eea097334d6	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Anna Bridge	142:4eea097334d6	191
Anna Bridge	142:4eea097334d6	192	#ifdef __cplusplus
Anna Bridge	142:4eea097334d6	193	}
Anna Bridge	142:4eea097334d6	194	#endif
Anna Bridge	142:4eea097334d6	195
Anna Bridge	142:4eea097334d6	196	#endif /* __CORE_CM4_H_GENERIC */
Anna Bridge	142:4eea097334d6	197
Anna Bridge	142:4eea097334d6	198	#ifndef __CMSIS_GENERIC
Anna Bridge	142:4eea097334d6	199
Anna Bridge	142:4eea097334d6	200	#ifndef __CORE_CM4_H_DEPENDANT
Anna Bridge	142:4eea097334d6	201	#define __CORE_CM4_H_DEPENDANT
Anna Bridge	142:4eea097334d6	202
Anna Bridge	142:4eea097334d6	203	#ifdef __cplusplus
Anna Bridge	142:4eea097334d6	204	extern "C" {
Anna Bridge	142:4eea097334d6	205	#endif
Anna Bridge	142:4eea097334d6	206
Anna Bridge	142:4eea097334d6	207	/* check device defines and use defaults */
Anna Bridge	142:4eea097334d6	208	#if defined __CHECK_DEVICE_DEFINES
Anna Bridge	142:4eea097334d6	209	#ifndef __CM4_REV
Anna Bridge	142:4eea097334d6	210	#define __CM4_REV 0x0000
Anna Bridge	142:4eea097334d6	211	#warning "__CM4_REV not defined in device header file; using default!"
Anna Bridge	142:4eea097334d6	212	#endif
Anna Bridge	142:4eea097334d6	213
Anna Bridge	142:4eea097334d6	214	#ifndef __FPU_PRESENT
Anna Bridge	142:4eea097334d6	215	#define __FPU_PRESENT 0
Anna Bridge	142:4eea097334d6	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge	142:4eea097334d6	217	#endif
Anna Bridge	142:4eea097334d6	218
Anna Bridge	142:4eea097334d6	219	#ifndef __MPU_PRESENT
Anna Bridge	142:4eea097334d6	220	#define __MPU_PRESENT 0
Anna Bridge	142:4eea097334d6	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge	142:4eea097334d6	222	#endif
Anna Bridge	142:4eea097334d6	223
Anna Bridge	142:4eea097334d6	224	#ifndef __NVIC_PRIO_BITS
Anna Bridge	142:4eea097334d6	225	#define __NVIC_PRIO_BITS 4
Anna Bridge	142:4eea097334d6	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge	142:4eea097334d6	227	#endif
Anna Bridge	142:4eea097334d6	228
Anna Bridge	142:4eea097334d6	229	#ifndef __Vendor_SysTickConfig
Anna Bridge	142:4eea097334d6	230	#define __Vendor_SysTickConfig 0
Anna Bridge	142:4eea097334d6	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge	142:4eea097334d6	232	#endif
Anna Bridge	142:4eea097334d6	233	#endif
Anna Bridge	142:4eea097334d6	234
Anna Bridge	142:4eea097334d6	235	/* IO definitions (access restrictions to peripheral registers) */
Anna Bridge	142:4eea097334d6	236	/**
Anna Bridge	142:4eea097334d6	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge	142:4eea097334d6	238
Anna Bridge	142:4eea097334d6	239	<strong>IO Type Qualifiers</strong> are used
Anna Bridge	142:4eea097334d6	240	\li to specify the access to peripheral variables.
Anna Bridge	142:4eea097334d6	241	\li for automatic generation of peripheral register debug information.
Anna Bridge	142:4eea097334d6	242	*/
Anna Bridge	142:4eea097334d6	243	#ifdef __cplusplus
Anna Bridge	142:4eea097334d6	244	#define __I volatile /!< Defines 'read only' permissions /
Anna Bridge	142:4eea097334d6	245	#else
Anna Bridge	142:4eea097334d6	246	#define __I volatile const /!< Defines 'read only' permissions /
Anna Bridge	142:4eea097334d6	247	#endif
Anna Bridge	142:4eea097334d6	248	#define __O volatile /!< Defines 'write only' permissions /
Anna Bridge	142:4eea097334d6	249	#define __IO volatile /!< Defines 'read / write' permissions /
Anna Bridge	142:4eea097334d6	250
Anna Bridge	142:4eea097334d6	251	#ifdef __cplusplus
Anna Bridge	142:4eea097334d6	252	#define __IM volatile /!< Defines 'read only' permissions /
Anna Bridge	142:4eea097334d6	253	#else
Anna Bridge	142:4eea097334d6	254	#define __IM volatile const /!< Defines 'read only' permissions /
Anna Bridge	142:4eea097334d6	255	#endif
Anna Bridge	142:4eea097334d6	256	#define __OM volatile /!< Defines 'write only' permissions /
Anna Bridge	142:4eea097334d6	257	#define __IOM volatile /!< Defines 'read / write' permissions /
Anna Bridge	142:4eea097334d6	258
Anna Bridge	142:4eea097334d6	259	/@} end of group Cortex_M4 /
Anna Bridge	142:4eea097334d6	260
Anna Bridge	142:4eea097334d6	261
Anna Bridge	142:4eea097334d6	262
Anna Bridge	142:4eea097334d6	263	/*******************************************************************************
Anna Bridge	142:4eea097334d6	264	* Register Abstraction
Anna Bridge	142:4eea097334d6	265	Core Register contain:
Anna Bridge	142:4eea097334d6	266	- Core Register
Anna Bridge	142:4eea097334d6	267	- Core NVIC Register
Anna Bridge	142:4eea097334d6	268	- Core SCB Register
Anna Bridge	142:4eea097334d6	269	- Core SysTick Register
Anna Bridge	142:4eea097334d6	270	- Core Debug Register
Anna Bridge	142:4eea097334d6	271	- Core MPU Register
Anna Bridge	142:4eea097334d6	272	- Core FPU Register
Anna Bridge	142:4eea097334d6	273	******************************************************************************/
Anna Bridge	142:4eea097334d6	274	/** \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge	142:4eea097334d6	275	\brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge	142:4eea097334d6	276	*/
Anna Bridge	142:4eea097334d6	277
Anna Bridge	142:4eea097334d6	278	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	279	\defgroup CMSIS_CORE Status and Control Registers
Anna Bridge	142:4eea097334d6	280	\brief Core Register type definitions.
Anna Bridge	142:4eea097334d6	281	@{
Anna Bridge	142:4eea097334d6	282	*/
Anna Bridge	142:4eea097334d6	283
Anna Bridge	142:4eea097334d6	284	/** \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge	142:4eea097334d6	285	*/
Anna Bridge	142:4eea097334d6	286	typedef union
Anna Bridge	142:4eea097334d6	287	{
Anna Bridge	142:4eea097334d6	288	struct
Anna Bridge	142:4eea097334d6	289	{
Anna Bridge	142:4eea097334d6	290	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Anna Bridge	142:4eea097334d6	291	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	142:4eea097334d6	292	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Anna Bridge	142:4eea097334d6	293	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	142:4eea097334d6	294	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	142:4eea097334d6	295	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	142:4eea097334d6	296	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	142:4eea097334d6	297	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	142:4eea097334d6	298	} b; /!< Structure used for bit access /
Anna Bridge	142:4eea097334d6	299	uint32_t w; /!< Type used for word access /
Anna Bridge	142:4eea097334d6	300	} APSR_Type;
Anna Bridge	142:4eea097334d6	301
Anna Bridge	142:4eea097334d6	302	/* APSR Register Definitions */
Anna Bridge	142:4eea097334d6	303	#define APSR_N_Pos 31 /!< APSR: N Position /
Anna Bridge	142:4eea097334d6	304	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Anna Bridge	142:4eea097334d6	305
Anna Bridge	142:4eea097334d6	306	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Anna Bridge	142:4eea097334d6	307	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Anna Bridge	142:4eea097334d6	308
Anna Bridge	142:4eea097334d6	309	#define APSR_C_Pos 29 /!< APSR: C Position /
Anna Bridge	142:4eea097334d6	310	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Anna Bridge	142:4eea097334d6	311
Anna Bridge	142:4eea097334d6	312	#define APSR_V_Pos 28 /!< APSR: V Position /
Anna Bridge	142:4eea097334d6	313	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Anna Bridge	142:4eea097334d6	314
Anna Bridge	142:4eea097334d6	315	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Anna Bridge	142:4eea097334d6	316	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Anna Bridge	142:4eea097334d6	317
Anna Bridge	142:4eea097334d6	318	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Anna Bridge	142:4eea097334d6	319	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Anna Bridge	142:4eea097334d6	320
Anna Bridge	142:4eea097334d6	321
Anna Bridge	142:4eea097334d6	322	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge	142:4eea097334d6	323	*/
Anna Bridge	142:4eea097334d6	324	typedef union
Anna Bridge	142:4eea097334d6	325	{
Anna Bridge	142:4eea097334d6	326	struct
Anna Bridge	142:4eea097334d6	327	{
Anna Bridge	142:4eea097334d6	328	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	142:4eea097334d6	329	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Anna Bridge	142:4eea097334d6	330	} b; /!< Structure used for bit access /
Anna Bridge	142:4eea097334d6	331	uint32_t w; /!< Type used for word access /
Anna Bridge	142:4eea097334d6	332	} IPSR_Type;
Anna Bridge	142:4eea097334d6	333
Anna Bridge	142:4eea097334d6	334	/* IPSR Register Definitions */
Anna Bridge	142:4eea097334d6	335	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Anna Bridge	142:4eea097334d6	336	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Anna Bridge	142:4eea097334d6	337
Anna Bridge	142:4eea097334d6	338
Anna Bridge	142:4eea097334d6	339	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge	142:4eea097334d6	340	*/
Anna Bridge	142:4eea097334d6	341	typedef union
Anna Bridge	142:4eea097334d6	342	{
Anna Bridge	142:4eea097334d6	343	struct
Anna Bridge	142:4eea097334d6	344	{
Anna Bridge	142:4eea097334d6	345	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	142:4eea097334d6	346	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Anna Bridge	142:4eea097334d6	347	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	142:4eea097334d6	348	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Anna Bridge	142:4eea097334d6	349	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Anna Bridge	142:4eea097334d6	350	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Anna Bridge	142:4eea097334d6	351	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	142:4eea097334d6	352	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	142:4eea097334d6	353	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	142:4eea097334d6	354	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	142:4eea097334d6	355	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	142:4eea097334d6	356	} b; /!< Structure used for bit access /
Anna Bridge	142:4eea097334d6	357	uint32_t w; /!< Type used for word access /
Anna Bridge	142:4eea097334d6	358	} xPSR_Type;
Anna Bridge	142:4eea097334d6	359
Anna Bridge	142:4eea097334d6	360	/* xPSR Register Definitions */
Anna Bridge	142:4eea097334d6	361	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Anna Bridge	142:4eea097334d6	362	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Anna Bridge	142:4eea097334d6	363
Anna Bridge	142:4eea097334d6	364	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Anna Bridge	142:4eea097334d6	365	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Anna Bridge	142:4eea097334d6	366
Anna Bridge	142:4eea097334d6	367	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Anna Bridge	142:4eea097334d6	368	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Anna Bridge	142:4eea097334d6	369
Anna Bridge	142:4eea097334d6	370	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Anna Bridge	142:4eea097334d6	371	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Anna Bridge	142:4eea097334d6	372
Anna Bridge	142:4eea097334d6	373	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Anna Bridge	142:4eea097334d6	374	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Anna Bridge	142:4eea097334d6	375
Anna Bridge	142:4eea097334d6	376	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Anna Bridge	142:4eea097334d6	377	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Anna Bridge	142:4eea097334d6	378
Anna Bridge	142:4eea097334d6	379	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Anna Bridge	142:4eea097334d6	380	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Anna Bridge	142:4eea097334d6	381
Anna Bridge	142:4eea097334d6	382	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Anna Bridge	142:4eea097334d6	383	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Anna Bridge	142:4eea097334d6	384
Anna Bridge	142:4eea097334d6	385	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Anna Bridge	142:4eea097334d6	386	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Anna Bridge	142:4eea097334d6	387
Anna Bridge	142:4eea097334d6	388
Anna Bridge	142:4eea097334d6	389	/** \brief Union type to access the Control Registers (CONTROL).
Anna Bridge	142:4eea097334d6	390	*/
Anna Bridge	142:4eea097334d6	391	typedef union
Anna Bridge	142:4eea097334d6	392	{
Anna Bridge	142:4eea097334d6	393	struct
Anna Bridge	142:4eea097334d6	394	{
Anna Bridge	142:4eea097334d6	395	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Anna Bridge	142:4eea097334d6	396	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Anna Bridge	142:4eea097334d6	397	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Anna Bridge	142:4eea097334d6	398	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Anna Bridge	142:4eea097334d6	399	} b; /!< Structure used for bit access /
Anna Bridge	142:4eea097334d6	400	uint32_t w; /!< Type used for word access /
Anna Bridge	142:4eea097334d6	401	} CONTROL_Type;
Anna Bridge	142:4eea097334d6	402
Anna Bridge	142:4eea097334d6	403	/* CONTROL Register Definitions */
Anna Bridge	142:4eea097334d6	404	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Anna Bridge	142:4eea097334d6	405	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Anna Bridge	142:4eea097334d6	406
Anna Bridge	142:4eea097334d6	407	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Anna Bridge	142:4eea097334d6	408	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Anna Bridge	142:4eea097334d6	409
Anna Bridge	142:4eea097334d6	410	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Anna Bridge	142:4eea097334d6	411	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Anna Bridge	142:4eea097334d6	412
Anna Bridge	142:4eea097334d6	413	/@} end of group CMSIS_CORE /
Anna Bridge	142:4eea097334d6	414
Anna Bridge	142:4eea097334d6	415
Anna Bridge	142:4eea097334d6	416	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	417	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge	142:4eea097334d6	418	\brief Type definitions for the NVIC Registers
Anna Bridge	142:4eea097334d6	419	@{
Anna Bridge	142:4eea097334d6	420	*/
Anna Bridge	142:4eea097334d6	421
Anna Bridge	142:4eea097334d6	422	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge	142:4eea097334d6	423	*/
Anna Bridge	142:4eea097334d6	424	typedef struct
Anna Bridge	142:4eea097334d6	425	{
Anna Bridge	142:4eea097334d6	426	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Anna Bridge	142:4eea097334d6	427	uint32_t RESERVED0[24];
Anna Bridge	142:4eea097334d6	428	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Anna Bridge	142:4eea097334d6	429	uint32_t RSERVED1[24];
Anna Bridge	142:4eea097334d6	430	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Anna Bridge	142:4eea097334d6	431	uint32_t RESERVED2[24];
Anna Bridge	142:4eea097334d6	432	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Anna Bridge	142:4eea097334d6	433	uint32_t RESERVED3[24];
Anna Bridge	142:4eea097334d6	434	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Anna Bridge	142:4eea097334d6	435	uint32_t RESERVED4[56];
Anna Bridge	142:4eea097334d6	436	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Anna Bridge	142:4eea097334d6	437	uint32_t RESERVED5[644];
Anna Bridge	142:4eea097334d6	438	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Anna Bridge	142:4eea097334d6	439	} NVIC_Type;
Anna Bridge	142:4eea097334d6	440
Anna Bridge	142:4eea097334d6	441	/* Software Triggered Interrupt Register Definitions */
Anna Bridge	142:4eea097334d6	442	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Anna Bridge	142:4eea097334d6	443	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Anna Bridge	142:4eea097334d6	444
Anna Bridge	142:4eea097334d6	445	/@} end of group CMSIS_NVIC /
Anna Bridge	142:4eea097334d6	446
Anna Bridge	142:4eea097334d6	447
Anna Bridge	142:4eea097334d6	448	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	449	\defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge	142:4eea097334d6	450	\brief Type definitions for the System Control Block Registers
Anna Bridge	142:4eea097334d6	451	@{
Anna Bridge	142:4eea097334d6	452	*/
Anna Bridge	142:4eea097334d6	453
Anna Bridge	142:4eea097334d6	454	/** \brief Structure type to access the System Control Block (SCB).
Anna Bridge	142:4eea097334d6	455	*/
Anna Bridge	142:4eea097334d6	456	typedef struct
Anna Bridge	142:4eea097334d6	457	{
Anna Bridge	142:4eea097334d6	458	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Anna Bridge	142:4eea097334d6	459	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Anna Bridge	142:4eea097334d6	460	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Anna Bridge	142:4eea097334d6	461	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Anna Bridge	142:4eea097334d6	462	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Anna Bridge	142:4eea097334d6	463	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Anna Bridge	142:4eea097334d6	464	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Anna Bridge	142:4eea097334d6	465	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Anna Bridge	142:4eea097334d6	466	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Anna Bridge	142:4eea097334d6	467	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Anna Bridge	142:4eea097334d6	468	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Anna Bridge	142:4eea097334d6	469	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Anna Bridge	142:4eea097334d6	470	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Anna Bridge	142:4eea097334d6	471	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Anna Bridge	142:4eea097334d6	472	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Anna Bridge	142:4eea097334d6	473	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Anna Bridge	142:4eea097334d6	474	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Anna Bridge	142:4eea097334d6	475	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Anna Bridge	142:4eea097334d6	476	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Anna Bridge	142:4eea097334d6	477	uint32_t RESERVED0[5];
Anna Bridge	142:4eea097334d6	478	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Anna Bridge	142:4eea097334d6	479	} SCB_Type;
Anna Bridge	142:4eea097334d6	480
Anna Bridge	142:4eea097334d6	481	/* SCB CPUID Register Definitions */
Anna Bridge	142:4eea097334d6	482	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Anna Bridge	142:4eea097334d6	483	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Anna Bridge	142:4eea097334d6	484
Anna Bridge	142:4eea097334d6	485	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Anna Bridge	142:4eea097334d6	486	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Anna Bridge	142:4eea097334d6	487
Anna Bridge	142:4eea097334d6	488	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Anna Bridge	142:4eea097334d6	489	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Anna Bridge	142:4eea097334d6	490
Anna Bridge	142:4eea097334d6	491	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Anna Bridge	142:4eea097334d6	492	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Anna Bridge	142:4eea097334d6	493
Anna Bridge	142:4eea097334d6	494	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Anna Bridge	142:4eea097334d6	495	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Anna Bridge	142:4eea097334d6	496
Anna Bridge	142:4eea097334d6	497	/* SCB Interrupt Control State Register Definitions */
Anna Bridge	142:4eea097334d6	498	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Anna Bridge	142:4eea097334d6	499	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Anna Bridge	142:4eea097334d6	500
Anna Bridge	142:4eea097334d6	501	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Anna Bridge	142:4eea097334d6	502	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Anna Bridge	142:4eea097334d6	503
Anna Bridge	142:4eea097334d6	504	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Anna Bridge	142:4eea097334d6	505	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Anna Bridge	142:4eea097334d6	506
Anna Bridge	142:4eea097334d6	507	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Anna Bridge	142:4eea097334d6	508	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Anna Bridge	142:4eea097334d6	509
Anna Bridge	142:4eea097334d6	510	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Anna Bridge	142:4eea097334d6	511	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Anna Bridge	142:4eea097334d6	512
Anna Bridge	142:4eea097334d6	513	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Anna Bridge	142:4eea097334d6	514	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Anna Bridge	142:4eea097334d6	515
Anna Bridge	142:4eea097334d6	516	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Anna Bridge	142:4eea097334d6	517	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Anna Bridge	142:4eea097334d6	518
Anna Bridge	142:4eea097334d6	519	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Anna Bridge	142:4eea097334d6	520	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Anna Bridge	142:4eea097334d6	521
Anna Bridge	142:4eea097334d6	522	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Anna Bridge	142:4eea097334d6	523	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Anna Bridge	142:4eea097334d6	524
Anna Bridge	142:4eea097334d6	525	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Anna Bridge	142:4eea097334d6	526	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Anna Bridge	142:4eea097334d6	527
Anna Bridge	142:4eea097334d6	528	/* SCB Vector Table Offset Register Definitions */
Anna Bridge	142:4eea097334d6	529	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Anna Bridge	142:4eea097334d6	530	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Anna Bridge	142:4eea097334d6	531
Anna Bridge	142:4eea097334d6	532	/* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge	142:4eea097334d6	533	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Anna Bridge	142:4eea097334d6	534	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Anna Bridge	142:4eea097334d6	535
Anna Bridge	142:4eea097334d6	536	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Anna Bridge	142:4eea097334d6	537	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Anna Bridge	142:4eea097334d6	538
Anna Bridge	142:4eea097334d6	539	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Anna Bridge	142:4eea097334d6	540	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Anna Bridge	142:4eea097334d6	541
Anna Bridge	142:4eea097334d6	542	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Anna Bridge	142:4eea097334d6	543	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Anna Bridge	142:4eea097334d6	544
Anna Bridge	142:4eea097334d6	545	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Anna Bridge	142:4eea097334d6	546	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Anna Bridge	142:4eea097334d6	547
Anna Bridge	142:4eea097334d6	548	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Anna Bridge	142:4eea097334d6	549	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Anna Bridge	142:4eea097334d6	550
Anna Bridge	142:4eea097334d6	551	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Anna Bridge	142:4eea097334d6	552	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Anna Bridge	142:4eea097334d6	553
Anna Bridge	142:4eea097334d6	554	/* SCB System Control Register Definitions */
Anna Bridge	142:4eea097334d6	555	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Anna Bridge	142:4eea097334d6	556	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Anna Bridge	142:4eea097334d6	557
Anna Bridge	142:4eea097334d6	558	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Anna Bridge	142:4eea097334d6	559	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Anna Bridge	142:4eea097334d6	560
Anna Bridge	142:4eea097334d6	561	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Anna Bridge	142:4eea097334d6	562	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Anna Bridge	142:4eea097334d6	563
Anna Bridge	142:4eea097334d6	564	/* SCB Configuration Control Register Definitions */
Anna Bridge	142:4eea097334d6	565	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Anna Bridge	142:4eea097334d6	566	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Anna Bridge	142:4eea097334d6	567
Anna Bridge	142:4eea097334d6	568	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Anna Bridge	142:4eea097334d6	569	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Anna Bridge	142:4eea097334d6	570
Anna Bridge	142:4eea097334d6	571	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Anna Bridge	142:4eea097334d6	572	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Anna Bridge	142:4eea097334d6	573
Anna Bridge	142:4eea097334d6	574	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Anna Bridge	142:4eea097334d6	575	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Anna Bridge	142:4eea097334d6	576
Anna Bridge	142:4eea097334d6	577	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Anna Bridge	142:4eea097334d6	578	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Anna Bridge	142:4eea097334d6	579
Anna Bridge	142:4eea097334d6	580	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Anna Bridge	142:4eea097334d6	581	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Anna Bridge	142:4eea097334d6	582
Anna Bridge	142:4eea097334d6	583	/* SCB System Handler Control and State Register Definitions */
Anna Bridge	142:4eea097334d6	584	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Anna Bridge	142:4eea097334d6	585	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Anna Bridge	142:4eea097334d6	586
Anna Bridge	142:4eea097334d6	587	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Anna Bridge	142:4eea097334d6	588	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Anna Bridge	142:4eea097334d6	589
Anna Bridge	142:4eea097334d6	590	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Anna Bridge	142:4eea097334d6	591	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Anna Bridge	142:4eea097334d6	592
Anna Bridge	142:4eea097334d6	593	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Anna Bridge	142:4eea097334d6	594	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Anna Bridge	142:4eea097334d6	595
Anna Bridge	142:4eea097334d6	596	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Anna Bridge	142:4eea097334d6	597	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Anna Bridge	142:4eea097334d6	598
Anna Bridge	142:4eea097334d6	599	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Anna Bridge	142:4eea097334d6	600	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Anna Bridge	142:4eea097334d6	601
Anna Bridge	142:4eea097334d6	602	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Anna Bridge	142:4eea097334d6	603	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Anna Bridge	142:4eea097334d6	604
Anna Bridge	142:4eea097334d6	605	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Anna Bridge	142:4eea097334d6	606	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Anna Bridge	142:4eea097334d6	607
Anna Bridge	142:4eea097334d6	608	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Anna Bridge	142:4eea097334d6	609	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Anna Bridge	142:4eea097334d6	610
Anna Bridge	142:4eea097334d6	611	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Anna Bridge	142:4eea097334d6	612	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Anna Bridge	142:4eea097334d6	613
Anna Bridge	142:4eea097334d6	614	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Anna Bridge	142:4eea097334d6	615	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Anna Bridge	142:4eea097334d6	616
Anna Bridge	142:4eea097334d6	617	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Anna Bridge	142:4eea097334d6	618	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Anna Bridge	142:4eea097334d6	619
Anna Bridge	142:4eea097334d6	620	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Anna Bridge	142:4eea097334d6	621	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Anna Bridge	142:4eea097334d6	622
Anna Bridge	142:4eea097334d6	623	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Anna Bridge	142:4eea097334d6	624	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Anna Bridge	142:4eea097334d6	625
Anna Bridge	142:4eea097334d6	626	/* SCB Configurable Fault Status Registers Definitions */
Anna Bridge	142:4eea097334d6	627	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Anna Bridge	142:4eea097334d6	628	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Anna Bridge	142:4eea097334d6	629
Anna Bridge	142:4eea097334d6	630	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Anna Bridge	142:4eea097334d6	631	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Anna Bridge	142:4eea097334d6	632
Anna Bridge	142:4eea097334d6	633	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Anna Bridge	142:4eea097334d6	634	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Anna Bridge	142:4eea097334d6	635
Anna Bridge	142:4eea097334d6	636	/* SCB Hard Fault Status Registers Definitions */
Anna Bridge	142:4eea097334d6	637	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Anna Bridge	142:4eea097334d6	638	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Anna Bridge	142:4eea097334d6	639
Anna Bridge	142:4eea097334d6	640	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Anna Bridge	142:4eea097334d6	641	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Anna Bridge	142:4eea097334d6	642
Anna Bridge	142:4eea097334d6	643	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Anna Bridge	142:4eea097334d6	644	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Anna Bridge	142:4eea097334d6	645
Anna Bridge	142:4eea097334d6	646	/* SCB Debug Fault Status Register Definitions */
Anna Bridge	142:4eea097334d6	647	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Anna Bridge	142:4eea097334d6	648	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Anna Bridge	142:4eea097334d6	649
Anna Bridge	142:4eea097334d6	650	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Anna Bridge	142:4eea097334d6	651	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Anna Bridge	142:4eea097334d6	652
Anna Bridge	142:4eea097334d6	653	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Anna Bridge	142:4eea097334d6	654	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Anna Bridge	142:4eea097334d6	655
Anna Bridge	142:4eea097334d6	656	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Anna Bridge	142:4eea097334d6	657	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Anna Bridge	142:4eea097334d6	658
Anna Bridge	142:4eea097334d6	659	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Anna Bridge	142:4eea097334d6	660	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Anna Bridge	142:4eea097334d6	661
Anna Bridge	142:4eea097334d6	662	/@} end of group CMSIS_SCB /
Anna Bridge	142:4eea097334d6	663
Anna Bridge	142:4eea097334d6	664
Anna Bridge	142:4eea097334d6	665	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	666	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge	142:4eea097334d6	667	\brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge	142:4eea097334d6	668	@{
Anna Bridge	142:4eea097334d6	669	*/
Anna Bridge	142:4eea097334d6	670
Anna Bridge	142:4eea097334d6	671	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge	142:4eea097334d6	672	*/
Anna Bridge	142:4eea097334d6	673	typedef struct
Anna Bridge	142:4eea097334d6	674	{
Anna Bridge	142:4eea097334d6	675	uint32_t RESERVED0[1];
Anna Bridge	142:4eea097334d6	676	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Anna Bridge	142:4eea097334d6	677	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Anna Bridge	142:4eea097334d6	678	} SCnSCB_Type;
Anna Bridge	142:4eea097334d6	679
Anna Bridge	142:4eea097334d6	680	/* Interrupt Controller Type Register Definitions */
Anna Bridge	142:4eea097334d6	681	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Anna Bridge	142:4eea097334d6	682	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Anna Bridge	142:4eea097334d6	683
Anna Bridge	142:4eea097334d6	684	/* Auxiliary Control Register Definitions */
Anna Bridge	142:4eea097334d6	685	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
Anna Bridge	142:4eea097334d6	686	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
Anna Bridge	142:4eea097334d6	687
Anna Bridge	142:4eea097334d6	688	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
Anna Bridge	142:4eea097334d6	689	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
Anna Bridge	142:4eea097334d6	690
Anna Bridge	142:4eea097334d6	691	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Anna Bridge	142:4eea097334d6	692	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Anna Bridge	142:4eea097334d6	693
Anna Bridge	142:4eea097334d6	694	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Anna Bridge	142:4eea097334d6	695	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Anna Bridge	142:4eea097334d6	696
Anna Bridge	142:4eea097334d6	697	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Anna Bridge	142:4eea097334d6	698	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Anna Bridge	142:4eea097334d6	699
Anna Bridge	142:4eea097334d6	700	/@} end of group CMSIS_SCnotSCB /
Anna Bridge	142:4eea097334d6	701
Anna Bridge	142:4eea097334d6	702
Anna Bridge	142:4eea097334d6	703	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	704	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge	142:4eea097334d6	705	\brief Type definitions for the System Timer Registers.
Anna Bridge	142:4eea097334d6	706	@{
Anna Bridge	142:4eea097334d6	707	*/
Anna Bridge	142:4eea097334d6	708
Anna Bridge	142:4eea097334d6	709	/** \brief Structure type to access the System Timer (SysTick).
Anna Bridge	142:4eea097334d6	710	*/
Anna Bridge	142:4eea097334d6	711	typedef struct
Anna Bridge	142:4eea097334d6	712	{
Anna Bridge	142:4eea097334d6	713	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Anna Bridge	142:4eea097334d6	714	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Anna Bridge	142:4eea097334d6	715	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Anna Bridge	142:4eea097334d6	716	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Anna Bridge	142:4eea097334d6	717	} SysTick_Type;
Anna Bridge	142:4eea097334d6	718
Anna Bridge	142:4eea097334d6	719	/* SysTick Control / Status Register Definitions */
Anna Bridge	142:4eea097334d6	720	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Anna Bridge	142:4eea097334d6	721	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Anna Bridge	142:4eea097334d6	722
Anna Bridge	142:4eea097334d6	723	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Anna Bridge	142:4eea097334d6	724	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Anna Bridge	142:4eea097334d6	725
Anna Bridge	142:4eea097334d6	726	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Anna Bridge	142:4eea097334d6	727	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Anna Bridge	142:4eea097334d6	728
Anna Bridge	142:4eea097334d6	729	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Anna Bridge	142:4eea097334d6	730	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Anna Bridge	142:4eea097334d6	731
Anna Bridge	142:4eea097334d6	732	/* SysTick Reload Register Definitions */
Anna Bridge	142:4eea097334d6	733	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Anna Bridge	142:4eea097334d6	734	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Anna Bridge	142:4eea097334d6	735
Anna Bridge	142:4eea097334d6	736	/* SysTick Current Register Definitions */
Anna Bridge	142:4eea097334d6	737	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Anna Bridge	142:4eea097334d6	738	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Anna Bridge	142:4eea097334d6	739
Anna Bridge	142:4eea097334d6	740	/* SysTick Calibration Register Definitions */
Anna Bridge	142:4eea097334d6	741	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Anna Bridge	142:4eea097334d6	742	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Anna Bridge	142:4eea097334d6	743
Anna Bridge	142:4eea097334d6	744	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Anna Bridge	142:4eea097334d6	745	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Anna Bridge	142:4eea097334d6	746
Anna Bridge	142:4eea097334d6	747	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Anna Bridge	142:4eea097334d6	748	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Anna Bridge	142:4eea097334d6	749
Anna Bridge	142:4eea097334d6	750	/@} end of group CMSIS_SysTick /
Anna Bridge	142:4eea097334d6	751
Anna Bridge	142:4eea097334d6	752
Anna Bridge	142:4eea097334d6	753	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	754	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge	142:4eea097334d6	755	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge	142:4eea097334d6	756	@{
Anna Bridge	142:4eea097334d6	757	*/
Anna Bridge	142:4eea097334d6	758
Anna Bridge	142:4eea097334d6	759	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge	142:4eea097334d6	760	*/
Anna Bridge	142:4eea097334d6	761	typedef struct
Anna Bridge	142:4eea097334d6	762	{
Anna Bridge	142:4eea097334d6	763	__O union
Anna Bridge	142:4eea097334d6	764	{
Anna Bridge	142:4eea097334d6	765	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Anna Bridge	142:4eea097334d6	766	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Anna Bridge	142:4eea097334d6	767	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Anna Bridge	142:4eea097334d6	768	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Anna Bridge	142:4eea097334d6	769	uint32_t RESERVED0[864];
Anna Bridge	142:4eea097334d6	770	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Anna Bridge	142:4eea097334d6	771	uint32_t RESERVED1[15];
Anna Bridge	142:4eea097334d6	772	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Anna Bridge	142:4eea097334d6	773	uint32_t RESERVED2[15];
Anna Bridge	142:4eea097334d6	774	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Anna Bridge	142:4eea097334d6	775	uint32_t RESERVED3[29];
Anna Bridge	142:4eea097334d6	776	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Anna Bridge	142:4eea097334d6	777	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Anna Bridge	142:4eea097334d6	778	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Anna Bridge	142:4eea097334d6	779	uint32_t RESERVED4[43];
Anna Bridge	142:4eea097334d6	780	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Anna Bridge	142:4eea097334d6	781	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Anna Bridge	142:4eea097334d6	782	uint32_t RESERVED5[6];
Anna Bridge	142:4eea097334d6	783	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Anna Bridge	142:4eea097334d6	784	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Anna Bridge	142:4eea097334d6	785	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Anna Bridge	142:4eea097334d6	786	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Anna Bridge	142:4eea097334d6	787	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Anna Bridge	142:4eea097334d6	788	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Anna Bridge	142:4eea097334d6	789	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Anna Bridge	142:4eea097334d6	790	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Anna Bridge	142:4eea097334d6	791	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Anna Bridge	142:4eea097334d6	792	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Anna Bridge	142:4eea097334d6	793	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Anna Bridge	142:4eea097334d6	794	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Anna Bridge	142:4eea097334d6	795	} ITM_Type;
Anna Bridge	142:4eea097334d6	796
Anna Bridge	142:4eea097334d6	797	/* ITM Trace Privilege Register Definitions */
Anna Bridge	142:4eea097334d6	798	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Anna Bridge	142:4eea097334d6	799	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Anna Bridge	142:4eea097334d6	800
Anna Bridge	142:4eea097334d6	801	/* ITM Trace Control Register Definitions */
Anna Bridge	142:4eea097334d6	802	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Anna Bridge	142:4eea097334d6	803	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Anna Bridge	142:4eea097334d6	804
Anna Bridge	142:4eea097334d6	805	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Anna Bridge	142:4eea097334d6	806	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Anna Bridge	142:4eea097334d6	807
Anna Bridge	142:4eea097334d6	808	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Anna Bridge	142:4eea097334d6	809	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Anna Bridge	142:4eea097334d6	810
Anna Bridge	142:4eea097334d6	811	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Anna Bridge	142:4eea097334d6	812	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Anna Bridge	142:4eea097334d6	813
Anna Bridge	142:4eea097334d6	814	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Anna Bridge	142:4eea097334d6	815	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Anna Bridge	142:4eea097334d6	816
Anna Bridge	142:4eea097334d6	817	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Anna Bridge	142:4eea097334d6	818	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Anna Bridge	142:4eea097334d6	819
Anna Bridge	142:4eea097334d6	820	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Anna Bridge	142:4eea097334d6	821	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Anna Bridge	142:4eea097334d6	822
Anna Bridge	142:4eea097334d6	823	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Anna Bridge	142:4eea097334d6	824	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Anna Bridge	142:4eea097334d6	825
Anna Bridge	142:4eea097334d6	826	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Anna Bridge	142:4eea097334d6	827	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Anna Bridge	142:4eea097334d6	828
Anna Bridge	142:4eea097334d6	829	/* ITM Integration Write Register Definitions */
Anna Bridge	142:4eea097334d6	830	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Anna Bridge	142:4eea097334d6	831	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Anna Bridge	142:4eea097334d6	832
Anna Bridge	142:4eea097334d6	833	/* ITM Integration Read Register Definitions */
Anna Bridge	142:4eea097334d6	834	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Anna Bridge	142:4eea097334d6	835	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Anna Bridge	142:4eea097334d6	836
Anna Bridge	142:4eea097334d6	837	/* ITM Integration Mode Control Register Definitions */
Anna Bridge	142:4eea097334d6	838	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Anna Bridge	142:4eea097334d6	839	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Anna Bridge	142:4eea097334d6	840
Anna Bridge	142:4eea097334d6	841	/* ITM Lock Status Register Definitions */
Anna Bridge	142:4eea097334d6	842	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Anna Bridge	142:4eea097334d6	843	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Anna Bridge	142:4eea097334d6	844
Anna Bridge	142:4eea097334d6	845	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Anna Bridge	142:4eea097334d6	846	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Anna Bridge	142:4eea097334d6	847
Anna Bridge	142:4eea097334d6	848	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Anna Bridge	142:4eea097334d6	849	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Anna Bridge	142:4eea097334d6	850
Anna Bridge	142:4eea097334d6	851	/@}/ /* end of group CMSIS_ITM */
Anna Bridge	142:4eea097334d6	852
Anna Bridge	142:4eea097334d6	853
Anna Bridge	142:4eea097334d6	854	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	855	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge	142:4eea097334d6	856	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge	142:4eea097334d6	857	@{
Anna Bridge	142:4eea097334d6	858	*/
Anna Bridge	142:4eea097334d6	859
Anna Bridge	142:4eea097334d6	860	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge	142:4eea097334d6	861	*/
Anna Bridge	142:4eea097334d6	862	typedef struct
Anna Bridge	142:4eea097334d6	863	{
Anna Bridge	142:4eea097334d6	864	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Anna Bridge	142:4eea097334d6	865	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Anna Bridge	142:4eea097334d6	866	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Anna Bridge	142:4eea097334d6	867	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Anna Bridge	142:4eea097334d6	868	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Anna Bridge	142:4eea097334d6	869	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Anna Bridge	142:4eea097334d6	870	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Anna Bridge	142:4eea097334d6	871	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Anna Bridge	142:4eea097334d6	872	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Anna Bridge	142:4eea097334d6	873	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Anna Bridge	142:4eea097334d6	874	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Anna Bridge	142:4eea097334d6	875	uint32_t RESERVED0[1];
Anna Bridge	142:4eea097334d6	876	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Anna Bridge	142:4eea097334d6	877	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Anna Bridge	142:4eea097334d6	878	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Anna Bridge	142:4eea097334d6	879	uint32_t RESERVED1[1];
Anna Bridge	142:4eea097334d6	880	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Anna Bridge	142:4eea097334d6	881	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Anna Bridge	142:4eea097334d6	882	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Anna Bridge	142:4eea097334d6	883	uint32_t RESERVED2[1];
Anna Bridge	142:4eea097334d6	884	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Anna Bridge	142:4eea097334d6	885	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Anna Bridge	142:4eea097334d6	886	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Anna Bridge	142:4eea097334d6	887	} DWT_Type;
Anna Bridge	142:4eea097334d6	888
Anna Bridge	142:4eea097334d6	889	/* DWT Control Register Definitions */
Anna Bridge	142:4eea097334d6	890	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Anna Bridge	142:4eea097334d6	891	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Anna Bridge	142:4eea097334d6	892
Anna Bridge	142:4eea097334d6	893	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Anna Bridge	142:4eea097334d6	894	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Anna Bridge	142:4eea097334d6	895
Anna Bridge	142:4eea097334d6	896	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Anna Bridge	142:4eea097334d6	897	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Anna Bridge	142:4eea097334d6	898
Anna Bridge	142:4eea097334d6	899	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Anna Bridge	142:4eea097334d6	900	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Anna Bridge	142:4eea097334d6	901
Anna Bridge	142:4eea097334d6	902	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Anna Bridge	142:4eea097334d6	903	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Anna Bridge	142:4eea097334d6	904
Anna Bridge	142:4eea097334d6	905	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Anna Bridge	142:4eea097334d6	906	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Anna Bridge	142:4eea097334d6	907
Anna Bridge	142:4eea097334d6	908	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Anna Bridge	142:4eea097334d6	909	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Anna Bridge	142:4eea097334d6	910
Anna Bridge	142:4eea097334d6	911	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Anna Bridge	142:4eea097334d6	912	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Anna Bridge	142:4eea097334d6	913
Anna Bridge	142:4eea097334d6	914	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Anna Bridge	142:4eea097334d6	915	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Anna Bridge	142:4eea097334d6	916
Anna Bridge	142:4eea097334d6	917	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Anna Bridge	142:4eea097334d6	918	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Anna Bridge	142:4eea097334d6	919
Anna Bridge	142:4eea097334d6	920	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Anna Bridge	142:4eea097334d6	921	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Anna Bridge	142:4eea097334d6	922
Anna Bridge	142:4eea097334d6	923	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Anna Bridge	142:4eea097334d6	924	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Anna Bridge	142:4eea097334d6	925
Anna Bridge	142:4eea097334d6	926	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Anna Bridge	142:4eea097334d6	927	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Anna Bridge	142:4eea097334d6	928
Anna Bridge	142:4eea097334d6	929	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Anna Bridge	142:4eea097334d6	930	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Anna Bridge	142:4eea097334d6	931
Anna Bridge	142:4eea097334d6	932	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Anna Bridge	142:4eea097334d6	933	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Anna Bridge	142:4eea097334d6	934
Anna Bridge	142:4eea097334d6	935	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Anna Bridge	142:4eea097334d6	936	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Anna Bridge	142:4eea097334d6	937
Anna Bridge	142:4eea097334d6	938	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Anna Bridge	142:4eea097334d6	939	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Anna Bridge	142:4eea097334d6	940
Anna Bridge	142:4eea097334d6	941	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Anna Bridge	142:4eea097334d6	942	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Anna Bridge	142:4eea097334d6	943
Anna Bridge	142:4eea097334d6	944	/* DWT CPI Count Register Definitions */
Anna Bridge	142:4eea097334d6	945	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Anna Bridge	142:4eea097334d6	946	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Anna Bridge	142:4eea097334d6	947
Anna Bridge	142:4eea097334d6	948	/* DWT Exception Overhead Count Register Definitions */
Anna Bridge	142:4eea097334d6	949	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Anna Bridge	142:4eea097334d6	950	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Anna Bridge	142:4eea097334d6	951
Anna Bridge	142:4eea097334d6	952	/* DWT Sleep Count Register Definitions */
Anna Bridge	142:4eea097334d6	953	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Anna Bridge	142:4eea097334d6	954	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Anna Bridge	142:4eea097334d6	955
Anna Bridge	142:4eea097334d6	956	/* DWT LSU Count Register Definitions */
Anna Bridge	142:4eea097334d6	957	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Anna Bridge	142:4eea097334d6	958	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Anna Bridge	142:4eea097334d6	959
Anna Bridge	142:4eea097334d6	960	/* DWT Folded-instruction Count Register Definitions */
Anna Bridge	142:4eea097334d6	961	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Anna Bridge	142:4eea097334d6	962	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Anna Bridge	142:4eea097334d6	963
Anna Bridge	142:4eea097334d6	964	/* DWT Comparator Mask Register Definitions */
Anna Bridge	142:4eea097334d6	965	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Anna Bridge	142:4eea097334d6	966	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Anna Bridge	142:4eea097334d6	967
Anna Bridge	142:4eea097334d6	968	/* DWT Comparator Function Register Definitions */
Anna Bridge	142:4eea097334d6	969	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Anna Bridge	142:4eea097334d6	970	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Anna Bridge	142:4eea097334d6	971
Anna Bridge	142:4eea097334d6	972	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Anna Bridge	142:4eea097334d6	973	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Anna Bridge	142:4eea097334d6	974
Anna Bridge	142:4eea097334d6	975	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Anna Bridge	142:4eea097334d6	976	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Anna Bridge	142:4eea097334d6	977
Anna Bridge	142:4eea097334d6	978	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Anna Bridge	142:4eea097334d6	979	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Anna Bridge	142:4eea097334d6	980
Anna Bridge	142:4eea097334d6	981	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Anna Bridge	142:4eea097334d6	982	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Anna Bridge	142:4eea097334d6	983
Anna Bridge	142:4eea097334d6	984	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Anna Bridge	142:4eea097334d6	985	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Anna Bridge	142:4eea097334d6	986
Anna Bridge	142:4eea097334d6	987	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Anna Bridge	142:4eea097334d6	988	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Anna Bridge	142:4eea097334d6	989
Anna Bridge	142:4eea097334d6	990	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Anna Bridge	142:4eea097334d6	991	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Anna Bridge	142:4eea097334d6	992
Anna Bridge	142:4eea097334d6	993	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Anna Bridge	142:4eea097334d6	994	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Anna Bridge	142:4eea097334d6	995
Anna Bridge	142:4eea097334d6	996	/@}/ /* end of group CMSIS_DWT */
Anna Bridge	142:4eea097334d6	997
Anna Bridge	142:4eea097334d6	998
Anna Bridge	142:4eea097334d6	999	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	1000	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge	142:4eea097334d6	1001	\brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge	142:4eea097334d6	1002	@{
Anna Bridge	142:4eea097334d6	1003	*/
Anna Bridge	142:4eea097334d6	1004
Anna Bridge	142:4eea097334d6	1005	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge	142:4eea097334d6	1006	*/
Anna Bridge	142:4eea097334d6	1007	typedef struct
Anna Bridge	142:4eea097334d6	1008	{
Anna Bridge	142:4eea097334d6	1009	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Anna Bridge	142:4eea097334d6	1010	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Anna Bridge	142:4eea097334d6	1011	uint32_t RESERVED0[2];
Anna Bridge	142:4eea097334d6	1012	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Anna Bridge	142:4eea097334d6	1013	uint32_t RESERVED1[55];
Anna Bridge	142:4eea097334d6	1014	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Anna Bridge	142:4eea097334d6	1015	uint32_t RESERVED2[131];
Anna Bridge	142:4eea097334d6	1016	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Anna Bridge	142:4eea097334d6	1017	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Anna Bridge	142:4eea097334d6	1018	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Anna Bridge	142:4eea097334d6	1019	uint32_t RESERVED3[759];
Anna Bridge	142:4eea097334d6	1020	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Anna Bridge	142:4eea097334d6	1021	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Anna Bridge	142:4eea097334d6	1022	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Anna Bridge	142:4eea097334d6	1023	uint32_t RESERVED4[1];
Anna Bridge	142:4eea097334d6	1024	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Anna Bridge	142:4eea097334d6	1025	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Anna Bridge	142:4eea097334d6	1026	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Anna Bridge	142:4eea097334d6	1027	uint32_t RESERVED5[39];
Anna Bridge	142:4eea097334d6	1028	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Anna Bridge	142:4eea097334d6	1029	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Anna Bridge	142:4eea097334d6	1030	uint32_t RESERVED7[8];
Anna Bridge	142:4eea097334d6	1031	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Anna Bridge	142:4eea097334d6	1032	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Anna Bridge	142:4eea097334d6	1033	} TPI_Type;
Anna Bridge	142:4eea097334d6	1034
Anna Bridge	142:4eea097334d6	1035	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	142:4eea097334d6	1036	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Anna Bridge	142:4eea097334d6	1037	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Anna Bridge	142:4eea097334d6	1038
Anna Bridge	142:4eea097334d6	1039	/* TPI Selected Pin Protocol Register Definitions */
Anna Bridge	142:4eea097334d6	1040	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Anna Bridge	142:4eea097334d6	1041	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Anna Bridge	142:4eea097334d6	1042
Anna Bridge	142:4eea097334d6	1043	/* TPI Formatter and Flush Status Register Definitions */
Anna Bridge	142:4eea097334d6	1044	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Anna Bridge	142:4eea097334d6	1045	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Anna Bridge	142:4eea097334d6	1046
Anna Bridge	142:4eea097334d6	1047	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Anna Bridge	142:4eea097334d6	1048	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Anna Bridge	142:4eea097334d6	1049
Anna Bridge	142:4eea097334d6	1050	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Anna Bridge	142:4eea097334d6	1051	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Anna Bridge	142:4eea097334d6	1052
Anna Bridge	142:4eea097334d6	1053	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Anna Bridge	142:4eea097334d6	1054	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Anna Bridge	142:4eea097334d6	1055
Anna Bridge	142:4eea097334d6	1056	/* TPI Formatter and Flush Control Register Definitions */
Anna Bridge	142:4eea097334d6	1057	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Anna Bridge	142:4eea097334d6	1058	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Anna Bridge	142:4eea097334d6	1059
Anna Bridge	142:4eea097334d6	1060	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Anna Bridge	142:4eea097334d6	1061	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Anna Bridge	142:4eea097334d6	1062
Anna Bridge	142:4eea097334d6	1063	/* TPI TRIGGER Register Definitions */
Anna Bridge	142:4eea097334d6	1064	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Anna Bridge	142:4eea097334d6	1065	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Anna Bridge	142:4eea097334d6	1066
Anna Bridge	142:4eea097334d6	1067	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge	142:4eea097334d6	1068	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Anna Bridge	142:4eea097334d6	1069	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Anna Bridge	142:4eea097334d6	1070
Anna Bridge	142:4eea097334d6	1071	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Anna Bridge	142:4eea097334d6	1072	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Anna Bridge	142:4eea097334d6	1073
Anna Bridge	142:4eea097334d6	1074	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Anna Bridge	142:4eea097334d6	1075	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Anna Bridge	142:4eea097334d6	1076
Anna Bridge	142:4eea097334d6	1077	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Anna Bridge	142:4eea097334d6	1078	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Anna Bridge	142:4eea097334d6	1079
Anna Bridge	142:4eea097334d6	1080	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Anna Bridge	142:4eea097334d6	1081	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Anna Bridge	142:4eea097334d6	1082
Anna Bridge	142:4eea097334d6	1083	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Anna Bridge	142:4eea097334d6	1084	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Anna Bridge	142:4eea097334d6	1085
Anna Bridge	142:4eea097334d6	1086	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Anna Bridge	142:4eea097334d6	1087	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Anna Bridge	142:4eea097334d6	1088
Anna Bridge	142:4eea097334d6	1089	/* TPI ITATBCTR2 Register Definitions */
Anna Bridge	142:4eea097334d6	1090	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Anna Bridge	142:4eea097334d6	1091	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Anna Bridge	142:4eea097334d6	1092
Anna Bridge	142:4eea097334d6	1093	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge	142:4eea097334d6	1094	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Anna Bridge	142:4eea097334d6	1095	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Anna Bridge	142:4eea097334d6	1096
Anna Bridge	142:4eea097334d6	1097	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Anna Bridge	142:4eea097334d6	1098	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Anna Bridge	142:4eea097334d6	1099
Anna Bridge	142:4eea097334d6	1100	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Anna Bridge	142:4eea097334d6	1101	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Anna Bridge	142:4eea097334d6	1102
Anna Bridge	142:4eea097334d6	1103	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Anna Bridge	142:4eea097334d6	1104	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Anna Bridge	142:4eea097334d6	1105
Anna Bridge	142:4eea097334d6	1106	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Anna Bridge	142:4eea097334d6	1107	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Anna Bridge	142:4eea097334d6	1108
Anna Bridge	142:4eea097334d6	1109	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Anna Bridge	142:4eea097334d6	1110	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Anna Bridge	142:4eea097334d6	1111
Anna Bridge	142:4eea097334d6	1112	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Anna Bridge	142:4eea097334d6	1113	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Anna Bridge	142:4eea097334d6	1114
Anna Bridge	142:4eea097334d6	1115	/* TPI ITATBCTR0 Register Definitions */
Anna Bridge	142:4eea097334d6	1116	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Anna Bridge	142:4eea097334d6	1117	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Anna Bridge	142:4eea097334d6	1118
Anna Bridge	142:4eea097334d6	1119	/* TPI Integration Mode Control Register Definitions */
Anna Bridge	142:4eea097334d6	1120	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Anna Bridge	142:4eea097334d6	1121	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Anna Bridge	142:4eea097334d6	1122
Anna Bridge	142:4eea097334d6	1123	/* TPI DEVID Register Definitions */
Anna Bridge	142:4eea097334d6	1124	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Anna Bridge	142:4eea097334d6	1125	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Anna Bridge	142:4eea097334d6	1126
Anna Bridge	142:4eea097334d6	1127	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Anna Bridge	142:4eea097334d6	1128	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Anna Bridge	142:4eea097334d6	1129
Anna Bridge	142:4eea097334d6	1130	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Anna Bridge	142:4eea097334d6	1131	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Anna Bridge	142:4eea097334d6	1132
Anna Bridge	142:4eea097334d6	1133	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Anna Bridge	142:4eea097334d6	1134	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Anna Bridge	142:4eea097334d6	1135
Anna Bridge	142:4eea097334d6	1136	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Anna Bridge	142:4eea097334d6	1137	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Anna Bridge	142:4eea097334d6	1138
Anna Bridge	142:4eea097334d6	1139	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Anna Bridge	142:4eea097334d6	1140	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Anna Bridge	142:4eea097334d6	1141
Anna Bridge	142:4eea097334d6	1142	/* TPI DEVTYPE Register Definitions */
Anna Bridge	142:4eea097334d6	1143	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Anna Bridge	142:4eea097334d6	1144	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Anna Bridge	142:4eea097334d6	1145
Anna Bridge	142:4eea097334d6	1146	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Anna Bridge	142:4eea097334d6	1147	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Anna Bridge	142:4eea097334d6	1148
Anna Bridge	142:4eea097334d6	1149	/@}/ /* end of group CMSIS_TPI */
Anna Bridge	142:4eea097334d6	1150
Anna Bridge	142:4eea097334d6	1151
Anna Bridge	142:4eea097334d6	1152	#if (__MPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	1153	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	1154	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge	142:4eea097334d6	1155	\brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge	142:4eea097334d6	1156	@{
Anna Bridge	142:4eea097334d6	1157	*/
Anna Bridge	142:4eea097334d6	1158
Anna Bridge	142:4eea097334d6	1159	/** \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge	142:4eea097334d6	1160	*/
Anna Bridge	142:4eea097334d6	1161	typedef struct
Anna Bridge	142:4eea097334d6	1162	{
Anna Bridge	142:4eea097334d6	1163	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Anna Bridge	142:4eea097334d6	1164	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Anna Bridge	142:4eea097334d6	1165	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Anna Bridge	142:4eea097334d6	1166	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Anna Bridge	142:4eea097334d6	1167	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Anna Bridge	142:4eea097334d6	1168	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Anna Bridge	142:4eea097334d6	1169	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Anna Bridge	142:4eea097334d6	1170	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Anna Bridge	142:4eea097334d6	1171	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Anna Bridge	142:4eea097334d6	1172	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Anna Bridge	142:4eea097334d6	1173	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Anna Bridge	142:4eea097334d6	1174	} MPU_Type;
Anna Bridge	142:4eea097334d6	1175
Anna Bridge	142:4eea097334d6	1176	/* MPU Type Register */
Anna Bridge	142:4eea097334d6	1177	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Anna Bridge	142:4eea097334d6	1178	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Anna Bridge	142:4eea097334d6	1179
Anna Bridge	142:4eea097334d6	1180	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Anna Bridge	142:4eea097334d6	1181	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Anna Bridge	142:4eea097334d6	1182
Anna Bridge	142:4eea097334d6	1183	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Anna Bridge	142:4eea097334d6	1184	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Anna Bridge	142:4eea097334d6	1185
Anna Bridge	142:4eea097334d6	1186	/* MPU Control Register */
Anna Bridge	142:4eea097334d6	1187	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Anna Bridge	142:4eea097334d6	1188	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Anna Bridge	142:4eea097334d6	1189
Anna Bridge	142:4eea097334d6	1190	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Anna Bridge	142:4eea097334d6	1191	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Anna Bridge	142:4eea097334d6	1192
Anna Bridge	142:4eea097334d6	1193	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Anna Bridge	142:4eea097334d6	1194	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Anna Bridge	142:4eea097334d6	1195
Anna Bridge	142:4eea097334d6	1196	/* MPU Region Number Register */
Anna Bridge	142:4eea097334d6	1197	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Anna Bridge	142:4eea097334d6	1198	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Anna Bridge	142:4eea097334d6	1199
Anna Bridge	142:4eea097334d6	1200	/* MPU Region Base Address Register */
Anna Bridge	142:4eea097334d6	1201	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Anna Bridge	142:4eea097334d6	1202	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Anna Bridge	142:4eea097334d6	1203
Anna Bridge	142:4eea097334d6	1204	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Anna Bridge	142:4eea097334d6	1205	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Anna Bridge	142:4eea097334d6	1206
Anna Bridge	142:4eea097334d6	1207	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Anna Bridge	142:4eea097334d6	1208	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Anna Bridge	142:4eea097334d6	1209
Anna Bridge	142:4eea097334d6	1210	/* MPU Region Attribute and Size Register */
Anna Bridge	142:4eea097334d6	1211	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Anna Bridge	142:4eea097334d6	1212	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Anna Bridge	142:4eea097334d6	1213
Anna Bridge	142:4eea097334d6	1214	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Anna Bridge	142:4eea097334d6	1215	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Anna Bridge	142:4eea097334d6	1216
Anna Bridge	142:4eea097334d6	1217	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Anna Bridge	142:4eea097334d6	1218	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Anna Bridge	142:4eea097334d6	1219
Anna Bridge	142:4eea097334d6	1220	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Anna Bridge	142:4eea097334d6	1221	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Anna Bridge	142:4eea097334d6	1222
Anna Bridge	142:4eea097334d6	1223	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Anna Bridge	142:4eea097334d6	1224	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Anna Bridge	142:4eea097334d6	1225
Anna Bridge	142:4eea097334d6	1226	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Anna Bridge	142:4eea097334d6	1227	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Anna Bridge	142:4eea097334d6	1228
Anna Bridge	142:4eea097334d6	1229	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Anna Bridge	142:4eea097334d6	1230	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Anna Bridge	142:4eea097334d6	1231
Anna Bridge	142:4eea097334d6	1232	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Anna Bridge	142:4eea097334d6	1233	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Anna Bridge	142:4eea097334d6	1234
Anna Bridge	142:4eea097334d6	1235	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Anna Bridge	142:4eea097334d6	1236	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Anna Bridge	142:4eea097334d6	1237
Anna Bridge	142:4eea097334d6	1238	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Anna Bridge	142:4eea097334d6	1239	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Anna Bridge	142:4eea097334d6	1240
Anna Bridge	142:4eea097334d6	1241	/@} end of group CMSIS_MPU /
Anna Bridge	142:4eea097334d6	1242	#endif
Anna Bridge	142:4eea097334d6	1243
Anna Bridge	142:4eea097334d6	1244
Anna Bridge	142:4eea097334d6	1245	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	1246	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	1247	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Anna Bridge	142:4eea097334d6	1248	\brief Type definitions for the Floating Point Unit (FPU)
Anna Bridge	142:4eea097334d6	1249	@{
Anna Bridge	142:4eea097334d6	1250	*/
Anna Bridge	142:4eea097334d6	1251
Anna Bridge	142:4eea097334d6	1252	/** \brief Structure type to access the Floating Point Unit (FPU).
Anna Bridge	142:4eea097334d6	1253	*/
Anna Bridge	142:4eea097334d6	1254	typedef struct
Anna Bridge	142:4eea097334d6	1255	{
Anna Bridge	142:4eea097334d6	1256	uint32_t RESERVED0[1];
Anna Bridge	142:4eea097334d6	1257	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Anna Bridge	142:4eea097334d6	1258	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Anna Bridge	142:4eea097334d6	1259	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Anna Bridge	142:4eea097334d6	1260	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Anna Bridge	142:4eea097334d6	1261	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Anna Bridge	142:4eea097334d6	1262	} FPU_Type;
Anna Bridge	142:4eea097334d6	1263
Anna Bridge	142:4eea097334d6	1264	/* Floating-Point Context Control Register */
Anna Bridge	142:4eea097334d6	1265	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Anna Bridge	142:4eea097334d6	1266	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Anna Bridge	142:4eea097334d6	1267
Anna Bridge	142:4eea097334d6	1268	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Anna Bridge	142:4eea097334d6	1269	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Anna Bridge	142:4eea097334d6	1270
Anna Bridge	142:4eea097334d6	1271	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Anna Bridge	142:4eea097334d6	1272	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Anna Bridge	142:4eea097334d6	1273
Anna Bridge	142:4eea097334d6	1274	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Anna Bridge	142:4eea097334d6	1275	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Anna Bridge	142:4eea097334d6	1276
Anna Bridge	142:4eea097334d6	1277	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Anna Bridge	142:4eea097334d6	1278	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Anna Bridge	142:4eea097334d6	1279
Anna Bridge	142:4eea097334d6	1280	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Anna Bridge	142:4eea097334d6	1281	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Anna Bridge	142:4eea097334d6	1282
Anna Bridge	142:4eea097334d6	1283	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Anna Bridge	142:4eea097334d6	1284	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Anna Bridge	142:4eea097334d6	1285
Anna Bridge	142:4eea097334d6	1286	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Anna Bridge	142:4eea097334d6	1287	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Anna Bridge	142:4eea097334d6	1288
Anna Bridge	142:4eea097334d6	1289	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Anna Bridge	142:4eea097334d6	1290	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Anna Bridge	142:4eea097334d6	1291
Anna Bridge	142:4eea097334d6	1292	/* Floating-Point Context Address Register */
Anna Bridge	142:4eea097334d6	1293	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Anna Bridge	142:4eea097334d6	1294	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Anna Bridge	142:4eea097334d6	1295
Anna Bridge	142:4eea097334d6	1296	/* Floating-Point Default Status Control Register */
Anna Bridge	142:4eea097334d6	1297	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Anna Bridge	142:4eea097334d6	1298	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Anna Bridge	142:4eea097334d6	1299
Anna Bridge	142:4eea097334d6	1300	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Anna Bridge	142:4eea097334d6	1301	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Anna Bridge	142:4eea097334d6	1302
Anna Bridge	142:4eea097334d6	1303	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Anna Bridge	142:4eea097334d6	1304	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Anna Bridge	142:4eea097334d6	1305
Anna Bridge	142:4eea097334d6	1306	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Anna Bridge	142:4eea097334d6	1307	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Anna Bridge	142:4eea097334d6	1308
Anna Bridge	142:4eea097334d6	1309	/* Media and FP Feature Register 0 */
Anna Bridge	142:4eea097334d6	1310	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Anna Bridge	142:4eea097334d6	1311	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Anna Bridge	142:4eea097334d6	1312
Anna Bridge	142:4eea097334d6	1313	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Anna Bridge	142:4eea097334d6	1314	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Anna Bridge	142:4eea097334d6	1315
Anna Bridge	142:4eea097334d6	1316	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Anna Bridge	142:4eea097334d6	1317	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Anna Bridge	142:4eea097334d6	1318
Anna Bridge	142:4eea097334d6	1319	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Anna Bridge	142:4eea097334d6	1320	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Anna Bridge	142:4eea097334d6	1321
Anna Bridge	142:4eea097334d6	1322	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Anna Bridge	142:4eea097334d6	1323	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Anna Bridge	142:4eea097334d6	1324
Anna Bridge	142:4eea097334d6	1325	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Anna Bridge	142:4eea097334d6	1326	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Anna Bridge	142:4eea097334d6	1327
Anna Bridge	142:4eea097334d6	1328	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Anna Bridge	142:4eea097334d6	1329	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Anna Bridge	142:4eea097334d6	1330
Anna Bridge	142:4eea097334d6	1331	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Anna Bridge	142:4eea097334d6	1332	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Anna Bridge	142:4eea097334d6	1333
Anna Bridge	142:4eea097334d6	1334	/* Media and FP Feature Register 1 */
Anna Bridge	142:4eea097334d6	1335	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Anna Bridge	142:4eea097334d6	1336	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Anna Bridge	142:4eea097334d6	1337
Anna Bridge	142:4eea097334d6	1338	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Anna Bridge	142:4eea097334d6	1339	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Anna Bridge	142:4eea097334d6	1340
Anna Bridge	142:4eea097334d6	1341	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Anna Bridge	142:4eea097334d6	1342	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Anna Bridge	142:4eea097334d6	1343
Anna Bridge	142:4eea097334d6	1344	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Anna Bridge	142:4eea097334d6	1345	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Anna Bridge	142:4eea097334d6	1346
Anna Bridge	142:4eea097334d6	1347	/@} end of group CMSIS_FPU /
Anna Bridge	142:4eea097334d6	1348	#endif
Anna Bridge	142:4eea097334d6	1349
Anna Bridge	142:4eea097334d6	1350
Anna Bridge	142:4eea097334d6	1351	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	1352	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge	142:4eea097334d6	1353	\brief Type definitions for the Core Debug Registers
Anna Bridge	142:4eea097334d6	1354	@{
Anna Bridge	142:4eea097334d6	1355	*/
Anna Bridge	142:4eea097334d6	1356
Anna Bridge	142:4eea097334d6	1357	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge	142:4eea097334d6	1358	*/
Anna Bridge	142:4eea097334d6	1359	typedef struct
Anna Bridge	142:4eea097334d6	1360	{
Anna Bridge	142:4eea097334d6	1361	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Anna Bridge	142:4eea097334d6	1362	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Anna Bridge	142:4eea097334d6	1363	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Anna Bridge	142:4eea097334d6	1364	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Anna Bridge	142:4eea097334d6	1365	} CoreDebug_Type;
Anna Bridge	142:4eea097334d6	1366
Anna Bridge	142:4eea097334d6	1367	/* Debug Halting Control and Status Register */
Anna Bridge	142:4eea097334d6	1368	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Anna Bridge	142:4eea097334d6	1369	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Anna Bridge	142:4eea097334d6	1370
Anna Bridge	142:4eea097334d6	1371	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Anna Bridge	142:4eea097334d6	1372	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Anna Bridge	142:4eea097334d6	1373
Anna Bridge	142:4eea097334d6	1374	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Anna Bridge	142:4eea097334d6	1375	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Anna Bridge	142:4eea097334d6	1376
Anna Bridge	142:4eea097334d6	1377	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Anna Bridge	142:4eea097334d6	1378	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Anna Bridge	142:4eea097334d6	1379
Anna Bridge	142:4eea097334d6	1380	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Anna Bridge	142:4eea097334d6	1381	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Anna Bridge	142:4eea097334d6	1382
Anna Bridge	142:4eea097334d6	1383	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Anna Bridge	142:4eea097334d6	1384	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Anna Bridge	142:4eea097334d6	1385
Anna Bridge	142:4eea097334d6	1386	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Anna Bridge	142:4eea097334d6	1387	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Anna Bridge	142:4eea097334d6	1388
Anna Bridge	142:4eea097334d6	1389	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Anna Bridge	142:4eea097334d6	1390	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Anna Bridge	142:4eea097334d6	1391
Anna Bridge	142:4eea097334d6	1392	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Anna Bridge	142:4eea097334d6	1393	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Anna Bridge	142:4eea097334d6	1394
Anna Bridge	142:4eea097334d6	1395	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Anna Bridge	142:4eea097334d6	1396	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Anna Bridge	142:4eea097334d6	1397
Anna Bridge	142:4eea097334d6	1398	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Anna Bridge	142:4eea097334d6	1399	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Anna Bridge	142:4eea097334d6	1400
Anna Bridge	142:4eea097334d6	1401	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Anna Bridge	142:4eea097334d6	1402	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Anna Bridge	142:4eea097334d6	1403
Anna Bridge	142:4eea097334d6	1404	/* Debug Core Register Selector Register */
Anna Bridge	142:4eea097334d6	1405	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Anna Bridge	142:4eea097334d6	1406	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Anna Bridge	142:4eea097334d6	1407
Anna Bridge	142:4eea097334d6	1408	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Anna Bridge	142:4eea097334d6	1409	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Anna Bridge	142:4eea097334d6	1410
Anna Bridge	142:4eea097334d6	1411	/* Debug Exception and Monitor Control Register */
Anna Bridge	142:4eea097334d6	1412	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Anna Bridge	142:4eea097334d6	1413	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Anna Bridge	142:4eea097334d6	1414
Anna Bridge	142:4eea097334d6	1415	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Anna Bridge	142:4eea097334d6	1416	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Anna Bridge	142:4eea097334d6	1417
Anna Bridge	142:4eea097334d6	1418	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Anna Bridge	142:4eea097334d6	1419	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Anna Bridge	142:4eea097334d6	1420
Anna Bridge	142:4eea097334d6	1421	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Anna Bridge	142:4eea097334d6	1422	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Anna Bridge	142:4eea097334d6	1423
Anna Bridge	142:4eea097334d6	1424	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Anna Bridge	142:4eea097334d6	1425	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Anna Bridge	142:4eea097334d6	1426
Anna Bridge	142:4eea097334d6	1427	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Anna Bridge	142:4eea097334d6	1428	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Anna Bridge	142:4eea097334d6	1429
Anna Bridge	142:4eea097334d6	1430	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Anna Bridge	142:4eea097334d6	1431	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Anna Bridge	142:4eea097334d6	1432
Anna Bridge	142:4eea097334d6	1433	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Anna Bridge	142:4eea097334d6	1434	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Anna Bridge	142:4eea097334d6	1435
Anna Bridge	142:4eea097334d6	1436	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Anna Bridge	142:4eea097334d6	1437	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Anna Bridge	142:4eea097334d6	1438
Anna Bridge	142:4eea097334d6	1439	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Anna Bridge	142:4eea097334d6	1440	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Anna Bridge	142:4eea097334d6	1441
Anna Bridge	142:4eea097334d6	1442	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Anna Bridge	142:4eea097334d6	1443	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Anna Bridge	142:4eea097334d6	1444
Anna Bridge	142:4eea097334d6	1445	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Anna Bridge	142:4eea097334d6	1446	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Anna Bridge	142:4eea097334d6	1447
Anna Bridge	142:4eea097334d6	1448	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Anna Bridge	142:4eea097334d6	1449	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Anna Bridge	142:4eea097334d6	1450
Anna Bridge	142:4eea097334d6	1451	/@} end of group CMSIS_CoreDebug /
Anna Bridge	142:4eea097334d6	1452
Anna Bridge	142:4eea097334d6	1453
Anna Bridge	142:4eea097334d6	1454	/** \ingroup CMSIS_core_register
Anna Bridge	142:4eea097334d6	1455	\defgroup CMSIS_core_base Core Definitions
Anna Bridge	142:4eea097334d6	1456	\brief Definitions for base addresses, unions, and structures.
Anna Bridge	142:4eea097334d6	1457	@{
Anna Bridge	142:4eea097334d6	1458	*/
Anna Bridge	142:4eea097334d6	1459
Anna Bridge	142:4eea097334d6	1460	/* Memory mapping of Cortex-M4 Hardware */
Anna Bridge	142:4eea097334d6	1461	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Anna Bridge	142:4eea097334d6	1462	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Anna Bridge	142:4eea097334d6	1463	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Anna Bridge	142:4eea097334d6	1464	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Anna Bridge	142:4eea097334d6	1465	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Anna Bridge	142:4eea097334d6	1466	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Anna Bridge	142:4eea097334d6	1467	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Anna Bridge	142:4eea097334d6	1468	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Anna Bridge	142:4eea097334d6	1469
Anna Bridge	142:4eea097334d6	1470	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Anna Bridge	142:4eea097334d6	1471	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Anna Bridge	142:4eea097334d6	1472	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Anna Bridge	142:4eea097334d6	1473	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Anna Bridge	142:4eea097334d6	1474	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Anna Bridge	142:4eea097334d6	1475	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Anna Bridge	142:4eea097334d6	1476	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Anna Bridge	142:4eea097334d6	1477	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Anna Bridge	142:4eea097334d6	1478
Anna Bridge	142:4eea097334d6	1479	#if (__MPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	1480	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Anna Bridge	142:4eea097334d6	1481	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Anna Bridge	142:4eea097334d6	1482	#endif
Anna Bridge	142:4eea097334d6	1483
Anna Bridge	142:4eea097334d6	1484	#if (__FPU_PRESENT == 1)
Anna Bridge	142:4eea097334d6	1485	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Anna Bridge	142:4eea097334d6	1486	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Anna Bridge	142:4eea097334d6	1487	#endif
Anna Bridge	142:4eea097334d6	1488
Anna Bridge	142:4eea097334d6	1489	/@} /
Anna Bridge	142:4eea097334d6	1490
Anna Bridge	142:4eea097334d6	1491
Anna Bridge	142:4eea097334d6	1492
Anna Bridge	142:4eea097334d6	1493	/*******************************************************************************
Anna Bridge	142:4eea097334d6	1494	* Hardware Abstraction Layer
Anna Bridge	142:4eea097334d6	1495	Core Function Interface contains:
Anna Bridge	142:4eea097334d6	1496	- Core NVIC Functions
Anna Bridge	142:4eea097334d6	1497	- Core SysTick Functions
Anna Bridge	142:4eea097334d6	1498	- Core Debug Functions
Anna Bridge	142:4eea097334d6	1499	- Core Register Access Functions
Anna Bridge	142:4eea097334d6	1500	******************************************************************************/
Anna Bridge	142:4eea097334d6	1501	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge	142:4eea097334d6	1502	*/
Anna Bridge	142:4eea097334d6	1503
Anna Bridge	142:4eea097334d6	1504
Anna Bridge	142:4eea097334d6	1505
Anna Bridge	142:4eea097334d6	1506	/* ########################## NVIC functions #################################### */
Anna Bridge	142:4eea097334d6	1507	/** \ingroup CMSIS_Core_FunctionInterface
Anna Bridge	142:4eea097334d6	1508	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge	142:4eea097334d6	1509	\brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge	142:4eea097334d6	1510	@{
Anna Bridge	142:4eea097334d6	1511	*/
Anna Bridge	142:4eea097334d6	1512
Anna Bridge	142:4eea097334d6	1513	#ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge	142:4eea097334d6	1514	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	142:4eea097334d6	1515	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge	142:4eea097334d6	1516	#endif
Anna Bridge	142:4eea097334d6	1517	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	142:4eea097334d6	1518	#else
Anna Bridge	142:4eea097334d6	1519	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge	142:4eea097334d6	1520	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge	142:4eea097334d6	1521	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge	142:4eea097334d6	1522	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge	142:4eea097334d6	1523	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge	142:4eea097334d6	1524	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge	142:4eea097334d6	1525	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge	142:4eea097334d6	1526	#define NVIC_GetActive __NVIC_GetActive
Anna Bridge	142:4eea097334d6	1527	#define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge	142:4eea097334d6	1528	#define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge	142:4eea097334d6	1529	#define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge	142:4eea097334d6	1530	#endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge	142:4eea097334d6	1531
Anna Bridge	142:4eea097334d6	1532	#ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge	142:4eea097334d6	1533	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	142:4eea097334d6	1534	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge	142:4eea097334d6	1535	#endif
Anna Bridge	142:4eea097334d6	1536	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	142:4eea097334d6	1537	#else
Anna Bridge	142:4eea097334d6	1538	#define NVIC_SetVector __NVIC_SetVector
Anna Bridge	142:4eea097334d6	1539	#define NVIC_GetVector __NVIC_GetVector
Anna Bridge	142:4eea097334d6	1540	#endif /* CMSIS_VECTAB_VIRTUAL */
Anna Bridge	142:4eea097334d6	1541
Anna Bridge	142:4eea097334d6	1542
Anna Bridge	142:4eea097334d6	1543	/** \brief Set Priority Grouping
Anna Bridge	142:4eea097334d6	1544
Anna Bridge	142:4eea097334d6	1545	The function sets the priority grouping field using the required unlock sequence.
Anna Bridge	142:4eea097334d6	1546	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	142:4eea097334d6	1547	Only values from 0..7 are used.
Anna Bridge	142:4eea097334d6	1548	In case of a conflict between priority grouping and available
Anna Bridge	142:4eea097334d6	1549	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	142:4eea097334d6	1550
Anna Bridge	142:4eea097334d6	1551	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	142:4eea097334d6	1552	*/
Anna Bridge	142:4eea097334d6	1553	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge	142:4eea097334d6	1554	{
Anna Bridge	142:4eea097334d6	1555	uint32_t reg_value;
Anna Bridge	142:4eea097334d6	1556	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	142:4eea097334d6	1557
Anna Bridge	142:4eea097334d6	1558	reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge	142:4eea097334d6	1559	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	142:4eea097334d6	1560	reg_value = (reg_value \|
Anna Bridge	142:4eea097334d6	1561	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	142:4eea097334d6	1562	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Anna Bridge	142:4eea097334d6	1563	SCB->AIRCR = reg_value;
Anna Bridge	142:4eea097334d6	1564	}
Anna Bridge	142:4eea097334d6	1565
Anna Bridge	142:4eea097334d6	1566
Anna Bridge	142:4eea097334d6	1567	/** \brief Get Priority Grouping
Anna Bridge	142:4eea097334d6	1568
Anna Bridge	142:4eea097334d6	1569	The function reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge	142:4eea097334d6	1570
Anna Bridge	142:4eea097334d6	1571	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	142:4eea097334d6	1572	*/
Anna Bridge	142:4eea097334d6	1573	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge	142:4eea097334d6	1574	{
Anna Bridge	142:4eea097334d6	1575	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	142:4eea097334d6	1576	}
Anna Bridge	142:4eea097334d6	1577
Anna Bridge	142:4eea097334d6	1578
Anna Bridge	142:4eea097334d6	1579	/** \brief Enable External Interrupt
Anna Bridge	142:4eea097334d6	1580
Anna Bridge	142:4eea097334d6	1581	The function enables a device-specific interrupt in the NVIC interrupt controller.
Anna Bridge	142:4eea097334d6	1582
Anna Bridge	142:4eea097334d6	1583	\param [in] IRQn External interrupt number. Value cannot be negative.
Anna Bridge	142:4eea097334d6	1584	*/
Anna Bridge	142:4eea097334d6	1585	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1586	{
Anna Bridge	142:4eea097334d6	1587	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge	142:4eea097334d6	1588	}
Anna Bridge	142:4eea097334d6	1589
Anna Bridge	142:4eea097334d6	1590
Anna Bridge	142:4eea097334d6	1591	/** \brief Disable External Interrupt
Anna Bridge	142:4eea097334d6	1592
Anna Bridge	142:4eea097334d6	1593	The function disables a device-specific interrupt in the NVIC interrupt controller.
Anna Bridge	142:4eea097334d6	1594
Anna Bridge	142:4eea097334d6	1595	\param [in] IRQn External interrupt number. Value cannot be negative.
Anna Bridge	142:4eea097334d6	1596	*/
Anna Bridge	142:4eea097334d6	1597	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1598	{
Anna Bridge	142:4eea097334d6	1599	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge	142:4eea097334d6	1600	__DSB();
Anna Bridge	142:4eea097334d6	1601	__ISB();
Anna Bridge	142:4eea097334d6	1602	}
Anna Bridge	142:4eea097334d6	1603
Anna Bridge	142:4eea097334d6	1604
Anna Bridge	142:4eea097334d6	1605	/** \brief Get Pending Interrupt
Anna Bridge	142:4eea097334d6	1606
Anna Bridge	142:4eea097334d6	1607	The function reads the pending register in the NVIC and returns the pending bit
Anna Bridge	142:4eea097334d6	1608	for the specified interrupt.
Anna Bridge	142:4eea097334d6	1609
Anna Bridge	142:4eea097334d6	1610	\param [in] IRQn Interrupt number.
Anna Bridge	142:4eea097334d6	1611
Anna Bridge	142:4eea097334d6	1612	\return 0 Interrupt status is not pending.
Anna Bridge	142:4eea097334d6	1613	\return 1 Interrupt status is pending.
Anna Bridge	142:4eea097334d6	1614	*/
Anna Bridge	142:4eea097334d6	1615	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1616	{
Anna Bridge	142:4eea097334d6	1617	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	142:4eea097334d6	1618	}
Anna Bridge	142:4eea097334d6	1619
Anna Bridge	142:4eea097334d6	1620
Anna Bridge	142:4eea097334d6	1621	/** \brief Set Pending Interrupt
Anna Bridge	142:4eea097334d6	1622
Anna Bridge	142:4eea097334d6	1623	The function sets the pending bit of an external interrupt.
Anna Bridge	142:4eea097334d6	1624
Anna Bridge	142:4eea097334d6	1625	\param [in] IRQn Interrupt number. Value cannot be negative.
Anna Bridge	142:4eea097334d6	1626	*/
Anna Bridge	142:4eea097334d6	1627	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1628	{
Anna Bridge	142:4eea097334d6	1629	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge	142:4eea097334d6	1630	}
Anna Bridge	142:4eea097334d6	1631
Anna Bridge	142:4eea097334d6	1632
Anna Bridge	142:4eea097334d6	1633	/** \brief Clear Pending Interrupt
Anna Bridge	142:4eea097334d6	1634
Anna Bridge	142:4eea097334d6	1635	The function clears the pending bit of an external interrupt.
Anna Bridge	142:4eea097334d6	1636
Anna Bridge	142:4eea097334d6	1637	\param [in] IRQn External interrupt number. Value cannot be negative.
Anna Bridge	142:4eea097334d6	1638	*/
Anna Bridge	142:4eea097334d6	1639	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1640	{
Anna Bridge	142:4eea097334d6	1641	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge	142:4eea097334d6	1642	}
Anna Bridge	142:4eea097334d6	1643
Anna Bridge	142:4eea097334d6	1644
Anna Bridge	142:4eea097334d6	1645	/** \brief Get Active Interrupt
Anna Bridge	142:4eea097334d6	1646
Anna Bridge	142:4eea097334d6	1647	The function reads the active register in NVIC and returns the active bit.
Anna Bridge	142:4eea097334d6	1648
Anna Bridge	142:4eea097334d6	1649	\param [in] IRQn Interrupt number.
Anna Bridge	142:4eea097334d6	1650
Anna Bridge	142:4eea097334d6	1651	\return 0 Interrupt status is not active.
Anna Bridge	142:4eea097334d6	1652	\return 1 Interrupt status is active.
Anna Bridge	142:4eea097334d6	1653	*/
Anna Bridge	142:4eea097334d6	1654	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1655	{
Anna Bridge	142:4eea097334d6	1656	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	142:4eea097334d6	1657	}
Anna Bridge	142:4eea097334d6	1658
Anna Bridge	142:4eea097334d6	1659
Anna Bridge	142:4eea097334d6	1660	/** \brief Set Interrupt Priority
Anna Bridge	142:4eea097334d6	1661
Anna Bridge	142:4eea097334d6	1662	The function sets the priority of an interrupt.
Anna Bridge	142:4eea097334d6	1663
Anna Bridge	142:4eea097334d6	1664	\note The priority cannot be set for every core interrupt.
Anna Bridge	142:4eea097334d6	1665
Anna Bridge	142:4eea097334d6	1666	\param [in] IRQn Interrupt number.
Anna Bridge	142:4eea097334d6	1667	\param [in] priority Priority to set.
Anna Bridge	142:4eea097334d6	1668	*/
Anna Bridge	142:4eea097334d6	1669	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	142:4eea097334d6	1670	{
Anna Bridge	142:4eea097334d6	1671	if((int32_t)IRQn < 0) {
Anna Bridge	142:4eea097334d6	1672	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	142:4eea097334d6	1673	}
Anna Bridge	142:4eea097334d6	1674	else {
Anna Bridge	142:4eea097334d6	1675	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	142:4eea097334d6	1676	}
Anna Bridge	142:4eea097334d6	1677	}
Anna Bridge	142:4eea097334d6	1678
Anna Bridge	142:4eea097334d6	1679
Anna Bridge	142:4eea097334d6	1680	/** \brief Get Interrupt Priority
Anna Bridge	142:4eea097334d6	1681
Anna Bridge	142:4eea097334d6	1682	The function reads the priority of an interrupt. The interrupt
Anna Bridge	142:4eea097334d6	1683	number can be positive to specify an external (device specific)
Anna Bridge	142:4eea097334d6	1684	interrupt, or negative to specify an internal (core) interrupt.
Anna Bridge	142:4eea097334d6	1685
Anna Bridge	142:4eea097334d6	1686
Anna Bridge	142:4eea097334d6	1687	\param [in] IRQn Interrupt number.
Anna Bridge	142:4eea097334d6	1688	\return Interrupt Priority. Value is aligned automatically to the implemented
Anna Bridge	142:4eea097334d6	1689	priority bits of the microcontroller.
Anna Bridge	142:4eea097334d6	1690	*/
Anna Bridge	142:4eea097334d6	1691	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge	142:4eea097334d6	1692	{
Anna Bridge	142:4eea097334d6	1693
Anna Bridge	142:4eea097334d6	1694	if((int32_t)IRQn < 0) {
Anna Bridge	142:4eea097334d6	1695	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Anna Bridge	142:4eea097334d6	1696	}
Anna Bridge	142:4eea097334d6	1697	else {
Anna Bridge	142:4eea097334d6	1698	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Anna Bridge	142:4eea097334d6	1699	}
Anna Bridge	142:4eea097334d6	1700	}
Anna Bridge	142:4eea097334d6	1701
Anna Bridge	142:4eea097334d6	1702
Anna Bridge	142:4eea097334d6	1703	/** \brief Encode Priority
Anna Bridge	142:4eea097334d6	1704
Anna Bridge	142:4eea097334d6	1705	The function encodes the priority for an interrupt with the given priority group,
Anna Bridge	142:4eea097334d6	1706	preemptive priority value, and subpriority value.
Anna Bridge	142:4eea097334d6	1707	In case of a conflict between priority grouping and available
Anna Bridge	142:4eea097334d6	1708	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	142:4eea097334d6	1709
Anna Bridge	142:4eea097334d6	1710	\param [in] PriorityGroup Used priority group.
Anna Bridge	142:4eea097334d6	1711	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	142:4eea097334d6	1712	\param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge	142:4eea097334d6	1713	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge	142:4eea097334d6	1714	*/
Anna Bridge	142:4eea097334d6	1715	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge	142:4eea097334d6	1716	{
Anna Bridge	142:4eea097334d6	1717	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	142:4eea097334d6	1718	uint32_t PreemptPriorityBits;
Anna Bridge	142:4eea097334d6	1719	uint32_t SubPriorityBits;
Anna Bridge	142:4eea097334d6	1720
Anna Bridge	142:4eea097334d6	1721	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	142:4eea097334d6	1722	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	142:4eea097334d6	1723
Anna Bridge	142:4eea097334d6	1724	return (
Anna Bridge	142:4eea097334d6	1725	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Anna Bridge	142:4eea097334d6	1726	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge	142:4eea097334d6	1727	);
Anna Bridge	142:4eea097334d6	1728	}
Anna Bridge	142:4eea097334d6	1729
Anna Bridge	142:4eea097334d6	1730
Anna Bridge	142:4eea097334d6	1731	/** \brief Decode Priority
Anna Bridge	142:4eea097334d6	1732
Anna Bridge	142:4eea097334d6	1733	The function decodes an interrupt priority value with a given priority group to
Anna Bridge	142:4eea097334d6	1734	preemptive priority value and subpriority value.
Anna Bridge	142:4eea097334d6	1735	In case of a conflict between priority grouping and available
Anna Bridge	142:4eea097334d6	1736	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge	142:4eea097334d6	1737
Anna Bridge	142:4eea097334d6	1738	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge	142:4eea097334d6	1739	\param [in] PriorityGroup Used priority group.
Anna Bridge	142:4eea097334d6	1740	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	142:4eea097334d6	1741	\param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge	142:4eea097334d6	1742	*/
Anna Bridge	142:4eea097334d6	1743	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Anna Bridge	142:4eea097334d6	1744	{
Anna Bridge	142:4eea097334d6	1745	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	142:4eea097334d6	1746	uint32_t PreemptPriorityBits;
Anna Bridge	142:4eea097334d6	1747	uint32_t SubPriorityBits;
Anna Bridge	142:4eea097334d6	1748
Anna Bridge	142:4eea097334d6	1749	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	142:4eea097334d6	1750	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	142:4eea097334d6	1751
Anna Bridge	142:4eea097334d6	1752	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge	142:4eea097334d6	1753	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge	142:4eea097334d6	1754	}
Anna Bridge	142:4eea097334d6	1755
Anna Bridge	142:4eea097334d6	1756
Anna Bridge	142:4eea097334d6	1757	/** \brief System Reset
Anna Bridge	142:4eea097334d6	1758
Anna Bridge	142:4eea097334d6	1759	The function initiates a system reset request to reset the MCU.
Anna Bridge	142:4eea097334d6	1760	*/
Anna Bridge	142:4eea097334d6	1761	__STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge	142:4eea097334d6	1762	{
Anna Bridge	142:4eea097334d6	1763	__DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge	142:4eea097334d6	1764	buffered write are completed before reset */
Anna Bridge	142:4eea097334d6	1765	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	142:4eea097334d6	1766	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Anna Bridge	142:4eea097334d6	1767	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge	142:4eea097334d6	1768	__DSB(); /* Ensure completion of memory access */
Anna Bridge	142:4eea097334d6	1769	while(1) { __NOP(); } /* wait until reset */
Anna Bridge	142:4eea097334d6	1770	}
Anna Bridge	142:4eea097334d6	1771
Anna Bridge	142:4eea097334d6	1772	/@} end of CMSIS_Core_NVICFunctions /
Anna Bridge	142:4eea097334d6	1773
Anna Bridge	142:4eea097334d6	1774
Anna Bridge	142:4eea097334d6	1775
Anna Bridge	142:4eea097334d6	1776	/* ################################## SysTick function ############################################ */
Anna Bridge	142:4eea097334d6	1777	/** \ingroup CMSIS_Core_FunctionInterface
Anna Bridge	142:4eea097334d6	1778	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge	142:4eea097334d6	1779	\brief Functions that configure the System.
Anna Bridge	142:4eea097334d6	1780	@{
Anna Bridge	142:4eea097334d6	1781	*/
Anna Bridge	142:4eea097334d6	1782
Anna Bridge	142:4eea097334d6	1783	#if (__Vendor_SysTickConfig == 0)
Anna Bridge	142:4eea097334d6	1784
Anna Bridge	142:4eea097334d6	1785	/** \brief System Tick Configuration
Anna Bridge	142:4eea097334d6	1786
Anna Bridge	142:4eea097334d6	1787	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge	142:4eea097334d6	1788	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	142:4eea097334d6	1789
Anna Bridge	142:4eea097334d6	1790	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	142:4eea097334d6	1791
Anna Bridge	142:4eea097334d6	1792	\return 0 Function succeeded.
Anna Bridge	142:4eea097334d6	1793	\return 1 Function failed.
Anna Bridge	142:4eea097334d6	1794
Anna Bridge	142:4eea097334d6	1795	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	142:4eea097334d6	1796	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	142:4eea097334d6	1797	must contain a vendor-specific implementation of this function.
Anna Bridge	142:4eea097334d6	1798
Anna Bridge	142:4eea097334d6	1799	*/
Anna Bridge	142:4eea097334d6	1800	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge	142:4eea097334d6	1801	{
Anna Bridge	142:4eea097334d6	1802	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Anna Bridge	142:4eea097334d6	1803
Anna Bridge	142:4eea097334d6	1804	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	142:4eea097334d6	1805	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	142:4eea097334d6	1806	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	142:4eea097334d6	1807	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	142:4eea097334d6	1808	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	142:4eea097334d6	1809	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	142:4eea097334d6	1810	return (0UL); /* Function successful */
Anna Bridge	142:4eea097334d6	1811	}
Anna Bridge	142:4eea097334d6	1812
Anna Bridge	142:4eea097334d6	1813	#endif
Anna Bridge	142:4eea097334d6	1814
Anna Bridge	142:4eea097334d6	1815	/@} end of CMSIS_Core_SysTickFunctions /
Anna Bridge	142:4eea097334d6	1816
Anna Bridge	142:4eea097334d6	1817
Anna Bridge	142:4eea097334d6	1818
Anna Bridge	142:4eea097334d6	1819	/* ##################################### Debug In/Output function ########################################### */
Anna Bridge	142:4eea097334d6	1820	/** \ingroup CMSIS_Core_FunctionInterface
Anna Bridge	142:4eea097334d6	1821	\defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge	142:4eea097334d6	1822	\brief Functions that access the ITM debug interface.
Anna Bridge	142:4eea097334d6	1823	@{
Anna Bridge	142:4eea097334d6	1824	*/
Anna Bridge	142:4eea097334d6	1825
Anna Bridge	142:4eea097334d6	1826	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Anna Bridge	142:4eea097334d6	1827	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Anna Bridge	142:4eea097334d6	1828
Anna Bridge	142:4eea097334d6	1829
Anna Bridge	142:4eea097334d6	1830	/** \brief ITM Send Character
Anna Bridge	142:4eea097334d6	1831
Anna Bridge	142:4eea097334d6	1832	The function transmits a character via the ITM channel 0, and
Anna Bridge	142:4eea097334d6	1833	\li Just returns when no debugger is connected that has booked the output.
Anna Bridge	142:4eea097334d6	1834	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge	142:4eea097334d6	1835
Anna Bridge	142:4eea097334d6	1836	\param [in] ch Character to transmit.
Anna Bridge	142:4eea097334d6	1837
Anna Bridge	142:4eea097334d6	1838	\returns Character to transmit.
Anna Bridge	142:4eea097334d6	1839	*/
Anna Bridge	142:4eea097334d6	1840	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge	142:4eea097334d6	1841	{
Anna Bridge	142:4eea097334d6	1842	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge	142:4eea097334d6	1843	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge	142:4eea097334d6	1844	{
Anna Bridge	142:4eea097334d6	1845	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Anna Bridge	142:4eea097334d6	1846	ITM->PORT[0].u8 = (uint8_t)ch;
Anna Bridge	142:4eea097334d6	1847	}
Anna Bridge	142:4eea097334d6	1848	return (ch);
Anna Bridge	142:4eea097334d6	1849	}
Anna Bridge	142:4eea097334d6	1850
Anna Bridge	142:4eea097334d6	1851
Anna Bridge	142:4eea097334d6	1852	/** \brief ITM Receive Character
Anna Bridge	142:4eea097334d6	1853
Anna Bridge	142:4eea097334d6	1854	The function inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge	142:4eea097334d6	1855
Anna Bridge	142:4eea097334d6	1856	\return Received character.
Anna Bridge	142:4eea097334d6	1857	\return -1 No character pending.
Anna Bridge	142:4eea097334d6	1858	*/
Anna Bridge	142:4eea097334d6	1859	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Anna Bridge	142:4eea097334d6	1860	int32_t ch = -1; /* no character available */
Anna Bridge	142:4eea097334d6	1861
Anna Bridge	142:4eea097334d6	1862	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Anna Bridge	142:4eea097334d6	1863	ch = ITM_RxBuffer;
Anna Bridge	142:4eea097334d6	1864	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge	142:4eea097334d6	1865	}
Anna Bridge	142:4eea097334d6	1866
Anna Bridge	142:4eea097334d6	1867	return (ch);
Anna Bridge	142:4eea097334d6	1868	}
Anna Bridge	142:4eea097334d6	1869
Anna Bridge	142:4eea097334d6	1870
Anna Bridge	142:4eea097334d6	1871	/** \brief ITM Check Character
Anna Bridge	142:4eea097334d6	1872
Anna Bridge	142:4eea097334d6	1873	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge	142:4eea097334d6	1874
Anna Bridge	142:4eea097334d6	1875	\return 0 No character available.
Anna Bridge	142:4eea097334d6	1876	\return 1 Character available.
Anna Bridge	142:4eea097334d6	1877	*/
Anna Bridge	142:4eea097334d6	1878	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Anna Bridge	142:4eea097334d6	1879
Anna Bridge	142:4eea097334d6	1880	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Anna Bridge	142:4eea097334d6	1881	return (0); /* no character available */
Anna Bridge	142:4eea097334d6	1882	} else {
Anna Bridge	142:4eea097334d6	1883	return (1); /* character available */
Anna Bridge	142:4eea097334d6	1884	}
Anna Bridge	142:4eea097334d6	1885	}
Anna Bridge	142:4eea097334d6	1886
Anna Bridge	142:4eea097334d6	1887	/@} end of CMSIS_core_DebugFunctions /
Anna Bridge	142:4eea097334d6	1888
Anna Bridge	142:4eea097334d6	1889
Anna Bridge	142:4eea097334d6	1890
Anna Bridge	142:4eea097334d6	1891
Anna Bridge	142:4eea097334d6	1892	#ifdef __cplusplus
Anna Bridge	142:4eea097334d6	1893	}
Anna Bridge	142:4eea097334d6	1894	#endif
Anna Bridge	142:4eea097334d6	1895
Anna Bridge	142:4eea097334d6	1896	#endif /* __CORE_CM4_H_DEPENDANT */
Anna Bridge	142:4eea097334d6	1897
Anna Bridge	142:4eea097334d6	1898	#endif /* __CMSIS_GENERIC */