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mbed 2

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TARGET_TB_SENSE_1/core_caFunc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
142:4eea097334d6 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file core_caFunc.h
Anna Bridge 142:4eea097334d6 3 * @brief CMSIS Cortex-A Core Function Access Header File
Anna Bridge 142:4eea097334d6 4 * @version V3.10
Anna Bridge 142:4eea097334d6 5 * @date 30 Oct 2013
Anna Bridge 142:4eea097334d6 6 *
Anna Bridge 142:4eea097334d6 7 * @note
Anna Bridge 142:4eea097334d6 8 *
Anna Bridge 142:4eea097334d6 9 ******************************************************************************/
Anna Bridge 142:4eea097334d6 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Anna Bridge 142:4eea097334d6 11
Anna Bridge 142:4eea097334d6 12 All rights reserved.
Anna Bridge 142:4eea097334d6 13 Redistribution and use in source and binary forms, with or without
Anna Bridge 142:4eea097334d6 14 modification, are permitted provided that the following conditions are met:
Anna Bridge 142:4eea097334d6 15 - Redistributions of source code must retain the above copyright
Anna Bridge 142:4eea097334d6 16 notice, this list of conditions and the following disclaimer.
Anna Bridge 142:4eea097334d6 17 - Redistributions in binary form must reproduce the above copyright
Anna Bridge 142:4eea097334d6 18 notice, this list of conditions and the following disclaimer in the
Anna Bridge 142:4eea097334d6 19 documentation and/or other materials provided with the distribution.
Anna Bridge 142:4eea097334d6 20 - Neither the name of ARM nor the names of its contributors may be used
Anna Bridge 142:4eea097334d6 21 to endorse or promote products derived from this software without
Anna Bridge 142:4eea097334d6 22 specific prior written permission.
Anna Bridge 142:4eea097334d6 23 *
Anna Bridge 142:4eea097334d6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Anna Bridge 142:4eea097334d6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Anna Bridge 142:4eea097334d6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Anna Bridge 142:4eea097334d6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Anna Bridge 142:4eea097334d6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Anna Bridge 142:4eea097334d6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Anna Bridge 142:4eea097334d6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Anna Bridge 142:4eea097334d6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Anna Bridge 142:4eea097334d6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Anna Bridge 142:4eea097334d6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Anna Bridge 142:4eea097334d6 34 POSSIBILITY OF SUCH DAMAGE.
Anna Bridge 142:4eea097334d6 35 ---------------------------------------------------------------------------*/
Anna Bridge 142:4eea097334d6 36
Anna Bridge 142:4eea097334d6 37
Anna Bridge 142:4eea097334d6 38 #ifndef __CORE_CAFUNC_H__
Anna Bridge 142:4eea097334d6 39 #define __CORE_CAFUNC_H__
Anna Bridge 142:4eea097334d6 40
Anna Bridge 142:4eea097334d6 41
Anna Bridge 142:4eea097334d6 42 /* ########################### Core Function Access ########################### */
Anna Bridge 142:4eea097334d6 43 /** \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 142:4eea097334d6 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Anna Bridge 142:4eea097334d6 45 @{
Anna Bridge 142:4eea097334d6 46 */
Anna Bridge 142:4eea097334d6 47
Anna Bridge 142:4eea097334d6 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Anna Bridge 142:4eea097334d6 49 /* ARM armcc specific functions */
Anna Bridge 142:4eea097334d6 50
Anna Bridge 142:4eea097334d6 51 #if (__ARMCC_VERSION < 400677)
Anna Bridge 142:4eea097334d6 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Anna Bridge 142:4eea097334d6 53 #endif
Anna Bridge 142:4eea097334d6 54
Anna Bridge 142:4eea097334d6 55 #define MODE_USR 0x10
Anna Bridge 142:4eea097334d6 56 #define MODE_FIQ 0x11
Anna Bridge 142:4eea097334d6 57 #define MODE_IRQ 0x12
Anna Bridge 142:4eea097334d6 58 #define MODE_SVC 0x13
Anna Bridge 142:4eea097334d6 59 #define MODE_MON 0x16
Anna Bridge 142:4eea097334d6 60 #define MODE_ABT 0x17
Anna Bridge 142:4eea097334d6 61 #define MODE_HYP 0x1A
Anna Bridge 142:4eea097334d6 62 #define MODE_UND 0x1B
Anna Bridge 142:4eea097334d6 63 #define MODE_SYS 0x1F
Anna Bridge 142:4eea097334d6 64
Anna Bridge 142:4eea097334d6 65 /** \brief Get APSR Register
Anna Bridge 142:4eea097334d6 66
Anna Bridge 142:4eea097334d6 67 This function returns the content of the APSR Register.
Anna Bridge 142:4eea097334d6 68
Anna Bridge 142:4eea097334d6 69 \return APSR Register value
Anna Bridge 142:4eea097334d6 70 */
Anna Bridge 142:4eea097334d6 71 __STATIC_INLINE uint32_t __get_APSR(void)
Anna Bridge 142:4eea097334d6 72 {
Anna Bridge 142:4eea097334d6 73 register uint32_t __regAPSR __ASM("apsr");
Anna Bridge 142:4eea097334d6 74 return(__regAPSR);
Anna Bridge 142:4eea097334d6 75 }
Anna Bridge 142:4eea097334d6 76
Anna Bridge 142:4eea097334d6 77
Anna Bridge 142:4eea097334d6 78 /** \brief Get CPSR Register
Anna Bridge 142:4eea097334d6 79
Anna Bridge 142:4eea097334d6 80 This function returns the content of the CPSR Register.
Anna Bridge 142:4eea097334d6 81
Anna Bridge 142:4eea097334d6 82 \return CPSR Register value
Anna Bridge 142:4eea097334d6 83 */
Anna Bridge 142:4eea097334d6 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Anna Bridge 142:4eea097334d6 85 {
Anna Bridge 142:4eea097334d6 86 register uint32_t __regCPSR __ASM("cpsr");
Anna Bridge 142:4eea097334d6 87 return(__regCPSR);
Anna Bridge 142:4eea097334d6 88 }
Anna Bridge 142:4eea097334d6 89
Anna Bridge 142:4eea097334d6 90 /** \brief Set Stack Pointer
Anna Bridge 142:4eea097334d6 91
Anna Bridge 142:4eea097334d6 92 This function assigns the given value to the current stack pointer.
Anna Bridge 142:4eea097334d6 93
Anna Bridge 142:4eea097334d6 94 \param [in] topOfStack Stack Pointer value to set
Anna Bridge 142:4eea097334d6 95 */
Anna Bridge 142:4eea097334d6 96 register uint32_t __regSP __ASM("sp");
Anna Bridge 142:4eea097334d6 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Anna Bridge 142:4eea097334d6 98 {
Anna Bridge 142:4eea097334d6 99 __regSP = topOfStack;
Anna Bridge 142:4eea097334d6 100 }
Anna Bridge 142:4eea097334d6 101
Anna Bridge 142:4eea097334d6 102
Anna Bridge 142:4eea097334d6 103 /** \brief Get link register
Anna Bridge 142:4eea097334d6 104
Anna Bridge 142:4eea097334d6 105 This function returns the value of the link register
Anna Bridge 142:4eea097334d6 106
Anna Bridge 142:4eea097334d6 107 \return Value of link register
Anna Bridge 142:4eea097334d6 108 */
Anna Bridge 142:4eea097334d6 109 register uint32_t __reglr __ASM("lr");
Anna Bridge 142:4eea097334d6 110 __STATIC_INLINE uint32_t __get_LR(void)
Anna Bridge 142:4eea097334d6 111 {
Anna Bridge 142:4eea097334d6 112 return(__reglr);
Anna Bridge 142:4eea097334d6 113 }
Anna Bridge 142:4eea097334d6 114
Anna Bridge 142:4eea097334d6 115 /** \brief Set link register
Anna Bridge 142:4eea097334d6 116
Anna Bridge 142:4eea097334d6 117 This function sets the value of the link register
Anna Bridge 142:4eea097334d6 118
Anna Bridge 142:4eea097334d6 119 \param [in] lr LR value to set
Anna Bridge 142:4eea097334d6 120 */
Anna Bridge 142:4eea097334d6 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Anna Bridge 142:4eea097334d6 122 {
Anna Bridge 142:4eea097334d6 123 __reglr = lr;
Anna Bridge 142:4eea097334d6 124 }
Anna Bridge 142:4eea097334d6 125
Anna Bridge 142:4eea097334d6 126 /** \brief Set Process Stack Pointer
Anna Bridge 142:4eea097334d6 127
Anna Bridge 142:4eea097334d6 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Anna Bridge 142:4eea097334d6 129
Anna Bridge 142:4eea097334d6 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Anna Bridge 142:4eea097334d6 131 */
Anna Bridge 142:4eea097334d6 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Anna Bridge 142:4eea097334d6 133 {
Anna Bridge 142:4eea097334d6 134 ARM
Anna Bridge 142:4eea097334d6 135 PRESERVE8
Anna Bridge 142:4eea097334d6 136
Anna Bridge 142:4eea097334d6 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Anna Bridge 142:4eea097334d6 138 MRS R1, CPSR
Anna Bridge 142:4eea097334d6 139 CPS #MODE_SYS ;no effect in USR mode
Anna Bridge 142:4eea097334d6 140 MOV SP, R0
Anna Bridge 142:4eea097334d6 141 MSR CPSR_c, R1 ;no effect in USR mode
Anna Bridge 142:4eea097334d6 142 ISB
Anna Bridge 142:4eea097334d6 143 BX LR
Anna Bridge 142:4eea097334d6 144
Anna Bridge 142:4eea097334d6 145 }
Anna Bridge 142:4eea097334d6 146
Anna Bridge 142:4eea097334d6 147 /** \brief Set User Mode
Anna Bridge 142:4eea097334d6 148
Anna Bridge 142:4eea097334d6 149 This function changes the processor state to User Mode
Anna Bridge 142:4eea097334d6 150 */
Anna Bridge 142:4eea097334d6 151 __STATIC_ASM void __set_CPS_USR(void)
Anna Bridge 142:4eea097334d6 152 {
Anna Bridge 142:4eea097334d6 153 ARM
Anna Bridge 142:4eea097334d6 154
Anna Bridge 142:4eea097334d6 155 CPS #MODE_USR
Anna Bridge 142:4eea097334d6 156 BX LR
Anna Bridge 142:4eea097334d6 157 }
Anna Bridge 142:4eea097334d6 158
Anna Bridge 142:4eea097334d6 159
Anna Bridge 142:4eea097334d6 160 /** \brief Enable FIQ
Anna Bridge 142:4eea097334d6 161
Anna Bridge 142:4eea097334d6 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Anna Bridge 142:4eea097334d6 163 Can only be executed in Privileged modes.
Anna Bridge 142:4eea097334d6 164 */
Anna Bridge 142:4eea097334d6 165 #define __enable_fault_irq __enable_fiq
Anna Bridge 142:4eea097334d6 166
Anna Bridge 142:4eea097334d6 167
Anna Bridge 142:4eea097334d6 168 /** \brief Disable FIQ
Anna Bridge 142:4eea097334d6 169
Anna Bridge 142:4eea097334d6 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Anna Bridge 142:4eea097334d6 171 Can only be executed in Privileged modes.
Anna Bridge 142:4eea097334d6 172 */
Anna Bridge 142:4eea097334d6 173 #define __disable_fault_irq __disable_fiq
Anna Bridge 142:4eea097334d6 174
Anna Bridge 142:4eea097334d6 175
Anna Bridge 142:4eea097334d6 176 /** \brief Get FPSCR
Anna Bridge 142:4eea097334d6 177
Anna Bridge 142:4eea097334d6 178 This function returns the current value of the Floating Point Status/Control register.
Anna Bridge 142:4eea097334d6 179
Anna Bridge 142:4eea097334d6 180 \return Floating Point Status/Control register value
Anna Bridge 142:4eea097334d6 181 */
Anna Bridge 142:4eea097334d6 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Anna Bridge 142:4eea097334d6 183 {
Anna Bridge 142:4eea097334d6 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Anna Bridge 142:4eea097334d6 185 register uint32_t __regfpscr __ASM("fpscr");
Anna Bridge 142:4eea097334d6 186 return(__regfpscr);
Anna Bridge 142:4eea097334d6 187 #else
Anna Bridge 142:4eea097334d6 188 return(0);
Anna Bridge 142:4eea097334d6 189 #endif
Anna Bridge 142:4eea097334d6 190 }
Anna Bridge 142:4eea097334d6 191
Anna Bridge 142:4eea097334d6 192
Anna Bridge 142:4eea097334d6 193 /** \brief Set FPSCR
Anna Bridge 142:4eea097334d6 194
Anna Bridge 142:4eea097334d6 195 This function assigns the given value to the Floating Point Status/Control register.
Anna Bridge 142:4eea097334d6 196
Anna Bridge 142:4eea097334d6 197 \param [in] fpscr Floating Point Status/Control value to set
Anna Bridge 142:4eea097334d6 198 */
Anna Bridge 142:4eea097334d6 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Anna Bridge 142:4eea097334d6 200 {
Anna Bridge 142:4eea097334d6 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Anna Bridge 142:4eea097334d6 202 register uint32_t __regfpscr __ASM("fpscr");
Anna Bridge 142:4eea097334d6 203 __regfpscr = (fpscr);
Anna Bridge 142:4eea097334d6 204 #endif
Anna Bridge 142:4eea097334d6 205 }
Anna Bridge 142:4eea097334d6 206
Anna Bridge 142:4eea097334d6 207 /** \brief Get FPEXC
Anna Bridge 142:4eea097334d6 208
Anna Bridge 142:4eea097334d6 209 This function returns the current value of the Floating Point Exception Control register.
Anna Bridge 142:4eea097334d6 210
Anna Bridge 142:4eea097334d6 211 \return Floating Point Exception Control register value
Anna Bridge 142:4eea097334d6 212 */
Anna Bridge 142:4eea097334d6 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Anna Bridge 142:4eea097334d6 214 {
Anna Bridge 142:4eea097334d6 215 #if (__FPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 216 register uint32_t __regfpexc __ASM("fpexc");
Anna Bridge 142:4eea097334d6 217 return(__regfpexc);
Anna Bridge 142:4eea097334d6 218 #else
Anna Bridge 142:4eea097334d6 219 return(0);
Anna Bridge 142:4eea097334d6 220 #endif
Anna Bridge 142:4eea097334d6 221 }
Anna Bridge 142:4eea097334d6 222
Anna Bridge 142:4eea097334d6 223
Anna Bridge 142:4eea097334d6 224 /** \brief Set FPEXC
Anna Bridge 142:4eea097334d6 225
Anna Bridge 142:4eea097334d6 226 This function assigns the given value to the Floating Point Exception Control register.
Anna Bridge 142:4eea097334d6 227
Anna Bridge 142:4eea097334d6 228 \param [in] fpscr Floating Point Exception Control value to set
Anna Bridge 142:4eea097334d6 229 */
Anna Bridge 142:4eea097334d6 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Anna Bridge 142:4eea097334d6 231 {
Anna Bridge 142:4eea097334d6 232 #if (__FPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 233 register uint32_t __regfpexc __ASM("fpexc");
Anna Bridge 142:4eea097334d6 234 __regfpexc = (fpexc);
Anna Bridge 142:4eea097334d6 235 #endif
Anna Bridge 142:4eea097334d6 236 }
Anna Bridge 142:4eea097334d6 237
Anna Bridge 142:4eea097334d6 238 /** \brief Get CPACR
Anna Bridge 142:4eea097334d6 239
Anna Bridge 142:4eea097334d6 240 This function returns the current value of the Coprocessor Access Control register.
Anna Bridge 142:4eea097334d6 241
Anna Bridge 142:4eea097334d6 242 \return Coprocessor Access Control register value
Anna Bridge 142:4eea097334d6 243 */
Anna Bridge 142:4eea097334d6 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Anna Bridge 142:4eea097334d6 245 {
Anna Bridge 142:4eea097334d6 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Anna Bridge 142:4eea097334d6 247 return __regCPACR;
Anna Bridge 142:4eea097334d6 248 }
Anna Bridge 142:4eea097334d6 249
Anna Bridge 142:4eea097334d6 250 /** \brief Set CPACR
Anna Bridge 142:4eea097334d6 251
Anna Bridge 142:4eea097334d6 252 This function assigns the given value to the Coprocessor Access Control register.
Anna Bridge 142:4eea097334d6 253
Anna Bridge 142:4eea097334d6 254 \param [in] cpacr Coprocessor Acccess Control value to set
Anna Bridge 142:4eea097334d6 255 */
Anna Bridge 142:4eea097334d6 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Anna Bridge 142:4eea097334d6 257 {
Anna Bridge 142:4eea097334d6 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Anna Bridge 142:4eea097334d6 259 __regCPACR = cpacr;
Anna Bridge 142:4eea097334d6 260 __ISB();
Anna Bridge 142:4eea097334d6 261 }
Anna Bridge 142:4eea097334d6 262
Anna Bridge 142:4eea097334d6 263 /** \brief Get CBAR
Anna Bridge 142:4eea097334d6 264
Anna Bridge 142:4eea097334d6 265 This function returns the value of the Configuration Base Address register.
Anna Bridge 142:4eea097334d6 266
Anna Bridge 142:4eea097334d6 267 \return Configuration Base Address register value
Anna Bridge 142:4eea097334d6 268 */
Anna Bridge 142:4eea097334d6 269 __STATIC_INLINE uint32_t __get_CBAR() {
Anna Bridge 142:4eea097334d6 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Anna Bridge 142:4eea097334d6 271 return(__regCBAR);
Anna Bridge 142:4eea097334d6 272 }
Anna Bridge 142:4eea097334d6 273
Anna Bridge 142:4eea097334d6 274 /** \brief Get TTBR0
Anna Bridge 142:4eea097334d6 275
Anna Bridge 142:4eea097334d6 276 This function returns the value of the Translation Table Base Register 0.
Anna Bridge 142:4eea097334d6 277
Anna Bridge 142:4eea097334d6 278 \return Translation Table Base Register 0 value
Anna Bridge 142:4eea097334d6 279 */
Anna Bridge 142:4eea097334d6 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Anna Bridge 142:4eea097334d6 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Anna Bridge 142:4eea097334d6 282 return(__regTTBR0);
Anna Bridge 142:4eea097334d6 283 }
Anna Bridge 142:4eea097334d6 284
Anna Bridge 142:4eea097334d6 285 /** \brief Set TTBR0
Anna Bridge 142:4eea097334d6 286
Anna Bridge 142:4eea097334d6 287 This function assigns the given value to the Translation Table Base Register 0.
Anna Bridge 142:4eea097334d6 288
Anna Bridge 142:4eea097334d6 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Anna Bridge 142:4eea097334d6 290 */
Anna Bridge 142:4eea097334d6 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Anna Bridge 142:4eea097334d6 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Anna Bridge 142:4eea097334d6 293 __regTTBR0 = ttbr0;
Anna Bridge 142:4eea097334d6 294 __ISB();
Anna Bridge 142:4eea097334d6 295 }
Anna Bridge 142:4eea097334d6 296
Anna Bridge 142:4eea097334d6 297 /** \brief Get DACR
Anna Bridge 142:4eea097334d6 298
Anna Bridge 142:4eea097334d6 299 This function returns the value of the Domain Access Control Register.
Anna Bridge 142:4eea097334d6 300
Anna Bridge 142:4eea097334d6 301 \return Domain Access Control Register value
Anna Bridge 142:4eea097334d6 302 */
Anna Bridge 142:4eea097334d6 303 __STATIC_INLINE uint32_t __get_DACR() {
Anna Bridge 142:4eea097334d6 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Anna Bridge 142:4eea097334d6 305 return(__regDACR);
Anna Bridge 142:4eea097334d6 306 }
Anna Bridge 142:4eea097334d6 307
Anna Bridge 142:4eea097334d6 308 /** \brief Set DACR
Anna Bridge 142:4eea097334d6 309
Anna Bridge 142:4eea097334d6 310 This function assigns the given value to the Domain Access Control Register.
Anna Bridge 142:4eea097334d6 311
Anna Bridge 142:4eea097334d6 312 \param [in] dacr Domain Access Control Register value to set
Anna Bridge 142:4eea097334d6 313 */
Anna Bridge 142:4eea097334d6 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Anna Bridge 142:4eea097334d6 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Anna Bridge 142:4eea097334d6 316 __regDACR = dacr;
Anna Bridge 142:4eea097334d6 317 __ISB();
Anna Bridge 142:4eea097334d6 318 }
Anna Bridge 142:4eea097334d6 319
Anna Bridge 142:4eea097334d6 320 /******************************** Cache and BTAC enable ****************************************************/
Anna Bridge 142:4eea097334d6 321
Anna Bridge 142:4eea097334d6 322 /** \brief Set SCTLR
Anna Bridge 142:4eea097334d6 323
Anna Bridge 142:4eea097334d6 324 This function assigns the given value to the System Control Register.
Anna Bridge 142:4eea097334d6 325
Anna Bridge 142:4eea097334d6 326 \param [in] sctlr System Control Register value to set
Anna Bridge 142:4eea097334d6 327 */
Anna Bridge 142:4eea097334d6 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Anna Bridge 142:4eea097334d6 329 {
Anna Bridge 142:4eea097334d6 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Anna Bridge 142:4eea097334d6 331 __regSCTLR = sctlr;
Anna Bridge 142:4eea097334d6 332 }
Anna Bridge 142:4eea097334d6 333
Anna Bridge 142:4eea097334d6 334 /** \brief Get SCTLR
Anna Bridge 142:4eea097334d6 335
Anna Bridge 142:4eea097334d6 336 This function returns the value of the System Control Register.
Anna Bridge 142:4eea097334d6 337
Anna Bridge 142:4eea097334d6 338 \return System Control Register value
Anna Bridge 142:4eea097334d6 339 */
Anna Bridge 142:4eea097334d6 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Anna Bridge 142:4eea097334d6 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Anna Bridge 142:4eea097334d6 342 return(__regSCTLR);
Anna Bridge 142:4eea097334d6 343 }
Anna Bridge 142:4eea097334d6 344
Anna Bridge 142:4eea097334d6 345 /** \brief Enable Caches
Anna Bridge 142:4eea097334d6 346
Anna Bridge 142:4eea097334d6 347 Enable Caches
Anna Bridge 142:4eea097334d6 348 */
Anna Bridge 142:4eea097334d6 349 __STATIC_INLINE void __enable_caches(void) {
Anna Bridge 142:4eea097334d6 350 // Set I bit 12 to enable I Cache
Anna Bridge 142:4eea097334d6 351 // Set C bit 2 to enable D Cache
Anna Bridge 142:4eea097334d6 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Anna Bridge 142:4eea097334d6 353 }
Anna Bridge 142:4eea097334d6 354
Anna Bridge 142:4eea097334d6 355 /** \brief Disable Caches
Anna Bridge 142:4eea097334d6 356
Anna Bridge 142:4eea097334d6 357 Disable Caches
Anna Bridge 142:4eea097334d6 358 */
Anna Bridge 142:4eea097334d6 359 __STATIC_INLINE void __disable_caches(void) {
Anna Bridge 142:4eea097334d6 360 // Clear I bit 12 to disable I Cache
Anna Bridge 142:4eea097334d6 361 // Clear C bit 2 to disable D Cache
Anna Bridge 142:4eea097334d6 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Anna Bridge 142:4eea097334d6 363 __ISB();
Anna Bridge 142:4eea097334d6 364 }
Anna Bridge 142:4eea097334d6 365
Anna Bridge 142:4eea097334d6 366 /** \brief Enable BTAC
Anna Bridge 142:4eea097334d6 367
Anna Bridge 142:4eea097334d6 368 Enable BTAC
Anna Bridge 142:4eea097334d6 369 */
Anna Bridge 142:4eea097334d6 370 __STATIC_INLINE void __enable_btac(void) {
Anna Bridge 142:4eea097334d6 371 // Set Z bit 11 to enable branch prediction
Anna Bridge 142:4eea097334d6 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Anna Bridge 142:4eea097334d6 373 __ISB();
Anna Bridge 142:4eea097334d6 374 }
Anna Bridge 142:4eea097334d6 375
Anna Bridge 142:4eea097334d6 376 /** \brief Disable BTAC
Anna Bridge 142:4eea097334d6 377
Anna Bridge 142:4eea097334d6 378 Disable BTAC
Anna Bridge 142:4eea097334d6 379 */
Anna Bridge 142:4eea097334d6 380 __STATIC_INLINE void __disable_btac(void) {
Anna Bridge 142:4eea097334d6 381 // Clear Z bit 11 to disable branch prediction
Anna Bridge 142:4eea097334d6 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Anna Bridge 142:4eea097334d6 383 }
Anna Bridge 142:4eea097334d6 384
Anna Bridge 142:4eea097334d6 385
Anna Bridge 142:4eea097334d6 386 /** \brief Enable MMU
Anna Bridge 142:4eea097334d6 387
Anna Bridge 142:4eea097334d6 388 Enable MMU
Anna Bridge 142:4eea097334d6 389 */
Anna Bridge 142:4eea097334d6 390 __STATIC_INLINE void __enable_mmu(void) {
Anna Bridge 142:4eea097334d6 391 // Set M bit 0 to enable the MMU
Anna Bridge 142:4eea097334d6 392 // Set AFE bit to enable simplified access permissions model
Anna Bridge 142:4eea097334d6 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Anna Bridge 142:4eea097334d6 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Anna Bridge 142:4eea097334d6 395 __ISB();
Anna Bridge 142:4eea097334d6 396 }
Anna Bridge 142:4eea097334d6 397
Anna Bridge 142:4eea097334d6 398 /** \brief Disable MMU
Anna Bridge 142:4eea097334d6 399
Anna Bridge 142:4eea097334d6 400 Disable MMU
Anna Bridge 142:4eea097334d6 401 */
Anna Bridge 142:4eea097334d6 402 __STATIC_INLINE void __disable_mmu(void) {
Anna Bridge 142:4eea097334d6 403 // Clear M bit 0 to disable the MMU
Anna Bridge 142:4eea097334d6 404 __set_SCTLR( __get_SCTLR() & ~1);
Anna Bridge 142:4eea097334d6 405 __ISB();
Anna Bridge 142:4eea097334d6 406 }
Anna Bridge 142:4eea097334d6 407
Anna Bridge 142:4eea097334d6 408 /******************************** TLB maintenance operations ************************************************/
Anna Bridge 142:4eea097334d6 409 /** \brief Invalidate the whole tlb
Anna Bridge 142:4eea097334d6 410
Anna Bridge 142:4eea097334d6 411 TLBIALL. Invalidate the whole tlb
Anna Bridge 142:4eea097334d6 412 */
Anna Bridge 142:4eea097334d6 413
Anna Bridge 142:4eea097334d6 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Anna Bridge 142:4eea097334d6 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Anna Bridge 142:4eea097334d6 416 __TLBIALL = 0;
Anna Bridge 142:4eea097334d6 417 __DSB();
Anna Bridge 142:4eea097334d6 418 __ISB();
Anna Bridge 142:4eea097334d6 419 }
Anna Bridge 142:4eea097334d6 420
Anna Bridge 142:4eea097334d6 421 /******************************** BTB maintenance operations ************************************************/
Anna Bridge 142:4eea097334d6 422 /** \brief Invalidate entire branch predictor array
Anna Bridge 142:4eea097334d6 423
Anna Bridge 142:4eea097334d6 424 BPIALL. Branch Predictor Invalidate All.
Anna Bridge 142:4eea097334d6 425 */
Anna Bridge 142:4eea097334d6 426
Anna Bridge 142:4eea097334d6 427 __STATIC_INLINE void __v7_inv_btac(void) {
Anna Bridge 142:4eea097334d6 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Anna Bridge 142:4eea097334d6 429 __BPIALL = 0;
Anna Bridge 142:4eea097334d6 430 __DSB(); //ensure completion of the invalidation
Anna Bridge 142:4eea097334d6 431 __ISB(); //ensure instruction fetch path sees new state
Anna Bridge 142:4eea097334d6 432 }
Anna Bridge 142:4eea097334d6 433
Anna Bridge 142:4eea097334d6 434
Anna Bridge 142:4eea097334d6 435 /******************************** L1 cache operations ******************************************************/
Anna Bridge 142:4eea097334d6 436
Anna Bridge 142:4eea097334d6 437 /** \brief Invalidate the whole I$
Anna Bridge 142:4eea097334d6 438
Anna Bridge 142:4eea097334d6 439 ICIALLU. Instruction Cache Invalidate All to PoU
Anna Bridge 142:4eea097334d6 440 */
Anna Bridge 142:4eea097334d6 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Anna Bridge 142:4eea097334d6 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Anna Bridge 142:4eea097334d6 443 __ICIALLU = 0;
Anna Bridge 142:4eea097334d6 444 __DSB(); //ensure completion of the invalidation
Anna Bridge 142:4eea097334d6 445 __ISB(); //ensure instruction fetch path sees new I cache state
Anna Bridge 142:4eea097334d6 446 }
Anna Bridge 142:4eea097334d6 447
Anna Bridge 142:4eea097334d6 448 /** \brief Clean D$ by MVA
Anna Bridge 142:4eea097334d6 449
Anna Bridge 142:4eea097334d6 450 DCCMVAC. Data cache clean by MVA to PoC
Anna Bridge 142:4eea097334d6 451 */
Anna Bridge 142:4eea097334d6 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Anna Bridge 142:4eea097334d6 454 __DCCMVAC = (uint32_t)va;
Anna Bridge 142:4eea097334d6 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 142:4eea097334d6 456 }
Anna Bridge 142:4eea097334d6 457
Anna Bridge 142:4eea097334d6 458 /** \brief Invalidate D$ by MVA
Anna Bridge 142:4eea097334d6 459
Anna Bridge 142:4eea097334d6 460 DCIMVAC. Data cache invalidate by MVA to PoC
Anna Bridge 142:4eea097334d6 461 */
Anna Bridge 142:4eea097334d6 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Anna Bridge 142:4eea097334d6 464 __DCIMVAC = (uint32_t)va;
Anna Bridge 142:4eea097334d6 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 142:4eea097334d6 466 }
Anna Bridge 142:4eea097334d6 467
Anna Bridge 142:4eea097334d6 468 /** \brief Clean and Invalidate D$ by MVA
Anna Bridge 142:4eea097334d6 469
Anna Bridge 142:4eea097334d6 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Anna Bridge 142:4eea097334d6 471 */
Anna Bridge 142:4eea097334d6 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Anna Bridge 142:4eea097334d6 474 __DCCIMVAC = (uint32_t)va;
Anna Bridge 142:4eea097334d6 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 142:4eea097334d6 476 }
Anna Bridge 142:4eea097334d6 477
Anna Bridge 142:4eea097334d6 478 /** \brief Clean and Invalidate the entire data or unified cache
Anna Bridge 142:4eea097334d6 479
Anna Bridge 142:4eea097334d6 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Anna Bridge 142:4eea097334d6 481 */
Anna Bridge 142:4eea097334d6 482 #pragma push
Anna Bridge 142:4eea097334d6 483 #pragma arm
Anna Bridge 142:4eea097334d6 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Anna Bridge 142:4eea097334d6 485 ARM
Anna Bridge 142:4eea097334d6 486
Anna Bridge 142:4eea097334d6 487 PUSH {R4-R11}
Anna Bridge 142:4eea097334d6 488
Anna Bridge 142:4eea097334d6 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Anna Bridge 142:4eea097334d6 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Anna Bridge 142:4eea097334d6 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Anna Bridge 142:4eea097334d6 492 BEQ Finished // If 0, no need to clean
Anna Bridge 142:4eea097334d6 493
Anna Bridge 142:4eea097334d6 494 MOV R10, #0 // R10 holds current cache level << 1
Anna Bridge 142:4eea097334d6 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Anna Bridge 142:4eea097334d6 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Anna Bridge 142:4eea097334d6 497 AND R1, R1, #7 // Isolate those lower 3 bits
Anna Bridge 142:4eea097334d6 498 CMP R1, #2
Anna Bridge 142:4eea097334d6 499 BLT Skip // No cache or only instruction cache at this level
Anna Bridge 142:4eea097334d6 500
Anna Bridge 142:4eea097334d6 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Anna Bridge 142:4eea097334d6 502 ISB // ISB to sync the change to the CacheSizeID reg
Anna Bridge 142:4eea097334d6 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Anna Bridge 142:4eea097334d6 504 AND R2, R1, #7 // Extract the line length field
Anna Bridge 142:4eea097334d6 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Anna Bridge 142:4eea097334d6 506 LDR R4, =0x3FF
Anna Bridge 142:4eea097334d6 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Anna Bridge 142:4eea097334d6 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Anna Bridge 142:4eea097334d6 509 LDR R7, =0x7FFF
Anna Bridge 142:4eea097334d6 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Anna Bridge 142:4eea097334d6 511
Anna Bridge 142:4eea097334d6 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Anna Bridge 142:4eea097334d6 513
Anna Bridge 142:4eea097334d6 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Anna Bridge 142:4eea097334d6 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Anna Bridge 142:4eea097334d6 516 CMP R0, #0
Anna Bridge 142:4eea097334d6 517 BNE Dccsw
Anna Bridge 142:4eea097334d6 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 519 B cont
Anna Bridge 142:4eea097334d6 520 Dccsw CMP R0, #1
Anna Bridge 142:4eea097334d6 521 BNE Dccisw
Anna Bridge 142:4eea097334d6 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Anna Bridge 142:4eea097334d6 523 B cont
Anna Bridge 142:4eea097334d6 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 525 cont SUBS R9, R9, #1 // Decrement the Way number
Anna Bridge 142:4eea097334d6 526 BGE Loop3
Anna Bridge 142:4eea097334d6 527 SUBS R7, R7, #1 // Decrement the Set number
Anna Bridge 142:4eea097334d6 528 BGE Loop2
Anna Bridge 142:4eea097334d6 529 Skip ADD R10, R10, #2 // Increment the cache number
Anna Bridge 142:4eea097334d6 530 CMP R3, R10
Anna Bridge 142:4eea097334d6 531 BGT Loop1
Anna Bridge 142:4eea097334d6 532
Anna Bridge 142:4eea097334d6 533 Finished
Anna Bridge 142:4eea097334d6 534 DSB
Anna Bridge 142:4eea097334d6 535 POP {R4-R11}
Anna Bridge 142:4eea097334d6 536 BX lr
Anna Bridge 142:4eea097334d6 537
Anna Bridge 142:4eea097334d6 538 }
Anna Bridge 142:4eea097334d6 539 #pragma pop
Anna Bridge 142:4eea097334d6 540
Anna Bridge 142:4eea097334d6 541
Anna Bridge 142:4eea097334d6 542 /** \brief Invalidate the whole D$
Anna Bridge 142:4eea097334d6 543
Anna Bridge 142:4eea097334d6 544 DCISW. Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 545 */
Anna Bridge 142:4eea097334d6 546
Anna Bridge 142:4eea097334d6 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Anna Bridge 142:4eea097334d6 548 __v7_all_cache(0);
Anna Bridge 142:4eea097334d6 549 }
Anna Bridge 142:4eea097334d6 550
Anna Bridge 142:4eea097334d6 551 /** \brief Clean the whole D$
Anna Bridge 142:4eea097334d6 552
Anna Bridge 142:4eea097334d6 553 DCCSW. Clean by Set/Way
Anna Bridge 142:4eea097334d6 554 */
Anna Bridge 142:4eea097334d6 555
Anna Bridge 142:4eea097334d6 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Anna Bridge 142:4eea097334d6 557 __v7_all_cache(1);
Anna Bridge 142:4eea097334d6 558 }
Anna Bridge 142:4eea097334d6 559
Anna Bridge 142:4eea097334d6 560 /** \brief Clean and invalidate the whole D$
Anna Bridge 142:4eea097334d6 561
Anna Bridge 142:4eea097334d6 562 DCCISW. Clean and Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 563 */
Anna Bridge 142:4eea097334d6 564
Anna Bridge 142:4eea097334d6 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Anna Bridge 142:4eea097334d6 566 __v7_all_cache(2);
Anna Bridge 142:4eea097334d6 567 }
Anna Bridge 142:4eea097334d6 568
Anna Bridge 142:4eea097334d6 569 #include "core_ca_mmu.h"
Anna Bridge 142:4eea097334d6 570
Anna Bridge 142:4eea097334d6 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Anna Bridge 142:4eea097334d6 572
Anna Bridge 142:4eea097334d6 573 #define __inline inline
Anna Bridge 142:4eea097334d6 574
Anna Bridge 142:4eea097334d6 575 inline static uint32_t __disable_irq_iar() {
Anna Bridge 142:4eea097334d6 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Anna Bridge 142:4eea097334d6 577 __disable_irq();
Anna Bridge 142:4eea097334d6 578 return irq_dis;
Anna Bridge 142:4eea097334d6 579 }
Anna Bridge 142:4eea097334d6 580
Anna Bridge 142:4eea097334d6 581 #define MODE_USR 0x10
Anna Bridge 142:4eea097334d6 582 #define MODE_FIQ 0x11
Anna Bridge 142:4eea097334d6 583 #define MODE_IRQ 0x12
Anna Bridge 142:4eea097334d6 584 #define MODE_SVC 0x13
Anna Bridge 142:4eea097334d6 585 #define MODE_MON 0x16
Anna Bridge 142:4eea097334d6 586 #define MODE_ABT 0x17
Anna Bridge 142:4eea097334d6 587 #define MODE_HYP 0x1A
Anna Bridge 142:4eea097334d6 588 #define MODE_UND 0x1B
Anna Bridge 142:4eea097334d6 589 #define MODE_SYS 0x1F
Anna Bridge 142:4eea097334d6 590
Anna Bridge 142:4eea097334d6 591 /** \brief Set Process Stack Pointer
Anna Bridge 142:4eea097334d6 592
Anna Bridge 142:4eea097334d6 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Anna Bridge 142:4eea097334d6 594
Anna Bridge 142:4eea097334d6 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Anna Bridge 142:4eea097334d6 596 */
Anna Bridge 142:4eea097334d6 597 // from rt_CMSIS.c
Anna Bridge 142:4eea097334d6 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Anna Bridge 142:4eea097334d6 599 __asm(
Anna Bridge 142:4eea097334d6 600 " ARM\n"
Anna Bridge 142:4eea097334d6 601 // " PRESERVE8\n"
Anna Bridge 142:4eea097334d6 602
Anna Bridge 142:4eea097334d6 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Anna Bridge 142:4eea097334d6 604 " MRS R1, CPSR \n"
Anna Bridge 142:4eea097334d6 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Anna Bridge 142:4eea097334d6 606 " MOV SP, R0 \n"
Anna Bridge 142:4eea097334d6 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Anna Bridge 142:4eea097334d6 608 " ISB \n"
Anna Bridge 142:4eea097334d6 609 " BX LR \n");
Anna Bridge 142:4eea097334d6 610 }
Anna Bridge 142:4eea097334d6 611
Anna Bridge 142:4eea097334d6 612 /** \brief Set User Mode
Anna Bridge 142:4eea097334d6 613
Anna Bridge 142:4eea097334d6 614 This function changes the processor state to User Mode
Anna Bridge 142:4eea097334d6 615 */
Anna Bridge 142:4eea097334d6 616 // from rt_CMSIS.c
Anna Bridge 142:4eea097334d6 617 __arm static inline void __set_CPS_USR(void) {
Anna Bridge 142:4eea097334d6 618 __asm(
Anna Bridge 142:4eea097334d6 619 " ARM \n"
Anna Bridge 142:4eea097334d6 620
Anna Bridge 142:4eea097334d6 621 " CPS #0x10 \n" // MODE_USR
Anna Bridge 142:4eea097334d6 622 " BX LR\n");
Anna Bridge 142:4eea097334d6 623 }
Anna Bridge 142:4eea097334d6 624
Anna Bridge 142:4eea097334d6 625 /** \brief Set TTBR0
Anna Bridge 142:4eea097334d6 626
Anna Bridge 142:4eea097334d6 627 This function assigns the given value to the Translation Table Base Register 0.
Anna Bridge 142:4eea097334d6 628
Anna Bridge 142:4eea097334d6 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Anna Bridge 142:4eea097334d6 630 */
Anna Bridge 142:4eea097334d6 631 // from mmu_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Anna Bridge 142:4eea097334d6 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 634 __ISB();
Anna Bridge 142:4eea097334d6 635 }
Anna Bridge 142:4eea097334d6 636
Anna Bridge 142:4eea097334d6 637 /** \brief Set DACR
Anna Bridge 142:4eea097334d6 638
Anna Bridge 142:4eea097334d6 639 This function assigns the given value to the Domain Access Control Register.
Anna Bridge 142:4eea097334d6 640
Anna Bridge 142:4eea097334d6 641 \param [in] dacr Domain Access Control Register value to set
Anna Bridge 142:4eea097334d6 642 */
Anna Bridge 142:4eea097334d6 643 // from mmu_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Anna Bridge 142:4eea097334d6 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 646 __ISB();
Anna Bridge 142:4eea097334d6 647 }
Anna Bridge 142:4eea097334d6 648
Anna Bridge 142:4eea097334d6 649
Anna Bridge 142:4eea097334d6 650 /******************************** Cache and BTAC enable ****************************************************/
Anna Bridge 142:4eea097334d6 651 /** \brief Set SCTLR
Anna Bridge 142:4eea097334d6 652
Anna Bridge 142:4eea097334d6 653 This function assigns the given value to the System Control Register.
Anna Bridge 142:4eea097334d6 654
Anna Bridge 142:4eea097334d6 655 \param [in] sctlr System Control Register value to set
Anna Bridge 142:4eea097334d6 656 */
Anna Bridge 142:4eea097334d6 657 // from __enable_mmu()
Anna Bridge 142:4eea097334d6 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Anna Bridge 142:4eea097334d6 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 660 }
Anna Bridge 142:4eea097334d6 661
Anna Bridge 142:4eea097334d6 662 /** \brief Get SCTLR
Anna Bridge 142:4eea097334d6 663
Anna Bridge 142:4eea097334d6 664 This function returns the value of the System Control Register.
Anna Bridge 142:4eea097334d6 665
Anna Bridge 142:4eea097334d6 666 \return System Control Register value
Anna Bridge 142:4eea097334d6 667 */
Anna Bridge 142:4eea097334d6 668 // from __enable_mmu()
Anna Bridge 142:4eea097334d6 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Anna Bridge 142:4eea097334d6 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Anna Bridge 142:4eea097334d6 671 return __regSCTLR;
Anna Bridge 142:4eea097334d6 672 }
Anna Bridge 142:4eea097334d6 673
Anna Bridge 142:4eea097334d6 674 /** \brief Enable Caches
Anna Bridge 142:4eea097334d6 675
Anna Bridge 142:4eea097334d6 676 Enable Caches
Anna Bridge 142:4eea097334d6 677 */
Anna Bridge 142:4eea097334d6 678 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 679 __STATIC_INLINE void __enable_caches(void) {
Anna Bridge 142:4eea097334d6 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Anna Bridge 142:4eea097334d6 681 }
Anna Bridge 142:4eea097334d6 682
Anna Bridge 142:4eea097334d6 683 /** \brief Enable BTAC
Anna Bridge 142:4eea097334d6 684
Anna Bridge 142:4eea097334d6 685 Enable BTAC
Anna Bridge 142:4eea097334d6 686 */
Anna Bridge 142:4eea097334d6 687 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 688 __STATIC_INLINE void __enable_btac(void) {
Anna Bridge 142:4eea097334d6 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Anna Bridge 142:4eea097334d6 690 __ISB();
Anna Bridge 142:4eea097334d6 691 }
Anna Bridge 142:4eea097334d6 692
Anna Bridge 142:4eea097334d6 693 /** \brief Enable MMU
Anna Bridge 142:4eea097334d6 694
Anna Bridge 142:4eea097334d6 695 Enable MMU
Anna Bridge 142:4eea097334d6 696 */
Anna Bridge 142:4eea097334d6 697 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 698 __STATIC_INLINE void __enable_mmu(void) {
Anna Bridge 142:4eea097334d6 699 // Set M bit 0 to enable the MMU
Anna Bridge 142:4eea097334d6 700 // Set AFE bit to enable simplified access permissions model
Anna Bridge 142:4eea097334d6 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Anna Bridge 142:4eea097334d6 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Anna Bridge 142:4eea097334d6 703 __ISB();
Anna Bridge 142:4eea097334d6 704 }
Anna Bridge 142:4eea097334d6 705
Anna Bridge 142:4eea097334d6 706 /******************************** TLB maintenance operations ************************************************/
Anna Bridge 142:4eea097334d6 707 /** \brief Invalidate the whole tlb
Anna Bridge 142:4eea097334d6 708
Anna Bridge 142:4eea097334d6 709 TLBIALL. Invalidate the whole tlb
Anna Bridge 142:4eea097334d6 710 */
Anna Bridge 142:4eea097334d6 711 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Anna Bridge 142:4eea097334d6 713 uint32_t val = 0;
Anna Bridge 142:4eea097334d6 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 717 __DSB();
Anna Bridge 142:4eea097334d6 718 __ISB();
Anna Bridge 142:4eea097334d6 719 }
Anna Bridge 142:4eea097334d6 720
Anna Bridge 142:4eea097334d6 721 /******************************** BTB maintenance operations ************************************************/
Anna Bridge 142:4eea097334d6 722 /** \brief Invalidate entire branch predictor array
Anna Bridge 142:4eea097334d6 723
Anna Bridge 142:4eea097334d6 724 BPIALL. Branch Predictor Invalidate All.
Anna Bridge 142:4eea097334d6 725 */
Anna Bridge 142:4eea097334d6 726 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 727 __STATIC_INLINE void __v7_inv_btac(void) {
Anna Bridge 142:4eea097334d6 728 uint32_t val = 0;
Anna Bridge 142:4eea097334d6 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Anna Bridge 142:4eea097334d6 730 __DSB(); //ensure completion of the invalidation
Anna Bridge 142:4eea097334d6 731 __ISB(); //ensure instruction fetch path sees new state
Anna Bridge 142:4eea097334d6 732 }
Anna Bridge 142:4eea097334d6 733
Anna Bridge 142:4eea097334d6 734
Anna Bridge 142:4eea097334d6 735 /******************************** L1 cache operations ******************************************************/
Anna Bridge 142:4eea097334d6 736
Anna Bridge 142:4eea097334d6 737 /** \brief Invalidate the whole I$
Anna Bridge 142:4eea097334d6 738
Anna Bridge 142:4eea097334d6 739 ICIALLU. Instruction Cache Invalidate All to PoU
Anna Bridge 142:4eea097334d6 740 */
Anna Bridge 142:4eea097334d6 741 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Anna Bridge 142:4eea097334d6 743 uint32_t val = 0;
Anna Bridge 142:4eea097334d6 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Anna Bridge 142:4eea097334d6 745 __DSB(); //ensure completion of the invalidation
Anna Bridge 142:4eea097334d6 746 __ISB(); //ensure instruction fetch path sees new I cache state
Anna Bridge 142:4eea097334d6 747 }
Anna Bridge 142:4eea097334d6 748
Anna Bridge 142:4eea097334d6 749 // from __v7_inv_dcache_all()
Anna Bridge 142:4eea097334d6 750 __arm static inline void __v7_all_cache(uint32_t op) {
Anna Bridge 142:4eea097334d6 751 __asm(
Anna Bridge 142:4eea097334d6 752 " ARM \n"
Anna Bridge 142:4eea097334d6 753
Anna Bridge 142:4eea097334d6 754 " PUSH {R4-R11} \n"
Anna Bridge 142:4eea097334d6 755
Anna Bridge 142:4eea097334d6 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Anna Bridge 142:4eea097334d6 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Anna Bridge 142:4eea097334d6 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Anna Bridge 142:4eea097334d6 759 " BEQ Finished\n" // If 0, no need to clean
Anna Bridge 142:4eea097334d6 760
Anna Bridge 142:4eea097334d6 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Anna Bridge 142:4eea097334d6 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Anna Bridge 142:4eea097334d6 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Anna Bridge 142:4eea097334d6 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Anna Bridge 142:4eea097334d6 765 " CMP R1, #2 \n"
Anna Bridge 142:4eea097334d6 766 " BLT Skip \n" // No cache or only instruction cache at this level
Anna Bridge 142:4eea097334d6 767
Anna Bridge 142:4eea097334d6 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Anna Bridge 142:4eea097334d6 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Anna Bridge 142:4eea097334d6 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Anna Bridge 142:4eea097334d6 771 " AND R2, R1, #7 \n" // Extract the line length field
Anna Bridge 142:4eea097334d6 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Anna Bridge 142:4eea097334d6 773 " movw R4, #0x3FF \n"
Anna Bridge 142:4eea097334d6 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Anna Bridge 142:4eea097334d6 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Anna Bridge 142:4eea097334d6 776 " movw R7, #0x7FFF \n"
Anna Bridge 142:4eea097334d6 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Anna Bridge 142:4eea097334d6 778
Anna Bridge 142:4eea097334d6 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Anna Bridge 142:4eea097334d6 780
Anna Bridge 142:4eea097334d6 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Anna Bridge 142:4eea097334d6 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Anna Bridge 142:4eea097334d6 783 " CMP R0, #0 \n"
Anna Bridge 142:4eea097334d6 784 " BNE Dccsw \n"
Anna Bridge 142:4eea097334d6 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 786 " B cont \n"
Anna Bridge 142:4eea097334d6 787 "Dccsw: CMP R0, #1 \n"
Anna Bridge 142:4eea097334d6 788 " BNE Dccisw \n"
Anna Bridge 142:4eea097334d6 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Anna Bridge 142:4eea097334d6 790 " B cont \n"
Anna Bridge 142:4eea097334d6 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Anna Bridge 142:4eea097334d6 793 " BGE Loop3 \n"
Anna Bridge 142:4eea097334d6 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Anna Bridge 142:4eea097334d6 795 " BGE Loop2 \n"
Anna Bridge 142:4eea097334d6 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Anna Bridge 142:4eea097334d6 797 " CMP R3, R10 \n"
Anna Bridge 142:4eea097334d6 798 " BGT Loop1 \n"
Anna Bridge 142:4eea097334d6 799
Anna Bridge 142:4eea097334d6 800 "Finished: \n"
Anna Bridge 142:4eea097334d6 801 " DSB \n"
Anna Bridge 142:4eea097334d6 802 " POP {R4-R11} \n"
Anna Bridge 142:4eea097334d6 803 " BX lr \n" );
Anna Bridge 142:4eea097334d6 804 }
Anna Bridge 142:4eea097334d6 805
Anna Bridge 142:4eea097334d6 806 /** \brief Invalidate the whole D$
Anna Bridge 142:4eea097334d6 807
Anna Bridge 142:4eea097334d6 808 DCISW. Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 809 */
Anna Bridge 142:4eea097334d6 810 // from system_Renesas_RZ_A1.c
Anna Bridge 142:4eea097334d6 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Anna Bridge 142:4eea097334d6 812 __v7_all_cache(0);
Anna Bridge 142:4eea097334d6 813 }
Anna Bridge 142:4eea097334d6 814 /** \brief Clean the whole D$
Anna Bridge 142:4eea097334d6 815
Anna Bridge 142:4eea097334d6 816 DCCSW. Clean by Set/Way
Anna Bridge 142:4eea097334d6 817 */
Anna Bridge 142:4eea097334d6 818
Anna Bridge 142:4eea097334d6 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Anna Bridge 142:4eea097334d6 820 __v7_all_cache(1);
Anna Bridge 142:4eea097334d6 821 }
Anna Bridge 142:4eea097334d6 822
Anna Bridge 142:4eea097334d6 823 /** \brief Clean and invalidate the whole D$
Anna Bridge 142:4eea097334d6 824
Anna Bridge 142:4eea097334d6 825 DCCISW. Clean and Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 826 */
Anna Bridge 142:4eea097334d6 827
Anna Bridge 142:4eea097334d6 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Anna Bridge 142:4eea097334d6 829 __v7_all_cache(2);
Anna Bridge 142:4eea097334d6 830 }
Anna Bridge 142:4eea097334d6 831 /** \brief Clean and Invalidate D$ by MVA
Anna Bridge 142:4eea097334d6 832
Anna Bridge 142:4eea097334d6 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Anna Bridge 142:4eea097334d6 834 */
Anna Bridge 142:4eea097334d6 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Anna Bridge 142:4eea097334d6 837 __DMB();
Anna Bridge 142:4eea097334d6 838 }
Anna Bridge 142:4eea097334d6 839
Anna Bridge 142:4eea097334d6 840 #include "core_ca_mmu.h"
Anna Bridge 142:4eea097334d6 841
Anna Bridge 142:4eea097334d6 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Anna Bridge 142:4eea097334d6 843 /* GNU gcc specific functions */
Anna Bridge 142:4eea097334d6 844
Anna Bridge 142:4eea097334d6 845 #define MODE_USR 0x10
Anna Bridge 142:4eea097334d6 846 #define MODE_FIQ 0x11
Anna Bridge 142:4eea097334d6 847 #define MODE_IRQ 0x12
Anna Bridge 142:4eea097334d6 848 #define MODE_SVC 0x13
Anna Bridge 142:4eea097334d6 849 #define MODE_MON 0x16
Anna Bridge 142:4eea097334d6 850 #define MODE_ABT 0x17
Anna Bridge 142:4eea097334d6 851 #define MODE_HYP 0x1A
Anna Bridge 142:4eea097334d6 852 #define MODE_UND 0x1B
Anna Bridge 142:4eea097334d6 853 #define MODE_SYS 0x1F
Anna Bridge 142:4eea097334d6 854
Anna Bridge 142:4eea097334d6 855
Anna Bridge 142:4eea097334d6 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Anna Bridge 142:4eea097334d6 857 {
Anna Bridge 142:4eea097334d6 858 __ASM volatile ("cpsie i");
Anna Bridge 142:4eea097334d6 859 }
Anna Bridge 142:4eea097334d6 860
Anna Bridge 142:4eea097334d6 861 /** \brief Disable IRQ Interrupts
Anna Bridge 142:4eea097334d6 862
Anna Bridge 142:4eea097334d6 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Anna Bridge 142:4eea097334d6 864 Can only be executed in Privileged modes.
Anna Bridge 142:4eea097334d6 865 */
Anna Bridge 142:4eea097334d6 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Anna Bridge 142:4eea097334d6 867 {
Anna Bridge 142:4eea097334d6 868 uint32_t result;
Anna Bridge 142:4eea097334d6 869
Anna Bridge 142:4eea097334d6 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Anna Bridge 142:4eea097334d6 871 __ASM volatile ("cpsid i");
Anna Bridge 142:4eea097334d6 872 return(result & 0x80);
Anna Bridge 142:4eea097334d6 873 }
Anna Bridge 142:4eea097334d6 874
Anna Bridge 142:4eea097334d6 875
Anna Bridge 142:4eea097334d6 876 /** \brief Get APSR Register
Anna Bridge 142:4eea097334d6 877
Anna Bridge 142:4eea097334d6 878 This function returns the content of the APSR Register.
Anna Bridge 142:4eea097334d6 879
Anna Bridge 142:4eea097334d6 880 \return APSR Register value
Anna Bridge 142:4eea097334d6 881 */
Anna Bridge 142:4eea097334d6 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Anna Bridge 142:4eea097334d6 883 {
Anna Bridge 142:4eea097334d6 884 #if 1
Anna Bridge 142:4eea097334d6 885 register uint32_t __regAPSR;
Anna Bridge 142:4eea097334d6 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Anna Bridge 142:4eea097334d6 887 #else
Anna Bridge 142:4eea097334d6 888 register uint32_t __regAPSR __ASM("apsr");
Anna Bridge 142:4eea097334d6 889 #endif
Anna Bridge 142:4eea097334d6 890 return(__regAPSR);
Anna Bridge 142:4eea097334d6 891 }
Anna Bridge 142:4eea097334d6 892
Anna Bridge 142:4eea097334d6 893
Anna Bridge 142:4eea097334d6 894 /** \brief Get CPSR Register
Anna Bridge 142:4eea097334d6 895
Anna Bridge 142:4eea097334d6 896 This function returns the content of the CPSR Register.
Anna Bridge 142:4eea097334d6 897
Anna Bridge 142:4eea097334d6 898 \return CPSR Register value
Anna Bridge 142:4eea097334d6 899 */
Anna Bridge 142:4eea097334d6 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Anna Bridge 142:4eea097334d6 901 {
Anna Bridge 142:4eea097334d6 902 #if 1
Anna Bridge 142:4eea097334d6 903 register uint32_t __regCPSR;
Anna Bridge 142:4eea097334d6 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Anna Bridge 142:4eea097334d6 905 #else
Anna Bridge 142:4eea097334d6 906 register uint32_t __regCPSR __ASM("cpsr");
Anna Bridge 142:4eea097334d6 907 #endif
Anna Bridge 142:4eea097334d6 908 return(__regCPSR);
Anna Bridge 142:4eea097334d6 909 }
Anna Bridge 142:4eea097334d6 910
Anna Bridge 142:4eea097334d6 911 #if 0
Anna Bridge 142:4eea097334d6 912 /** \brief Set Stack Pointer
Anna Bridge 142:4eea097334d6 913
Anna Bridge 142:4eea097334d6 914 This function assigns the given value to the current stack pointer.
Anna Bridge 142:4eea097334d6 915
Anna Bridge 142:4eea097334d6 916 \param [in] topOfStack Stack Pointer value to set
Anna Bridge 142:4eea097334d6 917 */
Anna Bridge 142:4eea097334d6 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Anna Bridge 142:4eea097334d6 919 {
Anna Bridge 142:4eea097334d6 920 register uint32_t __regSP __ASM("sp");
Anna Bridge 142:4eea097334d6 921 __regSP = topOfStack;
Anna Bridge 142:4eea097334d6 922 }
Anna Bridge 142:4eea097334d6 923 #endif
Anna Bridge 142:4eea097334d6 924
Anna Bridge 142:4eea097334d6 925 /** \brief Get link register
Anna Bridge 142:4eea097334d6 926
Anna Bridge 142:4eea097334d6 927 This function returns the value of the link register
Anna Bridge 142:4eea097334d6 928
Anna Bridge 142:4eea097334d6 929 \return Value of link register
Anna Bridge 142:4eea097334d6 930 */
Anna Bridge 142:4eea097334d6 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Anna Bridge 142:4eea097334d6 932 {
Anna Bridge 142:4eea097334d6 933 register uint32_t __reglr __ASM("lr");
Anna Bridge 142:4eea097334d6 934 return(__reglr);
Anna Bridge 142:4eea097334d6 935 }
Anna Bridge 142:4eea097334d6 936
Anna Bridge 142:4eea097334d6 937 #if 0
Anna Bridge 142:4eea097334d6 938 /** \brief Set link register
Anna Bridge 142:4eea097334d6 939
Anna Bridge 142:4eea097334d6 940 This function sets the value of the link register
Anna Bridge 142:4eea097334d6 941
Anna Bridge 142:4eea097334d6 942 \param [in] lr LR value to set
Anna Bridge 142:4eea097334d6 943 */
Anna Bridge 142:4eea097334d6 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Anna Bridge 142:4eea097334d6 945 {
Anna Bridge 142:4eea097334d6 946 register uint32_t __reglr __ASM("lr");
Anna Bridge 142:4eea097334d6 947 __reglr = lr;
Anna Bridge 142:4eea097334d6 948 }
Anna Bridge 142:4eea097334d6 949 #endif
Anna Bridge 142:4eea097334d6 950
Anna Bridge 142:4eea097334d6 951 /** \brief Set Process Stack Pointer
Anna Bridge 142:4eea097334d6 952
Anna Bridge 142:4eea097334d6 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Anna Bridge 142:4eea097334d6 954
Anna Bridge 142:4eea097334d6 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Anna Bridge 142:4eea097334d6 956 */
Anna Bridge 142:4eea097334d6 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Anna Bridge 142:4eea097334d6 958 {
Anna Bridge 142:4eea097334d6 959 __asm__ volatile (
Anna Bridge 142:4eea097334d6 960 ".ARM;"
Anna Bridge 142:4eea097334d6 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Anna Bridge 142:4eea097334d6 962
Anna Bridge 142:4eea097334d6 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Anna Bridge 142:4eea097334d6 964 "MRS R1, CPSR;"
Anna Bridge 142:4eea097334d6 965 "CPS %0;" /* ;no effect in USR mode */
Anna Bridge 142:4eea097334d6 966 "MOV SP, R0;"
Anna Bridge 142:4eea097334d6 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Anna Bridge 142:4eea097334d6 968 "ISB;"
Anna Bridge 142:4eea097334d6 969 //"BX LR;"
Anna Bridge 142:4eea097334d6 970 :
Anna Bridge 142:4eea097334d6 971 : "i"(MODE_SYS)
Anna Bridge 142:4eea097334d6 972 : "r0", "r1");
Anna Bridge 142:4eea097334d6 973 return;
Anna Bridge 142:4eea097334d6 974 }
Anna Bridge 142:4eea097334d6 975
Anna Bridge 142:4eea097334d6 976 /** \brief Set User Mode
Anna Bridge 142:4eea097334d6 977
Anna Bridge 142:4eea097334d6 978 This function changes the processor state to User Mode
Anna Bridge 142:4eea097334d6 979 */
Anna Bridge 142:4eea097334d6 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Anna Bridge 142:4eea097334d6 981 {
Anna Bridge 142:4eea097334d6 982 __asm__ volatile (
Anna Bridge 142:4eea097334d6 983 ".ARM;"
Anna Bridge 142:4eea097334d6 984
Anna Bridge 142:4eea097334d6 985 "CPS %0;"
Anna Bridge 142:4eea097334d6 986 //"BX LR;"
Anna Bridge 142:4eea097334d6 987 :
Anna Bridge 142:4eea097334d6 988 : "i"(MODE_USR)
Anna Bridge 142:4eea097334d6 989 : );
Anna Bridge 142:4eea097334d6 990 return;
Anna Bridge 142:4eea097334d6 991 }
Anna Bridge 142:4eea097334d6 992
Anna Bridge 142:4eea097334d6 993
Anna Bridge 142:4eea097334d6 994 /** \brief Enable FIQ
Anna Bridge 142:4eea097334d6 995
Anna Bridge 142:4eea097334d6 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Anna Bridge 142:4eea097334d6 997 Can only be executed in Privileged modes.
Anna Bridge 142:4eea097334d6 998 */
Anna Bridge 142:4eea097334d6 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Anna Bridge 142:4eea097334d6 1000
Anna Bridge 142:4eea097334d6 1001
Anna Bridge 142:4eea097334d6 1002 /** \brief Disable FIQ
Anna Bridge 142:4eea097334d6 1003
Anna Bridge 142:4eea097334d6 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Anna Bridge 142:4eea097334d6 1005 Can only be executed in Privileged modes.
Anna Bridge 142:4eea097334d6 1006 */
Anna Bridge 142:4eea097334d6 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Anna Bridge 142:4eea097334d6 1008
Anna Bridge 142:4eea097334d6 1009
Anna Bridge 142:4eea097334d6 1010 /** \brief Get FPSCR
Anna Bridge 142:4eea097334d6 1011
Anna Bridge 142:4eea097334d6 1012 This function returns the current value of the Floating Point Status/Control register.
Anna Bridge 142:4eea097334d6 1013
Anna Bridge 142:4eea097334d6 1014 \return Floating Point Status/Control register value
Anna Bridge 142:4eea097334d6 1015 */
Anna Bridge 142:4eea097334d6 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Anna Bridge 142:4eea097334d6 1017 {
Anna Bridge 142:4eea097334d6 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Anna Bridge 142:4eea097334d6 1019 #if 1
Anna Bridge 142:4eea097334d6 1020 uint32_t result;
Anna Bridge 142:4eea097334d6 1021
Anna Bridge 142:4eea097334d6 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Anna Bridge 142:4eea097334d6 1023 return (result);
Anna Bridge 142:4eea097334d6 1024 #else
Anna Bridge 142:4eea097334d6 1025 register uint32_t __regfpscr __ASM("fpscr");
Anna Bridge 142:4eea097334d6 1026 return(__regfpscr);
Anna Bridge 142:4eea097334d6 1027 #endif
Anna Bridge 142:4eea097334d6 1028 #else
Anna Bridge 142:4eea097334d6 1029 return(0);
Anna Bridge 142:4eea097334d6 1030 #endif
Anna Bridge 142:4eea097334d6 1031 }
Anna Bridge 142:4eea097334d6 1032
Anna Bridge 142:4eea097334d6 1033
Anna Bridge 142:4eea097334d6 1034 /** \brief Set FPSCR
Anna Bridge 142:4eea097334d6 1035
Anna Bridge 142:4eea097334d6 1036 This function assigns the given value to the Floating Point Status/Control register.
Anna Bridge 142:4eea097334d6 1037
Anna Bridge 142:4eea097334d6 1038 \param [in] fpscr Floating Point Status/Control value to set
Anna Bridge 142:4eea097334d6 1039 */
Anna Bridge 142:4eea097334d6 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Anna Bridge 142:4eea097334d6 1041 {
Anna Bridge 142:4eea097334d6 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Anna Bridge 142:4eea097334d6 1043 #if 1
Anna Bridge 142:4eea097334d6 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Anna Bridge 142:4eea097334d6 1045 #else
Anna Bridge 142:4eea097334d6 1046 register uint32_t __regfpscr __ASM("fpscr");
Anna Bridge 142:4eea097334d6 1047 __regfpscr = (fpscr);
Anna Bridge 142:4eea097334d6 1048 #endif
Anna Bridge 142:4eea097334d6 1049 #endif
Anna Bridge 142:4eea097334d6 1050 }
Anna Bridge 142:4eea097334d6 1051
Anna Bridge 142:4eea097334d6 1052 /** \brief Get FPEXC
Anna Bridge 142:4eea097334d6 1053
Anna Bridge 142:4eea097334d6 1054 This function returns the current value of the Floating Point Exception Control register.
Anna Bridge 142:4eea097334d6 1055
Anna Bridge 142:4eea097334d6 1056 \return Floating Point Exception Control register value
Anna Bridge 142:4eea097334d6 1057 */
Anna Bridge 142:4eea097334d6 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Anna Bridge 142:4eea097334d6 1059 {
Anna Bridge 142:4eea097334d6 1060 #if (__FPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 1061 #if 1
Anna Bridge 142:4eea097334d6 1062 uint32_t result;
Anna Bridge 142:4eea097334d6 1063
Anna Bridge 142:4eea097334d6 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Anna Bridge 142:4eea097334d6 1065 return (result);
Anna Bridge 142:4eea097334d6 1066 #else
Anna Bridge 142:4eea097334d6 1067 register uint32_t __regfpexc __ASM("fpexc");
Anna Bridge 142:4eea097334d6 1068 return(__regfpexc);
Anna Bridge 142:4eea097334d6 1069 #endif
Anna Bridge 142:4eea097334d6 1070 #else
Anna Bridge 142:4eea097334d6 1071 return(0);
Anna Bridge 142:4eea097334d6 1072 #endif
Anna Bridge 142:4eea097334d6 1073 }
Anna Bridge 142:4eea097334d6 1074
Anna Bridge 142:4eea097334d6 1075
Anna Bridge 142:4eea097334d6 1076 /** \brief Set FPEXC
Anna Bridge 142:4eea097334d6 1077
Anna Bridge 142:4eea097334d6 1078 This function assigns the given value to the Floating Point Exception Control register.
Anna Bridge 142:4eea097334d6 1079
Anna Bridge 142:4eea097334d6 1080 \param [in] fpscr Floating Point Exception Control value to set
Anna Bridge 142:4eea097334d6 1081 */
Anna Bridge 142:4eea097334d6 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Anna Bridge 142:4eea097334d6 1083 {
Anna Bridge 142:4eea097334d6 1084 #if (__FPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 1085 #if 1
Anna Bridge 142:4eea097334d6 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Anna Bridge 142:4eea097334d6 1087 #else
Anna Bridge 142:4eea097334d6 1088 register uint32_t __regfpexc __ASM("fpexc");
Anna Bridge 142:4eea097334d6 1089 __regfpexc = (fpexc);
Anna Bridge 142:4eea097334d6 1090 #endif
Anna Bridge 142:4eea097334d6 1091 #endif
Anna Bridge 142:4eea097334d6 1092 }
Anna Bridge 142:4eea097334d6 1093
Anna Bridge 142:4eea097334d6 1094 /** \brief Get CPACR
Anna Bridge 142:4eea097334d6 1095
Anna Bridge 142:4eea097334d6 1096 This function returns the current value of the Coprocessor Access Control register.
Anna Bridge 142:4eea097334d6 1097
Anna Bridge 142:4eea097334d6 1098 \return Coprocessor Access Control register value
Anna Bridge 142:4eea097334d6 1099 */
Anna Bridge 142:4eea097334d6 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Anna Bridge 142:4eea097334d6 1101 {
Anna Bridge 142:4eea097334d6 1102 #if 1
Anna Bridge 142:4eea097334d6 1103 register uint32_t __regCPACR;
Anna Bridge 142:4eea097334d6 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Anna Bridge 142:4eea097334d6 1105 #else
Anna Bridge 142:4eea097334d6 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Anna Bridge 142:4eea097334d6 1107 #endif
Anna Bridge 142:4eea097334d6 1108 return __regCPACR;
Anna Bridge 142:4eea097334d6 1109 }
Anna Bridge 142:4eea097334d6 1110
Anna Bridge 142:4eea097334d6 1111 /** \brief Set CPACR
Anna Bridge 142:4eea097334d6 1112
Anna Bridge 142:4eea097334d6 1113 This function assigns the given value to the Coprocessor Access Control register.
Anna Bridge 142:4eea097334d6 1114
Anna Bridge 142:4eea097334d6 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Anna Bridge 142:4eea097334d6 1116 */
Anna Bridge 142:4eea097334d6 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Anna Bridge 142:4eea097334d6 1118 {
Anna Bridge 142:4eea097334d6 1119 #if 1
Anna Bridge 142:4eea097334d6 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Anna Bridge 142:4eea097334d6 1121 #else
Anna Bridge 142:4eea097334d6 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Anna Bridge 142:4eea097334d6 1123 __regCPACR = cpacr;
Anna Bridge 142:4eea097334d6 1124 #endif
Anna Bridge 142:4eea097334d6 1125 __ISB();
Anna Bridge 142:4eea097334d6 1126 }
Anna Bridge 142:4eea097334d6 1127
Anna Bridge 142:4eea097334d6 1128 /** \brief Get CBAR
Anna Bridge 142:4eea097334d6 1129
Anna Bridge 142:4eea097334d6 1130 This function returns the value of the Configuration Base Address register.
Anna Bridge 142:4eea097334d6 1131
Anna Bridge 142:4eea097334d6 1132 \return Configuration Base Address register value
Anna Bridge 142:4eea097334d6 1133 */
Anna Bridge 142:4eea097334d6 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Anna Bridge 142:4eea097334d6 1135 #if 1
Anna Bridge 142:4eea097334d6 1136 register uint32_t __regCBAR;
Anna Bridge 142:4eea097334d6 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Anna Bridge 142:4eea097334d6 1138 #else
Anna Bridge 142:4eea097334d6 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Anna Bridge 142:4eea097334d6 1140 #endif
Anna Bridge 142:4eea097334d6 1141 return(__regCBAR);
Anna Bridge 142:4eea097334d6 1142 }
Anna Bridge 142:4eea097334d6 1143
Anna Bridge 142:4eea097334d6 1144 /** \brief Get TTBR0
Anna Bridge 142:4eea097334d6 1145
Anna Bridge 142:4eea097334d6 1146 This function returns the value of the Translation Table Base Register 0.
Anna Bridge 142:4eea097334d6 1147
Anna Bridge 142:4eea097334d6 1148 \return Translation Table Base Register 0 value
Anna Bridge 142:4eea097334d6 1149 */
Anna Bridge 142:4eea097334d6 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Anna Bridge 142:4eea097334d6 1151 #if 1
Anna Bridge 142:4eea097334d6 1152 register uint32_t __regTTBR0;
Anna Bridge 142:4eea097334d6 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Anna Bridge 142:4eea097334d6 1154 #else
Anna Bridge 142:4eea097334d6 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Anna Bridge 142:4eea097334d6 1156 #endif
Anna Bridge 142:4eea097334d6 1157 return(__regTTBR0);
Anna Bridge 142:4eea097334d6 1158 }
Anna Bridge 142:4eea097334d6 1159
Anna Bridge 142:4eea097334d6 1160 /** \brief Set TTBR0
Anna Bridge 142:4eea097334d6 1161
Anna Bridge 142:4eea097334d6 1162 This function assigns the given value to the Translation Table Base Register 0.
Anna Bridge 142:4eea097334d6 1163
Anna Bridge 142:4eea097334d6 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Anna Bridge 142:4eea097334d6 1165 */
Anna Bridge 142:4eea097334d6 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Anna Bridge 142:4eea097334d6 1167 #if 1
Anna Bridge 142:4eea097334d6 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Anna Bridge 142:4eea097334d6 1169 #else
Anna Bridge 142:4eea097334d6 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Anna Bridge 142:4eea097334d6 1171 __regTTBR0 = ttbr0;
Anna Bridge 142:4eea097334d6 1172 #endif
Anna Bridge 142:4eea097334d6 1173 __ISB();
Anna Bridge 142:4eea097334d6 1174 }
Anna Bridge 142:4eea097334d6 1175
Anna Bridge 142:4eea097334d6 1176 /** \brief Get DACR
Anna Bridge 142:4eea097334d6 1177
Anna Bridge 142:4eea097334d6 1178 This function returns the value of the Domain Access Control Register.
Anna Bridge 142:4eea097334d6 1179
Anna Bridge 142:4eea097334d6 1180 \return Domain Access Control Register value
Anna Bridge 142:4eea097334d6 1181 */
Anna Bridge 142:4eea097334d6 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Anna Bridge 142:4eea097334d6 1183 #if 1
Anna Bridge 142:4eea097334d6 1184 register uint32_t __regDACR;
Anna Bridge 142:4eea097334d6 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Anna Bridge 142:4eea097334d6 1186 #else
Anna Bridge 142:4eea097334d6 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Anna Bridge 142:4eea097334d6 1188 #endif
Anna Bridge 142:4eea097334d6 1189 return(__regDACR);
Anna Bridge 142:4eea097334d6 1190 }
Anna Bridge 142:4eea097334d6 1191
Anna Bridge 142:4eea097334d6 1192 /** \brief Set DACR
Anna Bridge 142:4eea097334d6 1193
Anna Bridge 142:4eea097334d6 1194 This function assigns the given value to the Domain Access Control Register.
Anna Bridge 142:4eea097334d6 1195
Anna Bridge 142:4eea097334d6 1196 \param [in] dacr Domain Access Control Register value to set
Anna Bridge 142:4eea097334d6 1197 */
Anna Bridge 142:4eea097334d6 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Anna Bridge 142:4eea097334d6 1199 #if 1
Anna Bridge 142:4eea097334d6 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Anna Bridge 142:4eea097334d6 1201 #else
Anna Bridge 142:4eea097334d6 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Anna Bridge 142:4eea097334d6 1203 __regDACR = dacr;
Anna Bridge 142:4eea097334d6 1204 #endif
Anna Bridge 142:4eea097334d6 1205 __ISB();
Anna Bridge 142:4eea097334d6 1206 }
Anna Bridge 142:4eea097334d6 1207
Anna Bridge 142:4eea097334d6 1208 /******************************** Cache and BTAC enable ****************************************************/
Anna Bridge 142:4eea097334d6 1209
Anna Bridge 142:4eea097334d6 1210 /** \brief Set SCTLR
Anna Bridge 142:4eea097334d6 1211
Anna Bridge 142:4eea097334d6 1212 This function assigns the given value to the System Control Register.
Anna Bridge 142:4eea097334d6 1213
Anna Bridge 142:4eea097334d6 1214 \param [in] sctlr System Control Register value to set
Anna Bridge 142:4eea097334d6 1215 */
Anna Bridge 142:4eea097334d6 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Anna Bridge 142:4eea097334d6 1217 {
Anna Bridge 142:4eea097334d6 1218 #if 1
Anna Bridge 142:4eea097334d6 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Anna Bridge 142:4eea097334d6 1220 #else
Anna Bridge 142:4eea097334d6 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Anna Bridge 142:4eea097334d6 1222 __regSCTLR = sctlr;
Anna Bridge 142:4eea097334d6 1223 #endif
Anna Bridge 142:4eea097334d6 1224 }
Anna Bridge 142:4eea097334d6 1225
Anna Bridge 142:4eea097334d6 1226 /** \brief Get SCTLR
Anna Bridge 142:4eea097334d6 1227
Anna Bridge 142:4eea097334d6 1228 This function returns the value of the System Control Register.
Anna Bridge 142:4eea097334d6 1229
Anna Bridge 142:4eea097334d6 1230 \return System Control Register value
Anna Bridge 142:4eea097334d6 1231 */
Anna Bridge 142:4eea097334d6 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Anna Bridge 142:4eea097334d6 1233 #if 1
Anna Bridge 142:4eea097334d6 1234 register uint32_t __regSCTLR;
Anna Bridge 142:4eea097334d6 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Anna Bridge 142:4eea097334d6 1236 #else
Anna Bridge 142:4eea097334d6 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Anna Bridge 142:4eea097334d6 1238 #endif
Anna Bridge 142:4eea097334d6 1239 return(__regSCTLR);
Anna Bridge 142:4eea097334d6 1240 }
Anna Bridge 142:4eea097334d6 1241
Anna Bridge 142:4eea097334d6 1242 /** \brief Enable Caches
Anna Bridge 142:4eea097334d6 1243
Anna Bridge 142:4eea097334d6 1244 Enable Caches
Anna Bridge 142:4eea097334d6 1245 */
Anna Bridge 142:4eea097334d6 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Anna Bridge 142:4eea097334d6 1247 // Set I bit 12 to enable I Cache
Anna Bridge 142:4eea097334d6 1248 // Set C bit 2 to enable D Cache
Anna Bridge 142:4eea097334d6 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Anna Bridge 142:4eea097334d6 1250 }
Anna Bridge 142:4eea097334d6 1251
Anna Bridge 142:4eea097334d6 1252 /** \brief Disable Caches
Anna Bridge 142:4eea097334d6 1253
Anna Bridge 142:4eea097334d6 1254 Disable Caches
Anna Bridge 142:4eea097334d6 1255 */
Anna Bridge 142:4eea097334d6 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Anna Bridge 142:4eea097334d6 1257 // Clear I bit 12 to disable I Cache
Anna Bridge 142:4eea097334d6 1258 // Clear C bit 2 to disable D Cache
Anna Bridge 142:4eea097334d6 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Anna Bridge 142:4eea097334d6 1260 __ISB();
Anna Bridge 142:4eea097334d6 1261 }
Anna Bridge 142:4eea097334d6 1262
Anna Bridge 142:4eea097334d6 1263 /** \brief Enable BTAC
Anna Bridge 142:4eea097334d6 1264
Anna Bridge 142:4eea097334d6 1265 Enable BTAC
Anna Bridge 142:4eea097334d6 1266 */
Anna Bridge 142:4eea097334d6 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Anna Bridge 142:4eea097334d6 1268 // Set Z bit 11 to enable branch prediction
Anna Bridge 142:4eea097334d6 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Anna Bridge 142:4eea097334d6 1270 __ISB();
Anna Bridge 142:4eea097334d6 1271 }
Anna Bridge 142:4eea097334d6 1272
Anna Bridge 142:4eea097334d6 1273 /** \brief Disable BTAC
Anna Bridge 142:4eea097334d6 1274
Anna Bridge 142:4eea097334d6 1275 Disable BTAC
Anna Bridge 142:4eea097334d6 1276 */
Anna Bridge 142:4eea097334d6 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Anna Bridge 142:4eea097334d6 1278 // Clear Z bit 11 to disable branch prediction
Anna Bridge 142:4eea097334d6 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Anna Bridge 142:4eea097334d6 1280 }
Anna Bridge 142:4eea097334d6 1281
Anna Bridge 142:4eea097334d6 1282
Anna Bridge 142:4eea097334d6 1283 /** \brief Enable MMU
Anna Bridge 142:4eea097334d6 1284
Anna Bridge 142:4eea097334d6 1285 Enable MMU
Anna Bridge 142:4eea097334d6 1286 */
Anna Bridge 142:4eea097334d6 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Anna Bridge 142:4eea097334d6 1288 // Set M bit 0 to enable the MMU
Anna Bridge 142:4eea097334d6 1289 // Set AFE bit to enable simplified access permissions model
Anna Bridge 142:4eea097334d6 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Anna Bridge 142:4eea097334d6 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Anna Bridge 142:4eea097334d6 1292 __ISB();
Anna Bridge 142:4eea097334d6 1293 }
Anna Bridge 142:4eea097334d6 1294
Anna Bridge 142:4eea097334d6 1295 /** \brief Disable MMU
Anna Bridge 142:4eea097334d6 1296
Anna Bridge 142:4eea097334d6 1297 Disable MMU
Anna Bridge 142:4eea097334d6 1298 */
Anna Bridge 142:4eea097334d6 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Anna Bridge 142:4eea097334d6 1300 // Clear M bit 0 to disable the MMU
Anna Bridge 142:4eea097334d6 1301 __set_SCTLR( __get_SCTLR() & ~1);
Anna Bridge 142:4eea097334d6 1302 __ISB();
Anna Bridge 142:4eea097334d6 1303 }
Anna Bridge 142:4eea097334d6 1304
Anna Bridge 142:4eea097334d6 1305 /******************************** TLB maintenance operations ************************************************/
Anna Bridge 142:4eea097334d6 1306 /** \brief Invalidate the whole tlb
Anna Bridge 142:4eea097334d6 1307
Anna Bridge 142:4eea097334d6 1308 TLBIALL. Invalidate the whole tlb
Anna Bridge 142:4eea097334d6 1309 */
Anna Bridge 142:4eea097334d6 1310
Anna Bridge 142:4eea097334d6 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Anna Bridge 142:4eea097334d6 1312 #if 1
Anna Bridge 142:4eea097334d6 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Anna Bridge 142:4eea097334d6 1314 #else
Anna Bridge 142:4eea097334d6 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Anna Bridge 142:4eea097334d6 1316 __TLBIALL = 0;
Anna Bridge 142:4eea097334d6 1317 #endif
Anna Bridge 142:4eea097334d6 1318 __DSB();
Anna Bridge 142:4eea097334d6 1319 __ISB();
Anna Bridge 142:4eea097334d6 1320 }
Anna Bridge 142:4eea097334d6 1321
Anna Bridge 142:4eea097334d6 1322 /******************************** BTB maintenance operations ************************************************/
Anna Bridge 142:4eea097334d6 1323 /** \brief Invalidate entire branch predictor array
Anna Bridge 142:4eea097334d6 1324
Anna Bridge 142:4eea097334d6 1325 BPIALL. Branch Predictor Invalidate All.
Anna Bridge 142:4eea097334d6 1326 */
Anna Bridge 142:4eea097334d6 1327
Anna Bridge 142:4eea097334d6 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Anna Bridge 142:4eea097334d6 1329 #if 1
Anna Bridge 142:4eea097334d6 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Anna Bridge 142:4eea097334d6 1331 #else
Anna Bridge 142:4eea097334d6 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Anna Bridge 142:4eea097334d6 1333 __BPIALL = 0;
Anna Bridge 142:4eea097334d6 1334 #endif
Anna Bridge 142:4eea097334d6 1335 __DSB(); //ensure completion of the invalidation
Anna Bridge 142:4eea097334d6 1336 __ISB(); //ensure instruction fetch path sees new state
Anna Bridge 142:4eea097334d6 1337 }
Anna Bridge 142:4eea097334d6 1338
Anna Bridge 142:4eea097334d6 1339
Anna Bridge 142:4eea097334d6 1340 /******************************** L1 cache operations ******************************************************/
Anna Bridge 142:4eea097334d6 1341
Anna Bridge 142:4eea097334d6 1342 /** \brief Invalidate the whole I$
Anna Bridge 142:4eea097334d6 1343
Anna Bridge 142:4eea097334d6 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Anna Bridge 142:4eea097334d6 1345 */
Anna Bridge 142:4eea097334d6 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Anna Bridge 142:4eea097334d6 1347 #if 1
Anna Bridge 142:4eea097334d6 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Anna Bridge 142:4eea097334d6 1349 #else
Anna Bridge 142:4eea097334d6 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Anna Bridge 142:4eea097334d6 1351 __ICIALLU = 0;
Anna Bridge 142:4eea097334d6 1352 #endif
Anna Bridge 142:4eea097334d6 1353 __DSB(); //ensure completion of the invalidation
Anna Bridge 142:4eea097334d6 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Anna Bridge 142:4eea097334d6 1355 }
Anna Bridge 142:4eea097334d6 1356
Anna Bridge 142:4eea097334d6 1357 /** \brief Clean D$ by MVA
Anna Bridge 142:4eea097334d6 1358
Anna Bridge 142:4eea097334d6 1359 DCCMVAC. Data cache clean by MVA to PoC
Anna Bridge 142:4eea097334d6 1360 */
Anna Bridge 142:4eea097334d6 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 1362 #if 1
Anna Bridge 142:4eea097334d6 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Anna Bridge 142:4eea097334d6 1364 #else
Anna Bridge 142:4eea097334d6 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Anna Bridge 142:4eea097334d6 1366 __DCCMVAC = (uint32_t)va;
Anna Bridge 142:4eea097334d6 1367 #endif
Anna Bridge 142:4eea097334d6 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 142:4eea097334d6 1369 }
Anna Bridge 142:4eea097334d6 1370
Anna Bridge 142:4eea097334d6 1371 /** \brief Invalidate D$ by MVA
Anna Bridge 142:4eea097334d6 1372
Anna Bridge 142:4eea097334d6 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Anna Bridge 142:4eea097334d6 1374 */
Anna Bridge 142:4eea097334d6 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 1376 #if 1
Anna Bridge 142:4eea097334d6 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Anna Bridge 142:4eea097334d6 1378 #else
Anna Bridge 142:4eea097334d6 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Anna Bridge 142:4eea097334d6 1380 __DCIMVAC = (uint32_t)va;
Anna Bridge 142:4eea097334d6 1381 #endif
Anna Bridge 142:4eea097334d6 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 142:4eea097334d6 1383 }
Anna Bridge 142:4eea097334d6 1384
Anna Bridge 142:4eea097334d6 1385 /** \brief Clean and Invalidate D$ by MVA
Anna Bridge 142:4eea097334d6 1386
Anna Bridge 142:4eea097334d6 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Anna Bridge 142:4eea097334d6 1388 */
Anna Bridge 142:4eea097334d6 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Anna Bridge 142:4eea097334d6 1390 #if 1
Anna Bridge 142:4eea097334d6 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Anna Bridge 142:4eea097334d6 1392 #else
Anna Bridge 142:4eea097334d6 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Anna Bridge 142:4eea097334d6 1394 __DCCIMVAC = (uint32_t)va;
Anna Bridge 142:4eea097334d6 1395 #endif
Anna Bridge 142:4eea097334d6 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 142:4eea097334d6 1397 }
Anna Bridge 142:4eea097334d6 1398
Anna Bridge 142:4eea097334d6 1399 /** \brief Clean and Invalidate the entire data or unified cache
Anna Bridge 142:4eea097334d6 1400
Anna Bridge 142:4eea097334d6 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Anna Bridge 142:4eea097334d6 1402 */
Anna Bridge 142:4eea097334d6 1403 extern void __v7_all_cache(uint32_t op);
Anna Bridge 142:4eea097334d6 1404
Anna Bridge 142:4eea097334d6 1405
Anna Bridge 142:4eea097334d6 1406 /** \brief Invalidate the whole D$
Anna Bridge 142:4eea097334d6 1407
Anna Bridge 142:4eea097334d6 1408 DCISW. Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 1409 */
Anna Bridge 142:4eea097334d6 1410
Anna Bridge 142:4eea097334d6 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Anna Bridge 142:4eea097334d6 1412 __v7_all_cache(0);
Anna Bridge 142:4eea097334d6 1413 }
Anna Bridge 142:4eea097334d6 1414
Anna Bridge 142:4eea097334d6 1415 /** \brief Clean the whole D$
Anna Bridge 142:4eea097334d6 1416
Anna Bridge 142:4eea097334d6 1417 DCCSW. Clean by Set/Way
Anna Bridge 142:4eea097334d6 1418 */
Anna Bridge 142:4eea097334d6 1419
Anna Bridge 142:4eea097334d6 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Anna Bridge 142:4eea097334d6 1421 __v7_all_cache(1);
Anna Bridge 142:4eea097334d6 1422 }
Anna Bridge 142:4eea097334d6 1423
Anna Bridge 142:4eea097334d6 1424 /** \brief Clean and invalidate the whole D$
Anna Bridge 142:4eea097334d6 1425
Anna Bridge 142:4eea097334d6 1426 DCCISW. Clean and Invalidate by Set/Way
Anna Bridge 142:4eea097334d6 1427 */
Anna Bridge 142:4eea097334d6 1428
Anna Bridge 142:4eea097334d6 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Anna Bridge 142:4eea097334d6 1430 __v7_all_cache(2);
Anna Bridge 142:4eea097334d6 1431 }
Anna Bridge 142:4eea097334d6 1432
Anna Bridge 142:4eea097334d6 1433 #include "core_ca_mmu.h"
Anna Bridge 142:4eea097334d6 1434
Anna Bridge 142:4eea097334d6 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Anna Bridge 142:4eea097334d6 1436
Anna Bridge 142:4eea097334d6 1437 #error TASKING Compiler support not implemented for Cortex-A
Anna Bridge 142:4eea097334d6 1438
Anna Bridge 142:4eea097334d6 1439 #endif
Anna Bridge 142:4eea097334d6 1440
Anna Bridge 142:4eea097334d6 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Anna Bridge 142:4eea097334d6 1442
Anna Bridge 142:4eea097334d6 1443
Anna Bridge 142:4eea097334d6 1444 #endif /* __CORE_CAFUNC_H__ */