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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RO359B/core_caFunc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**************************************************************************//**
AnnaBridge 143:86740a56073b 2 * @file core_caFunc.h
AnnaBridge 143:86740a56073b 3 * @brief CMSIS Cortex-A Core Function Access Header File
AnnaBridge 143:86740a56073b 4 * @version V3.10
AnnaBridge 143:86740a56073b 5 * @date 30 Oct 2013
AnnaBridge 143:86740a56073b 6 *
AnnaBridge 143:86740a56073b 7 * @note
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 ******************************************************************************/
AnnaBridge 143:86740a56073b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
AnnaBridge 143:86740a56073b 11
AnnaBridge 143:86740a56073b 12 All rights reserved.
AnnaBridge 143:86740a56073b 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 143:86740a56073b 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 15 - Redistributions of source code must retain the above copyright
AnnaBridge 143:86740a56073b 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 143:86740a56073b 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 143:86740a56073b 19 documentation and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 143:86740a56073b 21 to endorse or promote products derived from this software without
AnnaBridge 143:86740a56073b 22 specific prior written permission.
AnnaBridge 143:86740a56073b 23 *
AnnaBridge 143:86740a56073b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 143:86740a56073b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 143:86740a56073b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 143:86740a56073b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 143:86740a56073b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 143:86740a56073b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 143:86740a56073b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 143:86740a56073b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 143:86740a56073b 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 35 ---------------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 36
AnnaBridge 143:86740a56073b 37
AnnaBridge 143:86740a56073b 38 #ifndef __CORE_CAFUNC_H__
AnnaBridge 143:86740a56073b 39 #define __CORE_CAFUNC_H__
AnnaBridge 143:86740a56073b 40
AnnaBridge 143:86740a56073b 41
AnnaBridge 143:86740a56073b 42 /* ########################### Core Function Access ########################### */
AnnaBridge 143:86740a56073b 43 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 143:86740a56073b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 143:86740a56073b 45 @{
AnnaBridge 143:86740a56073b 46 */
AnnaBridge 143:86740a56073b 47
AnnaBridge 143:86740a56073b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
AnnaBridge 143:86740a56073b 49 /* ARM armcc specific functions */
AnnaBridge 143:86740a56073b 50
AnnaBridge 143:86740a56073b 51 #if (__ARMCC_VERSION < 400677)
AnnaBridge 143:86740a56073b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
AnnaBridge 143:86740a56073b 53 #endif
AnnaBridge 143:86740a56073b 54
AnnaBridge 143:86740a56073b 55 #define MODE_USR 0x10
AnnaBridge 143:86740a56073b 56 #define MODE_FIQ 0x11
AnnaBridge 143:86740a56073b 57 #define MODE_IRQ 0x12
AnnaBridge 143:86740a56073b 58 #define MODE_SVC 0x13
AnnaBridge 143:86740a56073b 59 #define MODE_MON 0x16
AnnaBridge 143:86740a56073b 60 #define MODE_ABT 0x17
AnnaBridge 143:86740a56073b 61 #define MODE_HYP 0x1A
AnnaBridge 143:86740a56073b 62 #define MODE_UND 0x1B
AnnaBridge 143:86740a56073b 63 #define MODE_SYS 0x1F
AnnaBridge 143:86740a56073b 64
AnnaBridge 143:86740a56073b 65 /** \brief Get APSR Register
AnnaBridge 143:86740a56073b 66
AnnaBridge 143:86740a56073b 67 This function returns the content of the APSR Register.
AnnaBridge 143:86740a56073b 68
AnnaBridge 143:86740a56073b 69 \return APSR Register value
AnnaBridge 143:86740a56073b 70 */
AnnaBridge 143:86740a56073b 71 __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 143:86740a56073b 72 {
AnnaBridge 143:86740a56073b 73 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 143:86740a56073b 74 return(__regAPSR);
AnnaBridge 143:86740a56073b 75 }
AnnaBridge 143:86740a56073b 76
AnnaBridge 143:86740a56073b 77
AnnaBridge 143:86740a56073b 78 /** \brief Get CPSR Register
AnnaBridge 143:86740a56073b 79
AnnaBridge 143:86740a56073b 80 This function returns the content of the CPSR Register.
AnnaBridge 143:86740a56073b 81
AnnaBridge 143:86740a56073b 82 \return CPSR Register value
AnnaBridge 143:86740a56073b 83 */
AnnaBridge 143:86740a56073b 84 __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 143:86740a56073b 85 {
AnnaBridge 143:86740a56073b 86 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 143:86740a56073b 87 return(__regCPSR);
AnnaBridge 143:86740a56073b 88 }
AnnaBridge 143:86740a56073b 89
AnnaBridge 143:86740a56073b 90 /** \brief Set Stack Pointer
AnnaBridge 143:86740a56073b 91
AnnaBridge 143:86740a56073b 92 This function assigns the given value to the current stack pointer.
AnnaBridge 143:86740a56073b 93
AnnaBridge 143:86740a56073b 94 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 143:86740a56073b 95 */
AnnaBridge 143:86740a56073b 96 register uint32_t __regSP __ASM("sp");
AnnaBridge 143:86740a56073b 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 143:86740a56073b 98 {
AnnaBridge 143:86740a56073b 99 __regSP = topOfStack;
AnnaBridge 143:86740a56073b 100 }
AnnaBridge 143:86740a56073b 101
AnnaBridge 143:86740a56073b 102
AnnaBridge 143:86740a56073b 103 /** \brief Get link register
AnnaBridge 143:86740a56073b 104
AnnaBridge 143:86740a56073b 105 This function returns the value of the link register
AnnaBridge 143:86740a56073b 106
AnnaBridge 143:86740a56073b 107 \return Value of link register
AnnaBridge 143:86740a56073b 108 */
AnnaBridge 143:86740a56073b 109 register uint32_t __reglr __ASM("lr");
AnnaBridge 143:86740a56073b 110 __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 143:86740a56073b 111 {
AnnaBridge 143:86740a56073b 112 return(__reglr);
AnnaBridge 143:86740a56073b 113 }
AnnaBridge 143:86740a56073b 114
AnnaBridge 143:86740a56073b 115 /** \brief Set link register
AnnaBridge 143:86740a56073b 116
AnnaBridge 143:86740a56073b 117 This function sets the value of the link register
AnnaBridge 143:86740a56073b 118
AnnaBridge 143:86740a56073b 119 \param [in] lr LR value to set
AnnaBridge 143:86740a56073b 120 */
AnnaBridge 143:86740a56073b 121 __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 143:86740a56073b 122 {
AnnaBridge 143:86740a56073b 123 __reglr = lr;
AnnaBridge 143:86740a56073b 124 }
AnnaBridge 143:86740a56073b 125
AnnaBridge 143:86740a56073b 126 /** \brief Set Process Stack Pointer
AnnaBridge 143:86740a56073b 127
AnnaBridge 143:86740a56073b 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 143:86740a56073b 129
AnnaBridge 143:86740a56073b 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 143:86740a56073b 131 */
AnnaBridge 143:86740a56073b 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 143:86740a56073b 133 {
AnnaBridge 143:86740a56073b 134 ARM
AnnaBridge 143:86740a56073b 135 PRESERVE8
AnnaBridge 143:86740a56073b 136
AnnaBridge 143:86740a56073b 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
AnnaBridge 143:86740a56073b 138 MRS R1, CPSR
AnnaBridge 143:86740a56073b 139 CPS #MODE_SYS ;no effect in USR mode
AnnaBridge 143:86740a56073b 140 MOV SP, R0
AnnaBridge 143:86740a56073b 141 MSR CPSR_c, R1 ;no effect in USR mode
AnnaBridge 143:86740a56073b 142 ISB
AnnaBridge 143:86740a56073b 143 BX LR
AnnaBridge 143:86740a56073b 144
AnnaBridge 143:86740a56073b 145 }
AnnaBridge 143:86740a56073b 146
AnnaBridge 143:86740a56073b 147 /** \brief Set User Mode
AnnaBridge 143:86740a56073b 148
AnnaBridge 143:86740a56073b 149 This function changes the processor state to User Mode
AnnaBridge 143:86740a56073b 150 */
AnnaBridge 143:86740a56073b 151 __STATIC_ASM void __set_CPS_USR(void)
AnnaBridge 143:86740a56073b 152 {
AnnaBridge 143:86740a56073b 153 ARM
AnnaBridge 143:86740a56073b 154
AnnaBridge 143:86740a56073b 155 CPS #MODE_USR
AnnaBridge 143:86740a56073b 156 BX LR
AnnaBridge 143:86740a56073b 157 }
AnnaBridge 143:86740a56073b 158
AnnaBridge 143:86740a56073b 159
AnnaBridge 143:86740a56073b 160 /** \brief Enable FIQ
AnnaBridge 143:86740a56073b 161
AnnaBridge 143:86740a56073b 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 143:86740a56073b 163 Can only be executed in Privileged modes.
AnnaBridge 143:86740a56073b 164 */
AnnaBridge 143:86740a56073b 165 #define __enable_fault_irq __enable_fiq
AnnaBridge 143:86740a56073b 166
AnnaBridge 143:86740a56073b 167
AnnaBridge 143:86740a56073b 168 /** \brief Disable FIQ
AnnaBridge 143:86740a56073b 169
AnnaBridge 143:86740a56073b 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 143:86740a56073b 171 Can only be executed in Privileged modes.
AnnaBridge 143:86740a56073b 172 */
AnnaBridge 143:86740a56073b 173 #define __disable_fault_irq __disable_fiq
AnnaBridge 143:86740a56073b 174
AnnaBridge 143:86740a56073b 175
AnnaBridge 143:86740a56073b 176 /** \brief Get FPSCR
AnnaBridge 143:86740a56073b 177
AnnaBridge 143:86740a56073b 178 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 143:86740a56073b 179
AnnaBridge 143:86740a56073b 180 \return Floating Point Status/Control register value
AnnaBridge 143:86740a56073b 181 */
AnnaBridge 143:86740a56073b 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 143:86740a56073b 183 {
AnnaBridge 143:86740a56073b 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 143:86740a56073b 185 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 143:86740a56073b 186 return(__regfpscr);
AnnaBridge 143:86740a56073b 187 #else
AnnaBridge 143:86740a56073b 188 return(0);
AnnaBridge 143:86740a56073b 189 #endif
AnnaBridge 143:86740a56073b 190 }
AnnaBridge 143:86740a56073b 191
AnnaBridge 143:86740a56073b 192
AnnaBridge 143:86740a56073b 193 /** \brief Set FPSCR
AnnaBridge 143:86740a56073b 194
AnnaBridge 143:86740a56073b 195 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 143:86740a56073b 196
AnnaBridge 143:86740a56073b 197 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 143:86740a56073b 198 */
AnnaBridge 143:86740a56073b 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 143:86740a56073b 200 {
AnnaBridge 143:86740a56073b 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 143:86740a56073b 202 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 143:86740a56073b 203 __regfpscr = (fpscr);
AnnaBridge 143:86740a56073b 204 #endif
AnnaBridge 143:86740a56073b 205 }
AnnaBridge 143:86740a56073b 206
AnnaBridge 143:86740a56073b 207 /** \brief Get FPEXC
AnnaBridge 143:86740a56073b 208
AnnaBridge 143:86740a56073b 209 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 143:86740a56073b 210
AnnaBridge 143:86740a56073b 211 \return Floating Point Exception Control register value
AnnaBridge 143:86740a56073b 212 */
AnnaBridge 143:86740a56073b 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 143:86740a56073b 214 {
AnnaBridge 143:86740a56073b 215 #if (__FPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 216 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 143:86740a56073b 217 return(__regfpexc);
AnnaBridge 143:86740a56073b 218 #else
AnnaBridge 143:86740a56073b 219 return(0);
AnnaBridge 143:86740a56073b 220 #endif
AnnaBridge 143:86740a56073b 221 }
AnnaBridge 143:86740a56073b 222
AnnaBridge 143:86740a56073b 223
AnnaBridge 143:86740a56073b 224 /** \brief Set FPEXC
AnnaBridge 143:86740a56073b 225
AnnaBridge 143:86740a56073b 226 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 143:86740a56073b 227
AnnaBridge 143:86740a56073b 228 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 143:86740a56073b 229 */
AnnaBridge 143:86740a56073b 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 143:86740a56073b 231 {
AnnaBridge 143:86740a56073b 232 #if (__FPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 233 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 143:86740a56073b 234 __regfpexc = (fpexc);
AnnaBridge 143:86740a56073b 235 #endif
AnnaBridge 143:86740a56073b 236 }
AnnaBridge 143:86740a56073b 237
AnnaBridge 143:86740a56073b 238 /** \brief Get CPACR
AnnaBridge 143:86740a56073b 239
AnnaBridge 143:86740a56073b 240 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 143:86740a56073b 241
AnnaBridge 143:86740a56073b 242 \return Coprocessor Access Control register value
AnnaBridge 143:86740a56073b 243 */
AnnaBridge 143:86740a56073b 244 __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 143:86740a56073b 245 {
AnnaBridge 143:86740a56073b 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 143:86740a56073b 247 return __regCPACR;
AnnaBridge 143:86740a56073b 248 }
AnnaBridge 143:86740a56073b 249
AnnaBridge 143:86740a56073b 250 /** \brief Set CPACR
AnnaBridge 143:86740a56073b 251
AnnaBridge 143:86740a56073b 252 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 143:86740a56073b 253
AnnaBridge 143:86740a56073b 254 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 143:86740a56073b 255 */
AnnaBridge 143:86740a56073b 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 143:86740a56073b 257 {
AnnaBridge 143:86740a56073b 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 143:86740a56073b 259 __regCPACR = cpacr;
AnnaBridge 143:86740a56073b 260 __ISB();
AnnaBridge 143:86740a56073b 261 }
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263 /** \brief Get CBAR
AnnaBridge 143:86740a56073b 264
AnnaBridge 143:86740a56073b 265 This function returns the value of the Configuration Base Address register.
AnnaBridge 143:86740a56073b 266
AnnaBridge 143:86740a56073b 267 \return Configuration Base Address register value
AnnaBridge 143:86740a56073b 268 */
AnnaBridge 143:86740a56073b 269 __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 143:86740a56073b 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 143:86740a56073b 271 return(__regCBAR);
AnnaBridge 143:86740a56073b 272 }
AnnaBridge 143:86740a56073b 273
AnnaBridge 143:86740a56073b 274 /** \brief Get TTBR0
AnnaBridge 143:86740a56073b 275
AnnaBridge 143:86740a56073b 276 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 143:86740a56073b 277
AnnaBridge 143:86740a56073b 278 \return Translation Table Base Register 0 value
AnnaBridge 143:86740a56073b 279 */
AnnaBridge 143:86740a56073b 280 __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 143:86740a56073b 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 143:86740a56073b 282 return(__regTTBR0);
AnnaBridge 143:86740a56073b 283 }
AnnaBridge 143:86740a56073b 284
AnnaBridge 143:86740a56073b 285 /** \brief Set TTBR0
AnnaBridge 143:86740a56073b 286
AnnaBridge 143:86740a56073b 287 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 143:86740a56073b 288
AnnaBridge 143:86740a56073b 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 143:86740a56073b 290 */
AnnaBridge 143:86740a56073b 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 143:86740a56073b 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 143:86740a56073b 293 __regTTBR0 = ttbr0;
AnnaBridge 143:86740a56073b 294 __ISB();
AnnaBridge 143:86740a56073b 295 }
AnnaBridge 143:86740a56073b 296
AnnaBridge 143:86740a56073b 297 /** \brief Get DACR
AnnaBridge 143:86740a56073b 298
AnnaBridge 143:86740a56073b 299 This function returns the value of the Domain Access Control Register.
AnnaBridge 143:86740a56073b 300
AnnaBridge 143:86740a56073b 301 \return Domain Access Control Register value
AnnaBridge 143:86740a56073b 302 */
AnnaBridge 143:86740a56073b 303 __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 143:86740a56073b 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 143:86740a56073b 305 return(__regDACR);
AnnaBridge 143:86740a56073b 306 }
AnnaBridge 143:86740a56073b 307
AnnaBridge 143:86740a56073b 308 /** \brief Set DACR
AnnaBridge 143:86740a56073b 309
AnnaBridge 143:86740a56073b 310 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 143:86740a56073b 311
AnnaBridge 143:86740a56073b 312 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 143:86740a56073b 313 */
AnnaBridge 143:86740a56073b 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 143:86740a56073b 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 143:86740a56073b 316 __regDACR = dacr;
AnnaBridge 143:86740a56073b 317 __ISB();
AnnaBridge 143:86740a56073b 318 }
AnnaBridge 143:86740a56073b 319
AnnaBridge 143:86740a56073b 320 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 143:86740a56073b 321
AnnaBridge 143:86740a56073b 322 /** \brief Set SCTLR
AnnaBridge 143:86740a56073b 323
AnnaBridge 143:86740a56073b 324 This function assigns the given value to the System Control Register.
AnnaBridge 143:86740a56073b 325
AnnaBridge 143:86740a56073b 326 \param [in] sctlr System Control Register value to set
AnnaBridge 143:86740a56073b 327 */
AnnaBridge 143:86740a56073b 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 143:86740a56073b 329 {
AnnaBridge 143:86740a56073b 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 143:86740a56073b 331 __regSCTLR = sctlr;
AnnaBridge 143:86740a56073b 332 }
AnnaBridge 143:86740a56073b 333
AnnaBridge 143:86740a56073b 334 /** \brief Get SCTLR
AnnaBridge 143:86740a56073b 335
AnnaBridge 143:86740a56073b 336 This function returns the value of the System Control Register.
AnnaBridge 143:86740a56073b 337
AnnaBridge 143:86740a56073b 338 \return System Control Register value
AnnaBridge 143:86740a56073b 339 */
AnnaBridge 143:86740a56073b 340 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 143:86740a56073b 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 143:86740a56073b 342 return(__regSCTLR);
AnnaBridge 143:86740a56073b 343 }
AnnaBridge 143:86740a56073b 344
AnnaBridge 143:86740a56073b 345 /** \brief Enable Caches
AnnaBridge 143:86740a56073b 346
AnnaBridge 143:86740a56073b 347 Enable Caches
AnnaBridge 143:86740a56073b 348 */
AnnaBridge 143:86740a56073b 349 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 143:86740a56073b 350 // Set I bit 12 to enable I Cache
AnnaBridge 143:86740a56073b 351 // Set C bit 2 to enable D Cache
AnnaBridge 143:86740a56073b 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 143:86740a56073b 353 }
AnnaBridge 143:86740a56073b 354
AnnaBridge 143:86740a56073b 355 /** \brief Disable Caches
AnnaBridge 143:86740a56073b 356
AnnaBridge 143:86740a56073b 357 Disable Caches
AnnaBridge 143:86740a56073b 358 */
AnnaBridge 143:86740a56073b 359 __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 143:86740a56073b 360 // Clear I bit 12 to disable I Cache
AnnaBridge 143:86740a56073b 361 // Clear C bit 2 to disable D Cache
AnnaBridge 143:86740a56073b 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 143:86740a56073b 363 __ISB();
AnnaBridge 143:86740a56073b 364 }
AnnaBridge 143:86740a56073b 365
AnnaBridge 143:86740a56073b 366 /** \brief Enable BTAC
AnnaBridge 143:86740a56073b 367
AnnaBridge 143:86740a56073b 368 Enable BTAC
AnnaBridge 143:86740a56073b 369 */
AnnaBridge 143:86740a56073b 370 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 143:86740a56073b 371 // Set Z bit 11 to enable branch prediction
AnnaBridge 143:86740a56073b 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 143:86740a56073b 373 __ISB();
AnnaBridge 143:86740a56073b 374 }
AnnaBridge 143:86740a56073b 375
AnnaBridge 143:86740a56073b 376 /** \brief Disable BTAC
AnnaBridge 143:86740a56073b 377
AnnaBridge 143:86740a56073b 378 Disable BTAC
AnnaBridge 143:86740a56073b 379 */
AnnaBridge 143:86740a56073b 380 __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 143:86740a56073b 381 // Clear Z bit 11 to disable branch prediction
AnnaBridge 143:86740a56073b 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 143:86740a56073b 383 }
AnnaBridge 143:86740a56073b 384
AnnaBridge 143:86740a56073b 385
AnnaBridge 143:86740a56073b 386 /** \brief Enable MMU
AnnaBridge 143:86740a56073b 387
AnnaBridge 143:86740a56073b 388 Enable MMU
AnnaBridge 143:86740a56073b 389 */
AnnaBridge 143:86740a56073b 390 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 143:86740a56073b 391 // Set M bit 0 to enable the MMU
AnnaBridge 143:86740a56073b 392 // Set AFE bit to enable simplified access permissions model
AnnaBridge 143:86740a56073b 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 143:86740a56073b 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 143:86740a56073b 395 __ISB();
AnnaBridge 143:86740a56073b 396 }
AnnaBridge 143:86740a56073b 397
AnnaBridge 143:86740a56073b 398 /** \brief Disable MMU
AnnaBridge 143:86740a56073b 399
AnnaBridge 143:86740a56073b 400 Disable MMU
AnnaBridge 143:86740a56073b 401 */
AnnaBridge 143:86740a56073b 402 __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 143:86740a56073b 403 // Clear M bit 0 to disable the MMU
AnnaBridge 143:86740a56073b 404 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 143:86740a56073b 405 __ISB();
AnnaBridge 143:86740a56073b 406 }
AnnaBridge 143:86740a56073b 407
AnnaBridge 143:86740a56073b 408 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 143:86740a56073b 409 /** \brief Invalidate the whole tlb
AnnaBridge 143:86740a56073b 410
AnnaBridge 143:86740a56073b 411 TLBIALL. Invalidate the whole tlb
AnnaBridge 143:86740a56073b 412 */
AnnaBridge 143:86740a56073b 413
AnnaBridge 143:86740a56073b 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 143:86740a56073b 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 143:86740a56073b 416 __TLBIALL = 0;
AnnaBridge 143:86740a56073b 417 __DSB();
AnnaBridge 143:86740a56073b 418 __ISB();
AnnaBridge 143:86740a56073b 419 }
AnnaBridge 143:86740a56073b 420
AnnaBridge 143:86740a56073b 421 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 143:86740a56073b 422 /** \brief Invalidate entire branch predictor array
AnnaBridge 143:86740a56073b 423
AnnaBridge 143:86740a56073b 424 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 143:86740a56073b 425 */
AnnaBridge 143:86740a56073b 426
AnnaBridge 143:86740a56073b 427 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 143:86740a56073b 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 143:86740a56073b 429 __BPIALL = 0;
AnnaBridge 143:86740a56073b 430 __DSB(); //ensure completion of the invalidation
AnnaBridge 143:86740a56073b 431 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 143:86740a56073b 432 }
AnnaBridge 143:86740a56073b 433
AnnaBridge 143:86740a56073b 434
AnnaBridge 143:86740a56073b 435 /******************************** L1 cache operations ******************************************************/
AnnaBridge 143:86740a56073b 436
AnnaBridge 143:86740a56073b 437 /** \brief Invalidate the whole I$
AnnaBridge 143:86740a56073b 438
AnnaBridge 143:86740a56073b 439 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 143:86740a56073b 440 */
AnnaBridge 143:86740a56073b 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 143:86740a56073b 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 143:86740a56073b 443 __ICIALLU = 0;
AnnaBridge 143:86740a56073b 444 __DSB(); //ensure completion of the invalidation
AnnaBridge 143:86740a56073b 445 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 143:86740a56073b 446 }
AnnaBridge 143:86740a56073b 447
AnnaBridge 143:86740a56073b 448 /** \brief Clean D$ by MVA
AnnaBridge 143:86740a56073b 449
AnnaBridge 143:86740a56073b 450 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 143:86740a56073b 451 */
AnnaBridge 143:86740a56073b 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 143:86740a56073b 454 __DCCMVAC = (uint32_t)va;
AnnaBridge 143:86740a56073b 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 143:86740a56073b 456 }
AnnaBridge 143:86740a56073b 457
AnnaBridge 143:86740a56073b 458 /** \brief Invalidate D$ by MVA
AnnaBridge 143:86740a56073b 459
AnnaBridge 143:86740a56073b 460 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 143:86740a56073b 461 */
AnnaBridge 143:86740a56073b 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 143:86740a56073b 464 __DCIMVAC = (uint32_t)va;
AnnaBridge 143:86740a56073b 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 143:86740a56073b 466 }
AnnaBridge 143:86740a56073b 467
AnnaBridge 143:86740a56073b 468 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 143:86740a56073b 469
AnnaBridge 143:86740a56073b 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 143:86740a56073b 471 */
AnnaBridge 143:86740a56073b 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 143:86740a56073b 474 __DCCIMVAC = (uint32_t)va;
AnnaBridge 143:86740a56073b 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 143:86740a56073b 476 }
AnnaBridge 143:86740a56073b 477
AnnaBridge 143:86740a56073b 478 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 143:86740a56073b 479
AnnaBridge 143:86740a56073b 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 143:86740a56073b 481 */
AnnaBridge 143:86740a56073b 482 #pragma push
AnnaBridge 143:86740a56073b 483 #pragma arm
AnnaBridge 143:86740a56073b 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
AnnaBridge 143:86740a56073b 485 ARM
AnnaBridge 143:86740a56073b 486
AnnaBridge 143:86740a56073b 487 PUSH {R4-R11}
AnnaBridge 143:86740a56073b 488
AnnaBridge 143:86740a56073b 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
AnnaBridge 143:86740a56073b 490 ANDS R3, R6, #0x07000000 // Extract coherency level
AnnaBridge 143:86740a56073b 491 MOV R3, R3, LSR #23 // Total cache levels << 1
AnnaBridge 143:86740a56073b 492 BEQ Finished // If 0, no need to clean
AnnaBridge 143:86740a56073b 493
AnnaBridge 143:86740a56073b 494 MOV R10, #0 // R10 holds current cache level << 1
AnnaBridge 143:86740a56073b 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
AnnaBridge 143:86740a56073b 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AnnaBridge 143:86740a56073b 497 AND R1, R1, #7 // Isolate those lower 3 bits
AnnaBridge 143:86740a56073b 498 CMP R1, #2
AnnaBridge 143:86740a56073b 499 BLT Skip // No cache or only instruction cache at this level
AnnaBridge 143:86740a56073b 500
AnnaBridge 143:86740a56073b 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
AnnaBridge 143:86740a56073b 502 ISB // ISB to sync the change to the CacheSizeID reg
AnnaBridge 143:86740a56073b 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AnnaBridge 143:86740a56073b 504 AND R2, R1, #7 // Extract the line length field
AnnaBridge 143:86740a56073b 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 143:86740a56073b 506 LDR R4, =0x3FF
AnnaBridge 143:86740a56073b 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
AnnaBridge 143:86740a56073b 508 CLZ R5, R4 // R5 is the bit position of the way size increment
AnnaBridge 143:86740a56073b 509 LDR R7, =0x7FFF
AnnaBridge 143:86740a56073b 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
AnnaBridge 143:86740a56073b 511
AnnaBridge 143:86740a56073b 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
AnnaBridge 143:86740a56073b 513
AnnaBridge 143:86740a56073b 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
AnnaBridge 143:86740a56073b 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
AnnaBridge 143:86740a56073b 516 CMP R0, #0
AnnaBridge 143:86740a56073b 517 BNE Dccsw
AnnaBridge 143:86740a56073b 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
AnnaBridge 143:86740a56073b 519 B cont
AnnaBridge 143:86740a56073b 520 Dccsw CMP R0, #1
AnnaBridge 143:86740a56073b 521 BNE Dccisw
AnnaBridge 143:86740a56073b 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
AnnaBridge 143:86740a56073b 523 B cont
AnnaBridge 143:86740a56073b 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 143:86740a56073b 525 cont SUBS R9, R9, #1 // Decrement the Way number
AnnaBridge 143:86740a56073b 526 BGE Loop3
AnnaBridge 143:86740a56073b 527 SUBS R7, R7, #1 // Decrement the Set number
AnnaBridge 143:86740a56073b 528 BGE Loop2
AnnaBridge 143:86740a56073b 529 Skip ADD R10, R10, #2 // Increment the cache number
AnnaBridge 143:86740a56073b 530 CMP R3, R10
AnnaBridge 143:86740a56073b 531 BGT Loop1
AnnaBridge 143:86740a56073b 532
AnnaBridge 143:86740a56073b 533 Finished
AnnaBridge 143:86740a56073b 534 DSB
AnnaBridge 143:86740a56073b 535 POP {R4-R11}
AnnaBridge 143:86740a56073b 536 BX lr
AnnaBridge 143:86740a56073b 537
AnnaBridge 143:86740a56073b 538 }
AnnaBridge 143:86740a56073b 539 #pragma pop
AnnaBridge 143:86740a56073b 540
AnnaBridge 143:86740a56073b 541
AnnaBridge 143:86740a56073b 542 /** \brief Invalidate the whole D$
AnnaBridge 143:86740a56073b 543
AnnaBridge 143:86740a56073b 544 DCISW. Invalidate by Set/Way
AnnaBridge 143:86740a56073b 545 */
AnnaBridge 143:86740a56073b 546
AnnaBridge 143:86740a56073b 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 143:86740a56073b 548 __v7_all_cache(0);
AnnaBridge 143:86740a56073b 549 }
AnnaBridge 143:86740a56073b 550
AnnaBridge 143:86740a56073b 551 /** \brief Clean the whole D$
AnnaBridge 143:86740a56073b 552
AnnaBridge 143:86740a56073b 553 DCCSW. Clean by Set/Way
AnnaBridge 143:86740a56073b 554 */
AnnaBridge 143:86740a56073b 555
AnnaBridge 143:86740a56073b 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 143:86740a56073b 557 __v7_all_cache(1);
AnnaBridge 143:86740a56073b 558 }
AnnaBridge 143:86740a56073b 559
AnnaBridge 143:86740a56073b 560 /** \brief Clean and invalidate the whole D$
AnnaBridge 143:86740a56073b 561
AnnaBridge 143:86740a56073b 562 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 143:86740a56073b 563 */
AnnaBridge 143:86740a56073b 564
AnnaBridge 143:86740a56073b 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 143:86740a56073b 566 __v7_all_cache(2);
AnnaBridge 143:86740a56073b 567 }
AnnaBridge 143:86740a56073b 568
AnnaBridge 143:86740a56073b 569 #include "core_ca_mmu.h"
AnnaBridge 143:86740a56073b 570
AnnaBridge 143:86740a56073b 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
AnnaBridge 143:86740a56073b 572
AnnaBridge 143:86740a56073b 573 #define __inline inline
AnnaBridge 143:86740a56073b 574
AnnaBridge 143:86740a56073b 575 inline static uint32_t __disable_irq_iar() {
AnnaBridge 143:86740a56073b 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
AnnaBridge 143:86740a56073b 577 __disable_irq();
AnnaBridge 143:86740a56073b 578 return irq_dis;
AnnaBridge 143:86740a56073b 579 }
AnnaBridge 143:86740a56073b 580
AnnaBridge 143:86740a56073b 581 #define MODE_USR 0x10
AnnaBridge 143:86740a56073b 582 #define MODE_FIQ 0x11
AnnaBridge 143:86740a56073b 583 #define MODE_IRQ 0x12
AnnaBridge 143:86740a56073b 584 #define MODE_SVC 0x13
AnnaBridge 143:86740a56073b 585 #define MODE_MON 0x16
AnnaBridge 143:86740a56073b 586 #define MODE_ABT 0x17
AnnaBridge 143:86740a56073b 587 #define MODE_HYP 0x1A
AnnaBridge 143:86740a56073b 588 #define MODE_UND 0x1B
AnnaBridge 143:86740a56073b 589 #define MODE_SYS 0x1F
AnnaBridge 143:86740a56073b 590
AnnaBridge 143:86740a56073b 591 /** \brief Set Process Stack Pointer
AnnaBridge 143:86740a56073b 592
AnnaBridge 143:86740a56073b 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 143:86740a56073b 594
AnnaBridge 143:86740a56073b 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 143:86740a56073b 596 */
AnnaBridge 143:86740a56073b 597 // from rt_CMSIS.c
AnnaBridge 143:86740a56073b 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
AnnaBridge 143:86740a56073b 599 __asm(
AnnaBridge 143:86740a56073b 600 " ARM\n"
AnnaBridge 143:86740a56073b 601 // " PRESERVE8\n"
AnnaBridge 143:86740a56073b 602
AnnaBridge 143:86740a56073b 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
AnnaBridge 143:86740a56073b 604 " MRS R1, CPSR \n"
AnnaBridge 143:86740a56073b 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
AnnaBridge 143:86740a56073b 606 " MOV SP, R0 \n"
AnnaBridge 143:86740a56073b 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
AnnaBridge 143:86740a56073b 608 " ISB \n"
AnnaBridge 143:86740a56073b 609 " BX LR \n");
AnnaBridge 143:86740a56073b 610 }
AnnaBridge 143:86740a56073b 611
AnnaBridge 143:86740a56073b 612 /** \brief Set User Mode
AnnaBridge 143:86740a56073b 613
AnnaBridge 143:86740a56073b 614 This function changes the processor state to User Mode
AnnaBridge 143:86740a56073b 615 */
AnnaBridge 143:86740a56073b 616 // from rt_CMSIS.c
AnnaBridge 143:86740a56073b 617 __arm static inline void __set_CPS_USR(void) {
AnnaBridge 143:86740a56073b 618 __asm(
AnnaBridge 143:86740a56073b 619 " ARM \n"
AnnaBridge 143:86740a56073b 620
AnnaBridge 143:86740a56073b 621 " CPS #0x10 \n" // MODE_USR
AnnaBridge 143:86740a56073b 622 " BX LR\n");
AnnaBridge 143:86740a56073b 623 }
AnnaBridge 143:86740a56073b 624
AnnaBridge 143:86740a56073b 625 /** \brief Set TTBR0
AnnaBridge 143:86740a56073b 626
AnnaBridge 143:86740a56073b 627 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 143:86740a56073b 628
AnnaBridge 143:86740a56073b 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 143:86740a56073b 630 */
AnnaBridge 143:86740a56073b 631 // from mmu_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 143:86740a56073b 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
AnnaBridge 143:86740a56073b 634 __ISB();
AnnaBridge 143:86740a56073b 635 }
AnnaBridge 143:86740a56073b 636
AnnaBridge 143:86740a56073b 637 /** \brief Set DACR
AnnaBridge 143:86740a56073b 638
AnnaBridge 143:86740a56073b 639 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 143:86740a56073b 640
AnnaBridge 143:86740a56073b 641 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 143:86740a56073b 642 */
AnnaBridge 143:86740a56073b 643 // from mmu_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 143:86740a56073b 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
AnnaBridge 143:86740a56073b 646 __ISB();
AnnaBridge 143:86740a56073b 647 }
AnnaBridge 143:86740a56073b 648
AnnaBridge 143:86740a56073b 649
AnnaBridge 143:86740a56073b 650 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 143:86740a56073b 651 /** \brief Set SCTLR
AnnaBridge 143:86740a56073b 652
AnnaBridge 143:86740a56073b 653 This function assigns the given value to the System Control Register.
AnnaBridge 143:86740a56073b 654
AnnaBridge 143:86740a56073b 655 \param [in] sctlr System Control Register value to set
AnnaBridge 143:86740a56073b 656 */
AnnaBridge 143:86740a56073b 657 // from __enable_mmu()
AnnaBridge 143:86740a56073b 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
AnnaBridge 143:86740a56073b 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
AnnaBridge 143:86740a56073b 660 }
AnnaBridge 143:86740a56073b 661
AnnaBridge 143:86740a56073b 662 /** \brief Get SCTLR
AnnaBridge 143:86740a56073b 663
AnnaBridge 143:86740a56073b 664 This function returns the value of the System Control Register.
AnnaBridge 143:86740a56073b 665
AnnaBridge 143:86740a56073b 666 \return System Control Register value
AnnaBridge 143:86740a56073b 667 */
AnnaBridge 143:86740a56073b 668 // from __enable_mmu()
AnnaBridge 143:86740a56073b 669 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 143:86740a56073b 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
AnnaBridge 143:86740a56073b 671 return __regSCTLR;
AnnaBridge 143:86740a56073b 672 }
AnnaBridge 143:86740a56073b 673
AnnaBridge 143:86740a56073b 674 /** \brief Enable Caches
AnnaBridge 143:86740a56073b 675
AnnaBridge 143:86740a56073b 676 Enable Caches
AnnaBridge 143:86740a56073b 677 */
AnnaBridge 143:86740a56073b 678 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 679 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 143:86740a56073b 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 143:86740a56073b 681 }
AnnaBridge 143:86740a56073b 682
AnnaBridge 143:86740a56073b 683 /** \brief Enable BTAC
AnnaBridge 143:86740a56073b 684
AnnaBridge 143:86740a56073b 685 Enable BTAC
AnnaBridge 143:86740a56073b 686 */
AnnaBridge 143:86740a56073b 687 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 688 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 143:86740a56073b 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 143:86740a56073b 690 __ISB();
AnnaBridge 143:86740a56073b 691 }
AnnaBridge 143:86740a56073b 692
AnnaBridge 143:86740a56073b 693 /** \brief Enable MMU
AnnaBridge 143:86740a56073b 694
AnnaBridge 143:86740a56073b 695 Enable MMU
AnnaBridge 143:86740a56073b 696 */
AnnaBridge 143:86740a56073b 697 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 698 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 143:86740a56073b 699 // Set M bit 0 to enable the MMU
AnnaBridge 143:86740a56073b 700 // Set AFE bit to enable simplified access permissions model
AnnaBridge 143:86740a56073b 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 143:86740a56073b 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 143:86740a56073b 703 __ISB();
AnnaBridge 143:86740a56073b 704 }
AnnaBridge 143:86740a56073b 705
AnnaBridge 143:86740a56073b 706 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 143:86740a56073b 707 /** \brief Invalidate the whole tlb
AnnaBridge 143:86740a56073b 708
AnnaBridge 143:86740a56073b 709 TLBIALL. Invalidate the whole tlb
AnnaBridge 143:86740a56073b 710 */
AnnaBridge 143:86740a56073b 711 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 143:86740a56073b 713 uint32_t val = 0;
AnnaBridge 143:86740a56073b 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
AnnaBridge 143:86740a56073b 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
AnnaBridge 143:86740a56073b 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
AnnaBridge 143:86740a56073b 717 __DSB();
AnnaBridge 143:86740a56073b 718 __ISB();
AnnaBridge 143:86740a56073b 719 }
AnnaBridge 143:86740a56073b 720
AnnaBridge 143:86740a56073b 721 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 143:86740a56073b 722 /** \brief Invalidate entire branch predictor array
AnnaBridge 143:86740a56073b 723
AnnaBridge 143:86740a56073b 724 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 143:86740a56073b 725 */
AnnaBridge 143:86740a56073b 726 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 727 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 143:86740a56073b 728 uint32_t val = 0;
AnnaBridge 143:86740a56073b 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
AnnaBridge 143:86740a56073b 730 __DSB(); //ensure completion of the invalidation
AnnaBridge 143:86740a56073b 731 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 143:86740a56073b 732 }
AnnaBridge 143:86740a56073b 733
AnnaBridge 143:86740a56073b 734
AnnaBridge 143:86740a56073b 735 /******************************** L1 cache operations ******************************************************/
AnnaBridge 143:86740a56073b 736
AnnaBridge 143:86740a56073b 737 /** \brief Invalidate the whole I$
AnnaBridge 143:86740a56073b 738
AnnaBridge 143:86740a56073b 739 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 143:86740a56073b 740 */
AnnaBridge 143:86740a56073b 741 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 143:86740a56073b 743 uint32_t val = 0;
AnnaBridge 143:86740a56073b 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
AnnaBridge 143:86740a56073b 745 __DSB(); //ensure completion of the invalidation
AnnaBridge 143:86740a56073b 746 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 143:86740a56073b 747 }
AnnaBridge 143:86740a56073b 748
AnnaBridge 143:86740a56073b 749 // from __v7_inv_dcache_all()
AnnaBridge 143:86740a56073b 750 __arm static inline void __v7_all_cache(uint32_t op) {
AnnaBridge 143:86740a56073b 751 __asm(
AnnaBridge 143:86740a56073b 752 " ARM \n"
AnnaBridge 143:86740a56073b 753
AnnaBridge 143:86740a56073b 754 " PUSH {R4-R11} \n"
AnnaBridge 143:86740a56073b 755
AnnaBridge 143:86740a56073b 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
AnnaBridge 143:86740a56073b 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
AnnaBridge 143:86740a56073b 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
AnnaBridge 143:86740a56073b 759 " BEQ Finished\n" // If 0, no need to clean
AnnaBridge 143:86740a56073b 760
AnnaBridge 143:86740a56073b 761 " MOV R10, #0\n" // R10 holds current cache level << 1
AnnaBridge 143:86740a56073b 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
AnnaBridge 143:86740a56073b 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
AnnaBridge 143:86740a56073b 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
AnnaBridge 143:86740a56073b 765 " CMP R1, #2 \n"
AnnaBridge 143:86740a56073b 766 " BLT Skip \n" // No cache or only instruction cache at this level
AnnaBridge 143:86740a56073b 767
AnnaBridge 143:86740a56073b 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
AnnaBridge 143:86740a56073b 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
AnnaBridge 143:86740a56073b 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
AnnaBridge 143:86740a56073b 771 " AND R2, R1, #7 \n" // Extract the line length field
AnnaBridge 143:86740a56073b 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 143:86740a56073b 773 " movw R4, #0x3FF \n"
AnnaBridge 143:86740a56073b 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
AnnaBridge 143:86740a56073b 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
AnnaBridge 143:86740a56073b 776 " movw R7, #0x7FFF \n"
AnnaBridge 143:86740a56073b 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
AnnaBridge 143:86740a56073b 778
AnnaBridge 143:86740a56073b 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
AnnaBridge 143:86740a56073b 780
AnnaBridge 143:86740a56073b 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
AnnaBridge 143:86740a56073b 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
AnnaBridge 143:86740a56073b 783 " CMP R0, #0 \n"
AnnaBridge 143:86740a56073b 784 " BNE Dccsw \n"
AnnaBridge 143:86740a56073b 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
AnnaBridge 143:86740a56073b 786 " B cont \n"
AnnaBridge 143:86740a56073b 787 "Dccsw: CMP R0, #1 \n"
AnnaBridge 143:86740a56073b 788 " BNE Dccisw \n"
AnnaBridge 143:86740a56073b 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
AnnaBridge 143:86740a56073b 790 " B cont \n"
AnnaBridge 143:86740a56073b 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
AnnaBridge 143:86740a56073b 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
AnnaBridge 143:86740a56073b 793 " BGE Loop3 \n"
AnnaBridge 143:86740a56073b 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
AnnaBridge 143:86740a56073b 795 " BGE Loop2 \n"
AnnaBridge 143:86740a56073b 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
AnnaBridge 143:86740a56073b 797 " CMP R3, R10 \n"
AnnaBridge 143:86740a56073b 798 " BGT Loop1 \n"
AnnaBridge 143:86740a56073b 799
AnnaBridge 143:86740a56073b 800 "Finished: \n"
AnnaBridge 143:86740a56073b 801 " DSB \n"
AnnaBridge 143:86740a56073b 802 " POP {R4-R11} \n"
AnnaBridge 143:86740a56073b 803 " BX lr \n" );
AnnaBridge 143:86740a56073b 804 }
AnnaBridge 143:86740a56073b 805
AnnaBridge 143:86740a56073b 806 /** \brief Invalidate the whole D$
AnnaBridge 143:86740a56073b 807
AnnaBridge 143:86740a56073b 808 DCISW. Invalidate by Set/Way
AnnaBridge 143:86740a56073b 809 */
AnnaBridge 143:86740a56073b 810 // from system_Renesas_RZ_A1.c
AnnaBridge 143:86740a56073b 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 143:86740a56073b 812 __v7_all_cache(0);
AnnaBridge 143:86740a56073b 813 }
AnnaBridge 143:86740a56073b 814 /** \brief Clean the whole D$
AnnaBridge 143:86740a56073b 815
AnnaBridge 143:86740a56073b 816 DCCSW. Clean by Set/Way
AnnaBridge 143:86740a56073b 817 */
AnnaBridge 143:86740a56073b 818
AnnaBridge 143:86740a56073b 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 143:86740a56073b 820 __v7_all_cache(1);
AnnaBridge 143:86740a56073b 821 }
AnnaBridge 143:86740a56073b 822
AnnaBridge 143:86740a56073b 823 /** \brief Clean and invalidate the whole D$
AnnaBridge 143:86740a56073b 824
AnnaBridge 143:86740a56073b 825 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 143:86740a56073b 826 */
AnnaBridge 143:86740a56073b 827
AnnaBridge 143:86740a56073b 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 143:86740a56073b 829 __v7_all_cache(2);
AnnaBridge 143:86740a56073b 830 }
AnnaBridge 143:86740a56073b 831 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 143:86740a56073b 832
AnnaBridge 143:86740a56073b 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 143:86740a56073b 834 */
AnnaBridge 143:86740a56073b 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
AnnaBridge 143:86740a56073b 837 __DMB();
AnnaBridge 143:86740a56073b 838 }
AnnaBridge 143:86740a56073b 839
AnnaBridge 143:86740a56073b 840 #include "core_ca_mmu.h"
AnnaBridge 143:86740a56073b 841
AnnaBridge 143:86740a56073b 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
AnnaBridge 143:86740a56073b 843 /* GNU gcc specific functions */
AnnaBridge 143:86740a56073b 844
AnnaBridge 143:86740a56073b 845 #define MODE_USR 0x10
AnnaBridge 143:86740a56073b 846 #define MODE_FIQ 0x11
AnnaBridge 143:86740a56073b 847 #define MODE_IRQ 0x12
AnnaBridge 143:86740a56073b 848 #define MODE_SVC 0x13
AnnaBridge 143:86740a56073b 849 #define MODE_MON 0x16
AnnaBridge 143:86740a56073b 850 #define MODE_ABT 0x17
AnnaBridge 143:86740a56073b 851 #define MODE_HYP 0x1A
AnnaBridge 143:86740a56073b 852 #define MODE_UND 0x1B
AnnaBridge 143:86740a56073b 853 #define MODE_SYS 0x1F
AnnaBridge 143:86740a56073b 854
AnnaBridge 143:86740a56073b 855
AnnaBridge 143:86740a56073b 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
AnnaBridge 143:86740a56073b 857 {
AnnaBridge 143:86740a56073b 858 __ASM volatile ("cpsie i");
AnnaBridge 143:86740a56073b 859 }
AnnaBridge 143:86740a56073b 860
AnnaBridge 143:86740a56073b 861 /** \brief Disable IRQ Interrupts
AnnaBridge 143:86740a56073b 862
AnnaBridge 143:86740a56073b 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 143:86740a56073b 864 Can only be executed in Privileged modes.
AnnaBridge 143:86740a56073b 865 */
AnnaBridge 143:86740a56073b 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
AnnaBridge 143:86740a56073b 867 {
AnnaBridge 143:86740a56073b 868 uint32_t result;
AnnaBridge 143:86740a56073b 869
AnnaBridge 143:86740a56073b 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
AnnaBridge 143:86740a56073b 871 __ASM volatile ("cpsid i");
AnnaBridge 143:86740a56073b 872 return(result & 0x80);
AnnaBridge 143:86740a56073b 873 }
AnnaBridge 143:86740a56073b 874
AnnaBridge 143:86740a56073b 875
AnnaBridge 143:86740a56073b 876 /** \brief Get APSR Register
AnnaBridge 143:86740a56073b 877
AnnaBridge 143:86740a56073b 878 This function returns the content of the APSR Register.
AnnaBridge 143:86740a56073b 879
AnnaBridge 143:86740a56073b 880 \return APSR Register value
AnnaBridge 143:86740a56073b 881 */
AnnaBridge 143:86740a56073b 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 143:86740a56073b 883 {
AnnaBridge 143:86740a56073b 884 #if 1
AnnaBridge 143:86740a56073b 885 register uint32_t __regAPSR;
AnnaBridge 143:86740a56073b 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
AnnaBridge 143:86740a56073b 887 #else
AnnaBridge 143:86740a56073b 888 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 143:86740a56073b 889 #endif
AnnaBridge 143:86740a56073b 890 return(__regAPSR);
AnnaBridge 143:86740a56073b 891 }
AnnaBridge 143:86740a56073b 892
AnnaBridge 143:86740a56073b 893
AnnaBridge 143:86740a56073b 894 /** \brief Get CPSR Register
AnnaBridge 143:86740a56073b 895
AnnaBridge 143:86740a56073b 896 This function returns the content of the CPSR Register.
AnnaBridge 143:86740a56073b 897
AnnaBridge 143:86740a56073b 898 \return CPSR Register value
AnnaBridge 143:86740a56073b 899 */
AnnaBridge 143:86740a56073b 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 143:86740a56073b 901 {
AnnaBridge 143:86740a56073b 902 #if 1
AnnaBridge 143:86740a56073b 903 register uint32_t __regCPSR;
AnnaBridge 143:86740a56073b 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
AnnaBridge 143:86740a56073b 905 #else
AnnaBridge 143:86740a56073b 906 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 143:86740a56073b 907 #endif
AnnaBridge 143:86740a56073b 908 return(__regCPSR);
AnnaBridge 143:86740a56073b 909 }
AnnaBridge 143:86740a56073b 910
AnnaBridge 143:86740a56073b 911 #if 0
AnnaBridge 143:86740a56073b 912 /** \brief Set Stack Pointer
AnnaBridge 143:86740a56073b 913
AnnaBridge 143:86740a56073b 914 This function assigns the given value to the current stack pointer.
AnnaBridge 143:86740a56073b 915
AnnaBridge 143:86740a56073b 916 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 143:86740a56073b 917 */
AnnaBridge 143:86740a56073b 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 143:86740a56073b 919 {
AnnaBridge 143:86740a56073b 920 register uint32_t __regSP __ASM("sp");
AnnaBridge 143:86740a56073b 921 __regSP = topOfStack;
AnnaBridge 143:86740a56073b 922 }
AnnaBridge 143:86740a56073b 923 #endif
AnnaBridge 143:86740a56073b 924
AnnaBridge 143:86740a56073b 925 /** \brief Get link register
AnnaBridge 143:86740a56073b 926
AnnaBridge 143:86740a56073b 927 This function returns the value of the link register
AnnaBridge 143:86740a56073b 928
AnnaBridge 143:86740a56073b 929 \return Value of link register
AnnaBridge 143:86740a56073b 930 */
AnnaBridge 143:86740a56073b 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 143:86740a56073b 932 {
AnnaBridge 143:86740a56073b 933 register uint32_t __reglr __ASM("lr");
AnnaBridge 143:86740a56073b 934 return(__reglr);
AnnaBridge 143:86740a56073b 935 }
AnnaBridge 143:86740a56073b 936
AnnaBridge 143:86740a56073b 937 #if 0
AnnaBridge 143:86740a56073b 938 /** \brief Set link register
AnnaBridge 143:86740a56073b 939
AnnaBridge 143:86740a56073b 940 This function sets the value of the link register
AnnaBridge 143:86740a56073b 941
AnnaBridge 143:86740a56073b 942 \param [in] lr LR value to set
AnnaBridge 143:86740a56073b 943 */
AnnaBridge 143:86740a56073b 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 143:86740a56073b 945 {
AnnaBridge 143:86740a56073b 946 register uint32_t __reglr __ASM("lr");
AnnaBridge 143:86740a56073b 947 __reglr = lr;
AnnaBridge 143:86740a56073b 948 }
AnnaBridge 143:86740a56073b 949 #endif
AnnaBridge 143:86740a56073b 950
AnnaBridge 143:86740a56073b 951 /** \brief Set Process Stack Pointer
AnnaBridge 143:86740a56073b 952
AnnaBridge 143:86740a56073b 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 143:86740a56073b 954
AnnaBridge 143:86740a56073b 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 143:86740a56073b 956 */
AnnaBridge 143:86740a56073b 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 143:86740a56073b 958 {
AnnaBridge 143:86740a56073b 959 __asm__ volatile (
AnnaBridge 143:86740a56073b 960 ".ARM;"
AnnaBridge 143:86740a56073b 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
AnnaBridge 143:86740a56073b 962
AnnaBridge 143:86740a56073b 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
AnnaBridge 143:86740a56073b 964 "MRS R1, CPSR;"
AnnaBridge 143:86740a56073b 965 "CPS %0;" /* ;no effect in USR mode */
AnnaBridge 143:86740a56073b 966 "MOV SP, R0;"
AnnaBridge 143:86740a56073b 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
AnnaBridge 143:86740a56073b 968 "ISB;"
AnnaBridge 143:86740a56073b 969 //"BX LR;"
AnnaBridge 143:86740a56073b 970 :
AnnaBridge 143:86740a56073b 971 : "i"(MODE_SYS)
AnnaBridge 143:86740a56073b 972 : "r0", "r1");
AnnaBridge 143:86740a56073b 973 return;
AnnaBridge 143:86740a56073b 974 }
AnnaBridge 143:86740a56073b 975
AnnaBridge 143:86740a56073b 976 /** \brief Set User Mode
AnnaBridge 143:86740a56073b 977
AnnaBridge 143:86740a56073b 978 This function changes the processor state to User Mode
AnnaBridge 143:86740a56073b 979 */
AnnaBridge 143:86740a56073b 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
AnnaBridge 143:86740a56073b 981 {
AnnaBridge 143:86740a56073b 982 __asm__ volatile (
AnnaBridge 143:86740a56073b 983 ".ARM;"
AnnaBridge 143:86740a56073b 984
AnnaBridge 143:86740a56073b 985 "CPS %0;"
AnnaBridge 143:86740a56073b 986 //"BX LR;"
AnnaBridge 143:86740a56073b 987 :
AnnaBridge 143:86740a56073b 988 : "i"(MODE_USR)
AnnaBridge 143:86740a56073b 989 : );
AnnaBridge 143:86740a56073b 990 return;
AnnaBridge 143:86740a56073b 991 }
AnnaBridge 143:86740a56073b 992
AnnaBridge 143:86740a56073b 993
AnnaBridge 143:86740a56073b 994 /** \brief Enable FIQ
AnnaBridge 143:86740a56073b 995
AnnaBridge 143:86740a56073b 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 143:86740a56073b 997 Can only be executed in Privileged modes.
AnnaBridge 143:86740a56073b 998 */
AnnaBridge 143:86740a56073b 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
AnnaBridge 143:86740a56073b 1000
AnnaBridge 143:86740a56073b 1001
AnnaBridge 143:86740a56073b 1002 /** \brief Disable FIQ
AnnaBridge 143:86740a56073b 1003
AnnaBridge 143:86740a56073b 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 143:86740a56073b 1005 Can only be executed in Privileged modes.
AnnaBridge 143:86740a56073b 1006 */
AnnaBridge 143:86740a56073b 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
AnnaBridge 143:86740a56073b 1008
AnnaBridge 143:86740a56073b 1009
AnnaBridge 143:86740a56073b 1010 /** \brief Get FPSCR
AnnaBridge 143:86740a56073b 1011
AnnaBridge 143:86740a56073b 1012 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 143:86740a56073b 1013
AnnaBridge 143:86740a56073b 1014 \return Floating Point Status/Control register value
AnnaBridge 143:86740a56073b 1015 */
AnnaBridge 143:86740a56073b 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 143:86740a56073b 1017 {
AnnaBridge 143:86740a56073b 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 143:86740a56073b 1019 #if 1
AnnaBridge 143:86740a56073b 1020 uint32_t result;
AnnaBridge 143:86740a56073b 1021
AnnaBridge 143:86740a56073b 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
AnnaBridge 143:86740a56073b 1023 return (result);
AnnaBridge 143:86740a56073b 1024 #else
AnnaBridge 143:86740a56073b 1025 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 143:86740a56073b 1026 return(__regfpscr);
AnnaBridge 143:86740a56073b 1027 #endif
AnnaBridge 143:86740a56073b 1028 #else
AnnaBridge 143:86740a56073b 1029 return(0);
AnnaBridge 143:86740a56073b 1030 #endif
AnnaBridge 143:86740a56073b 1031 }
AnnaBridge 143:86740a56073b 1032
AnnaBridge 143:86740a56073b 1033
AnnaBridge 143:86740a56073b 1034 /** \brief Set FPSCR
AnnaBridge 143:86740a56073b 1035
AnnaBridge 143:86740a56073b 1036 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 143:86740a56073b 1037
AnnaBridge 143:86740a56073b 1038 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 143:86740a56073b 1039 */
AnnaBridge 143:86740a56073b 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 143:86740a56073b 1041 {
AnnaBridge 143:86740a56073b 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 143:86740a56073b 1043 #if 1
AnnaBridge 143:86740a56073b 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
AnnaBridge 143:86740a56073b 1045 #else
AnnaBridge 143:86740a56073b 1046 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 143:86740a56073b 1047 __regfpscr = (fpscr);
AnnaBridge 143:86740a56073b 1048 #endif
AnnaBridge 143:86740a56073b 1049 #endif
AnnaBridge 143:86740a56073b 1050 }
AnnaBridge 143:86740a56073b 1051
AnnaBridge 143:86740a56073b 1052 /** \brief Get FPEXC
AnnaBridge 143:86740a56073b 1053
AnnaBridge 143:86740a56073b 1054 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 143:86740a56073b 1055
AnnaBridge 143:86740a56073b 1056 \return Floating Point Exception Control register value
AnnaBridge 143:86740a56073b 1057 */
AnnaBridge 143:86740a56073b 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 143:86740a56073b 1059 {
AnnaBridge 143:86740a56073b 1060 #if (__FPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 1061 #if 1
AnnaBridge 143:86740a56073b 1062 uint32_t result;
AnnaBridge 143:86740a56073b 1063
AnnaBridge 143:86740a56073b 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
AnnaBridge 143:86740a56073b 1065 return (result);
AnnaBridge 143:86740a56073b 1066 #else
AnnaBridge 143:86740a56073b 1067 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 143:86740a56073b 1068 return(__regfpexc);
AnnaBridge 143:86740a56073b 1069 #endif
AnnaBridge 143:86740a56073b 1070 #else
AnnaBridge 143:86740a56073b 1071 return(0);
AnnaBridge 143:86740a56073b 1072 #endif
AnnaBridge 143:86740a56073b 1073 }
AnnaBridge 143:86740a56073b 1074
AnnaBridge 143:86740a56073b 1075
AnnaBridge 143:86740a56073b 1076 /** \brief Set FPEXC
AnnaBridge 143:86740a56073b 1077
AnnaBridge 143:86740a56073b 1078 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 143:86740a56073b 1079
AnnaBridge 143:86740a56073b 1080 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 143:86740a56073b 1081 */
AnnaBridge 143:86740a56073b 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 143:86740a56073b 1083 {
AnnaBridge 143:86740a56073b 1084 #if (__FPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 1085 #if 1
AnnaBridge 143:86740a56073b 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
AnnaBridge 143:86740a56073b 1087 #else
AnnaBridge 143:86740a56073b 1088 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 143:86740a56073b 1089 __regfpexc = (fpexc);
AnnaBridge 143:86740a56073b 1090 #endif
AnnaBridge 143:86740a56073b 1091 #endif
AnnaBridge 143:86740a56073b 1092 }
AnnaBridge 143:86740a56073b 1093
AnnaBridge 143:86740a56073b 1094 /** \brief Get CPACR
AnnaBridge 143:86740a56073b 1095
AnnaBridge 143:86740a56073b 1096 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 143:86740a56073b 1097
AnnaBridge 143:86740a56073b 1098 \return Coprocessor Access Control register value
AnnaBridge 143:86740a56073b 1099 */
AnnaBridge 143:86740a56073b 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 143:86740a56073b 1101 {
AnnaBridge 143:86740a56073b 1102 #if 1
AnnaBridge 143:86740a56073b 1103 register uint32_t __regCPACR;
AnnaBridge 143:86740a56073b 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
AnnaBridge 143:86740a56073b 1105 #else
AnnaBridge 143:86740a56073b 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 143:86740a56073b 1107 #endif
AnnaBridge 143:86740a56073b 1108 return __regCPACR;
AnnaBridge 143:86740a56073b 1109 }
AnnaBridge 143:86740a56073b 1110
AnnaBridge 143:86740a56073b 1111 /** \brief Set CPACR
AnnaBridge 143:86740a56073b 1112
AnnaBridge 143:86740a56073b 1113 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 143:86740a56073b 1114
AnnaBridge 143:86740a56073b 1115 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 143:86740a56073b 1116 */
AnnaBridge 143:86740a56073b 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 143:86740a56073b 1118 {
AnnaBridge 143:86740a56073b 1119 #if 1
AnnaBridge 143:86740a56073b 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
AnnaBridge 143:86740a56073b 1121 #else
AnnaBridge 143:86740a56073b 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 143:86740a56073b 1123 __regCPACR = cpacr;
AnnaBridge 143:86740a56073b 1124 #endif
AnnaBridge 143:86740a56073b 1125 __ISB();
AnnaBridge 143:86740a56073b 1126 }
AnnaBridge 143:86740a56073b 1127
AnnaBridge 143:86740a56073b 1128 /** \brief Get CBAR
AnnaBridge 143:86740a56073b 1129
AnnaBridge 143:86740a56073b 1130 This function returns the value of the Configuration Base Address register.
AnnaBridge 143:86740a56073b 1131
AnnaBridge 143:86740a56073b 1132 \return Configuration Base Address register value
AnnaBridge 143:86740a56073b 1133 */
AnnaBridge 143:86740a56073b 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 143:86740a56073b 1135 #if 1
AnnaBridge 143:86740a56073b 1136 register uint32_t __regCBAR;
AnnaBridge 143:86740a56073b 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
AnnaBridge 143:86740a56073b 1138 #else
AnnaBridge 143:86740a56073b 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 143:86740a56073b 1140 #endif
AnnaBridge 143:86740a56073b 1141 return(__regCBAR);
AnnaBridge 143:86740a56073b 1142 }
AnnaBridge 143:86740a56073b 1143
AnnaBridge 143:86740a56073b 1144 /** \brief Get TTBR0
AnnaBridge 143:86740a56073b 1145
AnnaBridge 143:86740a56073b 1146 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 143:86740a56073b 1147
AnnaBridge 143:86740a56073b 1148 \return Translation Table Base Register 0 value
AnnaBridge 143:86740a56073b 1149 */
AnnaBridge 143:86740a56073b 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 143:86740a56073b 1151 #if 1
AnnaBridge 143:86740a56073b 1152 register uint32_t __regTTBR0;
AnnaBridge 143:86740a56073b 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
AnnaBridge 143:86740a56073b 1154 #else
AnnaBridge 143:86740a56073b 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 143:86740a56073b 1156 #endif
AnnaBridge 143:86740a56073b 1157 return(__regTTBR0);
AnnaBridge 143:86740a56073b 1158 }
AnnaBridge 143:86740a56073b 1159
AnnaBridge 143:86740a56073b 1160 /** \brief Set TTBR0
AnnaBridge 143:86740a56073b 1161
AnnaBridge 143:86740a56073b 1162 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 143:86740a56073b 1163
AnnaBridge 143:86740a56073b 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 143:86740a56073b 1165 */
AnnaBridge 143:86740a56073b 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 143:86740a56073b 1167 #if 1
AnnaBridge 143:86740a56073b 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
AnnaBridge 143:86740a56073b 1169 #else
AnnaBridge 143:86740a56073b 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 143:86740a56073b 1171 __regTTBR0 = ttbr0;
AnnaBridge 143:86740a56073b 1172 #endif
AnnaBridge 143:86740a56073b 1173 __ISB();
AnnaBridge 143:86740a56073b 1174 }
AnnaBridge 143:86740a56073b 1175
AnnaBridge 143:86740a56073b 1176 /** \brief Get DACR
AnnaBridge 143:86740a56073b 1177
AnnaBridge 143:86740a56073b 1178 This function returns the value of the Domain Access Control Register.
AnnaBridge 143:86740a56073b 1179
AnnaBridge 143:86740a56073b 1180 \return Domain Access Control Register value
AnnaBridge 143:86740a56073b 1181 */
AnnaBridge 143:86740a56073b 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 143:86740a56073b 1183 #if 1
AnnaBridge 143:86740a56073b 1184 register uint32_t __regDACR;
AnnaBridge 143:86740a56073b 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
AnnaBridge 143:86740a56073b 1186 #else
AnnaBridge 143:86740a56073b 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 143:86740a56073b 1188 #endif
AnnaBridge 143:86740a56073b 1189 return(__regDACR);
AnnaBridge 143:86740a56073b 1190 }
AnnaBridge 143:86740a56073b 1191
AnnaBridge 143:86740a56073b 1192 /** \brief Set DACR
AnnaBridge 143:86740a56073b 1193
AnnaBridge 143:86740a56073b 1194 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 143:86740a56073b 1195
AnnaBridge 143:86740a56073b 1196 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 143:86740a56073b 1197 */
AnnaBridge 143:86740a56073b 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 143:86740a56073b 1199 #if 1
AnnaBridge 143:86740a56073b 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
AnnaBridge 143:86740a56073b 1201 #else
AnnaBridge 143:86740a56073b 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 143:86740a56073b 1203 __regDACR = dacr;
AnnaBridge 143:86740a56073b 1204 #endif
AnnaBridge 143:86740a56073b 1205 __ISB();
AnnaBridge 143:86740a56073b 1206 }
AnnaBridge 143:86740a56073b 1207
AnnaBridge 143:86740a56073b 1208 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 143:86740a56073b 1209
AnnaBridge 143:86740a56073b 1210 /** \brief Set SCTLR
AnnaBridge 143:86740a56073b 1211
AnnaBridge 143:86740a56073b 1212 This function assigns the given value to the System Control Register.
AnnaBridge 143:86740a56073b 1213
AnnaBridge 143:86740a56073b 1214 \param [in] sctlr System Control Register value to set
AnnaBridge 143:86740a56073b 1215 */
AnnaBridge 143:86740a56073b 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 143:86740a56073b 1217 {
AnnaBridge 143:86740a56073b 1218 #if 1
AnnaBridge 143:86740a56073b 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
AnnaBridge 143:86740a56073b 1220 #else
AnnaBridge 143:86740a56073b 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 143:86740a56073b 1222 __regSCTLR = sctlr;
AnnaBridge 143:86740a56073b 1223 #endif
AnnaBridge 143:86740a56073b 1224 }
AnnaBridge 143:86740a56073b 1225
AnnaBridge 143:86740a56073b 1226 /** \brief Get SCTLR
AnnaBridge 143:86740a56073b 1227
AnnaBridge 143:86740a56073b 1228 This function returns the value of the System Control Register.
AnnaBridge 143:86740a56073b 1229
AnnaBridge 143:86740a56073b 1230 \return System Control Register value
AnnaBridge 143:86740a56073b 1231 */
AnnaBridge 143:86740a56073b 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 143:86740a56073b 1233 #if 1
AnnaBridge 143:86740a56073b 1234 register uint32_t __regSCTLR;
AnnaBridge 143:86740a56073b 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
AnnaBridge 143:86740a56073b 1236 #else
AnnaBridge 143:86740a56073b 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 143:86740a56073b 1238 #endif
AnnaBridge 143:86740a56073b 1239 return(__regSCTLR);
AnnaBridge 143:86740a56073b 1240 }
AnnaBridge 143:86740a56073b 1241
AnnaBridge 143:86740a56073b 1242 /** \brief Enable Caches
AnnaBridge 143:86740a56073b 1243
AnnaBridge 143:86740a56073b 1244 Enable Caches
AnnaBridge 143:86740a56073b 1245 */
AnnaBridge 143:86740a56073b 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 143:86740a56073b 1247 // Set I bit 12 to enable I Cache
AnnaBridge 143:86740a56073b 1248 // Set C bit 2 to enable D Cache
AnnaBridge 143:86740a56073b 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 143:86740a56073b 1250 }
AnnaBridge 143:86740a56073b 1251
AnnaBridge 143:86740a56073b 1252 /** \brief Disable Caches
AnnaBridge 143:86740a56073b 1253
AnnaBridge 143:86740a56073b 1254 Disable Caches
AnnaBridge 143:86740a56073b 1255 */
AnnaBridge 143:86740a56073b 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 143:86740a56073b 1257 // Clear I bit 12 to disable I Cache
AnnaBridge 143:86740a56073b 1258 // Clear C bit 2 to disable D Cache
AnnaBridge 143:86740a56073b 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 143:86740a56073b 1260 __ISB();
AnnaBridge 143:86740a56073b 1261 }
AnnaBridge 143:86740a56073b 1262
AnnaBridge 143:86740a56073b 1263 /** \brief Enable BTAC
AnnaBridge 143:86740a56073b 1264
AnnaBridge 143:86740a56073b 1265 Enable BTAC
AnnaBridge 143:86740a56073b 1266 */
AnnaBridge 143:86740a56073b 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 143:86740a56073b 1268 // Set Z bit 11 to enable branch prediction
AnnaBridge 143:86740a56073b 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 143:86740a56073b 1270 __ISB();
AnnaBridge 143:86740a56073b 1271 }
AnnaBridge 143:86740a56073b 1272
AnnaBridge 143:86740a56073b 1273 /** \brief Disable BTAC
AnnaBridge 143:86740a56073b 1274
AnnaBridge 143:86740a56073b 1275 Disable BTAC
AnnaBridge 143:86740a56073b 1276 */
AnnaBridge 143:86740a56073b 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 143:86740a56073b 1278 // Clear Z bit 11 to disable branch prediction
AnnaBridge 143:86740a56073b 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 143:86740a56073b 1280 }
AnnaBridge 143:86740a56073b 1281
AnnaBridge 143:86740a56073b 1282
AnnaBridge 143:86740a56073b 1283 /** \brief Enable MMU
AnnaBridge 143:86740a56073b 1284
AnnaBridge 143:86740a56073b 1285 Enable MMU
AnnaBridge 143:86740a56073b 1286 */
AnnaBridge 143:86740a56073b 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 143:86740a56073b 1288 // Set M bit 0 to enable the MMU
AnnaBridge 143:86740a56073b 1289 // Set AFE bit to enable simplified access permissions model
AnnaBridge 143:86740a56073b 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 143:86740a56073b 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 143:86740a56073b 1292 __ISB();
AnnaBridge 143:86740a56073b 1293 }
AnnaBridge 143:86740a56073b 1294
AnnaBridge 143:86740a56073b 1295 /** \brief Disable MMU
AnnaBridge 143:86740a56073b 1296
AnnaBridge 143:86740a56073b 1297 Disable MMU
AnnaBridge 143:86740a56073b 1298 */
AnnaBridge 143:86740a56073b 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 143:86740a56073b 1300 // Clear M bit 0 to disable the MMU
AnnaBridge 143:86740a56073b 1301 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 143:86740a56073b 1302 __ISB();
AnnaBridge 143:86740a56073b 1303 }
AnnaBridge 143:86740a56073b 1304
AnnaBridge 143:86740a56073b 1305 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 143:86740a56073b 1306 /** \brief Invalidate the whole tlb
AnnaBridge 143:86740a56073b 1307
AnnaBridge 143:86740a56073b 1308 TLBIALL. Invalidate the whole tlb
AnnaBridge 143:86740a56073b 1309 */
AnnaBridge 143:86740a56073b 1310
AnnaBridge 143:86740a56073b 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 143:86740a56073b 1312 #if 1
AnnaBridge 143:86740a56073b 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
AnnaBridge 143:86740a56073b 1314 #else
AnnaBridge 143:86740a56073b 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 143:86740a56073b 1316 __TLBIALL = 0;
AnnaBridge 143:86740a56073b 1317 #endif
AnnaBridge 143:86740a56073b 1318 __DSB();
AnnaBridge 143:86740a56073b 1319 __ISB();
AnnaBridge 143:86740a56073b 1320 }
AnnaBridge 143:86740a56073b 1321
AnnaBridge 143:86740a56073b 1322 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 143:86740a56073b 1323 /** \brief Invalidate entire branch predictor array
AnnaBridge 143:86740a56073b 1324
AnnaBridge 143:86740a56073b 1325 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 143:86740a56073b 1326 */
AnnaBridge 143:86740a56073b 1327
AnnaBridge 143:86740a56073b 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 143:86740a56073b 1329 #if 1
AnnaBridge 143:86740a56073b 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
AnnaBridge 143:86740a56073b 1331 #else
AnnaBridge 143:86740a56073b 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 143:86740a56073b 1333 __BPIALL = 0;
AnnaBridge 143:86740a56073b 1334 #endif
AnnaBridge 143:86740a56073b 1335 __DSB(); //ensure completion of the invalidation
AnnaBridge 143:86740a56073b 1336 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 143:86740a56073b 1337 }
AnnaBridge 143:86740a56073b 1338
AnnaBridge 143:86740a56073b 1339
AnnaBridge 143:86740a56073b 1340 /******************************** L1 cache operations ******************************************************/
AnnaBridge 143:86740a56073b 1341
AnnaBridge 143:86740a56073b 1342 /** \brief Invalidate the whole I$
AnnaBridge 143:86740a56073b 1343
AnnaBridge 143:86740a56073b 1344 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 143:86740a56073b 1345 */
AnnaBridge 143:86740a56073b 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 143:86740a56073b 1347 #if 1
AnnaBridge 143:86740a56073b 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
AnnaBridge 143:86740a56073b 1349 #else
AnnaBridge 143:86740a56073b 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 143:86740a56073b 1351 __ICIALLU = 0;
AnnaBridge 143:86740a56073b 1352 #endif
AnnaBridge 143:86740a56073b 1353 __DSB(); //ensure completion of the invalidation
AnnaBridge 143:86740a56073b 1354 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 143:86740a56073b 1355 }
AnnaBridge 143:86740a56073b 1356
AnnaBridge 143:86740a56073b 1357 /** \brief Clean D$ by MVA
AnnaBridge 143:86740a56073b 1358
AnnaBridge 143:86740a56073b 1359 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 143:86740a56073b 1360 */
AnnaBridge 143:86740a56073b 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 1362 #if 1
AnnaBridge 143:86740a56073b 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
AnnaBridge 143:86740a56073b 1364 #else
AnnaBridge 143:86740a56073b 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 143:86740a56073b 1366 __DCCMVAC = (uint32_t)va;
AnnaBridge 143:86740a56073b 1367 #endif
AnnaBridge 143:86740a56073b 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 143:86740a56073b 1369 }
AnnaBridge 143:86740a56073b 1370
AnnaBridge 143:86740a56073b 1371 /** \brief Invalidate D$ by MVA
AnnaBridge 143:86740a56073b 1372
AnnaBridge 143:86740a56073b 1373 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 143:86740a56073b 1374 */
AnnaBridge 143:86740a56073b 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 1376 #if 1
AnnaBridge 143:86740a56073b 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
AnnaBridge 143:86740a56073b 1378 #else
AnnaBridge 143:86740a56073b 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 143:86740a56073b 1380 __DCIMVAC = (uint32_t)va;
AnnaBridge 143:86740a56073b 1381 #endif
AnnaBridge 143:86740a56073b 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 143:86740a56073b 1383 }
AnnaBridge 143:86740a56073b 1384
AnnaBridge 143:86740a56073b 1385 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 143:86740a56073b 1386
AnnaBridge 143:86740a56073b 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 143:86740a56073b 1388 */
AnnaBridge 143:86740a56073b 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 143:86740a56073b 1390 #if 1
AnnaBridge 143:86740a56073b 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
AnnaBridge 143:86740a56073b 1392 #else
AnnaBridge 143:86740a56073b 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 143:86740a56073b 1394 __DCCIMVAC = (uint32_t)va;
AnnaBridge 143:86740a56073b 1395 #endif
AnnaBridge 143:86740a56073b 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 143:86740a56073b 1397 }
AnnaBridge 143:86740a56073b 1398
AnnaBridge 143:86740a56073b 1399 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 143:86740a56073b 1400
AnnaBridge 143:86740a56073b 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 143:86740a56073b 1402 */
AnnaBridge 143:86740a56073b 1403 extern void __v7_all_cache(uint32_t op);
AnnaBridge 143:86740a56073b 1404
AnnaBridge 143:86740a56073b 1405
AnnaBridge 143:86740a56073b 1406 /** \brief Invalidate the whole D$
AnnaBridge 143:86740a56073b 1407
AnnaBridge 143:86740a56073b 1408 DCISW. Invalidate by Set/Way
AnnaBridge 143:86740a56073b 1409 */
AnnaBridge 143:86740a56073b 1410
AnnaBridge 143:86740a56073b 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 143:86740a56073b 1412 __v7_all_cache(0);
AnnaBridge 143:86740a56073b 1413 }
AnnaBridge 143:86740a56073b 1414
AnnaBridge 143:86740a56073b 1415 /** \brief Clean the whole D$
AnnaBridge 143:86740a56073b 1416
AnnaBridge 143:86740a56073b 1417 DCCSW. Clean by Set/Way
AnnaBridge 143:86740a56073b 1418 */
AnnaBridge 143:86740a56073b 1419
AnnaBridge 143:86740a56073b 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 143:86740a56073b 1421 __v7_all_cache(1);
AnnaBridge 143:86740a56073b 1422 }
AnnaBridge 143:86740a56073b 1423
AnnaBridge 143:86740a56073b 1424 /** \brief Clean and invalidate the whole D$
AnnaBridge 143:86740a56073b 1425
AnnaBridge 143:86740a56073b 1426 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 143:86740a56073b 1427 */
AnnaBridge 143:86740a56073b 1428
AnnaBridge 143:86740a56073b 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 143:86740a56073b 1430 __v7_all_cache(2);
AnnaBridge 143:86740a56073b 1431 }
AnnaBridge 143:86740a56073b 1432
AnnaBridge 143:86740a56073b 1433 #include "core_ca_mmu.h"
AnnaBridge 143:86740a56073b 1434
AnnaBridge 143:86740a56073b 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
AnnaBridge 143:86740a56073b 1436
AnnaBridge 143:86740a56073b 1437 #error TASKING Compiler support not implemented for Cortex-A
AnnaBridge 143:86740a56073b 1438
AnnaBridge 143:86740a56073b 1439 #endif
AnnaBridge 143:86740a56073b 1440
AnnaBridge 143:86740a56073b 1441 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 143:86740a56073b 1442
AnnaBridge 143:86740a56073b 1443
AnnaBridge 143:86740a56073b 1444 #endif /* __CORE_CAFUNC_H__ */