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TARGET_NUCLEO_L432KC/core_sc300.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 131:faff56e089b2
Child:: 145:64910690c574

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/************************************************************************//
Kojto	122:f9eeca106725	2	* @file core_sc300.h
Kojto	122:f9eeca106725	3	* @brief CMSIS SC300 Core Peripheral Access Layer Header File
Kojto	122:f9eeca106725	4	* @version V4.10
Kojto	122:f9eeca106725	5	* @date 18. March 2015
Kojto	122:f9eeca106725	6	*
Kojto	122:f9eeca106725	7	* @note
Kojto	122:f9eeca106725	8	*
Kojto	122:f9eeca106725	9	******************************************************************************/
Kojto	122:f9eeca106725	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto	122:f9eeca106725	11
Kojto	122:f9eeca106725	12	All rights reserved.
Kojto	122:f9eeca106725	13	Redistribution and use in source and binary forms, with or without
Kojto	122:f9eeca106725	14	modification, are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	- Redistributions of source code must retain the above copyright
Kojto	122:f9eeca106725	16	notice, this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	- Redistributions in binary form must reproduce the above copyright
Kojto	122:f9eeca106725	18	notice, this list of conditions and the following disclaimer in the
Kojto	122:f9eeca106725	19	documentation and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	- Neither the name of ARM nor the names of its contributors may be used
Kojto	122:f9eeca106725	21	to endorse or promote products derived from this software without
Kojto	122:f9eeca106725	22	specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto	122:f9eeca106725	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto	122:f9eeca106725	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto	122:f9eeca106725	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto	122:f9eeca106725	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto	122:f9eeca106725	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto	122:f9eeca106725	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto	122:f9eeca106725	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto	122:f9eeca106725	34	POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	35	---------------------------------------------------------------------------*/
Kojto	122:f9eeca106725	36
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	#if defined ( __ICCARM__ )
Kojto	122:f9eeca106725	39	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	122:f9eeca106725	40	#endif
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifndef __CORE_SC300_H_GENERIC
Kojto	122:f9eeca106725	43	#define __CORE_SC300_H_GENERIC
Kojto	122:f9eeca106725	44
Kojto	122:f9eeca106725	45	#ifdef __cplusplus
Kojto	122:f9eeca106725	46	extern "C" {
Kojto	122:f9eeca106725	47	#endif
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	122:f9eeca106725	50	CMSIS violates the following MISRA-C:2004 rules:
Kojto	122:f9eeca106725	51
Kojto	122:f9eeca106725	52	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	122:f9eeca106725	53	Function definitions in header files are used to allow 'inlining'.
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	122:f9eeca106725	56	Unions are used for effective representation of core registers.
Kojto	122:f9eeca106725	57
Kojto	122:f9eeca106725	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	122:f9eeca106725	59	Function-like macros are used to allow more efficient code.
Kojto	122:f9eeca106725	60	*/
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62
Kojto	122:f9eeca106725	63	/*******************************************************************************
Kojto	122:f9eeca106725	64	* CMSIS definitions
Kojto	122:f9eeca106725	65	******************************************************************************/
Kojto	122:f9eeca106725	66	/** \ingroup SC3000
Kojto	122:f9eeca106725	67	@{
Kojto	122:f9eeca106725	68	*/
Kojto	122:f9eeca106725	69
Kojto	122:f9eeca106725	70	/* CMSIS SC300 definitions */
Kojto	122:f9eeca106725	71	#define __SC300_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	122:f9eeca106725	72	#define __SC300_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Kojto	122:f9eeca106725	73	#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) \| \
Kojto	122:f9eeca106725	74	__SC300_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	#define __CORTEX_SC (300) /!< Cortex secure core /
Kojto	122:f9eeca106725	77
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	#if defined ( __CC_ARM )
Kojto	122:f9eeca106725	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Kojto	122:f9eeca106725	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Kojto	122:f9eeca106725	82	#define __STATIC_INLINE static __inline
Kojto	122:f9eeca106725	83
Kojto	122:f9eeca106725	84	#elif defined ( __GNUC__ )
Kojto	122:f9eeca106725	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	122:f9eeca106725	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	122:f9eeca106725	87	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	88
Kojto	122:f9eeca106725	89	#elif defined ( __ICCARM__ )
Kojto	122:f9eeca106725	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Kojto	122:f9eeca106725	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Kojto	122:f9eeca106725	92	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	93
Kojto	122:f9eeca106725	94	#elif defined ( __TMS470__ )
Kojto	122:f9eeca106725	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Kojto	122:f9eeca106725	96	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	97
Kojto	122:f9eeca106725	98	#elif defined ( __TASKING__ )
Kojto	122:f9eeca106725	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Kojto	122:f9eeca106725	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Kojto	122:f9eeca106725	101	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	102
Kojto	122:f9eeca106725	103	#elif defined ( __CSMC__ )
Kojto	122:f9eeca106725	104	#define __packed
Kojto	122:f9eeca106725	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	122:f9eeca106725	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	122:f9eeca106725	107	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	108
Kojto	122:f9eeca106725	109	#endif
Kojto	122:f9eeca106725	110
Kojto	122:f9eeca106725	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	122:f9eeca106725	112	This core does not support an FPU at all
Kojto	122:f9eeca106725	113	*/
Kojto	122:f9eeca106725	114	#define __FPU_USED 0
Kojto	122:f9eeca106725	115
Kojto	122:f9eeca106725	116	#if defined ( __CC_ARM )
Kojto	122:f9eeca106725	117	#if defined __TARGET_FPU_VFP
Kojto	122:f9eeca106725	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	119	#endif
Kojto	122:f9eeca106725	120
Kojto	122:f9eeca106725	121	#elif defined ( __GNUC__ )
Kojto	122:f9eeca106725	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	122:f9eeca106725	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	124	#endif
Kojto	122:f9eeca106725	125
Kojto	122:f9eeca106725	126	#elif defined ( __ICCARM__ )
Kojto	122:f9eeca106725	127	#if defined __ARMVFP__
Kojto	122:f9eeca106725	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	129	#endif
Kojto	122:f9eeca106725	130
Kojto	122:f9eeca106725	131	#elif defined ( __TMS470__ )
Kojto	122:f9eeca106725	132	#if defined __TI__VFP_SUPPORT____
Kojto	122:f9eeca106725	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	134	#endif
Kojto	122:f9eeca106725	135
Kojto	122:f9eeca106725	136	#elif defined ( __TASKING__ )
Kojto	122:f9eeca106725	137	#if defined __FPU_VFP__
Kojto	122:f9eeca106725	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	139	#endif
Kojto	122:f9eeca106725	140
Kojto	122:f9eeca106725	141	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	122:f9eeca106725	142	#if ( __CSMC__ & 0x400) // FPU present for parser
Kojto	122:f9eeca106725	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	144	#endif
Kojto	122:f9eeca106725	145	#endif
Kojto	122:f9eeca106725	146
Kojto	122:f9eeca106725	147	#include <stdint.h> /* standard types definitions */
Kojto	122:f9eeca106725	148	#include <core_cmInstr.h> /* Core Instruction Access */
Kojto	122:f9eeca106725	149	#include <core_cmFunc.h> /* Core Function Access */
Kojto	122:f9eeca106725	150
Kojto	122:f9eeca106725	151	#ifdef __cplusplus
Kojto	122:f9eeca106725	152	}
Kojto	122:f9eeca106725	153	#endif
Kojto	122:f9eeca106725	154
Kojto	122:f9eeca106725	155	#endif /* __CORE_SC300_H_GENERIC */
Kojto	122:f9eeca106725	156
Kojto	122:f9eeca106725	157	#ifndef __CMSIS_GENERIC
Kojto	122:f9eeca106725	158
Kojto	122:f9eeca106725	159	#ifndef __CORE_SC300_H_DEPENDANT
Kojto	122:f9eeca106725	160	#define __CORE_SC300_H_DEPENDANT
Kojto	122:f9eeca106725	161
Kojto	122:f9eeca106725	162	#ifdef __cplusplus
Kojto	122:f9eeca106725	163	extern "C" {
Kojto	122:f9eeca106725	164	#endif
Kojto	122:f9eeca106725	165
Kojto	122:f9eeca106725	166	/* check device defines and use defaults */
Kojto	122:f9eeca106725	167	#if defined __CHECK_DEVICE_DEFINES
Kojto	122:f9eeca106725	168	#ifndef __SC300_REV
Kojto	122:f9eeca106725	169	#define __SC300_REV 0x0000
Kojto	122:f9eeca106725	170	#warning "__SC300_REV not defined in device header file; using default!"
Kojto	122:f9eeca106725	171	#endif
Kojto	122:f9eeca106725	172
Kojto	122:f9eeca106725	173	#ifndef __MPU_PRESENT
Kojto	122:f9eeca106725	174	#define __MPU_PRESENT 0
Kojto	122:f9eeca106725	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	176	#endif
Kojto	122:f9eeca106725	177
Kojto	122:f9eeca106725	178	#ifndef __NVIC_PRIO_BITS
Kojto	122:f9eeca106725	179	#define __NVIC_PRIO_BITS 4
Kojto	122:f9eeca106725	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	122:f9eeca106725	181	#endif
Kojto	122:f9eeca106725	182
Kojto	122:f9eeca106725	183	#ifndef __Vendor_SysTickConfig
Kojto	122:f9eeca106725	184	#define __Vendor_SysTickConfig 0
Kojto	122:f9eeca106725	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	122:f9eeca106725	186	#endif
Kojto	122:f9eeca106725	187	#endif
Kojto	122:f9eeca106725	188
Kojto	122:f9eeca106725	189	/* IO definitions (access restrictions to peripheral registers) */
Kojto	122:f9eeca106725	190	/**
Kojto	122:f9eeca106725	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	122:f9eeca106725	192
Kojto	122:f9eeca106725	193	<strong>IO Type Qualifiers</strong> are used
Kojto	122:f9eeca106725	194	\li to specify the access to peripheral variables.
Kojto	122:f9eeca106725	195	\li for automatic generation of peripheral register debug information.
Kojto	122:f9eeca106725	196	*/
Kojto	122:f9eeca106725	197	#ifdef __cplusplus
Kojto	122:f9eeca106725	198	#define __I volatile /!< Defines 'read only' permissions /
Kojto	122:f9eeca106725	199	#else
Kojto	122:f9eeca106725	200	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	122:f9eeca106725	201	#endif
Kojto	122:f9eeca106725	202	#define __O volatile /!< Defines 'write only' permissions /
Kojto	122:f9eeca106725	203	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	122:f9eeca106725	204
Kojto	122:f9eeca106725	205	/@} end of group SC300 /
Kojto	122:f9eeca106725	206
Kojto	122:f9eeca106725	207
Kojto	122:f9eeca106725	208
Kojto	122:f9eeca106725	209	/*******************************************************************************
Kojto	122:f9eeca106725	210	* Register Abstraction
Kojto	122:f9eeca106725	211	Core Register contain:
Kojto	122:f9eeca106725	212	- Core Register
Kojto	122:f9eeca106725	213	- Core NVIC Register
Kojto	122:f9eeca106725	214	- Core SCB Register
Kojto	122:f9eeca106725	215	- Core SysTick Register
Kojto	122:f9eeca106725	216	- Core Debug Register
Kojto	122:f9eeca106725	217	- Core MPU Register
Kojto	122:f9eeca106725	218	******************************************************************************/
Kojto	122:f9eeca106725	219	/** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto	122:f9eeca106725	220	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	122:f9eeca106725	221	*/
Kojto	122:f9eeca106725	222
Kojto	122:f9eeca106725	223	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	224	\defgroup CMSIS_CORE Status and Control Registers
Kojto	122:f9eeca106725	225	\brief Core Register type definitions.
Kojto	122:f9eeca106725	226	@{
Kojto	122:f9eeca106725	227	*/
Kojto	122:f9eeca106725	228
Kojto	122:f9eeca106725	229	/** \brief Union type to access the Application Program Status Register (APSR).
Kojto	122:f9eeca106725	230	*/
Kojto	122:f9eeca106725	231	typedef union
Kojto	122:f9eeca106725	232	{
Kojto	122:f9eeca106725	233	struct
Kojto	122:f9eeca106725	234	{
Kojto	122:f9eeca106725	235	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Kojto	122:f9eeca106725	236	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	122:f9eeca106725	237	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	122:f9eeca106725	238	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	122:f9eeca106725	239	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	122:f9eeca106725	240	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	122:f9eeca106725	241	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	242	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	243	} APSR_Type;
Kojto	122:f9eeca106725	244
Kojto	122:f9eeca106725	245	/* APSR Register Definitions */
Kojto	122:f9eeca106725	246	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	122:f9eeca106725	247	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	122:f9eeca106725	248
Kojto	122:f9eeca106725	249	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	122:f9eeca106725	250	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	122:f9eeca106725	251
Kojto	122:f9eeca106725	252	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	122:f9eeca106725	253	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	122:f9eeca106725	254
Kojto	122:f9eeca106725	255	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	122:f9eeca106725	256	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	122:f9eeca106725	257
Kojto	122:f9eeca106725	258	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	122:f9eeca106725	259	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	122:f9eeca106725	260
Kojto	122:f9eeca106725	261
Kojto	122:f9eeca106725	262	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	122:f9eeca106725	263	*/
Kojto	122:f9eeca106725	264	typedef union
Kojto	122:f9eeca106725	265	{
Kojto	122:f9eeca106725	266	struct
Kojto	122:f9eeca106725	267	{
Kojto	122:f9eeca106725	268	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	122:f9eeca106725	269	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	122:f9eeca106725	270	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	271	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	272	} IPSR_Type;
Kojto	122:f9eeca106725	273
Kojto	122:f9eeca106725	274	/* IPSR Register Definitions */
Kojto	122:f9eeca106725	275	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	122:f9eeca106725	276	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	122:f9eeca106725	277
Kojto	122:f9eeca106725	278
Kojto	122:f9eeca106725	279	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	122:f9eeca106725	280	*/
Kojto	122:f9eeca106725	281	typedef union
Kojto	122:f9eeca106725	282	{
Kojto	122:f9eeca106725	283	struct
Kojto	122:f9eeca106725	284	{
Kojto	122:f9eeca106725	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	122:f9eeca106725	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Kojto	122:f9eeca106725	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	122:f9eeca106725	288	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	122:f9eeca106725	289	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	122:f9eeca106725	290	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	122:f9eeca106725	291	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	122:f9eeca106725	292	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	122:f9eeca106725	293	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	122:f9eeca106725	294	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	295	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	296	} xPSR_Type;
Kojto	122:f9eeca106725	297
Kojto	122:f9eeca106725	298	/* xPSR Register Definitions */
Kojto	122:f9eeca106725	299	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	122:f9eeca106725	300	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	122:f9eeca106725	301
Kojto	122:f9eeca106725	302	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	122:f9eeca106725	303	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	122:f9eeca106725	304
Kojto	122:f9eeca106725	305	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	122:f9eeca106725	306	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	122:f9eeca106725	307
Kojto	122:f9eeca106725	308	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	122:f9eeca106725	309	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	122:f9eeca106725	310
Kojto	122:f9eeca106725	311	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	122:f9eeca106725	312	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	122:f9eeca106725	313
Kojto	122:f9eeca106725	314	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	122:f9eeca106725	315	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	122:f9eeca106725	316
Kojto	122:f9eeca106725	317	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	122:f9eeca106725	318	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	122:f9eeca106725	319
Kojto	122:f9eeca106725	320	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	122:f9eeca106725	321	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	122:f9eeca106725	322
Kojto	122:f9eeca106725	323
Kojto	122:f9eeca106725	324	/** \brief Union type to access the Control Registers (CONTROL).
Kojto	122:f9eeca106725	325	*/
Kojto	122:f9eeca106725	326	typedef union
Kojto	122:f9eeca106725	327	{
Kojto	122:f9eeca106725	328	struct
Kojto	122:f9eeca106725	329	{
Kojto	122:f9eeca106725	330	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	122:f9eeca106725	331	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	122:f9eeca106725	332	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
Kojto	122:f9eeca106725	333	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	334	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	335	} CONTROL_Type;
Kojto	122:f9eeca106725	336
Kojto	122:f9eeca106725	337	/* CONTROL Register Definitions */
Kojto	122:f9eeca106725	338	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	122:f9eeca106725	339	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	122:f9eeca106725	340
Kojto	122:f9eeca106725	341	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	122:f9eeca106725	342	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	122:f9eeca106725	343
Kojto	122:f9eeca106725	344	/@} end of group CMSIS_CORE /
Kojto	122:f9eeca106725	345
Kojto	122:f9eeca106725	346
Kojto	122:f9eeca106725	347	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	348	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	122:f9eeca106725	349	\brief Type definitions for the NVIC Registers
Kojto	122:f9eeca106725	350	@{
Kojto	122:f9eeca106725	351	*/
Kojto	122:f9eeca106725	352
Kojto	122:f9eeca106725	353	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	122:f9eeca106725	354	*/
Kojto	122:f9eeca106725	355	typedef struct
Kojto	122:f9eeca106725	356	{
Kojto	122:f9eeca106725	357	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	122:f9eeca106725	358	uint32_t RESERVED0[24];
Kojto	122:f9eeca106725	359	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	122:f9eeca106725	360	uint32_t RSERVED1[24];
Kojto	122:f9eeca106725	361	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	122:f9eeca106725	362	uint32_t RESERVED2[24];
Kojto	122:f9eeca106725	363	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	122:f9eeca106725	364	uint32_t RESERVED3[24];
Kojto	122:f9eeca106725	365	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	122:f9eeca106725	366	uint32_t RESERVED4[56];
Kojto	122:f9eeca106725	367	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	122:f9eeca106725	368	uint32_t RESERVED5[644];
Kojto	122:f9eeca106725	369	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	122:f9eeca106725	370	} NVIC_Type;
Kojto	122:f9eeca106725	371
Kojto	122:f9eeca106725	372	/* Software Triggered Interrupt Register Definitions */
Kojto	122:f9eeca106725	373	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	122:f9eeca106725	374	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Kojto	122:f9eeca106725	375
Kojto	122:f9eeca106725	376	/@} end of group CMSIS_NVIC /
Kojto	122:f9eeca106725	377
Kojto	122:f9eeca106725	378
Kojto	122:f9eeca106725	379	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	380	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	122:f9eeca106725	381	\brief Type definitions for the System Control Block Registers
Kojto	122:f9eeca106725	382	@{
Kojto	122:f9eeca106725	383	*/
Kojto	122:f9eeca106725	384
Kojto	122:f9eeca106725	385	/** \brief Structure type to access the System Control Block (SCB).
Kojto	122:f9eeca106725	386	*/
Kojto	122:f9eeca106725	387	typedef struct
Kojto	122:f9eeca106725	388	{
Kojto	122:f9eeca106725	389	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	122:f9eeca106725	390	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	122:f9eeca106725	391	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	122:f9eeca106725	392	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	122:f9eeca106725	393	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	122:f9eeca106725	394	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	122:f9eeca106725	395	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	122:f9eeca106725	396	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	122:f9eeca106725	397	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	122:f9eeca106725	398	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	122:f9eeca106725	399	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	122:f9eeca106725	400	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	122:f9eeca106725	401	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	122:f9eeca106725	402	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	122:f9eeca106725	403	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	122:f9eeca106725	404	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	122:f9eeca106725	405	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	122:f9eeca106725	406	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	122:f9eeca106725	407	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	122:f9eeca106725	408	uint32_t RESERVED0[5];
Kojto	122:f9eeca106725	409	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	122:f9eeca106725	410	uint32_t RESERVED1[129];
Kojto	122:f9eeca106725	411	__IO uint32_t SFCR; /!< Offset: 0x290 (R/W) Security Features Control Register /
Kojto	122:f9eeca106725	412	} SCB_Type;
Kojto	122:f9eeca106725	413
Kojto	122:f9eeca106725	414	/* SCB CPUID Register Definitions */
Kojto	122:f9eeca106725	415	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Kojto	122:f9eeca106725	416	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	122:f9eeca106725	417
Kojto	122:f9eeca106725	418	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Kojto	122:f9eeca106725	419	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	122:f9eeca106725	420
Kojto	122:f9eeca106725	421	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Kojto	122:f9eeca106725	422	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	122:f9eeca106725	423
Kojto	122:f9eeca106725	424	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Kojto	122:f9eeca106725	425	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	122:f9eeca106725	426
Kojto	122:f9eeca106725	427	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	122:f9eeca106725	428	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Kojto	122:f9eeca106725	429
Kojto	122:f9eeca106725	430	/* SCB Interrupt Control State Register Definitions */
Kojto	122:f9eeca106725	431	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Kojto	122:f9eeca106725	432	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Kojto	122:f9eeca106725	433
Kojto	122:f9eeca106725	434	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Kojto	122:f9eeca106725	435	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	122:f9eeca106725	436
Kojto	122:f9eeca106725	437	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Kojto	122:f9eeca106725	438	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	122:f9eeca106725	439
Kojto	122:f9eeca106725	440	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Kojto	122:f9eeca106725	441	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	122:f9eeca106725	442
Kojto	122:f9eeca106725	443	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Kojto	122:f9eeca106725	444	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	122:f9eeca106725	445
Kojto	122:f9eeca106725	446	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Kojto	122:f9eeca106725	447	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	122:f9eeca106725	448
Kojto	122:f9eeca106725	449	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Kojto	122:f9eeca106725	450	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	122:f9eeca106725	451
Kojto	122:f9eeca106725	452	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Kojto	122:f9eeca106725	453	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	122:f9eeca106725	454
Kojto	122:f9eeca106725	455	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Kojto	122:f9eeca106725	456	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	122:f9eeca106725	457
Kojto	122:f9eeca106725	458	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	122:f9eeca106725	459	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	122:f9eeca106725	460
Kojto	122:f9eeca106725	461	/* SCB Vector Table Offset Register Definitions */
Kojto	122:f9eeca106725	462	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
Kojto	122:f9eeca106725	463	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
Kojto	122:f9eeca106725	464
Kojto	122:f9eeca106725	465	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	122:f9eeca106725	466	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	122:f9eeca106725	467
Kojto	122:f9eeca106725	468	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	122:f9eeca106725	469	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Kojto	122:f9eeca106725	470	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	122:f9eeca106725	471
Kojto	122:f9eeca106725	472	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	122:f9eeca106725	473	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	122:f9eeca106725	474
Kojto	122:f9eeca106725	475	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Kojto	122:f9eeca106725	476	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	122:f9eeca106725	477
Kojto	122:f9eeca106725	478	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Kojto	122:f9eeca106725	479	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	122:f9eeca106725	480
Kojto	122:f9eeca106725	481	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	122:f9eeca106725	482	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	122:f9eeca106725	483
Kojto	122:f9eeca106725	484	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	122:f9eeca106725	485	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	122:f9eeca106725	486
Kojto	122:f9eeca106725	487	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	122:f9eeca106725	488	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Kojto	122:f9eeca106725	489
Kojto	122:f9eeca106725	490	/* SCB System Control Register Definitions */
Kojto	122:f9eeca106725	491	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Kojto	122:f9eeca106725	492	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	122:f9eeca106725	493
Kojto	122:f9eeca106725	494	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Kojto	122:f9eeca106725	495	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	122:f9eeca106725	496
Kojto	122:f9eeca106725	497	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Kojto	122:f9eeca106725	498	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	122:f9eeca106725	499
Kojto	122:f9eeca106725	500	/* SCB Configuration Control Register Definitions */
Kojto	122:f9eeca106725	501	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Kojto	122:f9eeca106725	502	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Kojto	122:f9eeca106725	503
Kojto	122:f9eeca106725	504	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Kojto	122:f9eeca106725	505	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	122:f9eeca106725	506
Kojto	122:f9eeca106725	507	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Kojto	122:f9eeca106725	508	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	122:f9eeca106725	509
Kojto	122:f9eeca106725	510	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Kojto	122:f9eeca106725	511	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	122:f9eeca106725	512
Kojto	122:f9eeca106725	513	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Kojto	122:f9eeca106725	514	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	122:f9eeca106725	515
Kojto	122:f9eeca106725	516	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	122:f9eeca106725	517	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Kojto	122:f9eeca106725	518
Kojto	122:f9eeca106725	519	/* SCB System Handler Control and State Register Definitions */
Kojto	122:f9eeca106725	520	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Kojto	122:f9eeca106725	521	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	122:f9eeca106725	522
Kojto	122:f9eeca106725	523	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	122:f9eeca106725	524	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	122:f9eeca106725	525
Kojto	122:f9eeca106725	526	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	122:f9eeca106725	527	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	122:f9eeca106725	528
Kojto	122:f9eeca106725	529	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	122:f9eeca106725	530	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	122:f9eeca106725	531
Kojto	122:f9eeca106725	532	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	122:f9eeca106725	533	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	122:f9eeca106725	534
Kojto	122:f9eeca106725	535	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	122:f9eeca106725	536	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	122:f9eeca106725	537
Kojto	122:f9eeca106725	538	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	122:f9eeca106725	539	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	122:f9eeca106725	540
Kojto	122:f9eeca106725	541	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Kojto	122:f9eeca106725	542	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	122:f9eeca106725	543
Kojto	122:f9eeca106725	544	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Kojto	122:f9eeca106725	545	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	122:f9eeca106725	546
Kojto	122:f9eeca106725	547	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Kojto	122:f9eeca106725	548	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	122:f9eeca106725	549
Kojto	122:f9eeca106725	550	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Kojto	122:f9eeca106725	551	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	122:f9eeca106725	552
Kojto	122:f9eeca106725	553	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Kojto	122:f9eeca106725	554	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	122:f9eeca106725	555
Kojto	122:f9eeca106725	556	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	122:f9eeca106725	557	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	122:f9eeca106725	558
Kojto	122:f9eeca106725	559	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	122:f9eeca106725	560	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	122:f9eeca106725	561
Kojto	122:f9eeca106725	562	/* SCB Configurable Fault Status Registers Definitions */
Kojto	122:f9eeca106725	563	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	122:f9eeca106725	564	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	122:f9eeca106725	565
Kojto	122:f9eeca106725	566	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	122:f9eeca106725	567	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	122:f9eeca106725	568
Kojto	122:f9eeca106725	569	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	122:f9eeca106725	570	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	122:f9eeca106725	571
Kojto	122:f9eeca106725	572	/* SCB Hard Fault Status Registers Definitions */
Kojto	122:f9eeca106725	573	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Kojto	122:f9eeca106725	574	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	122:f9eeca106725	575
Kojto	122:f9eeca106725	576	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Kojto	122:f9eeca106725	577	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	122:f9eeca106725	578
Kojto	122:f9eeca106725	579	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Kojto	122:f9eeca106725	580	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	122:f9eeca106725	581
Kojto	122:f9eeca106725	582	/* SCB Debug Fault Status Register Definitions */
Kojto	122:f9eeca106725	583	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Kojto	122:f9eeca106725	584	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	122:f9eeca106725	585
Kojto	122:f9eeca106725	586	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Kojto	122:f9eeca106725	587	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	122:f9eeca106725	588
Kojto	122:f9eeca106725	589	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Kojto	122:f9eeca106725	590	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	122:f9eeca106725	591
Kojto	122:f9eeca106725	592	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Kojto	122:f9eeca106725	593	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	122:f9eeca106725	594
Kojto	122:f9eeca106725	595	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	122:f9eeca106725	596	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Kojto	122:f9eeca106725	597
Kojto	122:f9eeca106725	598	/@} end of group CMSIS_SCB /
Kojto	122:f9eeca106725	599
Kojto	122:f9eeca106725	600
Kojto	122:f9eeca106725	601	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	602	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	122:f9eeca106725	603	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	122:f9eeca106725	604	@{
Kojto	122:f9eeca106725	605	*/
Kojto	122:f9eeca106725	606
Kojto	122:f9eeca106725	607	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	122:f9eeca106725	608	*/
Kojto	122:f9eeca106725	609	typedef struct
Kojto	122:f9eeca106725	610	{
Kojto	122:f9eeca106725	611	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	612	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	122:f9eeca106725	613	uint32_t RESERVED1[1];
Kojto	122:f9eeca106725	614	} SCnSCB_Type;
Kojto	122:f9eeca106725	615
Kojto	122:f9eeca106725	616	/* Interrupt Controller Type Register Definitions */
Kojto	122:f9eeca106725	617	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	122:f9eeca106725	618	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Kojto	122:f9eeca106725	619
Kojto	122:f9eeca106725	620	/@} end of group CMSIS_SCnotSCB /
Kojto	122:f9eeca106725	621
Kojto	122:f9eeca106725	622
Kojto	122:f9eeca106725	623	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	624	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	122:f9eeca106725	625	\brief Type definitions for the System Timer Registers.
Kojto	122:f9eeca106725	626	@{
Kojto	122:f9eeca106725	627	*/
Kojto	122:f9eeca106725	628
Kojto	122:f9eeca106725	629	/** \brief Structure type to access the System Timer (SysTick).
Kojto	122:f9eeca106725	630	*/
Kojto	122:f9eeca106725	631	typedef struct
Kojto	122:f9eeca106725	632	{
Kojto	122:f9eeca106725	633	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	122:f9eeca106725	634	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	122:f9eeca106725	635	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	122:f9eeca106725	636	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	122:f9eeca106725	637	} SysTick_Type;
Kojto	122:f9eeca106725	638
Kojto	122:f9eeca106725	639	/* SysTick Control / Status Register Definitions */
Kojto	122:f9eeca106725	640	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Kojto	122:f9eeca106725	641	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	122:f9eeca106725	642
Kojto	122:f9eeca106725	643	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Kojto	122:f9eeca106725	644	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	122:f9eeca106725	645
Kojto	122:f9eeca106725	646	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Kojto	122:f9eeca106725	647	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	122:f9eeca106725	648
Kojto	122:f9eeca106725	649	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	122:f9eeca106725	650	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Kojto	122:f9eeca106725	651
Kojto	122:f9eeca106725	652	/* SysTick Reload Register Definitions */
Kojto	122:f9eeca106725	653	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	122:f9eeca106725	654	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Kojto	122:f9eeca106725	655
Kojto	122:f9eeca106725	656	/* SysTick Current Register Definitions */
Kojto	122:f9eeca106725	657	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	122:f9eeca106725	658	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Kojto	122:f9eeca106725	659
Kojto	122:f9eeca106725	660	/* SysTick Calibration Register Definitions */
Kojto	122:f9eeca106725	661	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Kojto	122:f9eeca106725	662	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	122:f9eeca106725	663
Kojto	122:f9eeca106725	664	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Kojto	122:f9eeca106725	665	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	122:f9eeca106725	666
Kojto	122:f9eeca106725	667	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	122:f9eeca106725	668	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Kojto	122:f9eeca106725	669
Kojto	122:f9eeca106725	670	/@} end of group CMSIS_SysTick /
Kojto	122:f9eeca106725	671
Kojto	122:f9eeca106725	672
Kojto	122:f9eeca106725	673	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	674	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	122:f9eeca106725	675	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	122:f9eeca106725	676	@{
Kojto	122:f9eeca106725	677	*/
Kojto	122:f9eeca106725	678
Kojto	122:f9eeca106725	679	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	122:f9eeca106725	680	*/
Kojto	122:f9eeca106725	681	typedef struct
Kojto	122:f9eeca106725	682	{
Kojto	122:f9eeca106725	683	__O union
Kojto	122:f9eeca106725	684	{
Kojto	122:f9eeca106725	685	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	122:f9eeca106725	686	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	122:f9eeca106725	687	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	122:f9eeca106725	688	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	122:f9eeca106725	689	uint32_t RESERVED0[864];
Kojto	122:f9eeca106725	690	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	122:f9eeca106725	691	uint32_t RESERVED1[15];
Kojto	122:f9eeca106725	692	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	122:f9eeca106725	693	uint32_t RESERVED2[15];
Kojto	122:f9eeca106725	694	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	122:f9eeca106725	695	uint32_t RESERVED3[29];
Kojto	122:f9eeca106725	696	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	122:f9eeca106725	697	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	122:f9eeca106725	698	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	122:f9eeca106725	699	uint32_t RESERVED4[43];
Kojto	122:f9eeca106725	700	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	122:f9eeca106725	701	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	122:f9eeca106725	702	uint32_t RESERVED5[6];
Kojto	122:f9eeca106725	703	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	122:f9eeca106725	704	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	122:f9eeca106725	705	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	122:f9eeca106725	706	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	122:f9eeca106725	707	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	122:f9eeca106725	708	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	122:f9eeca106725	709	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	122:f9eeca106725	710	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	122:f9eeca106725	711	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	122:f9eeca106725	712	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	122:f9eeca106725	713	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	122:f9eeca106725	714	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	122:f9eeca106725	715	} ITM_Type;
Kojto	122:f9eeca106725	716
Kojto	122:f9eeca106725	717	/* ITM Trace Privilege Register Definitions */
Kojto	122:f9eeca106725	718	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	122:f9eeca106725	719	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Kojto	122:f9eeca106725	720
Kojto	122:f9eeca106725	721	/* ITM Trace Control Register Definitions */
Kojto	122:f9eeca106725	722	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Kojto	122:f9eeca106725	723	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	122:f9eeca106725	724
Kojto	122:f9eeca106725	725	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Kojto	122:f9eeca106725	726	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	122:f9eeca106725	727
Kojto	122:f9eeca106725	728	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Kojto	122:f9eeca106725	729	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	122:f9eeca106725	730
Kojto	122:f9eeca106725	731	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Kojto	122:f9eeca106725	732	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Kojto	122:f9eeca106725	733
Kojto	122:f9eeca106725	734	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Kojto	122:f9eeca106725	735	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	122:f9eeca106725	736
Kojto	122:f9eeca106725	737	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Kojto	122:f9eeca106725	738	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	122:f9eeca106725	739
Kojto	122:f9eeca106725	740	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Kojto	122:f9eeca106725	741	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	122:f9eeca106725	742
Kojto	122:f9eeca106725	743	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Kojto	122:f9eeca106725	744	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	122:f9eeca106725	745
Kojto	122:f9eeca106725	746	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	122:f9eeca106725	747	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Kojto	122:f9eeca106725	748
Kojto	122:f9eeca106725	749	/* ITM Integration Write Register Definitions */
Kojto	122:f9eeca106725	750	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	122:f9eeca106725	751	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Kojto	122:f9eeca106725	752
Kojto	122:f9eeca106725	753	/* ITM Integration Read Register Definitions */
Kojto	122:f9eeca106725	754	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	122:f9eeca106725	755	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Kojto	122:f9eeca106725	756
Kojto	122:f9eeca106725	757	/* ITM Integration Mode Control Register Definitions */
Kojto	122:f9eeca106725	758	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	122:f9eeca106725	759	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Kojto	122:f9eeca106725	760
Kojto	122:f9eeca106725	761	/* ITM Lock Status Register Definitions */
Kojto	122:f9eeca106725	762	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Kojto	122:f9eeca106725	763	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	122:f9eeca106725	764
Kojto	122:f9eeca106725	765	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Kojto	122:f9eeca106725	766	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	122:f9eeca106725	767
Kojto	122:f9eeca106725	768	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	122:f9eeca106725	769	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Kojto	122:f9eeca106725	770
Kojto	122:f9eeca106725	771	/@}/ /* end of group CMSIS_ITM */
Kojto	122:f9eeca106725	772
Kojto	122:f9eeca106725	773
Kojto	122:f9eeca106725	774	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	775	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	122:f9eeca106725	776	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	122:f9eeca106725	777	@{
Kojto	122:f9eeca106725	778	*/
Kojto	122:f9eeca106725	779
Kojto	122:f9eeca106725	780	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	122:f9eeca106725	781	*/
Kojto	122:f9eeca106725	782	typedef struct
Kojto	122:f9eeca106725	783	{
Kojto	122:f9eeca106725	784	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	122:f9eeca106725	785	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	122:f9eeca106725	786	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	122:f9eeca106725	787	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	122:f9eeca106725	788	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	122:f9eeca106725	789	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	122:f9eeca106725	790	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	122:f9eeca106725	791	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	122:f9eeca106725	792	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	122:f9eeca106725	793	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Kojto	122:f9eeca106725	794	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	122:f9eeca106725	795	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	796	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	122:f9eeca106725	797	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Kojto	122:f9eeca106725	798	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	122:f9eeca106725	799	uint32_t RESERVED1[1];
Kojto	122:f9eeca106725	800	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	122:f9eeca106725	801	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Kojto	122:f9eeca106725	802	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	122:f9eeca106725	803	uint32_t RESERVED2[1];
Kojto	122:f9eeca106725	804	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	122:f9eeca106725	805	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Kojto	122:f9eeca106725	806	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	122:f9eeca106725	807	} DWT_Type;
Kojto	122:f9eeca106725	808
Kojto	122:f9eeca106725	809	/* DWT Control Register Definitions */
Kojto	122:f9eeca106725	810	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Kojto	122:f9eeca106725	811	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	122:f9eeca106725	812
Kojto	122:f9eeca106725	813	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Kojto	122:f9eeca106725	814	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	122:f9eeca106725	815
Kojto	122:f9eeca106725	816	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Kojto	122:f9eeca106725	817	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	122:f9eeca106725	818
Kojto	122:f9eeca106725	819	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Kojto	122:f9eeca106725	820	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	122:f9eeca106725	821
Kojto	122:f9eeca106725	822	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Kojto	122:f9eeca106725	823	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	122:f9eeca106725	824
Kojto	122:f9eeca106725	825	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Kojto	122:f9eeca106725	826	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	122:f9eeca106725	827
Kojto	122:f9eeca106725	828	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Kojto	122:f9eeca106725	829	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	122:f9eeca106725	830
Kojto	122:f9eeca106725	831	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Kojto	122:f9eeca106725	832	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	122:f9eeca106725	833
Kojto	122:f9eeca106725	834	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	122:f9eeca106725	835	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	122:f9eeca106725	836
Kojto	122:f9eeca106725	837	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Kojto	122:f9eeca106725	838	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	122:f9eeca106725	839
Kojto	122:f9eeca106725	840	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Kojto	122:f9eeca106725	841	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	122:f9eeca106725	842
Kojto	122:f9eeca106725	843	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Kojto	122:f9eeca106725	844	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	122:f9eeca106725	845
Kojto	122:f9eeca106725	846	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Kojto	122:f9eeca106725	847	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	122:f9eeca106725	848
Kojto	122:f9eeca106725	849	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Kojto	122:f9eeca106725	850	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	122:f9eeca106725	851
Kojto	122:f9eeca106725	852	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Kojto	122:f9eeca106725	853	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	122:f9eeca106725	854
Kojto	122:f9eeca106725	855	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Kojto	122:f9eeca106725	856	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	122:f9eeca106725	857
Kojto	122:f9eeca106725	858	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Kojto	122:f9eeca106725	859	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	122:f9eeca106725	860
Kojto	122:f9eeca106725	861	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	122:f9eeca106725	862	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	122:f9eeca106725	863
Kojto	122:f9eeca106725	864	/* DWT CPI Count Register Definitions */
Kojto	122:f9eeca106725	865	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	122:f9eeca106725	866	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Kojto	122:f9eeca106725	867
Kojto	122:f9eeca106725	868	/* DWT Exception Overhead Count Register Definitions */
Kojto	122:f9eeca106725	869	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	122:f9eeca106725	870	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	122:f9eeca106725	871
Kojto	122:f9eeca106725	872	/* DWT Sleep Count Register Definitions */
Kojto	122:f9eeca106725	873	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	122:f9eeca106725	874	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	122:f9eeca106725	875
Kojto	122:f9eeca106725	876	/* DWT LSU Count Register Definitions */
Kojto	122:f9eeca106725	877	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	122:f9eeca106725	878	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	122:f9eeca106725	879
Kojto	122:f9eeca106725	880	/* DWT Folded-instruction Count Register Definitions */
Kojto	122:f9eeca106725	881	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	122:f9eeca106725	882	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	122:f9eeca106725	883
Kojto	122:f9eeca106725	884	/* DWT Comparator Mask Register Definitions */
Kojto	122:f9eeca106725	885	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	122:f9eeca106725	886	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Kojto	122:f9eeca106725	887
Kojto	122:f9eeca106725	888	/* DWT Comparator Function Register Definitions */
Kojto	122:f9eeca106725	889	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Kojto	122:f9eeca106725	890	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	122:f9eeca106725	891
Kojto	122:f9eeca106725	892	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Kojto	122:f9eeca106725	893	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Kojto	122:f9eeca106725	894
Kojto	122:f9eeca106725	895	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Kojto	122:f9eeca106725	896	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Kojto	122:f9eeca106725	897
Kojto	122:f9eeca106725	898	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	122:f9eeca106725	899	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	122:f9eeca106725	900
Kojto	122:f9eeca106725	901	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Kojto	122:f9eeca106725	902	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Kojto	122:f9eeca106725	903
Kojto	122:f9eeca106725	904	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Kojto	122:f9eeca106725	905	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Kojto	122:f9eeca106725	906
Kojto	122:f9eeca106725	907	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Kojto	122:f9eeca106725	908	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Kojto	122:f9eeca106725	909
Kojto	122:f9eeca106725	910	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Kojto	122:f9eeca106725	911	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Kojto	122:f9eeca106725	912
Kojto	122:f9eeca106725	913	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	122:f9eeca106725	914	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Kojto	122:f9eeca106725	915
Kojto	122:f9eeca106725	916	/@}/ /* end of group CMSIS_DWT */
Kojto	122:f9eeca106725	917
Kojto	122:f9eeca106725	918
Kojto	122:f9eeca106725	919	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	920	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	122:f9eeca106725	921	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	122:f9eeca106725	922	@{
Kojto	122:f9eeca106725	923	*/
Kojto	122:f9eeca106725	924
Kojto	122:f9eeca106725	925	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	122:f9eeca106725	926	*/
Kojto	122:f9eeca106725	927	typedef struct
Kojto	122:f9eeca106725	928	{
Kojto	122:f9eeca106725	929	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	122:f9eeca106725	930	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	122:f9eeca106725	931	uint32_t RESERVED0[2];
Kojto	122:f9eeca106725	932	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	122:f9eeca106725	933	uint32_t RESERVED1[55];
Kojto	122:f9eeca106725	934	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	122:f9eeca106725	935	uint32_t RESERVED2[131];
Kojto	122:f9eeca106725	936	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	122:f9eeca106725	937	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	122:f9eeca106725	938	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	122:f9eeca106725	939	uint32_t RESERVED3[759];
Kojto	122:f9eeca106725	940	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	122:f9eeca106725	941	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	122:f9eeca106725	942	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	122:f9eeca106725	943	uint32_t RESERVED4[1];
Kojto	122:f9eeca106725	944	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	122:f9eeca106725	945	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	122:f9eeca106725	946	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	122:f9eeca106725	947	uint32_t RESERVED5[39];
Kojto	122:f9eeca106725	948	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	122:f9eeca106725	949	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	122:f9eeca106725	950	uint32_t RESERVED7[8];
Kojto	122:f9eeca106725	951	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	122:f9eeca106725	952	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	122:f9eeca106725	953	} TPI_Type;
Kojto	122:f9eeca106725	954
Kojto	122:f9eeca106725	955	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	122:f9eeca106725	956	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	122:f9eeca106725	957	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Kojto	122:f9eeca106725	958
Kojto	122:f9eeca106725	959	/* TPI Selected Pin Protocol Register Definitions */
Kojto	122:f9eeca106725	960	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	122:f9eeca106725	961	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Kojto	122:f9eeca106725	962
Kojto	122:f9eeca106725	963	/* TPI Formatter and Flush Status Register Definitions */
Kojto	122:f9eeca106725	964	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Kojto	122:f9eeca106725	965	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	122:f9eeca106725	966
Kojto	122:f9eeca106725	967	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Kojto	122:f9eeca106725	968	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	122:f9eeca106725	969
Kojto	122:f9eeca106725	970	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Kojto	122:f9eeca106725	971	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	122:f9eeca106725	972
Kojto	122:f9eeca106725	973	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	122:f9eeca106725	974	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Kojto	122:f9eeca106725	975
Kojto	122:f9eeca106725	976	/* TPI Formatter and Flush Control Register Definitions */
Kojto	122:f9eeca106725	977	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Kojto	122:f9eeca106725	978	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	122:f9eeca106725	979
Kojto	122:f9eeca106725	980	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Kojto	122:f9eeca106725	981	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	122:f9eeca106725	982
Kojto	122:f9eeca106725	983	/* TPI TRIGGER Register Definitions */
Kojto	122:f9eeca106725	984	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	122:f9eeca106725	985	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	122:f9eeca106725	986
Kojto	122:f9eeca106725	987	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	122:f9eeca106725	988	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	122:f9eeca106725	989	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	122:f9eeca106725	990
Kojto	122:f9eeca106725	991	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Kojto	122:f9eeca106725	992	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	122:f9eeca106725	993
Kojto	122:f9eeca106725	994	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	122:f9eeca106725	995	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	122:f9eeca106725	996
Kojto	122:f9eeca106725	997	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Kojto	122:f9eeca106725	998	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	122:f9eeca106725	999
Kojto	122:f9eeca106725	1000	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Kojto	122:f9eeca106725	1001	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	122:f9eeca106725	1002
Kojto	122:f9eeca106725	1003	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Kojto	122:f9eeca106725	1004	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	122:f9eeca106725	1005
Kojto	122:f9eeca106725	1006	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	122:f9eeca106725	1007	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Kojto	122:f9eeca106725	1008
Kojto	122:f9eeca106725	1009	/* TPI ITATBCTR2 Register Definitions */
Kojto	122:f9eeca106725	1010	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	122:f9eeca106725	1011	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	122:f9eeca106725	1012
Kojto	122:f9eeca106725	1013	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	122:f9eeca106725	1014	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	122:f9eeca106725	1015	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	122:f9eeca106725	1016
Kojto	122:f9eeca106725	1017	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Kojto	122:f9eeca106725	1018	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	122:f9eeca106725	1019
Kojto	122:f9eeca106725	1020	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	122:f9eeca106725	1021	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	122:f9eeca106725	1022
Kojto	122:f9eeca106725	1023	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Kojto	122:f9eeca106725	1024	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	122:f9eeca106725	1025
Kojto	122:f9eeca106725	1026	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Kojto	122:f9eeca106725	1027	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	122:f9eeca106725	1028
Kojto	122:f9eeca106725	1029	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Kojto	122:f9eeca106725	1030	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	122:f9eeca106725	1031
Kojto	122:f9eeca106725	1032	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	122:f9eeca106725	1033	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Kojto	122:f9eeca106725	1034
Kojto	122:f9eeca106725	1035	/* TPI ITATBCTR0 Register Definitions */
Kojto	122:f9eeca106725	1036	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	122:f9eeca106725	1037	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	122:f9eeca106725	1038
Kojto	122:f9eeca106725	1039	/* TPI Integration Mode Control Register Definitions */
Kojto	122:f9eeca106725	1040	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	122:f9eeca106725	1041	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Kojto	122:f9eeca106725	1042
Kojto	122:f9eeca106725	1043	/* TPI DEVID Register Definitions */
Kojto	122:f9eeca106725	1044	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Kojto	122:f9eeca106725	1045	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	122:f9eeca106725	1046
Kojto	122:f9eeca106725	1047	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Kojto	122:f9eeca106725	1048	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	122:f9eeca106725	1049
Kojto	122:f9eeca106725	1050	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Kojto	122:f9eeca106725	1051	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	122:f9eeca106725	1052
Kojto	122:f9eeca106725	1053	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Kojto	122:f9eeca106725	1054	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	122:f9eeca106725	1055
Kojto	122:f9eeca106725	1056	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Kojto	122:f9eeca106725	1057	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	122:f9eeca106725	1058
Kojto	122:f9eeca106725	1059	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	122:f9eeca106725	1060	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Kojto	122:f9eeca106725	1061
Kojto	122:f9eeca106725	1062	/* TPI DEVTYPE Register Definitions */
Kojto	122:f9eeca106725	1063	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Kojto	122:f9eeca106725	1064	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	122:f9eeca106725	1065
Kojto	122:f9eeca106725	1066	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	122:f9eeca106725	1067	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	122:f9eeca106725	1068
Kojto	122:f9eeca106725	1069	/@}/ /* end of group CMSIS_TPI */
Kojto	122:f9eeca106725	1070
Kojto	122:f9eeca106725	1071
Kojto	122:f9eeca106725	1072	#if (__MPU_PRESENT == 1)
Kojto	122:f9eeca106725	1073	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1074	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	122:f9eeca106725	1075	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	122:f9eeca106725	1076	@{
Kojto	122:f9eeca106725	1077	*/
Kojto	122:f9eeca106725	1078
Kojto	122:f9eeca106725	1079	/** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto	122:f9eeca106725	1080	*/
Kojto	122:f9eeca106725	1081	typedef struct
Kojto	122:f9eeca106725	1082	{
Kojto	122:f9eeca106725	1083	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	122:f9eeca106725	1084	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	122:f9eeca106725	1085	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Kojto	122:f9eeca106725	1086	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	122:f9eeca106725	1087	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Kojto	122:f9eeca106725	1088	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Kojto	122:f9eeca106725	1089	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1090	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Kojto	122:f9eeca106725	1091	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1092	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Kojto	122:f9eeca106725	1093	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1094	} MPU_Type;
Kojto	122:f9eeca106725	1095
Kojto	122:f9eeca106725	1096	/* MPU Type Register */
Kojto	122:f9eeca106725	1097	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Kojto	122:f9eeca106725	1098	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	122:f9eeca106725	1099
Kojto	122:f9eeca106725	1100	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Kojto	122:f9eeca106725	1101	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	122:f9eeca106725	1102
Kojto	122:f9eeca106725	1103	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	122:f9eeca106725	1104	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Kojto	122:f9eeca106725	1105
Kojto	122:f9eeca106725	1106	/* MPU Control Register */
Kojto	122:f9eeca106725	1107	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Kojto	122:f9eeca106725	1108	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	122:f9eeca106725	1109
Kojto	122:f9eeca106725	1110	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Kojto	122:f9eeca106725	1111	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	122:f9eeca106725	1112
Kojto	122:f9eeca106725	1113	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	122:f9eeca106725	1114	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Kojto	122:f9eeca106725	1115
Kojto	122:f9eeca106725	1116	/* MPU Region Number Register */
Kojto	122:f9eeca106725	1117	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	122:f9eeca106725	1118	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Kojto	122:f9eeca106725	1119
Kojto	122:f9eeca106725	1120	/* MPU Region Base Address Register */
Kojto	122:f9eeca106725	1121	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Kojto	122:f9eeca106725	1122	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	122:f9eeca106725	1123
Kojto	122:f9eeca106725	1124	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Kojto	122:f9eeca106725	1125	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Kojto	122:f9eeca106725	1126
Kojto	122:f9eeca106725	1127	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	122:f9eeca106725	1128	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Kojto	122:f9eeca106725	1129
Kojto	122:f9eeca106725	1130	/* MPU Region Attribute and Size Register */
Kojto	122:f9eeca106725	1131	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Kojto	122:f9eeca106725	1132	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Kojto	122:f9eeca106725	1133
Kojto	122:f9eeca106725	1134	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Kojto	122:f9eeca106725	1135	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Kojto	122:f9eeca106725	1136
Kojto	122:f9eeca106725	1137	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Kojto	122:f9eeca106725	1138	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Kojto	122:f9eeca106725	1139
Kojto	122:f9eeca106725	1140	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Kojto	122:f9eeca106725	1141	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Kojto	122:f9eeca106725	1142
Kojto	122:f9eeca106725	1143	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Kojto	122:f9eeca106725	1144	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Kojto	122:f9eeca106725	1145
Kojto	122:f9eeca106725	1146	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Kojto	122:f9eeca106725	1147	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Kojto	122:f9eeca106725	1148
Kojto	122:f9eeca106725	1149	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Kojto	122:f9eeca106725	1150	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Kojto	122:f9eeca106725	1151
Kojto	122:f9eeca106725	1152	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Kojto	122:f9eeca106725	1153	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Kojto	122:f9eeca106725	1154
Kojto	122:f9eeca106725	1155	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Kojto	122:f9eeca106725	1156	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Kojto	122:f9eeca106725	1157
Kojto	122:f9eeca106725	1158	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	122:f9eeca106725	1159	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Kojto	122:f9eeca106725	1160
Kojto	122:f9eeca106725	1161	/@} end of group CMSIS_MPU /
Kojto	122:f9eeca106725	1162	#endif
Kojto	122:f9eeca106725	1163
Kojto	122:f9eeca106725	1164
Kojto	122:f9eeca106725	1165	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1166	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	122:f9eeca106725	1167	\brief Type definitions for the Core Debug Registers
Kojto	122:f9eeca106725	1168	@{
Kojto	122:f9eeca106725	1169	*/
Kojto	122:f9eeca106725	1170
Kojto	122:f9eeca106725	1171	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	122:f9eeca106725	1172	*/
Kojto	122:f9eeca106725	1173	typedef struct
Kojto	122:f9eeca106725	1174	{
Kojto	122:f9eeca106725	1175	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	122:f9eeca106725	1176	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	122:f9eeca106725	1177	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	122:f9eeca106725	1178	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	122:f9eeca106725	1179	} CoreDebug_Type;
Kojto	122:f9eeca106725	1180
Kojto	122:f9eeca106725	1181	/* Debug Halting Control and Status Register */
Kojto	122:f9eeca106725	1182	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	122:f9eeca106725	1183	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	122:f9eeca106725	1184
Kojto	122:f9eeca106725	1185	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	122:f9eeca106725	1186	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	122:f9eeca106725	1187
Kojto	122:f9eeca106725	1188	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	122:f9eeca106725	1189	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	122:f9eeca106725	1190
Kojto	122:f9eeca106725	1191	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	122:f9eeca106725	1192	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	122:f9eeca106725	1193
Kojto	122:f9eeca106725	1194	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	122:f9eeca106725	1195	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	122:f9eeca106725	1196
Kojto	122:f9eeca106725	1197	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Kojto	122:f9eeca106725	1198	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	122:f9eeca106725	1199
Kojto	122:f9eeca106725	1200	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	122:f9eeca106725	1201	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	122:f9eeca106725	1202
Kojto	122:f9eeca106725	1203	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	122:f9eeca106725	1204	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	122:f9eeca106725	1205
Kojto	122:f9eeca106725	1206	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	122:f9eeca106725	1207	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	122:f9eeca106725	1208
Kojto	122:f9eeca106725	1209	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Kojto	122:f9eeca106725	1210	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	122:f9eeca106725	1211
Kojto	122:f9eeca106725	1212	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Kojto	122:f9eeca106725	1213	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	122:f9eeca106725	1214
Kojto	122:f9eeca106725	1215	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	122:f9eeca106725	1216	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	122:f9eeca106725	1217
Kojto	122:f9eeca106725	1218	/* Debug Core Register Selector Register */
Kojto	122:f9eeca106725	1219	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Kojto	122:f9eeca106725	1220	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	122:f9eeca106725	1221
Kojto	122:f9eeca106725	1222	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	122:f9eeca106725	1223	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	122:f9eeca106725	1224
Kojto	122:f9eeca106725	1225	/* Debug Exception and Monitor Control Register */
Kojto	122:f9eeca106725	1226	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Kojto	122:f9eeca106725	1227	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	122:f9eeca106725	1228
Kojto	122:f9eeca106725	1229	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	122:f9eeca106725	1230	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	122:f9eeca106725	1231
Kojto	122:f9eeca106725	1232	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	122:f9eeca106725	1233	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	122:f9eeca106725	1234
Kojto	122:f9eeca106725	1235	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	122:f9eeca106725	1236	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	122:f9eeca106725	1237
Kojto	122:f9eeca106725	1238	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Kojto	122:f9eeca106725	1239	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	122:f9eeca106725	1240
Kojto	122:f9eeca106725	1241	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	122:f9eeca106725	1242	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	122:f9eeca106725	1243
Kojto	122:f9eeca106725	1244	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	122:f9eeca106725	1245	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	122:f9eeca106725	1246
Kojto	122:f9eeca106725	1247	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	122:f9eeca106725	1248	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	122:f9eeca106725	1249
Kojto	122:f9eeca106725	1250	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	122:f9eeca106725	1251	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	122:f9eeca106725	1252
Kojto	122:f9eeca106725	1253	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	122:f9eeca106725	1254	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	122:f9eeca106725	1255
Kojto	122:f9eeca106725	1256	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	122:f9eeca106725	1257	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	122:f9eeca106725	1258
Kojto	122:f9eeca106725	1259	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	122:f9eeca106725	1260	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	122:f9eeca106725	1261
Kojto	122:f9eeca106725	1262	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	122:f9eeca106725	1263	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	122:f9eeca106725	1264
Kojto	122:f9eeca106725	1265	/@} end of group CMSIS_CoreDebug /
Kojto	122:f9eeca106725	1266
Kojto	122:f9eeca106725	1267
Kojto	122:f9eeca106725	1268	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1269	\defgroup CMSIS_core_base Core Definitions
Kojto	122:f9eeca106725	1270	\brief Definitions for base addresses, unions, and structures.
Kojto	122:f9eeca106725	1271	@{
Kojto	122:f9eeca106725	1272	*/
Kojto	122:f9eeca106725	1273
Kojto	122:f9eeca106725	1274	/* Memory mapping of Cortex-M3 Hardware */
Kojto	122:f9eeca106725	1275	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	122:f9eeca106725	1276	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	122:f9eeca106725	1277	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	122:f9eeca106725	1278	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	122:f9eeca106725	1279	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	122:f9eeca106725	1280	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	122:f9eeca106725	1281	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	122:f9eeca106725	1282	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	122:f9eeca106725	1283
Kojto	122:f9eeca106725	1284	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	122:f9eeca106725	1285	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	122:f9eeca106725	1286	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	122:f9eeca106725	1287	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	122:f9eeca106725	1288	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	122:f9eeca106725	1289	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	122:f9eeca106725	1290	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	122:f9eeca106725	1291	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Kojto	122:f9eeca106725	1292
Kojto	122:f9eeca106725	1293	#if (__MPU_PRESENT == 1)
Kojto	122:f9eeca106725	1294	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	122:f9eeca106725	1295	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	122:f9eeca106725	1296	#endif
Kojto	122:f9eeca106725	1297
Kojto	122:f9eeca106725	1298	/@} /
Kojto	122:f9eeca106725	1299
Kojto	122:f9eeca106725	1300
Kojto	122:f9eeca106725	1301
Kojto	122:f9eeca106725	1302	/*******************************************************************************
Kojto	122:f9eeca106725	1303	* Hardware Abstraction Layer
Kojto	122:f9eeca106725	1304	Core Function Interface contains:
Kojto	122:f9eeca106725	1305	- Core NVIC Functions
Kojto	122:f9eeca106725	1306	- Core SysTick Functions
Kojto	122:f9eeca106725	1307	- Core Debug Functions
Kojto	122:f9eeca106725	1308	- Core Register Access Functions
Kojto	122:f9eeca106725	1309	******************************************************************************/
Kojto	122:f9eeca106725	1310	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	122:f9eeca106725	1311	*/
Kojto	122:f9eeca106725	1312
Kojto	122:f9eeca106725	1313
Kojto	122:f9eeca106725	1314
Kojto	122:f9eeca106725	1315	/* ########################## NVIC functions #################################### */
Kojto	122:f9eeca106725	1316	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1317	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	122:f9eeca106725	1318	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	122:f9eeca106725	1319	@{
Kojto	122:f9eeca106725	1320	*/
Kojto	122:f9eeca106725	1321
Kojto	122:f9eeca106725	1322	/** \brief Set Priority Grouping
Kojto	122:f9eeca106725	1323
Kojto	122:f9eeca106725	1324	The function sets the priority grouping field using the required unlock sequence.
Kojto	122:f9eeca106725	1325	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	122:f9eeca106725	1326	Only values from 0..7 are used.
Kojto	122:f9eeca106725	1327	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1328	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	122:f9eeca106725	1329
Kojto	122:f9eeca106725	1330	\param [in] PriorityGroup Priority grouping field.
Kojto	122:f9eeca106725	1331	*/
Kojto	122:f9eeca106725	1332	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	122:f9eeca106725	1333	{
Kojto	122:f9eeca106725	1334	uint32_t reg_value;
Kojto	122:f9eeca106725	1335	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1336
Kojto	122:f9eeca106725	1337	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	122:f9eeca106725	1338	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	122:f9eeca106725	1339	reg_value = (reg_value \|
Kojto	122:f9eeca106725	1340	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	122:f9eeca106725	1341	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto	122:f9eeca106725	1342	SCB->AIRCR = reg_value;
Kojto	122:f9eeca106725	1343	}
Kojto	122:f9eeca106725	1344
Kojto	122:f9eeca106725	1345
Kojto	122:f9eeca106725	1346	/** \brief Get Priority Grouping
Kojto	122:f9eeca106725	1347
Kojto	122:f9eeca106725	1348	The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	122:f9eeca106725	1349
Kojto	122:f9eeca106725	1350	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	122:f9eeca106725	1351	*/
Kojto	122:f9eeca106725	1352	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto	122:f9eeca106725	1353	{
Kojto	122:f9eeca106725	1354	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto	122:f9eeca106725	1355	}
Kojto	122:f9eeca106725	1356
Kojto	122:f9eeca106725	1357
Kojto	122:f9eeca106725	1358	/** \brief Enable External Interrupt
Kojto	122:f9eeca106725	1359
Kojto	122:f9eeca106725	1360	The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto	122:f9eeca106725	1361
Kojto	122:f9eeca106725	1362	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1363	*/
Kojto	122:f9eeca106725	1364	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1365	{
Kojto	122:f9eeca106725	1366	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1367	}
Kojto	122:f9eeca106725	1368
Kojto	122:f9eeca106725	1369
Kojto	122:f9eeca106725	1370	/** \brief Disable External Interrupt
Kojto	122:f9eeca106725	1371
Kojto	122:f9eeca106725	1372	The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto	122:f9eeca106725	1373
Kojto	122:f9eeca106725	1374	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1375	*/
Kojto	122:f9eeca106725	1376	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1377	{
Kojto	122:f9eeca106725	1378	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	131:faff56e089b2	1379	__DSB();
<>	131:faff56e089b2	1380	__ISB();
Kojto	122:f9eeca106725	1381	}
Kojto	122:f9eeca106725	1382
Kojto	122:f9eeca106725	1383
Kojto	122:f9eeca106725	1384	/** \brief Get Pending Interrupt
Kojto	122:f9eeca106725	1385
Kojto	122:f9eeca106725	1386	The function reads the pending register in the NVIC and returns the pending bit
Kojto	122:f9eeca106725	1387	for the specified interrupt.
Kojto	122:f9eeca106725	1388
Kojto	122:f9eeca106725	1389	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1390
Kojto	122:f9eeca106725	1391	\return 0 Interrupt status is not pending.
Kojto	122:f9eeca106725	1392	\return 1 Interrupt status is pending.
Kojto	122:f9eeca106725	1393	*/
Kojto	122:f9eeca106725	1394	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1395	{
Kojto	122:f9eeca106725	1396	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	122:f9eeca106725	1397	}
Kojto	122:f9eeca106725	1398
Kojto	122:f9eeca106725	1399
Kojto	122:f9eeca106725	1400	/** \brief Set Pending Interrupt
Kojto	122:f9eeca106725	1401
Kojto	122:f9eeca106725	1402	The function sets the pending bit of an external interrupt.
Kojto	122:f9eeca106725	1403
Kojto	122:f9eeca106725	1404	\param [in] IRQn Interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1405	*/
Kojto	122:f9eeca106725	1406	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1407	{
Kojto	122:f9eeca106725	1408	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1409	}
Kojto	122:f9eeca106725	1410
Kojto	122:f9eeca106725	1411
Kojto	122:f9eeca106725	1412	/** \brief Clear Pending Interrupt
Kojto	122:f9eeca106725	1413
Kojto	122:f9eeca106725	1414	The function clears the pending bit of an external interrupt.
Kojto	122:f9eeca106725	1415
Kojto	122:f9eeca106725	1416	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1417	*/
Kojto	122:f9eeca106725	1418	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1419	{
Kojto	122:f9eeca106725	1420	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1421	}
Kojto	122:f9eeca106725	1422
Kojto	122:f9eeca106725	1423
Kojto	122:f9eeca106725	1424	/** \brief Get Active Interrupt
Kojto	122:f9eeca106725	1425
Kojto	122:f9eeca106725	1426	The function reads the active register in NVIC and returns the active bit.
Kojto	122:f9eeca106725	1427
Kojto	122:f9eeca106725	1428	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1429
Kojto	122:f9eeca106725	1430	\return 0 Interrupt status is not active.
Kojto	122:f9eeca106725	1431	\return 1 Interrupt status is active.
Kojto	122:f9eeca106725	1432	*/
Kojto	122:f9eeca106725	1433	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1434	{
Kojto	122:f9eeca106725	1435	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	122:f9eeca106725	1436	}
Kojto	122:f9eeca106725	1437
Kojto	122:f9eeca106725	1438
Kojto	122:f9eeca106725	1439	/** \brief Set Interrupt Priority
Kojto	122:f9eeca106725	1440
Kojto	122:f9eeca106725	1441	The function sets the priority of an interrupt.
Kojto	122:f9eeca106725	1442
Kojto	122:f9eeca106725	1443	\note The priority cannot be set for every core interrupt.
Kojto	122:f9eeca106725	1444
Kojto	122:f9eeca106725	1445	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1446	\param [in] priority Priority to set.
Kojto	122:f9eeca106725	1447	*/
Kojto	122:f9eeca106725	1448	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	122:f9eeca106725	1449	{
Kojto	122:f9eeca106725	1450	if((int32_t)IRQn < 0) {
Kojto	122:f9eeca106725	1451	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	122:f9eeca106725	1452	}
Kojto	122:f9eeca106725	1453	else {
Kojto	122:f9eeca106725	1454	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	122:f9eeca106725	1455	}
Kojto	122:f9eeca106725	1456	}
Kojto	122:f9eeca106725	1457
Kojto	122:f9eeca106725	1458
Kojto	122:f9eeca106725	1459	/** \brief Get Interrupt Priority
Kojto	122:f9eeca106725	1460
Kojto	122:f9eeca106725	1461	The function reads the priority of an interrupt. The interrupt
Kojto	122:f9eeca106725	1462	number can be positive to specify an external (device specific)
Kojto	122:f9eeca106725	1463	interrupt, or negative to specify an internal (core) interrupt.
Kojto	122:f9eeca106725	1464
Kojto	122:f9eeca106725	1465
Kojto	122:f9eeca106725	1466	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1467	\return Interrupt Priority. Value is aligned automatically to the implemented
Kojto	122:f9eeca106725	1468	priority bits of the microcontroller.
Kojto	122:f9eeca106725	1469	*/
Kojto	122:f9eeca106725	1470	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1471	{
Kojto	122:f9eeca106725	1472
Kojto	122:f9eeca106725	1473	if((int32_t)IRQn < 0) {
Kojto	122:f9eeca106725	1474	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	122:f9eeca106725	1475	}
Kojto	122:f9eeca106725	1476	else {
Kojto	122:f9eeca106725	1477	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	122:f9eeca106725	1478	}
Kojto	122:f9eeca106725	1479	}
Kojto	122:f9eeca106725	1480
Kojto	122:f9eeca106725	1481
Kojto	122:f9eeca106725	1482	/** \brief Encode Priority
Kojto	122:f9eeca106725	1483
Kojto	122:f9eeca106725	1484	The function encodes the priority for an interrupt with the given priority group,
Kojto	122:f9eeca106725	1485	preemptive priority value, and subpriority value.
Kojto	122:f9eeca106725	1486	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1487	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	122:f9eeca106725	1488
Kojto	122:f9eeca106725	1489	\param [in] PriorityGroup Used priority group.
Kojto	122:f9eeca106725	1490	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	122:f9eeca106725	1491	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	122:f9eeca106725	1492	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	122:f9eeca106725	1493	*/
Kojto	122:f9eeca106725	1494	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	122:f9eeca106725	1495	{
Kojto	122:f9eeca106725	1496	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1497	uint32_t PreemptPriorityBits;
Kojto	122:f9eeca106725	1498	uint32_t SubPriorityBits;
Kojto	122:f9eeca106725	1499
Kojto	122:f9eeca106725	1500	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	122:f9eeca106725	1501	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	122:f9eeca106725	1502
Kojto	122:f9eeca106725	1503	return (
Kojto	122:f9eeca106725	1504	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	122:f9eeca106725	1505	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto	122:f9eeca106725	1506	);
Kojto	122:f9eeca106725	1507	}
Kojto	122:f9eeca106725	1508
Kojto	122:f9eeca106725	1509
Kojto	122:f9eeca106725	1510	/** \brief Decode Priority
Kojto	122:f9eeca106725	1511
Kojto	122:f9eeca106725	1512	The function decodes an interrupt priority value with a given priority group to
Kojto	122:f9eeca106725	1513	preemptive priority value and subpriority value.
Kojto	122:f9eeca106725	1514	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1515	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto	122:f9eeca106725	1516
Kojto	122:f9eeca106725	1517	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	122:f9eeca106725	1518	\param [in] PriorityGroup Used priority group.
Kojto	122:f9eeca106725	1519	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	122:f9eeca106725	1520	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	122:f9eeca106725	1521	*/
Kojto	122:f9eeca106725	1522	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto	122:f9eeca106725	1523	{
Kojto	122:f9eeca106725	1524	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1525	uint32_t PreemptPriorityBits;
Kojto	122:f9eeca106725	1526	uint32_t SubPriorityBits;
Kojto	122:f9eeca106725	1527
Kojto	122:f9eeca106725	1528	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	122:f9eeca106725	1529	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	122:f9eeca106725	1530
Kojto	122:f9eeca106725	1531	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	122:f9eeca106725	1532	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto	122:f9eeca106725	1533	}
Kojto	122:f9eeca106725	1534
Kojto	122:f9eeca106725	1535
Kojto	122:f9eeca106725	1536	/** \brief System Reset
Kojto	122:f9eeca106725	1537
Kojto	122:f9eeca106725	1538	The function initiates a system reset request to reset the MCU.
Kojto	122:f9eeca106725	1539	*/
Kojto	122:f9eeca106725	1540	__STATIC_INLINE void NVIC_SystemReset(void)
Kojto	122:f9eeca106725	1541	{
Kojto	122:f9eeca106725	1542	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	122:f9eeca106725	1543	buffered write are completed before reset */
Kojto	122:f9eeca106725	1544	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	122:f9eeca106725	1545	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	122:f9eeca106725	1546	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	122:f9eeca106725	1547	__DSB(); /* Ensure completion of memory access */
Kojto	122:f9eeca106725	1548	while(1) { __NOP(); } /* wait until reset */
Kojto	122:f9eeca106725	1549	}
Kojto	122:f9eeca106725	1550
Kojto	122:f9eeca106725	1551	/@} end of CMSIS_Core_NVICFunctions /
Kojto	122:f9eeca106725	1552
Kojto	122:f9eeca106725	1553
Kojto	122:f9eeca106725	1554
Kojto	122:f9eeca106725	1555	/* ################################## SysTick function ############################################ */
Kojto	122:f9eeca106725	1556	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1557	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	122:f9eeca106725	1558	\brief Functions that configure the System.
Kojto	122:f9eeca106725	1559	@{
Kojto	122:f9eeca106725	1560	*/
Kojto	122:f9eeca106725	1561
Kojto	122:f9eeca106725	1562	#if (__Vendor_SysTickConfig == 0)
Kojto	122:f9eeca106725	1563
Kojto	122:f9eeca106725	1564	/** \brief System Tick Configuration
Kojto	122:f9eeca106725	1565
Kojto	122:f9eeca106725	1566	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	122:f9eeca106725	1567	Counter is in free running mode to generate periodic interrupts.
Kojto	122:f9eeca106725	1568
Kojto	122:f9eeca106725	1569	\param [in] ticks Number of ticks between two interrupts.
Kojto	122:f9eeca106725	1570
Kojto	122:f9eeca106725	1571	\return 0 Function succeeded.
Kojto	122:f9eeca106725	1572	\return 1 Function failed.
Kojto	122:f9eeca106725	1573
Kojto	122:f9eeca106725	1574	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	122:f9eeca106725	1575	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	122:f9eeca106725	1576	must contain a vendor-specific implementation of this function.
Kojto	122:f9eeca106725	1577
Kojto	122:f9eeca106725	1578	*/
Kojto	122:f9eeca106725	1579	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	122:f9eeca106725	1580	{
Kojto	122:f9eeca106725	1581	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto	122:f9eeca106725	1582
Kojto	122:f9eeca106725	1583	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	122:f9eeca106725	1584	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	122:f9eeca106725	1585	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	122:f9eeca106725	1586	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	122:f9eeca106725	1587	SysTick_CTRL_TICKINT_Msk \|
Kojto	122:f9eeca106725	1588	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	122:f9eeca106725	1589	return (0UL); /* Function successful */
Kojto	122:f9eeca106725	1590	}
Kojto	122:f9eeca106725	1591
Kojto	122:f9eeca106725	1592	#endif
Kojto	122:f9eeca106725	1593
Kojto	122:f9eeca106725	1594	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	122:f9eeca106725	1595
Kojto	122:f9eeca106725	1596
Kojto	122:f9eeca106725	1597
Kojto	122:f9eeca106725	1598	/* ##################################### Debug In/Output function ########################################### */
Kojto	122:f9eeca106725	1599	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1600	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	122:f9eeca106725	1601	\brief Functions that access the ITM debug interface.
Kojto	122:f9eeca106725	1602	@{
Kojto	122:f9eeca106725	1603	*/
Kojto	122:f9eeca106725	1604
Kojto	122:f9eeca106725	1605	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	122:f9eeca106725	1606	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	122:f9eeca106725	1607
Kojto	122:f9eeca106725	1608
Kojto	122:f9eeca106725	1609	/** \brief ITM Send Character
Kojto	122:f9eeca106725	1610
Kojto	122:f9eeca106725	1611	The function transmits a character via the ITM channel 0, and
Kojto	122:f9eeca106725	1612	\li Just returns when no debugger is connected that has booked the output.
Kojto	122:f9eeca106725	1613	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	122:f9eeca106725	1614
Kojto	122:f9eeca106725	1615	\param [in] ch Character to transmit.
Kojto	122:f9eeca106725	1616
Kojto	122:f9eeca106725	1617	\returns Character to transmit.
Kojto	122:f9eeca106725	1618	*/
Kojto	122:f9eeca106725	1619	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	122:f9eeca106725	1620	{
Kojto	122:f9eeca106725	1621	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	122:f9eeca106725	1622	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto	122:f9eeca106725	1623	{
Kojto	122:f9eeca106725	1624	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	122:f9eeca106725	1625	ITM->PORT[0].u8 = (uint8_t)ch;
Kojto	122:f9eeca106725	1626	}
Kojto	122:f9eeca106725	1627	return (ch);
Kojto	122:f9eeca106725	1628	}
Kojto	122:f9eeca106725	1629
Kojto	122:f9eeca106725	1630
Kojto	122:f9eeca106725	1631	/** \brief ITM Receive Character
Kojto	122:f9eeca106725	1632
Kojto	122:f9eeca106725	1633	The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	122:f9eeca106725	1634
Kojto	122:f9eeca106725	1635	\return Received character.
Kojto	122:f9eeca106725	1636	\return -1 No character pending.
Kojto	122:f9eeca106725	1637	*/
Kojto	122:f9eeca106725	1638	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto	122:f9eeca106725	1639	int32_t ch = -1; /* no character available */
Kojto	122:f9eeca106725	1640
Kojto	122:f9eeca106725	1641	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto	122:f9eeca106725	1642	ch = ITM_RxBuffer;
Kojto	122:f9eeca106725	1643	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	122:f9eeca106725	1644	}
Kojto	122:f9eeca106725	1645
Kojto	122:f9eeca106725	1646	return (ch);
Kojto	122:f9eeca106725	1647	}
Kojto	122:f9eeca106725	1648
Kojto	122:f9eeca106725	1649
Kojto	122:f9eeca106725	1650	/** \brief ITM Check Character
Kojto	122:f9eeca106725	1651
Kojto	122:f9eeca106725	1652	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	122:f9eeca106725	1653
Kojto	122:f9eeca106725	1654	\return 0 No character available.
Kojto	122:f9eeca106725	1655	\return 1 Character available.
Kojto	122:f9eeca106725	1656	*/
Kojto	122:f9eeca106725	1657	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto	122:f9eeca106725	1658
Kojto	122:f9eeca106725	1659	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto	122:f9eeca106725	1660	return (0); /* no character available */
Kojto	122:f9eeca106725	1661	} else {
Kojto	122:f9eeca106725	1662	return (1); /* character available */
Kojto	122:f9eeca106725	1663	}
Kojto	122:f9eeca106725	1664	}
Kojto	122:f9eeca106725	1665
Kojto	122:f9eeca106725	1666	/@} end of CMSIS_core_DebugFunctions /
Kojto	122:f9eeca106725	1667
Kojto	122:f9eeca106725	1668
Kojto	122:f9eeca106725	1669
Kojto	122:f9eeca106725	1670
Kojto	122:f9eeca106725	1671	#ifdef __cplusplus
Kojto	122:f9eeca106725	1672	}
Kojto	122:f9eeca106725	1673	#endif
Kojto	122:f9eeca106725	1674
Kojto	122:f9eeca106725	1675	#endif /* __CORE_SC300_H_DEPENDANT */
Kojto	122:f9eeca106725	1676
Kojto	122:f9eeca106725	1677	#endif /* __CMSIS_GENERIC */