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TARGET_NUCLEO_L432KC/core_cm3.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 131:faff56e089b2
Child:: 145:64910690c574

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/************************************************************************//
Kojto	122:f9eeca106725	2	* @file core_cm3.h
Kojto	122:f9eeca106725	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto	122:f9eeca106725	4	* @version V4.10
Kojto	122:f9eeca106725	5	* @date 18. March 2015
Kojto	122:f9eeca106725	6	*
Kojto	122:f9eeca106725	7	* @note
Kojto	122:f9eeca106725	8	*
Kojto	122:f9eeca106725	9	******************************************************************************/
Kojto	122:f9eeca106725	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto	122:f9eeca106725	11
Kojto	122:f9eeca106725	12	All rights reserved.
Kojto	122:f9eeca106725	13	Redistribution and use in source and binary forms, with or without
Kojto	122:f9eeca106725	14	modification, are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	- Redistributions of source code must retain the above copyright
Kojto	122:f9eeca106725	16	notice, this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	- Redistributions in binary form must reproduce the above copyright
Kojto	122:f9eeca106725	18	notice, this list of conditions and the following disclaimer in the
Kojto	122:f9eeca106725	19	documentation and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	- Neither the name of ARM nor the names of its contributors may be used
Kojto	122:f9eeca106725	21	to endorse or promote products derived from this software without
Kojto	122:f9eeca106725	22	specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto	122:f9eeca106725	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto	122:f9eeca106725	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto	122:f9eeca106725	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto	122:f9eeca106725	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto	122:f9eeca106725	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto	122:f9eeca106725	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto	122:f9eeca106725	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto	122:f9eeca106725	34	POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	35	---------------------------------------------------------------------------*/
Kojto	122:f9eeca106725	36
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	#if defined ( __ICCARM__ )
Kojto	122:f9eeca106725	39	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	122:f9eeca106725	40	#endif
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifndef __CORE_CM3_H_GENERIC
Kojto	122:f9eeca106725	43	#define __CORE_CM3_H_GENERIC
Kojto	122:f9eeca106725	44
Kojto	122:f9eeca106725	45	#ifdef __cplusplus
Kojto	122:f9eeca106725	46	extern "C" {
Kojto	122:f9eeca106725	47	#endif
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	122:f9eeca106725	50	CMSIS violates the following MISRA-C:2004 rules:
Kojto	122:f9eeca106725	51
Kojto	122:f9eeca106725	52	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	122:f9eeca106725	53	Function definitions in header files are used to allow 'inlining'.
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	122:f9eeca106725	56	Unions are used for effective representation of core registers.
Kojto	122:f9eeca106725	57
Kojto	122:f9eeca106725	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	122:f9eeca106725	59	Function-like macros are used to allow more efficient code.
Kojto	122:f9eeca106725	60	*/
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62
Kojto	122:f9eeca106725	63	/*******************************************************************************
Kojto	122:f9eeca106725	64	* CMSIS definitions
Kojto	122:f9eeca106725	65	******************************************************************************/
Kojto	122:f9eeca106725	66	/** \ingroup Cortex_M3
Kojto	122:f9eeca106725	67	@{
Kojto	122:f9eeca106725	68	*/
Kojto	122:f9eeca106725	69
Kojto	122:f9eeca106725	70	/* CMSIS CM3 definitions */
Kojto	122:f9eeca106725	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	122:f9eeca106725	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Kojto	122:f9eeca106725	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
Kojto	122:f9eeca106725	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
Kojto	122:f9eeca106725	77
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	#if defined ( __CC_ARM )
Kojto	122:f9eeca106725	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Kojto	122:f9eeca106725	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Kojto	122:f9eeca106725	82	#define __STATIC_INLINE static __inline
Kojto	122:f9eeca106725	83
Kojto	122:f9eeca106725	84	#elif defined ( __GNUC__ )
Kojto	122:f9eeca106725	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	122:f9eeca106725	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	122:f9eeca106725	87	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	88
Kojto	122:f9eeca106725	89	#elif defined ( __ICCARM__ )
Kojto	122:f9eeca106725	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Kojto	122:f9eeca106725	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Kojto	122:f9eeca106725	92	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	93
Kojto	122:f9eeca106725	94	#elif defined ( __TMS470__ )
Kojto	122:f9eeca106725	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Kojto	122:f9eeca106725	96	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	97
Kojto	122:f9eeca106725	98	#elif defined ( __TASKING__ )
Kojto	122:f9eeca106725	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Kojto	122:f9eeca106725	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Kojto	122:f9eeca106725	101	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	102
Kojto	122:f9eeca106725	103	#elif defined ( __CSMC__ )
Kojto	122:f9eeca106725	104	#define __packed
Kojto	122:f9eeca106725	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	122:f9eeca106725	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	122:f9eeca106725	107	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	108
Kojto	122:f9eeca106725	109	#endif
Kojto	122:f9eeca106725	110
Kojto	122:f9eeca106725	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	122:f9eeca106725	112	This core does not support an FPU at all
Kojto	122:f9eeca106725	113	*/
Kojto	122:f9eeca106725	114	#define __FPU_USED 0
Kojto	122:f9eeca106725	115
Kojto	122:f9eeca106725	116	#if defined ( __CC_ARM )
Kojto	122:f9eeca106725	117	#if defined __TARGET_FPU_VFP
Kojto	122:f9eeca106725	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	119	#endif
Kojto	122:f9eeca106725	120
Kojto	122:f9eeca106725	121	#elif defined ( __GNUC__ )
Kojto	122:f9eeca106725	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	122:f9eeca106725	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	124	#endif
Kojto	122:f9eeca106725	125
Kojto	122:f9eeca106725	126	#elif defined ( __ICCARM__ )
Kojto	122:f9eeca106725	127	#if defined __ARMVFP__
Kojto	122:f9eeca106725	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	129	#endif
Kojto	122:f9eeca106725	130
Kojto	122:f9eeca106725	131	#elif defined ( __TMS470__ )
Kojto	122:f9eeca106725	132	#if defined __TI__VFP_SUPPORT____
Kojto	122:f9eeca106725	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	134	#endif
Kojto	122:f9eeca106725	135
Kojto	122:f9eeca106725	136	#elif defined ( __TASKING__ )
Kojto	122:f9eeca106725	137	#if defined __FPU_VFP__
Kojto	122:f9eeca106725	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	139	#endif
Kojto	122:f9eeca106725	140
Kojto	122:f9eeca106725	141	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	122:f9eeca106725	142	#if ( __CSMC__ & 0x400) // FPU present for parser
Kojto	122:f9eeca106725	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	144	#endif
Kojto	122:f9eeca106725	145	#endif
Kojto	122:f9eeca106725	146
Kojto	122:f9eeca106725	147	#include <stdint.h> /* standard types definitions */
Kojto	122:f9eeca106725	148	#include <core_cmInstr.h> /* Core Instruction Access */
Kojto	122:f9eeca106725	149	#include <core_cmFunc.h> /* Core Function Access */
Kojto	122:f9eeca106725	150
Kojto	122:f9eeca106725	151	#ifdef __cplusplus
Kojto	122:f9eeca106725	152	}
Kojto	122:f9eeca106725	153	#endif
Kojto	122:f9eeca106725	154
Kojto	122:f9eeca106725	155	#endif /* __CORE_CM3_H_GENERIC */
Kojto	122:f9eeca106725	156
Kojto	122:f9eeca106725	157	#ifndef __CMSIS_GENERIC
Kojto	122:f9eeca106725	158
Kojto	122:f9eeca106725	159	#ifndef __CORE_CM3_H_DEPENDANT
Kojto	122:f9eeca106725	160	#define __CORE_CM3_H_DEPENDANT
Kojto	122:f9eeca106725	161
Kojto	122:f9eeca106725	162	#ifdef __cplusplus
Kojto	122:f9eeca106725	163	extern "C" {
Kojto	122:f9eeca106725	164	#endif
Kojto	122:f9eeca106725	165
Kojto	122:f9eeca106725	166	/* check device defines and use defaults */
Kojto	122:f9eeca106725	167	#if defined __CHECK_DEVICE_DEFINES
Kojto	122:f9eeca106725	168	#ifndef __CM3_REV
Kojto	122:f9eeca106725	169	#define __CM3_REV 0x0200
Kojto	122:f9eeca106725	170	#warning "__CM3_REV not defined in device header file; using default!"
Kojto	122:f9eeca106725	171	#endif
Kojto	122:f9eeca106725	172
Kojto	122:f9eeca106725	173	#ifndef __MPU_PRESENT
Kojto	122:f9eeca106725	174	#define __MPU_PRESENT 0
Kojto	122:f9eeca106725	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	176	#endif
Kojto	122:f9eeca106725	177
Kojto	122:f9eeca106725	178	#ifndef __NVIC_PRIO_BITS
Kojto	122:f9eeca106725	179	#define __NVIC_PRIO_BITS 4
Kojto	122:f9eeca106725	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	122:f9eeca106725	181	#endif
Kojto	122:f9eeca106725	182
Kojto	122:f9eeca106725	183	#ifndef __Vendor_SysTickConfig
Kojto	122:f9eeca106725	184	#define __Vendor_SysTickConfig 0
Kojto	122:f9eeca106725	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	122:f9eeca106725	186	#endif
Kojto	122:f9eeca106725	187	#endif
Kojto	122:f9eeca106725	188
Kojto	122:f9eeca106725	189	/* IO definitions (access restrictions to peripheral registers) */
Kojto	122:f9eeca106725	190	/**
Kojto	122:f9eeca106725	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	122:f9eeca106725	192
Kojto	122:f9eeca106725	193	<strong>IO Type Qualifiers</strong> are used
Kojto	122:f9eeca106725	194	\li to specify the access to peripheral variables.
Kojto	122:f9eeca106725	195	\li for automatic generation of peripheral register debug information.
Kojto	122:f9eeca106725	196	*/
Kojto	122:f9eeca106725	197	#ifdef __cplusplus
Kojto	122:f9eeca106725	198	#define __I volatile /!< Defines 'read only' permissions /
Kojto	122:f9eeca106725	199	#else
Kojto	122:f9eeca106725	200	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	122:f9eeca106725	201	#endif
Kojto	122:f9eeca106725	202	#define __O volatile /!< Defines 'write only' permissions /
Kojto	122:f9eeca106725	203	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	122:f9eeca106725	204
<>	128:9bcdf88f62b0	205	#ifdef __cplusplus
<>	128:9bcdf88f62b0	206	#define __IM volatile /!< Defines 'read only' permissions /
<>	128:9bcdf88f62b0	207	#else
<>	128:9bcdf88f62b0	208	#define __IM volatile const /!< Defines 'read only' permissions /
<>	128:9bcdf88f62b0	209	#endif
<>	128:9bcdf88f62b0	210	#define __OM volatile /!< Defines 'write only' permissions /
<>	128:9bcdf88f62b0	211	#define __IOM volatile /!< Defines 'read / write' permissions /
<>	128:9bcdf88f62b0	212
Kojto	122:f9eeca106725	213	/@} end of group Cortex_M3 /
Kojto	122:f9eeca106725	214
Kojto	122:f9eeca106725	215
Kojto	122:f9eeca106725	216
Kojto	122:f9eeca106725	217	/*******************************************************************************
Kojto	122:f9eeca106725	218	* Register Abstraction
Kojto	122:f9eeca106725	219	Core Register contain:
Kojto	122:f9eeca106725	220	- Core Register
Kojto	122:f9eeca106725	221	- Core NVIC Register
Kojto	122:f9eeca106725	222	- Core SCB Register
Kojto	122:f9eeca106725	223	- Core SysTick Register
Kojto	122:f9eeca106725	224	- Core Debug Register
Kojto	122:f9eeca106725	225	- Core MPU Register
Kojto	122:f9eeca106725	226	******************************************************************************/
Kojto	122:f9eeca106725	227	/** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto	122:f9eeca106725	228	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	122:f9eeca106725	229	*/
Kojto	122:f9eeca106725	230
Kojto	122:f9eeca106725	231	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	232	\defgroup CMSIS_CORE Status and Control Registers
Kojto	122:f9eeca106725	233	\brief Core Register type definitions.
Kojto	122:f9eeca106725	234	@{
Kojto	122:f9eeca106725	235	*/
Kojto	122:f9eeca106725	236
Kojto	122:f9eeca106725	237	/** \brief Union type to access the Application Program Status Register (APSR).
Kojto	122:f9eeca106725	238	*/
Kojto	122:f9eeca106725	239	typedef union
Kojto	122:f9eeca106725	240	{
Kojto	122:f9eeca106725	241	struct
Kojto	122:f9eeca106725	242	{
Kojto	122:f9eeca106725	243	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Kojto	122:f9eeca106725	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	122:f9eeca106725	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	122:f9eeca106725	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	122:f9eeca106725	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	122:f9eeca106725	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	122:f9eeca106725	249	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	250	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	251	} APSR_Type;
Kojto	122:f9eeca106725	252
Kojto	122:f9eeca106725	253	/* APSR Register Definitions */
Kojto	122:f9eeca106725	254	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	122:f9eeca106725	255	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	122:f9eeca106725	256
Kojto	122:f9eeca106725	257	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	122:f9eeca106725	258	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	122:f9eeca106725	259
Kojto	122:f9eeca106725	260	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	122:f9eeca106725	261	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	122:f9eeca106725	262
Kojto	122:f9eeca106725	263	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	122:f9eeca106725	264	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	122:f9eeca106725	265
Kojto	122:f9eeca106725	266	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	122:f9eeca106725	267	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	122:f9eeca106725	268
Kojto	122:f9eeca106725	269
Kojto	122:f9eeca106725	270	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	122:f9eeca106725	271	*/
Kojto	122:f9eeca106725	272	typedef union
Kojto	122:f9eeca106725	273	{
Kojto	122:f9eeca106725	274	struct
Kojto	122:f9eeca106725	275	{
Kojto	122:f9eeca106725	276	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	122:f9eeca106725	277	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	122:f9eeca106725	278	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	279	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	280	} IPSR_Type;
Kojto	122:f9eeca106725	281
Kojto	122:f9eeca106725	282	/* IPSR Register Definitions */
Kojto	122:f9eeca106725	283	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	122:f9eeca106725	284	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	122:f9eeca106725	285
Kojto	122:f9eeca106725	286
Kojto	122:f9eeca106725	287	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	122:f9eeca106725	288	*/
Kojto	122:f9eeca106725	289	typedef union
Kojto	122:f9eeca106725	290	{
Kojto	122:f9eeca106725	291	struct
Kojto	122:f9eeca106725	292	{
Kojto	122:f9eeca106725	293	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	122:f9eeca106725	294	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Kojto	122:f9eeca106725	295	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	122:f9eeca106725	296	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	122:f9eeca106725	297	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	122:f9eeca106725	298	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	122:f9eeca106725	299	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	122:f9eeca106725	300	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	122:f9eeca106725	301	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	122:f9eeca106725	302	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	303	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	304	} xPSR_Type;
Kojto	122:f9eeca106725	305
Kojto	122:f9eeca106725	306	/* xPSR Register Definitions */
Kojto	122:f9eeca106725	307	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	122:f9eeca106725	308	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	122:f9eeca106725	309
Kojto	122:f9eeca106725	310	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	122:f9eeca106725	311	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	122:f9eeca106725	312
Kojto	122:f9eeca106725	313	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	122:f9eeca106725	314	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	122:f9eeca106725	315
Kojto	122:f9eeca106725	316	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	122:f9eeca106725	317	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	122:f9eeca106725	318
Kojto	122:f9eeca106725	319	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	122:f9eeca106725	320	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	122:f9eeca106725	321
Kojto	122:f9eeca106725	322	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	122:f9eeca106725	323	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	122:f9eeca106725	324
Kojto	122:f9eeca106725	325	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	122:f9eeca106725	326	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	122:f9eeca106725	327
Kojto	122:f9eeca106725	328	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	122:f9eeca106725	329	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	122:f9eeca106725	330
Kojto	122:f9eeca106725	331
Kojto	122:f9eeca106725	332	/** \brief Union type to access the Control Registers (CONTROL).
Kojto	122:f9eeca106725	333	*/
Kojto	122:f9eeca106725	334	typedef union
Kojto	122:f9eeca106725	335	{
Kojto	122:f9eeca106725	336	struct
Kojto	122:f9eeca106725	337	{
Kojto	122:f9eeca106725	338	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	122:f9eeca106725	339	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	122:f9eeca106725	340	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
Kojto	122:f9eeca106725	341	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	342	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	343	} CONTROL_Type;
Kojto	122:f9eeca106725	344
Kojto	122:f9eeca106725	345	/* CONTROL Register Definitions */
Kojto	122:f9eeca106725	346	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	122:f9eeca106725	347	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	122:f9eeca106725	348
Kojto	122:f9eeca106725	349	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	122:f9eeca106725	350	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	122:f9eeca106725	351
Kojto	122:f9eeca106725	352	/@} end of group CMSIS_CORE /
Kojto	122:f9eeca106725	353
Kojto	122:f9eeca106725	354
Kojto	122:f9eeca106725	355	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	356	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	122:f9eeca106725	357	\brief Type definitions for the NVIC Registers
Kojto	122:f9eeca106725	358	@{
Kojto	122:f9eeca106725	359	*/
Kojto	122:f9eeca106725	360
Kojto	122:f9eeca106725	361	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	122:f9eeca106725	362	*/
Kojto	122:f9eeca106725	363	typedef struct
Kojto	122:f9eeca106725	364	{
Kojto	122:f9eeca106725	365	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	122:f9eeca106725	366	uint32_t RESERVED0[24];
Kojto	122:f9eeca106725	367	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	122:f9eeca106725	368	uint32_t RSERVED1[24];
Kojto	122:f9eeca106725	369	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	122:f9eeca106725	370	uint32_t RESERVED2[24];
Kojto	122:f9eeca106725	371	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	122:f9eeca106725	372	uint32_t RESERVED3[24];
Kojto	122:f9eeca106725	373	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	122:f9eeca106725	374	uint32_t RESERVED4[56];
Kojto	122:f9eeca106725	375	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	122:f9eeca106725	376	uint32_t RESERVED5[644];
Kojto	122:f9eeca106725	377	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	122:f9eeca106725	378	} NVIC_Type;
Kojto	122:f9eeca106725	379
Kojto	122:f9eeca106725	380	/* Software Triggered Interrupt Register Definitions */
Kojto	122:f9eeca106725	381	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	122:f9eeca106725	382	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Kojto	122:f9eeca106725	383
Kojto	122:f9eeca106725	384	/@} end of group CMSIS_NVIC /
Kojto	122:f9eeca106725	385
Kojto	122:f9eeca106725	386
Kojto	122:f9eeca106725	387	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	388	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	122:f9eeca106725	389	\brief Type definitions for the System Control Block Registers
Kojto	122:f9eeca106725	390	@{
Kojto	122:f9eeca106725	391	*/
Kojto	122:f9eeca106725	392
Kojto	122:f9eeca106725	393	/** \brief Structure type to access the System Control Block (SCB).
Kojto	122:f9eeca106725	394	*/
Kojto	122:f9eeca106725	395	typedef struct
Kojto	122:f9eeca106725	396	{
Kojto	122:f9eeca106725	397	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	122:f9eeca106725	398	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	122:f9eeca106725	399	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	122:f9eeca106725	400	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	122:f9eeca106725	401	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	122:f9eeca106725	402	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	122:f9eeca106725	403	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	122:f9eeca106725	404	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	122:f9eeca106725	405	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	122:f9eeca106725	406	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	122:f9eeca106725	407	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	122:f9eeca106725	408	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	122:f9eeca106725	409	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	122:f9eeca106725	410	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	122:f9eeca106725	411	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	122:f9eeca106725	412	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	122:f9eeca106725	413	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	122:f9eeca106725	414	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	122:f9eeca106725	415	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	122:f9eeca106725	416	uint32_t RESERVED0[5];
Kojto	122:f9eeca106725	417	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	122:f9eeca106725	418	} SCB_Type;
Kojto	122:f9eeca106725	419
Kojto	122:f9eeca106725	420	/* SCB CPUID Register Definitions */
Kojto	122:f9eeca106725	421	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Kojto	122:f9eeca106725	422	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	122:f9eeca106725	423
Kojto	122:f9eeca106725	424	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Kojto	122:f9eeca106725	425	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	122:f9eeca106725	426
Kojto	122:f9eeca106725	427	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Kojto	122:f9eeca106725	428	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	122:f9eeca106725	429
Kojto	122:f9eeca106725	430	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Kojto	122:f9eeca106725	431	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	122:f9eeca106725	432
Kojto	122:f9eeca106725	433	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	122:f9eeca106725	434	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Kojto	122:f9eeca106725	435
Kojto	122:f9eeca106725	436	/* SCB Interrupt Control State Register Definitions */
Kojto	122:f9eeca106725	437	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Kojto	122:f9eeca106725	438	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Kojto	122:f9eeca106725	439
Kojto	122:f9eeca106725	440	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Kojto	122:f9eeca106725	441	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	122:f9eeca106725	442
Kojto	122:f9eeca106725	443	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Kojto	122:f9eeca106725	444	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	122:f9eeca106725	445
Kojto	122:f9eeca106725	446	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Kojto	122:f9eeca106725	447	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	122:f9eeca106725	448
Kojto	122:f9eeca106725	449	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Kojto	122:f9eeca106725	450	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	122:f9eeca106725	451
Kojto	122:f9eeca106725	452	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Kojto	122:f9eeca106725	453	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	122:f9eeca106725	454
Kojto	122:f9eeca106725	455	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Kojto	122:f9eeca106725	456	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	122:f9eeca106725	457
Kojto	122:f9eeca106725	458	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Kojto	122:f9eeca106725	459	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	122:f9eeca106725	460
Kojto	122:f9eeca106725	461	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Kojto	122:f9eeca106725	462	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	122:f9eeca106725	463
Kojto	122:f9eeca106725	464	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	122:f9eeca106725	465	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	122:f9eeca106725	466
Kojto	122:f9eeca106725	467	/* SCB Vector Table Offset Register Definitions */
Kojto	122:f9eeca106725	468	#if (__CM3_REV < 0x0201) /* core r2p1 */
Kojto	122:f9eeca106725	469	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
Kojto	122:f9eeca106725	470	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
Kojto	122:f9eeca106725	471
Kojto	122:f9eeca106725	472	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	122:f9eeca106725	473	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	122:f9eeca106725	474	#else
Kojto	122:f9eeca106725	475	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	122:f9eeca106725	476	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	122:f9eeca106725	477	#endif
Kojto	122:f9eeca106725	478
Kojto	122:f9eeca106725	479	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	122:f9eeca106725	480	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Kojto	122:f9eeca106725	481	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	122:f9eeca106725	482
Kojto	122:f9eeca106725	483	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	122:f9eeca106725	484	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	122:f9eeca106725	485
Kojto	122:f9eeca106725	486	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Kojto	122:f9eeca106725	487	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	122:f9eeca106725	488
Kojto	122:f9eeca106725	489	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Kojto	122:f9eeca106725	490	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	122:f9eeca106725	491
Kojto	122:f9eeca106725	492	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	122:f9eeca106725	493	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	122:f9eeca106725	494
Kojto	122:f9eeca106725	495	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	122:f9eeca106725	496	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	122:f9eeca106725	497
Kojto	122:f9eeca106725	498	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	122:f9eeca106725	499	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Kojto	122:f9eeca106725	500
Kojto	122:f9eeca106725	501	/* SCB System Control Register Definitions */
Kojto	122:f9eeca106725	502	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Kojto	122:f9eeca106725	503	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	122:f9eeca106725	504
Kojto	122:f9eeca106725	505	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Kojto	122:f9eeca106725	506	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	122:f9eeca106725	507
Kojto	122:f9eeca106725	508	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Kojto	122:f9eeca106725	509	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	122:f9eeca106725	510
Kojto	122:f9eeca106725	511	/* SCB Configuration Control Register Definitions */
Kojto	122:f9eeca106725	512	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Kojto	122:f9eeca106725	513	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Kojto	122:f9eeca106725	514
Kojto	122:f9eeca106725	515	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Kojto	122:f9eeca106725	516	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	122:f9eeca106725	517
Kojto	122:f9eeca106725	518	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Kojto	122:f9eeca106725	519	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	122:f9eeca106725	520
Kojto	122:f9eeca106725	521	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Kojto	122:f9eeca106725	522	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	122:f9eeca106725	523
Kojto	122:f9eeca106725	524	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Kojto	122:f9eeca106725	525	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	122:f9eeca106725	526
Kojto	122:f9eeca106725	527	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	122:f9eeca106725	528	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Kojto	122:f9eeca106725	529
Kojto	122:f9eeca106725	530	/* SCB System Handler Control and State Register Definitions */
Kojto	122:f9eeca106725	531	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Kojto	122:f9eeca106725	532	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	122:f9eeca106725	533
Kojto	122:f9eeca106725	534	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	122:f9eeca106725	535	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	122:f9eeca106725	536
Kojto	122:f9eeca106725	537	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	122:f9eeca106725	538	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	122:f9eeca106725	539
Kojto	122:f9eeca106725	540	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	122:f9eeca106725	541	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	122:f9eeca106725	542
Kojto	122:f9eeca106725	543	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	122:f9eeca106725	544	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	122:f9eeca106725	545
Kojto	122:f9eeca106725	546	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	122:f9eeca106725	547	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	122:f9eeca106725	548
Kojto	122:f9eeca106725	549	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	122:f9eeca106725	550	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	122:f9eeca106725	551
Kojto	122:f9eeca106725	552	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Kojto	122:f9eeca106725	553	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	122:f9eeca106725	554
Kojto	122:f9eeca106725	555	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Kojto	122:f9eeca106725	556	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	122:f9eeca106725	557
Kojto	122:f9eeca106725	558	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Kojto	122:f9eeca106725	559	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	122:f9eeca106725	560
Kojto	122:f9eeca106725	561	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Kojto	122:f9eeca106725	562	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	122:f9eeca106725	563
Kojto	122:f9eeca106725	564	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Kojto	122:f9eeca106725	565	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	122:f9eeca106725	566
Kojto	122:f9eeca106725	567	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	122:f9eeca106725	568	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	122:f9eeca106725	569
Kojto	122:f9eeca106725	570	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	122:f9eeca106725	571	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	122:f9eeca106725	572
Kojto	122:f9eeca106725	573	/* SCB Configurable Fault Status Registers Definitions */
Kojto	122:f9eeca106725	574	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	122:f9eeca106725	575	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	122:f9eeca106725	576
Kojto	122:f9eeca106725	577	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	122:f9eeca106725	578	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	122:f9eeca106725	579
Kojto	122:f9eeca106725	580	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	122:f9eeca106725	581	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	122:f9eeca106725	582
Kojto	122:f9eeca106725	583	/* SCB Hard Fault Status Registers Definitions */
Kojto	122:f9eeca106725	584	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Kojto	122:f9eeca106725	585	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	122:f9eeca106725	586
Kojto	122:f9eeca106725	587	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Kojto	122:f9eeca106725	588	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	122:f9eeca106725	589
Kojto	122:f9eeca106725	590	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Kojto	122:f9eeca106725	591	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	122:f9eeca106725	592
Kojto	122:f9eeca106725	593	/* SCB Debug Fault Status Register Definitions */
Kojto	122:f9eeca106725	594	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Kojto	122:f9eeca106725	595	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	122:f9eeca106725	596
Kojto	122:f9eeca106725	597	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Kojto	122:f9eeca106725	598	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	122:f9eeca106725	599
Kojto	122:f9eeca106725	600	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Kojto	122:f9eeca106725	601	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	122:f9eeca106725	602
Kojto	122:f9eeca106725	603	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Kojto	122:f9eeca106725	604	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	122:f9eeca106725	605
Kojto	122:f9eeca106725	606	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	122:f9eeca106725	607	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Kojto	122:f9eeca106725	608
Kojto	122:f9eeca106725	609	/@} end of group CMSIS_SCB /
Kojto	122:f9eeca106725	610
Kojto	122:f9eeca106725	611
Kojto	122:f9eeca106725	612	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	613	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	122:f9eeca106725	614	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	122:f9eeca106725	615	@{
Kojto	122:f9eeca106725	616	*/
Kojto	122:f9eeca106725	617
Kojto	122:f9eeca106725	618	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	122:f9eeca106725	619	*/
Kojto	122:f9eeca106725	620	typedef struct
Kojto	122:f9eeca106725	621	{
Kojto	122:f9eeca106725	622	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	623	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	122:f9eeca106725	624	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kojto	122:f9eeca106725	625	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Kojto	122:f9eeca106725	626	#else
Kojto	122:f9eeca106725	627	uint32_t RESERVED1[1];
Kojto	122:f9eeca106725	628	#endif
Kojto	122:f9eeca106725	629	} SCnSCB_Type;
Kojto	122:f9eeca106725	630
Kojto	122:f9eeca106725	631	/* Interrupt Controller Type Register Definitions */
Kojto	122:f9eeca106725	632	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	122:f9eeca106725	633	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Kojto	122:f9eeca106725	634
Kojto	122:f9eeca106725	635	/* Auxiliary Control Register Definitions */
Kojto	122:f9eeca106725	636
Kojto	122:f9eeca106725	637	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Kojto	122:f9eeca106725	638	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Kojto	122:f9eeca106725	639
Kojto	122:f9eeca106725	640	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Kojto	122:f9eeca106725	641	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Kojto	122:f9eeca106725	642
Kojto	122:f9eeca106725	643	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	122:f9eeca106725	644	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Kojto	122:f9eeca106725	645
Kojto	122:f9eeca106725	646	/@} end of group CMSIS_SCnotSCB /
Kojto	122:f9eeca106725	647
Kojto	122:f9eeca106725	648
Kojto	122:f9eeca106725	649	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	650	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	122:f9eeca106725	651	\brief Type definitions for the System Timer Registers.
Kojto	122:f9eeca106725	652	@{
Kojto	122:f9eeca106725	653	*/
Kojto	122:f9eeca106725	654
Kojto	122:f9eeca106725	655	/** \brief Structure type to access the System Timer (SysTick).
Kojto	122:f9eeca106725	656	*/
Kojto	122:f9eeca106725	657	typedef struct
Kojto	122:f9eeca106725	658	{
Kojto	122:f9eeca106725	659	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	122:f9eeca106725	660	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	122:f9eeca106725	661	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	122:f9eeca106725	662	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	122:f9eeca106725	663	} SysTick_Type;
Kojto	122:f9eeca106725	664
Kojto	122:f9eeca106725	665	/* SysTick Control / Status Register Definitions */
Kojto	122:f9eeca106725	666	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Kojto	122:f9eeca106725	667	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	122:f9eeca106725	668
Kojto	122:f9eeca106725	669	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Kojto	122:f9eeca106725	670	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	122:f9eeca106725	671
Kojto	122:f9eeca106725	672	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Kojto	122:f9eeca106725	673	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	122:f9eeca106725	674
Kojto	122:f9eeca106725	675	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	122:f9eeca106725	676	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Kojto	122:f9eeca106725	677
Kojto	122:f9eeca106725	678	/* SysTick Reload Register Definitions */
Kojto	122:f9eeca106725	679	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	122:f9eeca106725	680	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Kojto	122:f9eeca106725	681
Kojto	122:f9eeca106725	682	/* SysTick Current Register Definitions */
Kojto	122:f9eeca106725	683	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	122:f9eeca106725	684	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Kojto	122:f9eeca106725	685
Kojto	122:f9eeca106725	686	/* SysTick Calibration Register Definitions */
Kojto	122:f9eeca106725	687	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Kojto	122:f9eeca106725	688	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	122:f9eeca106725	689
Kojto	122:f9eeca106725	690	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Kojto	122:f9eeca106725	691	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	122:f9eeca106725	692
Kojto	122:f9eeca106725	693	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	122:f9eeca106725	694	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Kojto	122:f9eeca106725	695
Kojto	122:f9eeca106725	696	/@} end of group CMSIS_SysTick /
Kojto	122:f9eeca106725	697
Kojto	122:f9eeca106725	698
Kojto	122:f9eeca106725	699	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	700	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	122:f9eeca106725	701	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	122:f9eeca106725	702	@{
Kojto	122:f9eeca106725	703	*/
Kojto	122:f9eeca106725	704
Kojto	122:f9eeca106725	705	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	122:f9eeca106725	706	*/
Kojto	122:f9eeca106725	707	typedef struct
Kojto	122:f9eeca106725	708	{
Kojto	122:f9eeca106725	709	__O union
Kojto	122:f9eeca106725	710	{
Kojto	122:f9eeca106725	711	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	122:f9eeca106725	712	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	122:f9eeca106725	713	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	122:f9eeca106725	714	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	122:f9eeca106725	715	uint32_t RESERVED0[864];
Kojto	122:f9eeca106725	716	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	122:f9eeca106725	717	uint32_t RESERVED1[15];
Kojto	122:f9eeca106725	718	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	122:f9eeca106725	719	uint32_t RESERVED2[15];
Kojto	122:f9eeca106725	720	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	122:f9eeca106725	721	uint32_t RESERVED3[29];
Kojto	122:f9eeca106725	722	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	122:f9eeca106725	723	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	122:f9eeca106725	724	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	122:f9eeca106725	725	uint32_t RESERVED4[43];
Kojto	122:f9eeca106725	726	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	122:f9eeca106725	727	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	122:f9eeca106725	728	uint32_t RESERVED5[6];
Kojto	122:f9eeca106725	729	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	122:f9eeca106725	730	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	122:f9eeca106725	731	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	122:f9eeca106725	732	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	122:f9eeca106725	733	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	122:f9eeca106725	734	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	122:f9eeca106725	735	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	122:f9eeca106725	736	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	122:f9eeca106725	737	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	122:f9eeca106725	738	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	122:f9eeca106725	739	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	122:f9eeca106725	740	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	122:f9eeca106725	741	} ITM_Type;
Kojto	122:f9eeca106725	742
Kojto	122:f9eeca106725	743	/* ITM Trace Privilege Register Definitions */
Kojto	122:f9eeca106725	744	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	122:f9eeca106725	745	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Kojto	122:f9eeca106725	746
Kojto	122:f9eeca106725	747	/* ITM Trace Control Register Definitions */
Kojto	122:f9eeca106725	748	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Kojto	122:f9eeca106725	749	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	122:f9eeca106725	750
Kojto	122:f9eeca106725	751	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Kojto	122:f9eeca106725	752	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	122:f9eeca106725	753
Kojto	122:f9eeca106725	754	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Kojto	122:f9eeca106725	755	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	122:f9eeca106725	756
Kojto	122:f9eeca106725	757	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Kojto	122:f9eeca106725	758	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Kojto	122:f9eeca106725	759
Kojto	122:f9eeca106725	760	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Kojto	122:f9eeca106725	761	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	122:f9eeca106725	762
Kojto	122:f9eeca106725	763	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Kojto	122:f9eeca106725	764	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	122:f9eeca106725	765
Kojto	122:f9eeca106725	766	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Kojto	122:f9eeca106725	767	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	122:f9eeca106725	768
Kojto	122:f9eeca106725	769	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Kojto	122:f9eeca106725	770	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	122:f9eeca106725	771
Kojto	122:f9eeca106725	772	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	122:f9eeca106725	773	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Kojto	122:f9eeca106725	774
Kojto	122:f9eeca106725	775	/* ITM Integration Write Register Definitions */
Kojto	122:f9eeca106725	776	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	122:f9eeca106725	777	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Kojto	122:f9eeca106725	778
Kojto	122:f9eeca106725	779	/* ITM Integration Read Register Definitions */
Kojto	122:f9eeca106725	780	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	122:f9eeca106725	781	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Kojto	122:f9eeca106725	782
Kojto	122:f9eeca106725	783	/* ITM Integration Mode Control Register Definitions */
Kojto	122:f9eeca106725	784	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	122:f9eeca106725	785	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Kojto	122:f9eeca106725	786
Kojto	122:f9eeca106725	787	/* ITM Lock Status Register Definitions */
Kojto	122:f9eeca106725	788	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Kojto	122:f9eeca106725	789	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	122:f9eeca106725	790
Kojto	122:f9eeca106725	791	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Kojto	122:f9eeca106725	792	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	122:f9eeca106725	793
Kojto	122:f9eeca106725	794	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	122:f9eeca106725	795	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Kojto	122:f9eeca106725	796
Kojto	122:f9eeca106725	797	/@}/ /* end of group CMSIS_ITM */
Kojto	122:f9eeca106725	798
Kojto	122:f9eeca106725	799
Kojto	122:f9eeca106725	800	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	801	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	122:f9eeca106725	802	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	122:f9eeca106725	803	@{
Kojto	122:f9eeca106725	804	*/
Kojto	122:f9eeca106725	805
Kojto	122:f9eeca106725	806	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	122:f9eeca106725	807	*/
Kojto	122:f9eeca106725	808	typedef struct
Kojto	122:f9eeca106725	809	{
Kojto	122:f9eeca106725	810	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	122:f9eeca106725	811	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	122:f9eeca106725	812	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	122:f9eeca106725	813	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	122:f9eeca106725	814	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	122:f9eeca106725	815	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	122:f9eeca106725	816	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	122:f9eeca106725	817	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	122:f9eeca106725	818	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	122:f9eeca106725	819	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Kojto	122:f9eeca106725	820	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	122:f9eeca106725	821	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	822	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	122:f9eeca106725	823	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Kojto	122:f9eeca106725	824	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	122:f9eeca106725	825	uint32_t RESERVED1[1];
Kojto	122:f9eeca106725	826	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	122:f9eeca106725	827	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Kojto	122:f9eeca106725	828	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	122:f9eeca106725	829	uint32_t RESERVED2[1];
Kojto	122:f9eeca106725	830	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	122:f9eeca106725	831	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Kojto	122:f9eeca106725	832	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	122:f9eeca106725	833	} DWT_Type;
Kojto	122:f9eeca106725	834
Kojto	122:f9eeca106725	835	/* DWT Control Register Definitions */
Kojto	122:f9eeca106725	836	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Kojto	122:f9eeca106725	837	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	122:f9eeca106725	838
Kojto	122:f9eeca106725	839	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Kojto	122:f9eeca106725	840	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	122:f9eeca106725	841
Kojto	122:f9eeca106725	842	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Kojto	122:f9eeca106725	843	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	122:f9eeca106725	844
Kojto	122:f9eeca106725	845	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Kojto	122:f9eeca106725	846	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	122:f9eeca106725	847
Kojto	122:f9eeca106725	848	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Kojto	122:f9eeca106725	849	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	122:f9eeca106725	850
Kojto	122:f9eeca106725	851	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Kojto	122:f9eeca106725	852	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	122:f9eeca106725	853
Kojto	122:f9eeca106725	854	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Kojto	122:f9eeca106725	855	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	122:f9eeca106725	856
Kojto	122:f9eeca106725	857	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Kojto	122:f9eeca106725	858	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	122:f9eeca106725	859
Kojto	122:f9eeca106725	860	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	122:f9eeca106725	861	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	122:f9eeca106725	862
Kojto	122:f9eeca106725	863	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Kojto	122:f9eeca106725	864	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	122:f9eeca106725	865
Kojto	122:f9eeca106725	866	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Kojto	122:f9eeca106725	867	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	122:f9eeca106725	868
Kojto	122:f9eeca106725	869	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Kojto	122:f9eeca106725	870	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	122:f9eeca106725	871
Kojto	122:f9eeca106725	872	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Kojto	122:f9eeca106725	873	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	122:f9eeca106725	874
Kojto	122:f9eeca106725	875	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Kojto	122:f9eeca106725	876	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	122:f9eeca106725	877
Kojto	122:f9eeca106725	878	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Kojto	122:f9eeca106725	879	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	122:f9eeca106725	880
Kojto	122:f9eeca106725	881	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Kojto	122:f9eeca106725	882	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	122:f9eeca106725	883
Kojto	122:f9eeca106725	884	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Kojto	122:f9eeca106725	885	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	122:f9eeca106725	886
Kojto	122:f9eeca106725	887	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	122:f9eeca106725	888	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	122:f9eeca106725	889
Kojto	122:f9eeca106725	890	/* DWT CPI Count Register Definitions */
Kojto	122:f9eeca106725	891	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	122:f9eeca106725	892	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Kojto	122:f9eeca106725	893
Kojto	122:f9eeca106725	894	/* DWT Exception Overhead Count Register Definitions */
Kojto	122:f9eeca106725	895	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	122:f9eeca106725	896	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	122:f9eeca106725	897
Kojto	122:f9eeca106725	898	/* DWT Sleep Count Register Definitions */
Kojto	122:f9eeca106725	899	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	122:f9eeca106725	900	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	122:f9eeca106725	901
Kojto	122:f9eeca106725	902	/* DWT LSU Count Register Definitions */
Kojto	122:f9eeca106725	903	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	122:f9eeca106725	904	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	122:f9eeca106725	905
Kojto	122:f9eeca106725	906	/* DWT Folded-instruction Count Register Definitions */
Kojto	122:f9eeca106725	907	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	122:f9eeca106725	908	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	122:f9eeca106725	909
Kojto	122:f9eeca106725	910	/* DWT Comparator Mask Register Definitions */
Kojto	122:f9eeca106725	911	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	122:f9eeca106725	912	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Kojto	122:f9eeca106725	913
Kojto	122:f9eeca106725	914	/* DWT Comparator Function Register Definitions */
Kojto	122:f9eeca106725	915	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Kojto	122:f9eeca106725	916	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	122:f9eeca106725	917
Kojto	122:f9eeca106725	918	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Kojto	122:f9eeca106725	919	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Kojto	122:f9eeca106725	920
Kojto	122:f9eeca106725	921	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Kojto	122:f9eeca106725	922	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Kojto	122:f9eeca106725	923
Kojto	122:f9eeca106725	924	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	122:f9eeca106725	925	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	122:f9eeca106725	926
Kojto	122:f9eeca106725	927	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Kojto	122:f9eeca106725	928	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Kojto	122:f9eeca106725	929
Kojto	122:f9eeca106725	930	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Kojto	122:f9eeca106725	931	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Kojto	122:f9eeca106725	932
Kojto	122:f9eeca106725	933	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Kojto	122:f9eeca106725	934	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Kojto	122:f9eeca106725	935
Kojto	122:f9eeca106725	936	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Kojto	122:f9eeca106725	937	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Kojto	122:f9eeca106725	938
Kojto	122:f9eeca106725	939	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	122:f9eeca106725	940	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Kojto	122:f9eeca106725	941
Kojto	122:f9eeca106725	942	/@}/ /* end of group CMSIS_DWT */
Kojto	122:f9eeca106725	943
Kojto	122:f9eeca106725	944
Kojto	122:f9eeca106725	945	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	946	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	122:f9eeca106725	947	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	122:f9eeca106725	948	@{
Kojto	122:f9eeca106725	949	*/
Kojto	122:f9eeca106725	950
Kojto	122:f9eeca106725	951	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	122:f9eeca106725	952	*/
Kojto	122:f9eeca106725	953	typedef struct
Kojto	122:f9eeca106725	954	{
Kojto	122:f9eeca106725	955	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	122:f9eeca106725	956	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	122:f9eeca106725	957	uint32_t RESERVED0[2];
Kojto	122:f9eeca106725	958	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	122:f9eeca106725	959	uint32_t RESERVED1[55];
Kojto	122:f9eeca106725	960	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	122:f9eeca106725	961	uint32_t RESERVED2[131];
Kojto	122:f9eeca106725	962	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	122:f9eeca106725	963	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	122:f9eeca106725	964	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	122:f9eeca106725	965	uint32_t RESERVED3[759];
Kojto	122:f9eeca106725	966	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	122:f9eeca106725	967	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	122:f9eeca106725	968	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	122:f9eeca106725	969	uint32_t RESERVED4[1];
Kojto	122:f9eeca106725	970	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	122:f9eeca106725	971	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	122:f9eeca106725	972	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	122:f9eeca106725	973	uint32_t RESERVED5[39];
Kojto	122:f9eeca106725	974	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	122:f9eeca106725	975	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	122:f9eeca106725	976	uint32_t RESERVED7[8];
Kojto	122:f9eeca106725	977	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	122:f9eeca106725	978	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	122:f9eeca106725	979	} TPI_Type;
Kojto	122:f9eeca106725	980
Kojto	122:f9eeca106725	981	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	122:f9eeca106725	982	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	122:f9eeca106725	983	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Kojto	122:f9eeca106725	984
Kojto	122:f9eeca106725	985	/* TPI Selected Pin Protocol Register Definitions */
Kojto	122:f9eeca106725	986	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	122:f9eeca106725	987	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Kojto	122:f9eeca106725	988
Kojto	122:f9eeca106725	989	/* TPI Formatter and Flush Status Register Definitions */
Kojto	122:f9eeca106725	990	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Kojto	122:f9eeca106725	991	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	122:f9eeca106725	992
Kojto	122:f9eeca106725	993	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Kojto	122:f9eeca106725	994	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	122:f9eeca106725	995
Kojto	122:f9eeca106725	996	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Kojto	122:f9eeca106725	997	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	122:f9eeca106725	998
Kojto	122:f9eeca106725	999	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	122:f9eeca106725	1000	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Kojto	122:f9eeca106725	1001
Kojto	122:f9eeca106725	1002	/* TPI Formatter and Flush Control Register Definitions */
Kojto	122:f9eeca106725	1003	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Kojto	122:f9eeca106725	1004	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	122:f9eeca106725	1005
Kojto	122:f9eeca106725	1006	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Kojto	122:f9eeca106725	1007	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	122:f9eeca106725	1008
Kojto	122:f9eeca106725	1009	/* TPI TRIGGER Register Definitions */
Kojto	122:f9eeca106725	1010	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	122:f9eeca106725	1011	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	122:f9eeca106725	1012
Kojto	122:f9eeca106725	1013	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	122:f9eeca106725	1014	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	122:f9eeca106725	1015	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	122:f9eeca106725	1016
Kojto	122:f9eeca106725	1017	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Kojto	122:f9eeca106725	1018	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	122:f9eeca106725	1019
Kojto	122:f9eeca106725	1020	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	122:f9eeca106725	1021	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	122:f9eeca106725	1022
Kojto	122:f9eeca106725	1023	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Kojto	122:f9eeca106725	1024	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	122:f9eeca106725	1025
Kojto	122:f9eeca106725	1026	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Kojto	122:f9eeca106725	1027	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	122:f9eeca106725	1028
Kojto	122:f9eeca106725	1029	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Kojto	122:f9eeca106725	1030	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	122:f9eeca106725	1031
Kojto	122:f9eeca106725	1032	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	122:f9eeca106725	1033	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Kojto	122:f9eeca106725	1034
Kojto	122:f9eeca106725	1035	/* TPI ITATBCTR2 Register Definitions */
Kojto	122:f9eeca106725	1036	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	122:f9eeca106725	1037	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	122:f9eeca106725	1038
Kojto	122:f9eeca106725	1039	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	122:f9eeca106725	1040	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	122:f9eeca106725	1041	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	122:f9eeca106725	1042
Kojto	122:f9eeca106725	1043	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Kojto	122:f9eeca106725	1044	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	122:f9eeca106725	1045
Kojto	122:f9eeca106725	1046	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	122:f9eeca106725	1047	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	122:f9eeca106725	1048
Kojto	122:f9eeca106725	1049	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Kojto	122:f9eeca106725	1050	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	122:f9eeca106725	1051
Kojto	122:f9eeca106725	1052	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Kojto	122:f9eeca106725	1053	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	122:f9eeca106725	1054
Kojto	122:f9eeca106725	1055	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Kojto	122:f9eeca106725	1056	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	122:f9eeca106725	1057
Kojto	122:f9eeca106725	1058	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	122:f9eeca106725	1059	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Kojto	122:f9eeca106725	1060
Kojto	122:f9eeca106725	1061	/* TPI ITATBCTR0 Register Definitions */
Kojto	122:f9eeca106725	1062	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	122:f9eeca106725	1063	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	122:f9eeca106725	1064
Kojto	122:f9eeca106725	1065	/* TPI Integration Mode Control Register Definitions */
Kojto	122:f9eeca106725	1066	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	122:f9eeca106725	1067	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Kojto	122:f9eeca106725	1068
Kojto	122:f9eeca106725	1069	/* TPI DEVID Register Definitions */
Kojto	122:f9eeca106725	1070	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Kojto	122:f9eeca106725	1071	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	122:f9eeca106725	1072
Kojto	122:f9eeca106725	1073	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Kojto	122:f9eeca106725	1074	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	122:f9eeca106725	1075
Kojto	122:f9eeca106725	1076	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Kojto	122:f9eeca106725	1077	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	122:f9eeca106725	1078
Kojto	122:f9eeca106725	1079	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Kojto	122:f9eeca106725	1080	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	122:f9eeca106725	1081
Kojto	122:f9eeca106725	1082	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Kojto	122:f9eeca106725	1083	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	122:f9eeca106725	1084
Kojto	122:f9eeca106725	1085	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	122:f9eeca106725	1086	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Kojto	122:f9eeca106725	1087
Kojto	122:f9eeca106725	1088	/* TPI DEVTYPE Register Definitions */
Kojto	122:f9eeca106725	1089	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Kojto	122:f9eeca106725	1090	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	122:f9eeca106725	1091
Kojto	122:f9eeca106725	1092	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	122:f9eeca106725	1093	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	122:f9eeca106725	1094
Kojto	122:f9eeca106725	1095	/@}/ /* end of group CMSIS_TPI */
Kojto	122:f9eeca106725	1096
Kojto	122:f9eeca106725	1097
Kojto	122:f9eeca106725	1098	#if (__MPU_PRESENT == 1)
Kojto	122:f9eeca106725	1099	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1100	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	122:f9eeca106725	1101	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	122:f9eeca106725	1102	@{
Kojto	122:f9eeca106725	1103	*/
Kojto	122:f9eeca106725	1104
Kojto	122:f9eeca106725	1105	/** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto	122:f9eeca106725	1106	*/
Kojto	122:f9eeca106725	1107	typedef struct
Kojto	122:f9eeca106725	1108	{
Kojto	122:f9eeca106725	1109	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	122:f9eeca106725	1110	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	122:f9eeca106725	1111	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Kojto	122:f9eeca106725	1112	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	122:f9eeca106725	1113	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Kojto	122:f9eeca106725	1114	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Kojto	122:f9eeca106725	1115	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1116	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Kojto	122:f9eeca106725	1117	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1118	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Kojto	122:f9eeca106725	1119	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1120	} MPU_Type;
Kojto	122:f9eeca106725	1121
Kojto	122:f9eeca106725	1122	/* MPU Type Register */
Kojto	122:f9eeca106725	1123	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Kojto	122:f9eeca106725	1124	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	122:f9eeca106725	1125
Kojto	122:f9eeca106725	1126	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Kojto	122:f9eeca106725	1127	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	122:f9eeca106725	1128
Kojto	122:f9eeca106725	1129	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	122:f9eeca106725	1130	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Kojto	122:f9eeca106725	1131
Kojto	122:f9eeca106725	1132	/* MPU Control Register */
Kojto	122:f9eeca106725	1133	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Kojto	122:f9eeca106725	1134	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	122:f9eeca106725	1135
Kojto	122:f9eeca106725	1136	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Kojto	122:f9eeca106725	1137	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	122:f9eeca106725	1138
Kojto	122:f9eeca106725	1139	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	122:f9eeca106725	1140	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Kojto	122:f9eeca106725	1141
Kojto	122:f9eeca106725	1142	/* MPU Region Number Register */
Kojto	122:f9eeca106725	1143	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	122:f9eeca106725	1144	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Kojto	122:f9eeca106725	1145
Kojto	122:f9eeca106725	1146	/* MPU Region Base Address Register */
Kojto	122:f9eeca106725	1147	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Kojto	122:f9eeca106725	1148	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	122:f9eeca106725	1149
Kojto	122:f9eeca106725	1150	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Kojto	122:f9eeca106725	1151	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Kojto	122:f9eeca106725	1152
Kojto	122:f9eeca106725	1153	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	122:f9eeca106725	1154	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Kojto	122:f9eeca106725	1155
Kojto	122:f9eeca106725	1156	/* MPU Region Attribute and Size Register */
Kojto	122:f9eeca106725	1157	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Kojto	122:f9eeca106725	1158	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Kojto	122:f9eeca106725	1159
Kojto	122:f9eeca106725	1160	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Kojto	122:f9eeca106725	1161	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Kojto	122:f9eeca106725	1162
Kojto	122:f9eeca106725	1163	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Kojto	122:f9eeca106725	1164	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Kojto	122:f9eeca106725	1165
Kojto	122:f9eeca106725	1166	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Kojto	122:f9eeca106725	1167	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Kojto	122:f9eeca106725	1168
Kojto	122:f9eeca106725	1169	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Kojto	122:f9eeca106725	1170	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Kojto	122:f9eeca106725	1171
Kojto	122:f9eeca106725	1172	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Kojto	122:f9eeca106725	1173	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Kojto	122:f9eeca106725	1174
Kojto	122:f9eeca106725	1175	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Kojto	122:f9eeca106725	1176	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Kojto	122:f9eeca106725	1177
Kojto	122:f9eeca106725	1178	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Kojto	122:f9eeca106725	1179	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Kojto	122:f9eeca106725	1180
Kojto	122:f9eeca106725	1181	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Kojto	122:f9eeca106725	1182	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Kojto	122:f9eeca106725	1183
Kojto	122:f9eeca106725	1184	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	122:f9eeca106725	1185	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Kojto	122:f9eeca106725	1186
Kojto	122:f9eeca106725	1187	/@} end of group CMSIS_MPU /
Kojto	122:f9eeca106725	1188	#endif
Kojto	122:f9eeca106725	1189
Kojto	122:f9eeca106725	1190
Kojto	122:f9eeca106725	1191	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1192	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	122:f9eeca106725	1193	\brief Type definitions for the Core Debug Registers
Kojto	122:f9eeca106725	1194	@{
Kojto	122:f9eeca106725	1195	*/
Kojto	122:f9eeca106725	1196
Kojto	122:f9eeca106725	1197	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	122:f9eeca106725	1198	*/
Kojto	122:f9eeca106725	1199	typedef struct
Kojto	122:f9eeca106725	1200	{
Kojto	122:f9eeca106725	1201	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	122:f9eeca106725	1202	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	122:f9eeca106725	1203	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	122:f9eeca106725	1204	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	122:f9eeca106725	1205	} CoreDebug_Type;
Kojto	122:f9eeca106725	1206
Kojto	122:f9eeca106725	1207	/* Debug Halting Control and Status Register */
Kojto	122:f9eeca106725	1208	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	122:f9eeca106725	1209	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	122:f9eeca106725	1210
Kojto	122:f9eeca106725	1211	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	122:f9eeca106725	1212	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	122:f9eeca106725	1213
Kojto	122:f9eeca106725	1214	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	122:f9eeca106725	1215	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	122:f9eeca106725	1216
Kojto	122:f9eeca106725	1217	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	122:f9eeca106725	1218	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	122:f9eeca106725	1219
Kojto	122:f9eeca106725	1220	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	122:f9eeca106725	1221	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	122:f9eeca106725	1222
Kojto	122:f9eeca106725	1223	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Kojto	122:f9eeca106725	1224	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	122:f9eeca106725	1225
Kojto	122:f9eeca106725	1226	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	122:f9eeca106725	1227	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	122:f9eeca106725	1228
Kojto	122:f9eeca106725	1229	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	122:f9eeca106725	1230	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	122:f9eeca106725	1231
Kojto	122:f9eeca106725	1232	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	122:f9eeca106725	1233	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	122:f9eeca106725	1234
Kojto	122:f9eeca106725	1235	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Kojto	122:f9eeca106725	1236	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	122:f9eeca106725	1237
Kojto	122:f9eeca106725	1238	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Kojto	122:f9eeca106725	1239	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	122:f9eeca106725	1240
Kojto	122:f9eeca106725	1241	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	122:f9eeca106725	1242	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	122:f9eeca106725	1243
Kojto	122:f9eeca106725	1244	/* Debug Core Register Selector Register */
Kojto	122:f9eeca106725	1245	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Kojto	122:f9eeca106725	1246	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	122:f9eeca106725	1247
Kojto	122:f9eeca106725	1248	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	122:f9eeca106725	1249	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	122:f9eeca106725	1250
Kojto	122:f9eeca106725	1251	/* Debug Exception and Monitor Control Register */
Kojto	122:f9eeca106725	1252	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Kojto	122:f9eeca106725	1253	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	122:f9eeca106725	1254
Kojto	122:f9eeca106725	1255	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	122:f9eeca106725	1256	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	122:f9eeca106725	1257
Kojto	122:f9eeca106725	1258	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	122:f9eeca106725	1259	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	122:f9eeca106725	1260
Kojto	122:f9eeca106725	1261	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	122:f9eeca106725	1262	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	122:f9eeca106725	1263
Kojto	122:f9eeca106725	1264	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Kojto	122:f9eeca106725	1265	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	122:f9eeca106725	1266
Kojto	122:f9eeca106725	1267	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	122:f9eeca106725	1268	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	122:f9eeca106725	1269
Kojto	122:f9eeca106725	1270	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	122:f9eeca106725	1271	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	122:f9eeca106725	1272
Kojto	122:f9eeca106725	1273	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	122:f9eeca106725	1274	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	122:f9eeca106725	1275
Kojto	122:f9eeca106725	1276	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	122:f9eeca106725	1277	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	122:f9eeca106725	1278
Kojto	122:f9eeca106725	1279	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	122:f9eeca106725	1280	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	122:f9eeca106725	1281
Kojto	122:f9eeca106725	1282	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	122:f9eeca106725	1283	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	122:f9eeca106725	1284
Kojto	122:f9eeca106725	1285	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	122:f9eeca106725	1286	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	122:f9eeca106725	1287
Kojto	122:f9eeca106725	1288	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	122:f9eeca106725	1289	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	122:f9eeca106725	1290
Kojto	122:f9eeca106725	1291	/@} end of group CMSIS_CoreDebug /
Kojto	122:f9eeca106725	1292
Kojto	122:f9eeca106725	1293
Kojto	122:f9eeca106725	1294	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1295	\defgroup CMSIS_core_base Core Definitions
Kojto	122:f9eeca106725	1296	\brief Definitions for base addresses, unions, and structures.
Kojto	122:f9eeca106725	1297	@{
Kojto	122:f9eeca106725	1298	*/
Kojto	122:f9eeca106725	1299
Kojto	122:f9eeca106725	1300	/* Memory mapping of Cortex-M3 Hardware */
Kojto	122:f9eeca106725	1301	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	122:f9eeca106725	1302	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	122:f9eeca106725	1303	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	122:f9eeca106725	1304	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	122:f9eeca106725	1305	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	122:f9eeca106725	1306	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	122:f9eeca106725	1307	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	122:f9eeca106725	1308	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	122:f9eeca106725	1309
Kojto	122:f9eeca106725	1310	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	122:f9eeca106725	1311	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	122:f9eeca106725	1312	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	122:f9eeca106725	1313	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	122:f9eeca106725	1314	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	122:f9eeca106725	1315	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	122:f9eeca106725	1316	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	122:f9eeca106725	1317	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Kojto	122:f9eeca106725	1318
Kojto	122:f9eeca106725	1319	#if (__MPU_PRESENT == 1)
Kojto	122:f9eeca106725	1320	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	122:f9eeca106725	1321	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	122:f9eeca106725	1322	#endif
Kojto	122:f9eeca106725	1323
Kojto	122:f9eeca106725	1324	/@} /
Kojto	122:f9eeca106725	1325
Kojto	122:f9eeca106725	1326
Kojto	122:f9eeca106725	1327
Kojto	122:f9eeca106725	1328	/*******************************************************************************
Kojto	122:f9eeca106725	1329	* Hardware Abstraction Layer
Kojto	122:f9eeca106725	1330	Core Function Interface contains:
Kojto	122:f9eeca106725	1331	- Core NVIC Functions
Kojto	122:f9eeca106725	1332	- Core SysTick Functions
Kojto	122:f9eeca106725	1333	- Core Debug Functions
Kojto	122:f9eeca106725	1334	- Core Register Access Functions
Kojto	122:f9eeca106725	1335	******************************************************************************/
Kojto	122:f9eeca106725	1336	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	122:f9eeca106725	1337	*/
Kojto	122:f9eeca106725	1338
Kojto	122:f9eeca106725	1339
Kojto	122:f9eeca106725	1340
Kojto	122:f9eeca106725	1341	/* ########################## NVIC functions #################################### */
Kojto	122:f9eeca106725	1342	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1343	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	122:f9eeca106725	1344	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	122:f9eeca106725	1345	@{
Kojto	122:f9eeca106725	1346	*/
Kojto	122:f9eeca106725	1347
<>	127:25aea2a3f4e3	1348	#ifdef CMSIS_NVIC_VIRTUAL
<>	127:25aea2a3f4e3	1349	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<>	127:25aea2a3f4e3	1350	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<>	127:25aea2a3f4e3	1351	#endif
<>	127:25aea2a3f4e3	1352	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<>	127:25aea2a3f4e3	1353	#else
<>	127:25aea2a3f4e3	1354	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<>	127:25aea2a3f4e3	1355	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<>	127:25aea2a3f4e3	1356	#define NVIC_EnableIRQ __NVIC_EnableIRQ
<>	127:25aea2a3f4e3	1357	#define NVIC_DisableIRQ __NVIC_DisableIRQ
<>	127:25aea2a3f4e3	1358	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<>	127:25aea2a3f4e3	1359	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<>	127:25aea2a3f4e3	1360	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<>	127:25aea2a3f4e3	1361	#define NVIC_GetActive __NVIC_GetActive
<>	127:25aea2a3f4e3	1362	#define NVIC_SetPriority __NVIC_SetPriority
<>	127:25aea2a3f4e3	1363	#define NVIC_GetPriority __NVIC_GetPriority
<>	128:9bcdf88f62b0	1364	#define NVIC_SystemReset __NVIC_SystemReset
<>	127:25aea2a3f4e3	1365	#endif /* CMSIS_NVIC_VIRTUAL */
<>	127:25aea2a3f4e3	1366
<>	127:25aea2a3f4e3	1367	#ifdef CMSIS_VECTAB_VIRTUAL
<>	127:25aea2a3f4e3	1368	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<>	127:25aea2a3f4e3	1369	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<>	127:25aea2a3f4e3	1370	#endif
<>	127:25aea2a3f4e3	1371	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<>	127:25aea2a3f4e3	1372	#else
<>	127:25aea2a3f4e3	1373	#define NVIC_SetVector __NVIC_SetVector
<>	127:25aea2a3f4e3	1374	#define NVIC_GetVector __NVIC_GetVector
<>	127:25aea2a3f4e3	1375	#endif /* CMSIS_VECTAB_VIRTUAL */
<>	127:25aea2a3f4e3	1376
Kojto	122:f9eeca106725	1377	/** \brief Set Priority Grouping
Kojto	122:f9eeca106725	1378
Kojto	122:f9eeca106725	1379	The function sets the priority grouping field using the required unlock sequence.
Kojto	122:f9eeca106725	1380	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	122:f9eeca106725	1381	Only values from 0..7 are used.
Kojto	122:f9eeca106725	1382	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	122:f9eeca106725	1384
Kojto	122:f9eeca106725	1385	\param [in] PriorityGroup Priority grouping field.
Kojto	122:f9eeca106725	1386	*/
<>	127:25aea2a3f4e3	1387	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	122:f9eeca106725	1388	{
Kojto	122:f9eeca106725	1389	uint32_t reg_value;
Kojto	122:f9eeca106725	1390	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1391
Kojto	122:f9eeca106725	1392	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	122:f9eeca106725	1393	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	122:f9eeca106725	1394	reg_value = (reg_value \|
Kojto	122:f9eeca106725	1395	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	122:f9eeca106725	1396	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto	122:f9eeca106725	1397	SCB->AIRCR = reg_value;
Kojto	122:f9eeca106725	1398	}
Kojto	122:f9eeca106725	1399
Kojto	122:f9eeca106725	1400
Kojto	122:f9eeca106725	1401	/** \brief Get Priority Grouping
Kojto	122:f9eeca106725	1402
Kojto	122:f9eeca106725	1403	The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	122:f9eeca106725	1404
Kojto	122:f9eeca106725	1405	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	122:f9eeca106725	1406	*/
<>	127:25aea2a3f4e3	1407	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Kojto	122:f9eeca106725	1408	{
Kojto	122:f9eeca106725	1409	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto	122:f9eeca106725	1410	}
Kojto	122:f9eeca106725	1411
Kojto	122:f9eeca106725	1412
Kojto	122:f9eeca106725	1413	/** \brief Enable External Interrupt
Kojto	122:f9eeca106725	1414
Kojto	122:f9eeca106725	1415	The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto	122:f9eeca106725	1416
Kojto	122:f9eeca106725	1417	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1418	*/
<>	127:25aea2a3f4e3	1419	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1420	{
Kojto	122:f9eeca106725	1421	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1422	}
Kojto	122:f9eeca106725	1423
Kojto	122:f9eeca106725	1424
Kojto	122:f9eeca106725	1425	/** \brief Disable External Interrupt
Kojto	122:f9eeca106725	1426
Kojto	122:f9eeca106725	1427	The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto	122:f9eeca106725	1428
Kojto	122:f9eeca106725	1429	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1430	*/
<>	127:25aea2a3f4e3	1431	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1432	{
Kojto	122:f9eeca106725	1433	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	131:faff56e089b2	1434	__DSB();
<>	131:faff56e089b2	1435	__ISB();
Kojto	122:f9eeca106725	1436	}
Kojto	122:f9eeca106725	1437
Kojto	122:f9eeca106725	1438
Kojto	122:f9eeca106725	1439	/** \brief Get Pending Interrupt
Kojto	122:f9eeca106725	1440
Kojto	122:f9eeca106725	1441	The function reads the pending register in the NVIC and returns the pending bit
Kojto	122:f9eeca106725	1442	for the specified interrupt.
Kojto	122:f9eeca106725	1443
Kojto	122:f9eeca106725	1444	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1445
Kojto	122:f9eeca106725	1446	\return 0 Interrupt status is not pending.
Kojto	122:f9eeca106725	1447	\return 1 Interrupt status is pending.
Kojto	122:f9eeca106725	1448	*/
<>	127:25aea2a3f4e3	1449	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1450	{
Kojto	122:f9eeca106725	1451	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	122:f9eeca106725	1452	}
Kojto	122:f9eeca106725	1453
Kojto	122:f9eeca106725	1454
Kojto	122:f9eeca106725	1455	/** \brief Set Pending Interrupt
Kojto	122:f9eeca106725	1456
Kojto	122:f9eeca106725	1457	The function sets the pending bit of an external interrupt.
Kojto	122:f9eeca106725	1458
Kojto	122:f9eeca106725	1459	\param [in] IRQn Interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1460	*/
<>	127:25aea2a3f4e3	1461	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1462	{
Kojto	122:f9eeca106725	1463	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1464	}
Kojto	122:f9eeca106725	1465
Kojto	122:f9eeca106725	1466
Kojto	122:f9eeca106725	1467	/** \brief Clear Pending Interrupt
Kojto	122:f9eeca106725	1468
Kojto	122:f9eeca106725	1469	The function clears the pending bit of an external interrupt.
Kojto	122:f9eeca106725	1470
Kojto	122:f9eeca106725	1471	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1472	*/
<>	127:25aea2a3f4e3	1473	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1474	{
Kojto	122:f9eeca106725	1475	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1476	}
Kojto	122:f9eeca106725	1477
Kojto	122:f9eeca106725	1478
Kojto	122:f9eeca106725	1479	/** \brief Get Active Interrupt
Kojto	122:f9eeca106725	1480
Kojto	122:f9eeca106725	1481	The function reads the active register in NVIC and returns the active bit.
Kojto	122:f9eeca106725	1482
Kojto	122:f9eeca106725	1483	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1484
Kojto	122:f9eeca106725	1485	\return 0 Interrupt status is not active.
Kojto	122:f9eeca106725	1486	\return 1 Interrupt status is active.
Kojto	122:f9eeca106725	1487	*/
<>	127:25aea2a3f4e3	1488	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1489	{
Kojto	122:f9eeca106725	1490	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	122:f9eeca106725	1491	}
Kojto	122:f9eeca106725	1492
Kojto	122:f9eeca106725	1493
Kojto	122:f9eeca106725	1494	/** \brief Set Interrupt Priority
Kojto	122:f9eeca106725	1495
Kojto	122:f9eeca106725	1496	The function sets the priority of an interrupt.
Kojto	122:f9eeca106725	1497
Kojto	122:f9eeca106725	1498	\note The priority cannot be set for every core interrupt.
Kojto	122:f9eeca106725	1499
Kojto	122:f9eeca106725	1500	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1501	\param [in] priority Priority to set.
Kojto	122:f9eeca106725	1502	*/
<>	127:25aea2a3f4e3	1503	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	122:f9eeca106725	1504	{
Kojto	122:f9eeca106725	1505	if((int32_t)IRQn < 0) {
Kojto	122:f9eeca106725	1506	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	122:f9eeca106725	1507	}
Kojto	122:f9eeca106725	1508	else {
Kojto	122:f9eeca106725	1509	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	122:f9eeca106725	1510	}
Kojto	122:f9eeca106725	1511	}
Kojto	122:f9eeca106725	1512
Kojto	122:f9eeca106725	1513
Kojto	122:f9eeca106725	1514	/** \brief Get Interrupt Priority
Kojto	122:f9eeca106725	1515
Kojto	122:f9eeca106725	1516	The function reads the priority of an interrupt. The interrupt
Kojto	122:f9eeca106725	1517	number can be positive to specify an external (device specific)
Kojto	122:f9eeca106725	1518	interrupt, or negative to specify an internal (core) interrupt.
Kojto	122:f9eeca106725	1519
Kojto	122:f9eeca106725	1520
Kojto	122:f9eeca106725	1521	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1522	\return Interrupt Priority. Value is aligned automatically to the implemented
Kojto	122:f9eeca106725	1523	priority bits of the microcontroller.
Kojto	122:f9eeca106725	1524	*/
<>	127:25aea2a3f4e3	1525	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1526	{
Kojto	122:f9eeca106725	1527
Kojto	122:f9eeca106725	1528	if((int32_t)IRQn < 0) {
Kojto	122:f9eeca106725	1529	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	122:f9eeca106725	1530	}
Kojto	122:f9eeca106725	1531	else {
Kojto	122:f9eeca106725	1532	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	122:f9eeca106725	1533	}
Kojto	122:f9eeca106725	1534	}
Kojto	122:f9eeca106725	1535
Kojto	122:f9eeca106725	1536
Kojto	122:f9eeca106725	1537	/** \brief Encode Priority
Kojto	122:f9eeca106725	1538
Kojto	122:f9eeca106725	1539	The function encodes the priority for an interrupt with the given priority group,
Kojto	122:f9eeca106725	1540	preemptive priority value, and subpriority value.
Kojto	122:f9eeca106725	1541	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1542	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	122:f9eeca106725	1543
Kojto	122:f9eeca106725	1544	\param [in] PriorityGroup Used priority group.
Kojto	122:f9eeca106725	1545	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	122:f9eeca106725	1546	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	122:f9eeca106725	1547	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	122:f9eeca106725	1548	*/
Kojto	122:f9eeca106725	1549	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	122:f9eeca106725	1550	{
Kojto	122:f9eeca106725	1551	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1552	uint32_t PreemptPriorityBits;
Kojto	122:f9eeca106725	1553	uint32_t SubPriorityBits;
Kojto	122:f9eeca106725	1554
Kojto	122:f9eeca106725	1555	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	122:f9eeca106725	1556	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	122:f9eeca106725	1557
Kojto	122:f9eeca106725	1558	return (
Kojto	122:f9eeca106725	1559	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	122:f9eeca106725	1560	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto	122:f9eeca106725	1561	);
Kojto	122:f9eeca106725	1562	}
Kojto	122:f9eeca106725	1563
Kojto	122:f9eeca106725	1564
Kojto	122:f9eeca106725	1565	/** \brief Decode Priority
Kojto	122:f9eeca106725	1566
Kojto	122:f9eeca106725	1567	The function decodes an interrupt priority value with a given priority group to
Kojto	122:f9eeca106725	1568	preemptive priority value and subpriority value.
Kojto	122:f9eeca106725	1569	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1570	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto	122:f9eeca106725	1571
Kojto	122:f9eeca106725	1572	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	122:f9eeca106725	1573	\param [in] PriorityGroup Used priority group.
Kojto	122:f9eeca106725	1574	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	122:f9eeca106725	1575	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	122:f9eeca106725	1576	*/
Kojto	122:f9eeca106725	1577	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto	122:f9eeca106725	1578	{
Kojto	122:f9eeca106725	1579	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1580	uint32_t PreemptPriorityBits;
Kojto	122:f9eeca106725	1581	uint32_t SubPriorityBits;
Kojto	122:f9eeca106725	1582
Kojto	122:f9eeca106725	1583	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	122:f9eeca106725	1584	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	122:f9eeca106725	1585
Kojto	122:f9eeca106725	1586	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	122:f9eeca106725	1587	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto	122:f9eeca106725	1588	}
Kojto	122:f9eeca106725	1589
Kojto	122:f9eeca106725	1590
Kojto	122:f9eeca106725	1591	/** \brief System Reset
Kojto	122:f9eeca106725	1592
Kojto	122:f9eeca106725	1593	The function initiates a system reset request to reset the MCU.
Kojto	122:f9eeca106725	1594	*/
<>	128:9bcdf88f62b0	1595	__STATIC_INLINE void __NVIC_SystemReset(void)
Kojto	122:f9eeca106725	1596	{
Kojto	122:f9eeca106725	1597	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	122:f9eeca106725	1598	buffered write are completed before reset */
Kojto	122:f9eeca106725	1599	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	122:f9eeca106725	1600	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	122:f9eeca106725	1601	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	122:f9eeca106725	1602	__DSB(); /* Ensure completion of memory access */
Kojto	122:f9eeca106725	1603	while(1) { __NOP(); } /* wait until reset */
Kojto	122:f9eeca106725	1604	}
Kojto	122:f9eeca106725	1605
Kojto	122:f9eeca106725	1606	/@} end of CMSIS_Core_NVICFunctions /
Kojto	122:f9eeca106725	1607
Kojto	122:f9eeca106725	1608
Kojto	122:f9eeca106725	1609
Kojto	122:f9eeca106725	1610	/* ################################## SysTick function ############################################ */
Kojto	122:f9eeca106725	1611	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1612	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	122:f9eeca106725	1613	\brief Functions that configure the System.
Kojto	122:f9eeca106725	1614	@{
Kojto	122:f9eeca106725	1615	*/
Kojto	122:f9eeca106725	1616
Kojto	122:f9eeca106725	1617	#if (__Vendor_SysTickConfig == 0)
Kojto	122:f9eeca106725	1618
Kojto	122:f9eeca106725	1619	/** \brief System Tick Configuration
Kojto	122:f9eeca106725	1620
Kojto	122:f9eeca106725	1621	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	122:f9eeca106725	1622	Counter is in free running mode to generate periodic interrupts.
Kojto	122:f9eeca106725	1623
Kojto	122:f9eeca106725	1624	\param [in] ticks Number of ticks between two interrupts.
Kojto	122:f9eeca106725	1625
Kojto	122:f9eeca106725	1626	\return 0 Function succeeded.
Kojto	122:f9eeca106725	1627	\return 1 Function failed.
Kojto	122:f9eeca106725	1628
Kojto	122:f9eeca106725	1629	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	122:f9eeca106725	1630	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	122:f9eeca106725	1631	must contain a vendor-specific implementation of this function.
Kojto	122:f9eeca106725	1632
Kojto	122:f9eeca106725	1633	*/
Kojto	122:f9eeca106725	1634	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	122:f9eeca106725	1635	{
Kojto	122:f9eeca106725	1636	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto	122:f9eeca106725	1637
Kojto	122:f9eeca106725	1638	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	122:f9eeca106725	1639	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	122:f9eeca106725	1640	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	122:f9eeca106725	1641	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	122:f9eeca106725	1642	SysTick_CTRL_TICKINT_Msk \|
Kojto	122:f9eeca106725	1643	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	122:f9eeca106725	1644	return (0UL); /* Function successful */
Kojto	122:f9eeca106725	1645	}
Kojto	122:f9eeca106725	1646
Kojto	122:f9eeca106725	1647	#endif
Kojto	122:f9eeca106725	1648
Kojto	122:f9eeca106725	1649	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	122:f9eeca106725	1650
Kojto	122:f9eeca106725	1651
Kojto	122:f9eeca106725	1652
Kojto	122:f9eeca106725	1653	/* ##################################### Debug In/Output function ########################################### */
Kojto	122:f9eeca106725	1654	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1655	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	122:f9eeca106725	1656	\brief Functions that access the ITM debug interface.
Kojto	122:f9eeca106725	1657	@{
Kojto	122:f9eeca106725	1658	*/
Kojto	122:f9eeca106725	1659
Kojto	122:f9eeca106725	1660	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	122:f9eeca106725	1661	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	122:f9eeca106725	1662
Kojto	122:f9eeca106725	1663
Kojto	122:f9eeca106725	1664	/** \brief ITM Send Character
Kojto	122:f9eeca106725	1665
Kojto	122:f9eeca106725	1666	The function transmits a character via the ITM channel 0, and
Kojto	122:f9eeca106725	1667	\li Just returns when no debugger is connected that has booked the output.
Kojto	122:f9eeca106725	1668	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	122:f9eeca106725	1669
Kojto	122:f9eeca106725	1670	\param [in] ch Character to transmit.
Kojto	122:f9eeca106725	1671
Kojto	122:f9eeca106725	1672	\returns Character to transmit.
Kojto	122:f9eeca106725	1673	*/
Kojto	122:f9eeca106725	1674	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	122:f9eeca106725	1675	{
Kojto	122:f9eeca106725	1676	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	122:f9eeca106725	1677	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto	122:f9eeca106725	1678	{
Kojto	122:f9eeca106725	1679	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	122:f9eeca106725	1680	ITM->PORT[0].u8 = (uint8_t)ch;
Kojto	122:f9eeca106725	1681	}
Kojto	122:f9eeca106725	1682	return (ch);
Kojto	122:f9eeca106725	1683	}
Kojto	122:f9eeca106725	1684
Kojto	122:f9eeca106725	1685
Kojto	122:f9eeca106725	1686	/** \brief ITM Receive Character
Kojto	122:f9eeca106725	1687
Kojto	122:f9eeca106725	1688	The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	122:f9eeca106725	1689
Kojto	122:f9eeca106725	1690	\return Received character.
Kojto	122:f9eeca106725	1691	\return -1 No character pending.
Kojto	122:f9eeca106725	1692	*/
Kojto	122:f9eeca106725	1693	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto	122:f9eeca106725	1694	int32_t ch = -1; /* no character available */
Kojto	122:f9eeca106725	1695
Kojto	122:f9eeca106725	1696	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto	122:f9eeca106725	1697	ch = ITM_RxBuffer;
Kojto	122:f9eeca106725	1698	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	122:f9eeca106725	1699	}
Kojto	122:f9eeca106725	1700
Kojto	122:f9eeca106725	1701	return (ch);
Kojto	122:f9eeca106725	1702	}
Kojto	122:f9eeca106725	1703
Kojto	122:f9eeca106725	1704
Kojto	122:f9eeca106725	1705	/** \brief ITM Check Character
Kojto	122:f9eeca106725	1706
Kojto	122:f9eeca106725	1707	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	122:f9eeca106725	1708
Kojto	122:f9eeca106725	1709	\return 0 No character available.
Kojto	122:f9eeca106725	1710	\return 1 Character available.
Kojto	122:f9eeca106725	1711	*/
Kojto	122:f9eeca106725	1712	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto	122:f9eeca106725	1713
Kojto	122:f9eeca106725	1714	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto	122:f9eeca106725	1715	return (0); /* no character available */
Kojto	122:f9eeca106725	1716	} else {
Kojto	122:f9eeca106725	1717	return (1); /* character available */
Kojto	122:f9eeca106725	1718	}
Kojto	122:f9eeca106725	1719	}
Kojto	122:f9eeca106725	1720
Kojto	122:f9eeca106725	1721	/@} end of CMSIS_core_DebugFunctions /
Kojto	122:f9eeca106725	1722
Kojto	122:f9eeca106725	1723
Kojto	122:f9eeca106725	1724
Kojto	122:f9eeca106725	1725
Kojto	122:f9eeca106725	1726	#ifdef __cplusplus
Kojto	122:f9eeca106725	1727	}
Kojto	122:f9eeca106725	1728	#endif
Kojto	122:f9eeca106725	1729
Kojto	122:f9eeca106725	1730	#endif /* __CORE_CM3_H_DEPENDANT */
Kojto	122:f9eeca106725	1731
Kojto	122:f9eeca106725	1732	#endif /* __CMSIS_GENERIC */