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TARGET_NUCLEO_F446RE/core_cm0plus.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 106:ba1f97679dad 1 /**************************************************************************//**
Kojto 106:ba1f97679dad 2 * @file core_cm0plus.h
Kojto 106:ba1f97679dad 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 106:ba1f97679dad 6 *
Kojto 106:ba1f97679dad 7 * @note
Kojto 106:ba1f97679dad 8 *
Kojto 106:ba1f97679dad 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 106:ba1f97679dad 11
Kojto 106:ba1f97679dad 12 All rights reserved.
Kojto 106:ba1f97679dad 13 Redistribution and use in source and binary forms, with or without
Kojto 106:ba1f97679dad 14 modification, are permitted provided that the following conditions are met:
Kojto 106:ba1f97679dad 15 - Redistributions of source code must retain the above copyright
Kojto 106:ba1f97679dad 16 notice, this list of conditions and the following disclaimer.
Kojto 106:ba1f97679dad 17 - Redistributions in binary form must reproduce the above copyright
Kojto 106:ba1f97679dad 18 notice, this list of conditions and the following disclaimer in the
Kojto 106:ba1f97679dad 19 documentation and/or other materials provided with the distribution.
Kojto 106:ba1f97679dad 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 106:ba1f97679dad 21 to endorse or promote products derived from this software without
Kojto 106:ba1f97679dad 22 specific prior written permission.
Kojto 106:ba1f97679dad 23 *
Kojto 106:ba1f97679dad 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 106:ba1f97679dad 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 106:ba1f97679dad 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 106:ba1f97679dad 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 106:ba1f97679dad 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 106:ba1f97679dad 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 106:ba1f97679dad 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 106:ba1f97679dad 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 106:ba1f97679dad 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 106:ba1f97679dad 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 106:ba1f97679dad 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 106:ba1f97679dad 35 ---------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 36
Kojto 106:ba1f97679dad 37
Kojto 106:ba1f97679dad 38 #if defined ( __ICCARM__ )
Kojto 106:ba1f97679dad 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 106:ba1f97679dad 40 #endif
Kojto 106:ba1f97679dad 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 106:ba1f97679dad 45 #ifdef __cplusplus
Kojto 106:ba1f97679dad 46 extern "C" {
Kojto 106:ba1f97679dad 47 #endif
Kojto 106:ba1f97679dad 48
Kojto 106:ba1f97679dad 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 106:ba1f97679dad 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 106:ba1f97679dad 51
Kojto 106:ba1f97679dad 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 106:ba1f97679dad 53 Function definitions in header files are used to allow 'inlining'.
Kojto 106:ba1f97679dad 54
Kojto 106:ba1f97679dad 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 106:ba1f97679dad 56 Unions are used for effective representation of core registers.
Kojto 106:ba1f97679dad 57
Kojto 106:ba1f97679dad 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 106:ba1f97679dad 59 Function-like macros are used to allow more efficient code.
Kojto 106:ba1f97679dad 60 */
Kojto 106:ba1f97679dad 61
Kojto 106:ba1f97679dad 62
Kojto 106:ba1f97679dad 63 /*******************************************************************************
Kojto 106:ba1f97679dad 64 * CMSIS definitions
Kojto 106:ba1f97679dad 65 ******************************************************************************/
Kojto 106:ba1f97679dad 66 /** \ingroup Cortex-M0+
Kojto 106:ba1f97679dad 67 @{
Kojto 106:ba1f97679dad 68 */
Kojto 106:ba1f97679dad 69
Kojto 106:ba1f97679dad 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 106:ba1f97679dad 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 106:ba1f97679dad 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 106:ba1f97679dad 75
Kojto 106:ba1f97679dad 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 106:ba1f97679dad 77
Kojto 106:ba1f97679dad 78
Kojto 106:ba1f97679dad 79 #if defined ( __CC_ARM )
Kojto 106:ba1f97679dad 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 106:ba1f97679dad 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 106:ba1f97679dad 82 #define __STATIC_INLINE static __inline
Kojto 106:ba1f97679dad 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 106:ba1f97679dad 89 #elif defined ( __ICCARM__ )
Kojto 106:ba1f97679dad 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 106:ba1f97679dad 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 106:ba1f97679dad 92 #define __STATIC_INLINE static inline
Kojto 106:ba1f97679dad 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 106:ba1f97679dad 96 #define __STATIC_INLINE static inline
Kojto 106:ba1f97679dad 97
Kojto 106:ba1f97679dad 98 #elif defined ( __TASKING__ )
Kojto 106:ba1f97679dad 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 106:ba1f97679dad 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 106:ba1f97679dad 101 #define __STATIC_INLINE static inline
Kojto 106:ba1f97679dad 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 106:ba1f97679dad 109 #endif
Kojto 106:ba1f97679dad 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 106:ba1f97679dad 113 */
Kojto 106:ba1f97679dad 114 #define __FPU_USED 0
Kojto 106:ba1f97679dad 115
Kojto 106:ba1f97679dad 116 #if defined ( __CC_ARM )
Kojto 106:ba1f97679dad 117 #if defined __TARGET_FPU_VFP
Kojto 106:ba1f97679dad 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 106:ba1f97679dad 119 #endif
Kojto 106:ba1f97679dad 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 106:ba1f97679dad 126 #elif defined ( __ICCARM__ )
Kojto 106:ba1f97679dad 127 #if defined __ARMVFP__
Kojto 106:ba1f97679dad 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 106:ba1f97679dad 129 #endif
Kojto 106:ba1f97679dad 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 106:ba1f97679dad 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 106:ba1f97679dad 134 #endif
Kojto 106:ba1f97679dad 135
Kojto 106:ba1f97679dad 136 #elif defined ( __TASKING__ )
Kojto 106:ba1f97679dad 137 #if defined __FPU_VFP__
Kojto 106:ba1f97679dad 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 106:ba1f97679dad 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 106:ba1f97679dad 145 #endif
Kojto 106:ba1f97679dad 146
Kojto 106:ba1f97679dad 147 #include <stdint.h> /* standard types definitions */
Kojto 106:ba1f97679dad 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 106:ba1f97679dad 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 106:ba1f97679dad 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 106:ba1f97679dad 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 106:ba1f97679dad 156
Kojto 106:ba1f97679dad 157 #ifndef __CMSIS_GENERIC
Kojto 106:ba1f97679dad 158
Kojto 106:ba1f97679dad 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 106:ba1f97679dad 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 106:ba1f97679dad 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 106:ba1f97679dad 166 /* check device defines and use defaults */
Kojto 106:ba1f97679dad 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 106:ba1f97679dad 168 #ifndef __CM0PLUS_REV
Kojto 106:ba1f97679dad 169 #define __CM0PLUS_REV 0x0000
Kojto 106:ba1f97679dad 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 106:ba1f97679dad 171 #endif
Kojto 106:ba1f97679dad 172
Kojto 106:ba1f97679dad 173 #ifndef __MPU_PRESENT
Kojto 106:ba1f97679dad 174 #define __MPU_PRESENT 0
Kojto 106:ba1f97679dad 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 106:ba1f97679dad 176 #endif
Kojto 106:ba1f97679dad 177
Kojto 106:ba1f97679dad 178 #ifndef __VTOR_PRESENT
Kojto 106:ba1f97679dad 179 #define __VTOR_PRESENT 0
Kojto 106:ba1f97679dad 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 106:ba1f97679dad 181 #endif
Kojto 106:ba1f97679dad 182
Kojto 106:ba1f97679dad 183 #ifndef __NVIC_PRIO_BITS
Kojto 106:ba1f97679dad 184 #define __NVIC_PRIO_BITS 2
Kojto 106:ba1f97679dad 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 106:ba1f97679dad 186 #endif
Kojto 106:ba1f97679dad 187
Kojto 106:ba1f97679dad 188 #ifndef __Vendor_SysTickConfig
Kojto 106:ba1f97679dad 189 #define __Vendor_SysTickConfig 0
Kojto 106:ba1f97679dad 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 106:ba1f97679dad 191 #endif
Kojto 106:ba1f97679dad 192 #endif
Kojto 106:ba1f97679dad 193
Kojto 106:ba1f97679dad 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 106:ba1f97679dad 195 /**
Kojto 106:ba1f97679dad 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 106:ba1f97679dad 197
Kojto 106:ba1f97679dad 198 <strong>IO Type Qualifiers</strong> are used
Kojto 106:ba1f97679dad 199 \li to specify the access to peripheral variables.
Kojto 106:ba1f97679dad 200 \li for automatic generation of peripheral register debug information.
Kojto 106:ba1f97679dad 201 */
Kojto 106:ba1f97679dad 202 #ifdef __cplusplus
Kojto 106:ba1f97679dad 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 106:ba1f97679dad 204 #else
Kojto 106:ba1f97679dad 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 106:ba1f97679dad 206 #endif
Kojto 106:ba1f97679dad 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 106:ba1f97679dad 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 106:ba1f97679dad 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 106:ba1f97679dad 218 /*@} end of group Cortex-M0+ */
Kojto 106:ba1f97679dad 219
Kojto 106:ba1f97679dad 220
Kojto 106:ba1f97679dad 221
Kojto 106:ba1f97679dad 222 /*******************************************************************************
Kojto 106:ba1f97679dad 223 * Register Abstraction
Kojto 106:ba1f97679dad 224 Core Register contain:
Kojto 106:ba1f97679dad 225 - Core Register
Kojto 106:ba1f97679dad 226 - Core NVIC Register
Kojto 106:ba1f97679dad 227 - Core SCB Register
Kojto 106:ba1f97679dad 228 - Core SysTick Register
Kojto 106:ba1f97679dad 229 - Core MPU Register
Kojto 106:ba1f97679dad 230 ******************************************************************************/
Kojto 106:ba1f97679dad 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 106:ba1f97679dad 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 106:ba1f97679dad 233 */
Kojto 106:ba1f97679dad 234
Kojto 106:ba1f97679dad 235 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 106:ba1f97679dad 237 \brief Core Register type definitions.
Kojto 106:ba1f97679dad 238 @{
Kojto 106:ba1f97679dad 239 */
Kojto 106:ba1f97679dad 240
Kojto 106:ba1f97679dad 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 106:ba1f97679dad 242 */
Kojto 106:ba1f97679dad 243 typedef union
Kojto 106:ba1f97679dad 244 {
Kojto 106:ba1f97679dad 245 struct
Kojto 106:ba1f97679dad 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 106:ba1f97679dad 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 106:ba1f97679dad 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 106:ba1f97679dad 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 106:ba1f97679dad 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 106:ba1f97679dad 252 } b; /*!< Structure used for bit access */
Kojto 106:ba1f97679dad 253 uint32_t w; /*!< Type used for word access */
Kojto 106:ba1f97679dad 254 } APSR_Type;
Kojto 106:ba1f97679dad 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
Kojto 106:ba1f97679dad 269
Kojto 106:ba1f97679dad 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 106:ba1f97679dad 271 */
Kojto 106:ba1f97679dad 272 typedef union
Kojto 106:ba1f97679dad 273 {
Kojto 106:ba1f97679dad 274 struct
Kojto 106:ba1f97679dad 275 {
Kojto 106:ba1f97679dad 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 106:ba1f97679dad 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 106:ba1f97679dad 278 } b; /*!< Structure used for bit access */
Kojto 106:ba1f97679dad 279 uint32_t w; /*!< Type used for word access */
Kojto 106:ba1f97679dad 280 } IPSR_Type;
Kojto 106:ba1f97679dad 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
Kojto 106:ba1f97679dad 286
Kojto 106:ba1f97679dad 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 106:ba1f97679dad 288 */
Kojto 106:ba1f97679dad 289 typedef union
Kojto 106:ba1f97679dad 290 {
Kojto 106:ba1f97679dad 291 struct
Kojto 106:ba1f97679dad 292 {
Kojto 106:ba1f97679dad 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 106:ba1f97679dad 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 106:ba1f97679dad 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 106:ba1f97679dad 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 106:ba1f97679dad 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 106:ba1f97679dad 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 106:ba1f97679dad 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 106:ba1f97679dad 301 } b; /*!< Structure used for bit access */
Kojto 106:ba1f97679dad 302 uint32_t w; /*!< Type used for word access */
Kojto 106:ba1f97679dad 303 } xPSR_Type;
Kojto 106:ba1f97679dad 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
Kojto 106:ba1f97679dad 324
Kojto 106:ba1f97679dad 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 106:ba1f97679dad 326 */
Kojto 106:ba1f97679dad 327 typedef union
Kojto 106:ba1f97679dad 328 {
Kojto 106:ba1f97679dad 329 struct
Kojto 106:ba1f97679dad 330 {
Kojto 106:ba1f97679dad 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 106:ba1f97679dad 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 106:ba1f97679dad 334 } b; /*!< Structure used for bit access */
Kojto 106:ba1f97679dad 335 uint32_t w; /*!< Type used for word access */
Kojto 106:ba1f97679dad 336 } CONTROL_Type;
Kojto 106:ba1f97679dad 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
Kojto 106:ba1f97679dad 345 /*@} end of group CMSIS_CORE */
Kojto 106:ba1f97679dad 346
Kojto 106:ba1f97679dad 347
Kojto 106:ba1f97679dad 348 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 106:ba1f97679dad 350 \brief Type definitions for the NVIC Registers
Kojto 106:ba1f97679dad 351 @{
Kojto 106:ba1f97679dad 352 */
Kojto 106:ba1f97679dad 353
Kojto 106:ba1f97679dad 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 106:ba1f97679dad 355 */
Kojto 106:ba1f97679dad 356 typedef struct
Kojto 106:ba1f97679dad 357 {
Kojto 106:ba1f97679dad 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 106:ba1f97679dad 359 uint32_t RESERVED0[31];
Kojto 106:ba1f97679dad 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 106:ba1f97679dad 361 uint32_t RSERVED1[31];
Kojto 106:ba1f97679dad 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 106:ba1f97679dad 363 uint32_t RESERVED2[31];
Kojto 106:ba1f97679dad 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 106:ba1f97679dad 365 uint32_t RESERVED3[31];
Kojto 106:ba1f97679dad 366 uint32_t RESERVED4[64];
Kojto 106:ba1f97679dad 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 106:ba1f97679dad 368 } NVIC_Type;
Kojto 106:ba1f97679dad 369
Kojto 106:ba1f97679dad 370 /*@} end of group CMSIS_NVIC */
Kojto 106:ba1f97679dad 371
Kojto 106:ba1f97679dad 372
Kojto 106:ba1f97679dad 373 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 106:ba1f97679dad 375 \brief Type definitions for the System Control Block Registers
Kojto 106:ba1f97679dad 376 @{
Kojto 106:ba1f97679dad 377 */
Kojto 106:ba1f97679dad 378
Kojto 106:ba1f97679dad 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 106:ba1f97679dad 380 */
Kojto 106:ba1f97679dad 381 typedef struct
Kojto 106:ba1f97679dad 382 {
Kojto 106:ba1f97679dad 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 106:ba1f97679dad 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 106:ba1f97679dad 385 #if (__VTOR_PRESENT == 1)
Kojto 106:ba1f97679dad 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 106:ba1f97679dad 387 #else
Kojto 106:ba1f97679dad 388 uint32_t RESERVED0;
Kojto 106:ba1f97679dad 389 #endif
Kojto 106:ba1f97679dad 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 106:ba1f97679dad 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 106:ba1f97679dad 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 106:ba1f97679dad 393 uint32_t RESERVED1;
Kojto 106:ba1f97679dad 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 106:ba1f97679dad 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 106:ba1f97679dad 396 } SCB_Type;
Kojto 106:ba1f97679dad 397
Kojto 106:ba1f97679dad 398 /* SCB CPUID Register Definitions */
Kojto 106:ba1f97679dad 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 106:ba1f97679dad 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 106:ba1f97679dad 401
Kojto 106:ba1f97679dad 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 106:ba1f97679dad 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 106:ba1f97679dad 404
Kojto 106:ba1f97679dad 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 106:ba1f97679dad 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 106:ba1f97679dad 407
Kojto 106:ba1f97679dad 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 106:ba1f97679dad 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 106:ba1f97679dad 410
Kojto 106:ba1f97679dad 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 106:ba1f97679dad 413
Kojto 106:ba1f97679dad 414 /* SCB Interrupt Control State Register Definitions */
Kojto 106:ba1f97679dad 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 106:ba1f97679dad 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 106:ba1f97679dad 417
Kojto 106:ba1f97679dad 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 106:ba1f97679dad 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 106:ba1f97679dad 420
Kojto 106:ba1f97679dad 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 106:ba1f97679dad 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 106:ba1f97679dad 423
Kojto 106:ba1f97679dad 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 106:ba1f97679dad 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 106:ba1f97679dad 426
Kojto 106:ba1f97679dad 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 106:ba1f97679dad 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 106:ba1f97679dad 429
Kojto 106:ba1f97679dad 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 106:ba1f97679dad 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 106:ba1f97679dad 432
Kojto 106:ba1f97679dad 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 106:ba1f97679dad 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 106:ba1f97679dad 435
Kojto 106:ba1f97679dad 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 106:ba1f97679dad 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 106:ba1f97679dad 438
Kojto 106:ba1f97679dad 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 106:ba1f97679dad 441
Kojto 106:ba1f97679dad 442 #if (__VTOR_PRESENT == 1)
Kojto 106:ba1f97679dad 443 /* SCB Interrupt Control State Register Definitions */
Kojto 106:ba1f97679dad 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 106:ba1f97679dad 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 106:ba1f97679dad 446 #endif
Kojto 106:ba1f97679dad 447
Kojto 106:ba1f97679dad 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 106:ba1f97679dad 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 106:ba1f97679dad 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 106:ba1f97679dad 451
Kojto 106:ba1f97679dad 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 106:ba1f97679dad 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 106:ba1f97679dad 454
Kojto 106:ba1f97679dad 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 106:ba1f97679dad 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 106:ba1f97679dad 457
Kojto 106:ba1f97679dad 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 106:ba1f97679dad 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 106:ba1f97679dad 460
Kojto 106:ba1f97679dad 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 106:ba1f97679dad 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 106:ba1f97679dad 463
Kojto 106:ba1f97679dad 464 /* SCB System Control Register Definitions */
Kojto 106:ba1f97679dad 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 106:ba1f97679dad 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 106:ba1f97679dad 467
Kojto 106:ba1f97679dad 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 106:ba1f97679dad 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 106:ba1f97679dad 470
Kojto 106:ba1f97679dad 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 106:ba1f97679dad 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 106:ba1f97679dad 473
Kojto 106:ba1f97679dad 474 /* SCB Configuration Control Register Definitions */
Kojto 106:ba1f97679dad 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 106:ba1f97679dad 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 106:ba1f97679dad 477
Kojto 106:ba1f97679dad 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 106:ba1f97679dad 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 106:ba1f97679dad 480
Kojto 106:ba1f97679dad 481 /* SCB System Handler Control and State Register Definitions */
Kojto 106:ba1f97679dad 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 106:ba1f97679dad 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 106:ba1f97679dad 484
Kojto 106:ba1f97679dad 485 /*@} end of group CMSIS_SCB */
Kojto 106:ba1f97679dad 486
Kojto 106:ba1f97679dad 487
Kojto 106:ba1f97679dad 488 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 106:ba1f97679dad 490 \brief Type definitions for the System Timer Registers.
Kojto 106:ba1f97679dad 491 @{
Kojto 106:ba1f97679dad 492 */
Kojto 106:ba1f97679dad 493
Kojto 106:ba1f97679dad 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 106:ba1f97679dad 495 */
Kojto 106:ba1f97679dad 496 typedef struct
Kojto 106:ba1f97679dad 497 {
Kojto 106:ba1f97679dad 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 106:ba1f97679dad 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 106:ba1f97679dad 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 106:ba1f97679dad 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 106:ba1f97679dad 502 } SysTick_Type;
Kojto 106:ba1f97679dad 503
Kojto 106:ba1f97679dad 504 /* SysTick Control / Status Register Definitions */
Kojto 106:ba1f97679dad 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 106:ba1f97679dad 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 106:ba1f97679dad 507
Kojto 106:ba1f97679dad 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 106:ba1f97679dad 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 106:ba1f97679dad 510
Kojto 106:ba1f97679dad 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 106:ba1f97679dad 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 106:ba1f97679dad 513
Kojto 106:ba1f97679dad 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 106:ba1f97679dad 516
Kojto 106:ba1f97679dad 517 /* SysTick Reload Register Definitions */
Kojto 106:ba1f97679dad 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 106:ba1f97679dad 520
Kojto 106:ba1f97679dad 521 /* SysTick Current Register Definitions */
Kojto 106:ba1f97679dad 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 106:ba1f97679dad 524
Kojto 106:ba1f97679dad 525 /* SysTick Calibration Register Definitions */
Kojto 106:ba1f97679dad 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 106:ba1f97679dad 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 106:ba1f97679dad 528
Kojto 106:ba1f97679dad 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 106:ba1f97679dad 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 106:ba1f97679dad 531
Kojto 106:ba1f97679dad 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 106:ba1f97679dad 534
Kojto 106:ba1f97679dad 535 /*@} end of group CMSIS_SysTick */
Kojto 106:ba1f97679dad 536
Kojto 106:ba1f97679dad 537 #if (__MPU_PRESENT == 1)
Kojto 106:ba1f97679dad 538 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 106:ba1f97679dad 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 106:ba1f97679dad 541 @{
Kojto 106:ba1f97679dad 542 */
Kojto 106:ba1f97679dad 543
Kojto 106:ba1f97679dad 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 106:ba1f97679dad 545 */
Kojto 106:ba1f97679dad 546 typedef struct
Kojto 106:ba1f97679dad 547 {
Kojto 106:ba1f97679dad 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 106:ba1f97679dad 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 106:ba1f97679dad 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 106:ba1f97679dad 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 106:ba1f97679dad 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 106:ba1f97679dad 553 } MPU_Type;
Kojto 106:ba1f97679dad 554
Kojto 106:ba1f97679dad 555 /* MPU Type Register */
Kojto 106:ba1f97679dad 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 106:ba1f97679dad 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 106:ba1f97679dad 558
Kojto 106:ba1f97679dad 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 106:ba1f97679dad 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 106:ba1f97679dad 561
Kojto 106:ba1f97679dad 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 106:ba1f97679dad 564
Kojto 106:ba1f97679dad 565 /* MPU Control Register */
Kojto 106:ba1f97679dad 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 106:ba1f97679dad 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 106:ba1f97679dad 568
Kojto 106:ba1f97679dad 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 106:ba1f97679dad 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 106:ba1f97679dad 571
Kojto 106:ba1f97679dad 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 106:ba1f97679dad 574
Kojto 106:ba1f97679dad 575 /* MPU Region Number Register */
Kojto 106:ba1f97679dad 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 106:ba1f97679dad 578
Kojto 106:ba1f97679dad 579 /* MPU Region Base Address Register */
Kojto 106:ba1f97679dad 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 106:ba1f97679dad 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 106:ba1f97679dad 582
Kojto 106:ba1f97679dad 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 106:ba1f97679dad 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 106:ba1f97679dad 585
Kojto 106:ba1f97679dad 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 106:ba1f97679dad 588
Kojto 106:ba1f97679dad 589 /* MPU Region Attribute and Size Register */
Kojto 106:ba1f97679dad 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 106:ba1f97679dad 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 106:ba1f97679dad 592
Kojto 106:ba1f97679dad 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 106:ba1f97679dad 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 106:ba1f97679dad 595
Kojto 106:ba1f97679dad 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 106:ba1f97679dad 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 106:ba1f97679dad 598
Kojto 106:ba1f97679dad 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 106:ba1f97679dad 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 106:ba1f97679dad 601
Kojto 106:ba1f97679dad 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 106:ba1f97679dad 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 106:ba1f97679dad 604
Kojto 106:ba1f97679dad 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 106:ba1f97679dad 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 106:ba1f97679dad 607
Kojto 106:ba1f97679dad 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 106:ba1f97679dad 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 106:ba1f97679dad 610
Kojto 106:ba1f97679dad 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 106:ba1f97679dad 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 106:ba1f97679dad 613
Kojto 106:ba1f97679dad 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 106:ba1f97679dad 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 106:ba1f97679dad 616
Kojto 106:ba1f97679dad 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 106:ba1f97679dad 619
Kojto 106:ba1f97679dad 620 /*@} end of group CMSIS_MPU */
Kojto 106:ba1f97679dad 621 #endif
Kojto 106:ba1f97679dad 622
Kojto 106:ba1f97679dad 623
Kojto 106:ba1f97679dad 624 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 106:ba1f97679dad 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 106:ba1f97679dad 627 are only accessible over DAP and not via processor. Therefore
Kojto 106:ba1f97679dad 628 they are not covered by the Cortex-M0 header file.
Kojto 106:ba1f97679dad 629 @{
Kojto 106:ba1f97679dad 630 */
Kojto 106:ba1f97679dad 631 /*@} end of group CMSIS_CoreDebug */
Kojto 106:ba1f97679dad 632
Kojto 106:ba1f97679dad 633
Kojto 106:ba1f97679dad 634 /** \ingroup CMSIS_core_register
Kojto 106:ba1f97679dad 635 \defgroup CMSIS_core_base Core Definitions
Kojto 106:ba1f97679dad 636 \brief Definitions for base addresses, unions, and structures.
Kojto 106:ba1f97679dad 637 @{
Kojto 106:ba1f97679dad 638 */
Kojto 106:ba1f97679dad 639
Kojto 106:ba1f97679dad 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 106:ba1f97679dad 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 106:ba1f97679dad 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 106:ba1f97679dad 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 106:ba1f97679dad 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 106:ba1f97679dad 645
Kojto 106:ba1f97679dad 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 106:ba1f97679dad 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 106:ba1f97679dad 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 106:ba1f97679dad 649
Kojto 106:ba1f97679dad 650 #if (__MPU_PRESENT == 1)
Kojto 106:ba1f97679dad 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 106:ba1f97679dad 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 106:ba1f97679dad 653 #endif
Kojto 106:ba1f97679dad 654
Kojto 106:ba1f97679dad 655 /*@} */
Kojto 106:ba1f97679dad 656
Kojto 106:ba1f97679dad 657
Kojto 106:ba1f97679dad 658
Kojto 106:ba1f97679dad 659 /*******************************************************************************
Kojto 106:ba1f97679dad 660 * Hardware Abstraction Layer
Kojto 106:ba1f97679dad 661 Core Function Interface contains:
Kojto 106:ba1f97679dad 662 - Core NVIC Functions
Kojto 106:ba1f97679dad 663 - Core SysTick Functions
Kojto 106:ba1f97679dad 664 - Core Register Access Functions
Kojto 106:ba1f97679dad 665 ******************************************************************************/
Kojto 106:ba1f97679dad 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 106:ba1f97679dad 667 */
Kojto 106:ba1f97679dad 668
Kojto 106:ba1f97679dad 669
Kojto 106:ba1f97679dad 670
Kojto 106:ba1f97679dad 671 /* ########################## NVIC functions #################################### */
Kojto 106:ba1f97679dad 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 106:ba1f97679dad 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 106:ba1f97679dad 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 106:ba1f97679dad 675 @{
Kojto 106:ba1f97679dad 676 */
Kojto 106:ba1f97679dad 677
Kojto 106:ba1f97679dad 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 106:ba1f97679dad 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 106:ba1f97679dad 683
Kojto 106:ba1f97679dad 684
Kojto 106:ba1f97679dad 685 /** \brief Enable External Interrupt
Kojto 106:ba1f97679dad 686
Kojto 106:ba1f97679dad 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 106:ba1f97679dad 688
Kojto 106:ba1f97679dad 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 106:ba1f97679dad 690 */
Kojto 106:ba1f97679dad 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 106:ba1f97679dad 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 106:ba1f97679dad 694 }
Kojto 106:ba1f97679dad 695
Kojto 106:ba1f97679dad 696
Kojto 106:ba1f97679dad 697 /** \brief Disable External Interrupt
Kojto 106:ba1f97679dad 698
Kojto 106:ba1f97679dad 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 106:ba1f97679dad 700
Kojto 106:ba1f97679dad 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 106:ba1f97679dad 702 */
Kojto 106:ba1f97679dad 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 106:ba1f97679dad 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 106:ba1f97679dad 708 }
Kojto 106:ba1f97679dad 709
Kojto 106:ba1f97679dad 710
Kojto 106:ba1f97679dad 711 /** \brief Get Pending Interrupt
Kojto 106:ba1f97679dad 712
Kojto 106:ba1f97679dad 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 106:ba1f97679dad 714 for the specified interrupt.
Kojto 106:ba1f97679dad 715
Kojto 106:ba1f97679dad 716 \param [in] IRQn Interrupt number.
Kojto 106:ba1f97679dad 717
Kojto 106:ba1f97679dad 718 \return 0 Interrupt status is not pending.
Kojto 106:ba1f97679dad 719 \return 1 Interrupt status is pending.
Kojto 106:ba1f97679dad 720 */
Kojto 106:ba1f97679dad 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 106:ba1f97679dad 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 106:ba1f97679dad 724 }
Kojto 106:ba1f97679dad 725
Kojto 106:ba1f97679dad 726
Kojto 106:ba1f97679dad 727 /** \brief Set Pending Interrupt
Kojto 106:ba1f97679dad 728
Kojto 106:ba1f97679dad 729 The function sets the pending bit of an external interrupt.
Kojto 106:ba1f97679dad 730
Kojto 106:ba1f97679dad 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 106:ba1f97679dad 732 */
Kojto 106:ba1f97679dad 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 106:ba1f97679dad 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 106:ba1f97679dad 736 }
Kojto 106:ba1f97679dad 737
Kojto 106:ba1f97679dad 738
Kojto 106:ba1f97679dad 739 /** \brief Clear Pending Interrupt
Kojto 106:ba1f97679dad 740
Kojto 106:ba1f97679dad 741 The function clears the pending bit of an external interrupt.
Kojto 106:ba1f97679dad 742
Kojto 106:ba1f97679dad 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 106:ba1f97679dad 744 */
Kojto 106:ba1f97679dad 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 106:ba1f97679dad 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 106:ba1f97679dad 748 }
Kojto 106:ba1f97679dad 749
Kojto 106:ba1f97679dad 750
Kojto 106:ba1f97679dad 751 /** \brief Set Interrupt Priority
Kojto 106:ba1f97679dad 752
Kojto 106:ba1f97679dad 753 The function sets the priority of an interrupt.
Kojto 106:ba1f97679dad 754
Kojto 106:ba1f97679dad 755 \note The priority cannot be set for every core interrupt.
Kojto 106:ba1f97679dad 756
Kojto 106:ba1f97679dad 757 \param [in] IRQn Interrupt number.
Kojto 106:ba1f97679dad 758 \param [in] priority Priority to set.
Kojto 106:ba1f97679dad 759 */
Kojto 106:ba1f97679dad 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 106:ba1f97679dad 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
Kojto 106:ba1f97679dad 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
Kojto 106:ba1f97679dad 770 }
Kojto 106:ba1f97679dad 771
Kojto 106:ba1f97679dad 772
Kojto 106:ba1f97679dad 773 /** \brief Get Interrupt Priority
Kojto 106:ba1f97679dad 774
Kojto 106:ba1f97679dad 775 The function reads the priority of an interrupt. The interrupt
Kojto 106:ba1f97679dad 776 number can be positive to specify an external (device specific)
Kojto 106:ba1f97679dad 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 106:ba1f97679dad 778
Kojto 106:ba1f97679dad 779
Kojto 106:ba1f97679dad 780 \param [in] IRQn Interrupt number.
Kojto 106:ba1f97679dad 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 106:ba1f97679dad 782 priority bits of the microcontroller.
Kojto 106:ba1f97679dad 783 */
Kojto 106:ba1f97679dad 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 106:ba1f97679dad 785 {
Kojto 106:ba1f97679dad 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
Kojto 106:ba1f97679dad 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
Kojto 106:ba1f97679dad 793 }
Kojto 106:ba1f97679dad 794
Kojto 106:ba1f97679dad 795
Kojto 106:ba1f97679dad 796 /** \brief System Reset
Kojto 106:ba1f97679dad 797
Kojto 106:ba1f97679dad 798 The function initiates a system reset request to reset the MCU.
Kojto 106:ba1f97679dad 799 */
Kojto 106:ba1f97679dad 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 106:ba1f97679dad 801 {
Kojto 106:ba1f97679dad 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 106:ba1f97679dad 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 106:ba1f97679dad 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 106:ba1f97679dad 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
Kojto 106:ba1f97679dad 808 }
Kojto 106:ba1f97679dad 809
Kojto 106:ba1f97679dad 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 106:ba1f97679dad 811
Kojto 106:ba1f97679dad 812
Kojto 106:ba1f97679dad 813
Kojto 106:ba1f97679dad 814 /* ################################## SysTick function ############################################ */
Kojto 106:ba1f97679dad 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 106:ba1f97679dad 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 106:ba1f97679dad 817 \brief Functions that configure the System.
Kojto 106:ba1f97679dad 818 @{
Kojto 106:ba1f97679dad 819 */
Kojto 106:ba1f97679dad 820
Kojto 106:ba1f97679dad 821 #if (__Vendor_SysTickConfig == 0)
Kojto 106:ba1f97679dad 822
Kojto 106:ba1f97679dad 823 /** \brief System Tick Configuration
Kojto 106:ba1f97679dad 824
Kojto 106:ba1f97679dad 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 106:ba1f97679dad 826 Counter is in free running mode to generate periodic interrupts.
Kojto 106:ba1f97679dad 827
Kojto 106:ba1f97679dad 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 106:ba1f97679dad 829
Kojto 106:ba1f97679dad 830 \return 0 Function succeeded.
Kojto 106:ba1f97679dad 831 \return 1 Function failed.
Kojto 106:ba1f97679dad 832
Kojto 106:ba1f97679dad 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 106:ba1f97679dad 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 106:ba1f97679dad 835 must contain a vendor-specific implementation of this function.
Kojto 106:ba1f97679dad 836
Kojto 106:ba1f97679dad 837 */
Kojto 106:ba1f97679dad 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 106:ba1f97679dad 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 106:ba1f97679dad 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 106:ba1f97679dad 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 106:ba1f97679dad 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
Kojto 106:ba1f97679dad 849 }
Kojto 106:ba1f97679dad 850
Kojto 106:ba1f97679dad 851 #endif
Kojto 106:ba1f97679dad 852
Kojto 106:ba1f97679dad 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 106:ba1f97679dad 854
Kojto 106:ba1f97679dad 855
Kojto 106:ba1f97679dad 856
Kojto 106:ba1f97679dad 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
Kojto 106:ba1f97679dad 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 106:ba1f97679dad 863
Kojto 106:ba1f97679dad 864 #endif /* __CMSIS_GENERIC */