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TARGET_NUCLEO_F439ZI/TARGET_STM/TARGET_STM32F4/pin_device.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
138:093f2bd7b9eb
Child:
170:e95d10626187
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 138:093f2bd7b9eb 1 /* mbed Microcontroller Library
<> 138:093f2bd7b9eb 2 *******************************************************************************
<> 138:093f2bd7b9eb 3 * Copyright (c) 2016, STMicroelectronics
<> 138:093f2bd7b9eb 4 * All rights reserved.
<> 138:093f2bd7b9eb 5 *
<> 138:093f2bd7b9eb 6 * Redistribution and use in source and binary forms, with or without
<> 138:093f2bd7b9eb 7 * modification, are permitted provided that the following conditions are met:
<> 138:093f2bd7b9eb 8 *
<> 138:093f2bd7b9eb 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 138:093f2bd7b9eb 10 * this list of conditions and the following disclaimer.
<> 138:093f2bd7b9eb 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 138:093f2bd7b9eb 12 * this list of conditions and the following disclaimer in the documentation
<> 138:093f2bd7b9eb 13 * and/or other materials provided with the distribution.
<> 138:093f2bd7b9eb 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 138:093f2bd7b9eb 15 * may be used to endorse or promote products derived from this software
<> 138:093f2bd7b9eb 16 * without specific prior written permission.
<> 138:093f2bd7b9eb 17 *
<> 138:093f2bd7b9eb 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 138:093f2bd7b9eb 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 138:093f2bd7b9eb 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 138:093f2bd7b9eb 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 138:093f2bd7b9eb 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 138:093f2bd7b9eb 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 138:093f2bd7b9eb 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 138:093f2bd7b9eb 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 138:093f2bd7b9eb 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 138:093f2bd7b9eb 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 138:093f2bd7b9eb 28 *******************************************************************************
<> 138:093f2bd7b9eb 29 */
<> 138:093f2bd7b9eb 30 #ifndef MBED_PIN_DEVICE_H
<> 138:093f2bd7b9eb 31 #define MBED_PIN_DEVICE_H
<> 138:093f2bd7b9eb 32
<> 138:093f2bd7b9eb 33 #include "cmsis.h"
<> 138:093f2bd7b9eb 34
<> 138:093f2bd7b9eb 35 // when LL is available, below include can be used
<> 138:093f2bd7b9eb 36 // #include "stm32f4xx_ll_gpio.h"
<> 138:093f2bd7b9eb 37 // until then let's define locally the required functions
<> 138:093f2bd7b9eb 38 #define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
<> 138:093f2bd7b9eb 39 #define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
<> 138:093f2bd7b9eb 40 #define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
<> 138:093f2bd7b9eb 41 #define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
<> 138:093f2bd7b9eb 42 #define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
<> 138:093f2bd7b9eb 43 #define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
<> 138:093f2bd7b9eb 44 #define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
<> 138:093f2bd7b9eb 45 #define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
<> 138:093f2bd7b9eb 46 #define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
<> 138:093f2bd7b9eb 47 #define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
<> 138:093f2bd7b9eb 48 #define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
<> 138:093f2bd7b9eb 49 #define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
<> 138:093f2bd7b9eb 50 #define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
<> 138:093f2bd7b9eb 51 #define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
<> 138:093f2bd7b9eb 52 #define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
<> 138:093f2bd7b9eb 53 #define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
<> 138:093f2bd7b9eb 54
<> 138:093f2bd7b9eb 55 #define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */
<> 138:093f2bd7b9eb 56 #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
<> 138:093f2bd7b9eb 57 #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
<> 138:093f2bd7b9eb 58 #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
<> 138:093f2bd7b9eb 59
<> 138:093f2bd7b9eb 60 #define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
<> 138:093f2bd7b9eb 61 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
<> 138:093f2bd7b9eb 62
<> 138:093f2bd7b9eb 63 #define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */
<> 138:093f2bd7b9eb 64 #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
<> 138:093f2bd7b9eb 65 #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
<> 138:093f2bd7b9eb 66
<> 138:093f2bd7b9eb 67 #define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */
<> 138:093f2bd7b9eb 68 #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
<> 138:093f2bd7b9eb 69 #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
<> 138:093f2bd7b9eb 70 #define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
<> 138:093f2bd7b9eb 71
<> 138:093f2bd7b9eb 72 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
<> 138:093f2bd7b9eb 73 {
<> 138:093f2bd7b9eb 74 MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)),
<> 138:093f2bd7b9eb 75 (Alternate << (POSITION_VAL(Pin) * 4U)));
<> 138:093f2bd7b9eb 76 }
<> 138:093f2bd7b9eb 77 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
<> 138:093f2bd7b9eb 78 {
<> 138:093f2bd7b9eb 79 MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)),
<> 138:093f2bd7b9eb 80 (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
<> 138:093f2bd7b9eb 81 }
<> 138:093f2bd7b9eb 82 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
<> 138:093f2bd7b9eb 83 {
<> 138:093f2bd7b9eb 84 MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
<> 138:093f2bd7b9eb 85 }
<> 138:093f2bd7b9eb 86 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
<> 138:093f2bd7b9eb 87 {
<> 138:093f2bd7b9eb 88 return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
<> 138:093f2bd7b9eb 89 }
<> 138:093f2bd7b9eb 90 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
<> 138:093f2bd7b9eb 91 {
<> 138:093f2bd7b9eb 92 MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
<> 138:093f2bd7b9eb 93 }
<> 138:093f2bd7b9eb 94 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
<> 138:093f2bd7b9eb 95 {
<> 138:093f2bd7b9eb 96 MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
<> 138:093f2bd7b9eb 97 }
<> 138:093f2bd7b9eb 98 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
<> 138:093f2bd7b9eb 99 {
<> 138:093f2bd7b9eb 100 MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
<> 138:093f2bd7b9eb 101 (Speed << (POSITION_VAL(Pin) * 2U)));
<> 138:093f2bd7b9eb 102 }
<> 138:093f2bd7b9eb 103 // Above lines shall be defined in LL when available
<> 138:093f2bd7b9eb 104
<> 138:093f2bd7b9eb 105 extern const uint32_t ll_pin_defines[16];
<> 138:093f2bd7b9eb 106
<> 138:093f2bd7b9eb 107 /* Family specific implementations */
<> 138:093f2bd7b9eb 108 static inline void stm_pin_DisconnectDebug(PinName pin)
<> 138:093f2bd7b9eb 109 {
<> 138:093f2bd7b9eb 110 /* empty for now */
<> 138:093f2bd7b9eb 111 }
<> 138:093f2bd7b9eb 112
<> 138:093f2bd7b9eb 113 static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
<> 138:093f2bd7b9eb 114 {
<> 138:093f2bd7b9eb 115 switch (pull_config) {
<> 138:093f2bd7b9eb 116 case GPIO_PULLUP:
<> 138:093f2bd7b9eb 117 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
<> 138:093f2bd7b9eb 118 break;
<> 138:093f2bd7b9eb 119 case GPIO_PULLDOWN:
<> 138:093f2bd7b9eb 120 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
<> 138:093f2bd7b9eb 121 break;
<> 138:093f2bd7b9eb 122 default:
<> 138:093f2bd7b9eb 123 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_NO);
<> 138:093f2bd7b9eb 124 break;
<> 138:093f2bd7b9eb 125 }
<> 138:093f2bd7b9eb 126 }
<> 138:093f2bd7b9eb 127
<> 138:093f2bd7b9eb 128 static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
<> 138:093f2bd7b9eb 129 {
<> 138:093f2bd7b9eb 130 uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
<> 138:093f2bd7b9eb 131
<> 138:093f2bd7b9eb 132 if (STM_PIN(pin) > 7)
<> 138:093f2bd7b9eb 133 LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
<> 138:093f2bd7b9eb 134 else
<> 138:093f2bd7b9eb 135 LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
<> 138:093f2bd7b9eb 136 }
<> 138:093f2bd7b9eb 137
<> 138:093f2bd7b9eb 138 #endif