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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F030R8/core_cm4_simd.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
77:869cf507173a 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**************************************************************************//**
emilmont 77:869cf507173a 2 * @file core_cm4_simd.h
emilmont 77:869cf507173a 3 * @brief CMSIS Cortex-M4 SIMD Header File
emilmont 77:869cf507173a 4 * @version V3.20
emilmont 77:869cf507173a 5 * @date 25. February 2013
emilmont 77:869cf507173a 6 *
emilmont 77:869cf507173a 7 * @note
emilmont 77:869cf507173a 8 *
emilmont 77:869cf507173a 9 ******************************************************************************/
emilmont 77:869cf507173a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 77:869cf507173a 11
emilmont 77:869cf507173a 12 All rights reserved.
emilmont 77:869cf507173a 13 Redistribution and use in source and binary forms, with or without
emilmont 77:869cf507173a 14 modification, are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 - Redistributions of source code must retain the above copyright
emilmont 77:869cf507173a 16 notice, this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 - Redistributions in binary form must reproduce the above copyright
emilmont 77:869cf507173a 18 notice, this list of conditions and the following disclaimer in the
emilmont 77:869cf507173a 19 documentation and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 77:869cf507173a 21 to endorse or promote products derived from this software without
emilmont 77:869cf507173a 22 specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 77:869cf507173a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 77:869cf507173a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 77:869cf507173a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 77:869cf507173a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 77:869cf507173a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 77:869cf507173a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 77:869cf507173a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 77:869cf507173a 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 ---------------------------------------------------------------------------*/
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 #ifdef __cplusplus
emilmont 77:869cf507173a 39 extern "C" {
emilmont 77:869cf507173a 40 #endif
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifndef __CORE_CM4_SIMD_H
emilmont 77:869cf507173a 43 #define __CORE_CM4_SIMD_H
emilmont 77:869cf507173a 44
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /*******************************************************************************
emilmont 77:869cf507173a 47 * Hardware Abstraction Layer
emilmont 77:869cf507173a 48 ******************************************************************************/
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 /* ################### Compiler specific Intrinsics ########################### */
emilmont 77:869cf507173a 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
emilmont 77:869cf507173a 53 Access to dedicated SIMD instructions
emilmont 77:869cf507173a 54 @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 77:869cf507173a 58 /* ARM armcc specific functions */
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 61 #define __SADD8 __sadd8
emilmont 77:869cf507173a 62 #define __QADD8 __qadd8
emilmont 77:869cf507173a 63 #define __SHADD8 __shadd8
emilmont 77:869cf507173a 64 #define __UADD8 __uadd8
emilmont 77:869cf507173a 65 #define __UQADD8 __uqadd8
emilmont 77:869cf507173a 66 #define __UHADD8 __uhadd8
emilmont 77:869cf507173a 67 #define __SSUB8 __ssub8
emilmont 77:869cf507173a 68 #define __QSUB8 __qsub8
emilmont 77:869cf507173a 69 #define __SHSUB8 __shsub8
emilmont 77:869cf507173a 70 #define __USUB8 __usub8
emilmont 77:869cf507173a 71 #define __UQSUB8 __uqsub8
emilmont 77:869cf507173a 72 #define __UHSUB8 __uhsub8
emilmont 77:869cf507173a 73 #define __SADD16 __sadd16
emilmont 77:869cf507173a 74 #define __QADD16 __qadd16
emilmont 77:869cf507173a 75 #define __SHADD16 __shadd16
emilmont 77:869cf507173a 76 #define __UADD16 __uadd16
emilmont 77:869cf507173a 77 #define __UQADD16 __uqadd16
emilmont 77:869cf507173a 78 #define __UHADD16 __uhadd16
emilmont 77:869cf507173a 79 #define __SSUB16 __ssub16
emilmont 77:869cf507173a 80 #define __QSUB16 __qsub16
emilmont 77:869cf507173a 81 #define __SHSUB16 __shsub16
emilmont 77:869cf507173a 82 #define __USUB16 __usub16
emilmont 77:869cf507173a 83 #define __UQSUB16 __uqsub16
emilmont 77:869cf507173a 84 #define __UHSUB16 __uhsub16
emilmont 77:869cf507173a 85 #define __SASX __sasx
emilmont 77:869cf507173a 86 #define __QASX __qasx
emilmont 77:869cf507173a 87 #define __SHASX __shasx
emilmont 77:869cf507173a 88 #define __UASX __uasx
emilmont 77:869cf507173a 89 #define __UQASX __uqasx
emilmont 77:869cf507173a 90 #define __UHASX __uhasx
emilmont 77:869cf507173a 91 #define __SSAX __ssax
emilmont 77:869cf507173a 92 #define __QSAX __qsax
emilmont 77:869cf507173a 93 #define __SHSAX __shsax
emilmont 77:869cf507173a 94 #define __USAX __usax
emilmont 77:869cf507173a 95 #define __UQSAX __uqsax
emilmont 77:869cf507173a 96 #define __UHSAX __uhsax
emilmont 77:869cf507173a 97 #define __USAD8 __usad8
emilmont 77:869cf507173a 98 #define __USADA8 __usada8
emilmont 77:869cf507173a 99 #define __SSAT16 __ssat16
emilmont 77:869cf507173a 100 #define __USAT16 __usat16
emilmont 77:869cf507173a 101 #define __UXTB16 __uxtb16
emilmont 77:869cf507173a 102 #define __UXTAB16 __uxtab16
emilmont 77:869cf507173a 103 #define __SXTB16 __sxtb16
emilmont 77:869cf507173a 104 #define __SXTAB16 __sxtab16
emilmont 77:869cf507173a 105 #define __SMUAD __smuad
emilmont 77:869cf507173a 106 #define __SMUADX __smuadx
emilmont 77:869cf507173a 107 #define __SMLAD __smlad
emilmont 77:869cf507173a 108 #define __SMLADX __smladx
emilmont 77:869cf507173a 109 #define __SMLALD __smlald
emilmont 77:869cf507173a 110 #define __SMLALDX __smlaldx
emilmont 77:869cf507173a 111 #define __SMUSD __smusd
emilmont 77:869cf507173a 112 #define __SMUSDX __smusdx
emilmont 77:869cf507173a 113 #define __SMLSD __smlsd
emilmont 77:869cf507173a 114 #define __SMLSDX __smlsdx
emilmont 77:869cf507173a 115 #define __SMLSLD __smlsld
emilmont 77:869cf507173a 116 #define __SMLSLDX __smlsldx
emilmont 77:869cf507173a 117 #define __SEL __sel
emilmont 77:869cf507173a 118 #define __QADD __qadd
emilmont 77:869cf507173a 119 #define __QSUB __qsub
emilmont 77:869cf507173a 120
emilmont 77:869cf507173a 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
emilmont 77:869cf507173a 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
emilmont 77:869cf507173a 123
emilmont 77:869cf507173a 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
emilmont 77:869cf507173a 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
emilmont 77:869cf507173a 126
emilmont 77:869cf507173a 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
emilmont 77:869cf507173a 128 ((int64_t)(ARG3) << 32) ) >> 32))
emilmont 77:869cf507173a 129
emilmont 77:869cf507173a 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 131
emilmont 77:869cf507173a 132
emilmont 77:869cf507173a 133
emilmont 77:869cf507173a 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 77:869cf507173a 135 /* IAR iccarm specific functions */
emilmont 77:869cf507173a 136
emilmont 77:869cf507173a 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 138 #include <cmsis_iar.h>
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 141
emilmont 77:869cf507173a 142
emilmont 77:869cf507173a 143
emilmont 77:869cf507173a 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 77:869cf507173a 145 /* TI CCS specific functions */
emilmont 77:869cf507173a 146
emilmont 77:869cf507173a 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 148 #include <cmsis_ccs.h>
emilmont 77:869cf507173a 149
emilmont 77:869cf507173a 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 151
emilmont 77:869cf507173a 152
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 77:869cf507173a 155 /* GNU gcc specific functions */
emilmont 77:869cf507173a 156
emilmont 77:869cf507173a 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 159 {
emilmont 77:869cf507173a 160 uint32_t result;
emilmont 77:869cf507173a 161
emilmont 77:869cf507173a 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 163 return(result);
emilmont 77:869cf507173a 164 }
emilmont 77:869cf507173a 165
emilmont 77:869cf507173a 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 167 {
emilmont 77:869cf507173a 168 uint32_t result;
emilmont 77:869cf507173a 169
emilmont 77:869cf507173a 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 171 return(result);
emilmont 77:869cf507173a 172 }
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 175 {
emilmont 77:869cf507173a 176 uint32_t result;
emilmont 77:869cf507173a 177
emilmont 77:869cf507173a 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 179 return(result);
emilmont 77:869cf507173a 180 }
emilmont 77:869cf507173a 181
emilmont 77:869cf507173a 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 183 {
emilmont 77:869cf507173a 184 uint32_t result;
emilmont 77:869cf507173a 185
emilmont 77:869cf507173a 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 187 return(result);
emilmont 77:869cf507173a 188 }
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 191 {
emilmont 77:869cf507173a 192 uint32_t result;
emilmont 77:869cf507173a 193
emilmont 77:869cf507173a 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 195 return(result);
emilmont 77:869cf507173a 196 }
emilmont 77:869cf507173a 197
emilmont 77:869cf507173a 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 199 {
emilmont 77:869cf507173a 200 uint32_t result;
emilmont 77:869cf507173a 201
emilmont 77:869cf507173a 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 203 return(result);
emilmont 77:869cf507173a 204 }
emilmont 77:869cf507173a 205
emilmont 77:869cf507173a 206
emilmont 77:869cf507173a 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 208 {
emilmont 77:869cf507173a 209 uint32_t result;
emilmont 77:869cf507173a 210
emilmont 77:869cf507173a 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 212 return(result);
emilmont 77:869cf507173a 213 }
emilmont 77:869cf507173a 214
emilmont 77:869cf507173a 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 216 {
emilmont 77:869cf507173a 217 uint32_t result;
emilmont 77:869cf507173a 218
emilmont 77:869cf507173a 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 220 return(result);
emilmont 77:869cf507173a 221 }
emilmont 77:869cf507173a 222
emilmont 77:869cf507173a 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 224 {
emilmont 77:869cf507173a 225 uint32_t result;
emilmont 77:869cf507173a 226
emilmont 77:869cf507173a 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 228 return(result);
emilmont 77:869cf507173a 229 }
emilmont 77:869cf507173a 230
emilmont 77:869cf507173a 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 232 {
emilmont 77:869cf507173a 233 uint32_t result;
emilmont 77:869cf507173a 234
emilmont 77:869cf507173a 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 236 return(result);
emilmont 77:869cf507173a 237 }
emilmont 77:869cf507173a 238
emilmont 77:869cf507173a 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 240 {
emilmont 77:869cf507173a 241 uint32_t result;
emilmont 77:869cf507173a 242
emilmont 77:869cf507173a 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 244 return(result);
emilmont 77:869cf507173a 245 }
emilmont 77:869cf507173a 246
emilmont 77:869cf507173a 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 248 {
emilmont 77:869cf507173a 249 uint32_t result;
emilmont 77:869cf507173a 250
emilmont 77:869cf507173a 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 252 return(result);
emilmont 77:869cf507173a 253 }
emilmont 77:869cf507173a 254
emilmont 77:869cf507173a 255
emilmont 77:869cf507173a 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 257 {
emilmont 77:869cf507173a 258 uint32_t result;
emilmont 77:869cf507173a 259
emilmont 77:869cf507173a 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 261 return(result);
emilmont 77:869cf507173a 262 }
emilmont 77:869cf507173a 263
emilmont 77:869cf507173a 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 265 {
emilmont 77:869cf507173a 266 uint32_t result;
emilmont 77:869cf507173a 267
emilmont 77:869cf507173a 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 269 return(result);
emilmont 77:869cf507173a 270 }
emilmont 77:869cf507173a 271
emilmont 77:869cf507173a 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 273 {
emilmont 77:869cf507173a 274 uint32_t result;
emilmont 77:869cf507173a 275
emilmont 77:869cf507173a 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 277 return(result);
emilmont 77:869cf507173a 278 }
emilmont 77:869cf507173a 279
emilmont 77:869cf507173a 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 281 {
emilmont 77:869cf507173a 282 uint32_t result;
emilmont 77:869cf507173a 283
emilmont 77:869cf507173a 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 285 return(result);
emilmont 77:869cf507173a 286 }
emilmont 77:869cf507173a 287
emilmont 77:869cf507173a 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 289 {
emilmont 77:869cf507173a 290 uint32_t result;
emilmont 77:869cf507173a 291
emilmont 77:869cf507173a 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 293 return(result);
emilmont 77:869cf507173a 294 }
emilmont 77:869cf507173a 295
emilmont 77:869cf507173a 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 297 {
emilmont 77:869cf507173a 298 uint32_t result;
emilmont 77:869cf507173a 299
emilmont 77:869cf507173a 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 301 return(result);
emilmont 77:869cf507173a 302 }
emilmont 77:869cf507173a 303
emilmont 77:869cf507173a 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 305 {
emilmont 77:869cf507173a 306 uint32_t result;
emilmont 77:869cf507173a 307
emilmont 77:869cf507173a 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 309 return(result);
emilmont 77:869cf507173a 310 }
emilmont 77:869cf507173a 311
emilmont 77:869cf507173a 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 313 {
emilmont 77:869cf507173a 314 uint32_t result;
emilmont 77:869cf507173a 315
emilmont 77:869cf507173a 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 317 return(result);
emilmont 77:869cf507173a 318 }
emilmont 77:869cf507173a 319
emilmont 77:869cf507173a 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 321 {
emilmont 77:869cf507173a 322 uint32_t result;
emilmont 77:869cf507173a 323
emilmont 77:869cf507173a 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 325 return(result);
emilmont 77:869cf507173a 326 }
emilmont 77:869cf507173a 327
emilmont 77:869cf507173a 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 329 {
emilmont 77:869cf507173a 330 uint32_t result;
emilmont 77:869cf507173a 331
emilmont 77:869cf507173a 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 333 return(result);
emilmont 77:869cf507173a 334 }
emilmont 77:869cf507173a 335
emilmont 77:869cf507173a 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 337 {
emilmont 77:869cf507173a 338 uint32_t result;
emilmont 77:869cf507173a 339
emilmont 77:869cf507173a 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 341 return(result);
emilmont 77:869cf507173a 342 }
emilmont 77:869cf507173a 343
emilmont 77:869cf507173a 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 345 {
emilmont 77:869cf507173a 346 uint32_t result;
emilmont 77:869cf507173a 347
emilmont 77:869cf507173a 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 349 return(result);
emilmont 77:869cf507173a 350 }
emilmont 77:869cf507173a 351
emilmont 77:869cf507173a 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 353 {
emilmont 77:869cf507173a 354 uint32_t result;
emilmont 77:869cf507173a 355
emilmont 77:869cf507173a 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 357 return(result);
emilmont 77:869cf507173a 358 }
emilmont 77:869cf507173a 359
emilmont 77:869cf507173a 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 361 {
emilmont 77:869cf507173a 362 uint32_t result;
emilmont 77:869cf507173a 363
emilmont 77:869cf507173a 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 365 return(result);
emilmont 77:869cf507173a 366 }
emilmont 77:869cf507173a 367
emilmont 77:869cf507173a 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 369 {
emilmont 77:869cf507173a 370 uint32_t result;
emilmont 77:869cf507173a 371
emilmont 77:869cf507173a 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 373 return(result);
emilmont 77:869cf507173a 374 }
emilmont 77:869cf507173a 375
emilmont 77:869cf507173a 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 377 {
emilmont 77:869cf507173a 378 uint32_t result;
emilmont 77:869cf507173a 379
emilmont 77:869cf507173a 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 381 return(result);
emilmont 77:869cf507173a 382 }
emilmont 77:869cf507173a 383
emilmont 77:869cf507173a 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 385 {
emilmont 77:869cf507173a 386 uint32_t result;
emilmont 77:869cf507173a 387
emilmont 77:869cf507173a 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 389 return(result);
emilmont 77:869cf507173a 390 }
emilmont 77:869cf507173a 391
emilmont 77:869cf507173a 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 393 {
emilmont 77:869cf507173a 394 uint32_t result;
emilmont 77:869cf507173a 395
emilmont 77:869cf507173a 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 397 return(result);
emilmont 77:869cf507173a 398 }
emilmont 77:869cf507173a 399
emilmont 77:869cf507173a 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 401 {
emilmont 77:869cf507173a 402 uint32_t result;
emilmont 77:869cf507173a 403
emilmont 77:869cf507173a 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 405 return(result);
emilmont 77:869cf507173a 406 }
emilmont 77:869cf507173a 407
emilmont 77:869cf507173a 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 409 {
emilmont 77:869cf507173a 410 uint32_t result;
emilmont 77:869cf507173a 411
emilmont 77:869cf507173a 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 413 return(result);
emilmont 77:869cf507173a 414 }
emilmont 77:869cf507173a 415
emilmont 77:869cf507173a 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 417 {
emilmont 77:869cf507173a 418 uint32_t result;
emilmont 77:869cf507173a 419
emilmont 77:869cf507173a 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 421 return(result);
emilmont 77:869cf507173a 422 }
emilmont 77:869cf507173a 423
emilmont 77:869cf507173a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 425 {
emilmont 77:869cf507173a 426 uint32_t result;
emilmont 77:869cf507173a 427
emilmont 77:869cf507173a 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 429 return(result);
emilmont 77:869cf507173a 430 }
emilmont 77:869cf507173a 431
emilmont 77:869cf507173a 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 433 {
emilmont 77:869cf507173a 434 uint32_t result;
emilmont 77:869cf507173a 435
emilmont 77:869cf507173a 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 437 return(result);
emilmont 77:869cf507173a 438 }
emilmont 77:869cf507173a 439
emilmont 77:869cf507173a 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 441 {
emilmont 77:869cf507173a 442 uint32_t result;
emilmont 77:869cf507173a 443
emilmont 77:869cf507173a 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 445 return(result);
emilmont 77:869cf507173a 446 }
emilmont 77:869cf507173a 447
emilmont 77:869cf507173a 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 449 {
emilmont 77:869cf507173a 450 uint32_t result;
emilmont 77:869cf507173a 451
emilmont 77:869cf507173a 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 453 return(result);
emilmont 77:869cf507173a 454 }
emilmont 77:869cf507173a 455
emilmont 77:869cf507173a 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 77:869cf507173a 457 {
emilmont 77:869cf507173a 458 uint32_t result;
emilmont 77:869cf507173a 459
emilmont 77:869cf507173a 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 77:869cf507173a 461 return(result);
emilmont 77:869cf507173a 462 }
emilmont 77:869cf507173a 463
emilmont 77:869cf507173a 464 #define __SSAT16(ARG1,ARG2) \
emilmont 77:869cf507173a 465 ({ \
emilmont 77:869cf507173a 466 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 77:869cf507173a 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 77:869cf507173a 468 __RES; \
emilmont 77:869cf507173a 469 })
emilmont 77:869cf507173a 470
emilmont 77:869cf507173a 471 #define __USAT16(ARG1,ARG2) \
emilmont 77:869cf507173a 472 ({ \
emilmont 77:869cf507173a 473 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 77:869cf507173a 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 77:869cf507173a 475 __RES; \
emilmont 77:869cf507173a 476 })
emilmont 77:869cf507173a 477
emilmont 77:869cf507173a 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
emilmont 77:869cf507173a 479 {
emilmont 77:869cf507173a 480 uint32_t result;
emilmont 77:869cf507173a 481
emilmont 77:869cf507173a 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
emilmont 77:869cf507173a 483 return(result);
emilmont 77:869cf507173a 484 }
emilmont 77:869cf507173a 485
emilmont 77:869cf507173a 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 487 {
emilmont 77:869cf507173a 488 uint32_t result;
emilmont 77:869cf507173a 489
emilmont 77:869cf507173a 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 491 return(result);
emilmont 77:869cf507173a 492 }
emilmont 77:869cf507173a 493
emilmont 77:869cf507173a 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
emilmont 77:869cf507173a 495 {
emilmont 77:869cf507173a 496 uint32_t result;
emilmont 77:869cf507173a 497
emilmont 77:869cf507173a 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
emilmont 77:869cf507173a 499 return(result);
emilmont 77:869cf507173a 500 }
emilmont 77:869cf507173a 501
emilmont 77:869cf507173a 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 503 {
emilmont 77:869cf507173a 504 uint32_t result;
emilmont 77:869cf507173a 505
emilmont 77:869cf507173a 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 507 return(result);
emilmont 77:869cf507173a 508 }
emilmont 77:869cf507173a 509
emilmont 77:869cf507173a 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 511 {
emilmont 77:869cf507173a 512 uint32_t result;
emilmont 77:869cf507173a 513
emilmont 77:869cf507173a 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 515 return(result);
emilmont 77:869cf507173a 516 }
emilmont 77:869cf507173a 517
emilmont 77:869cf507173a 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 519 {
emilmont 77:869cf507173a 520 uint32_t result;
emilmont 77:869cf507173a 521
emilmont 77:869cf507173a 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 523 return(result);
emilmont 77:869cf507173a 524 }
emilmont 77:869cf507173a 525
emilmont 77:869cf507173a 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 77:869cf507173a 527 {
emilmont 77:869cf507173a 528 uint32_t result;
emilmont 77:869cf507173a 529
emilmont 77:869cf507173a 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 77:869cf507173a 531 return(result);
emilmont 77:869cf507173a 532 }
emilmont 77:869cf507173a 533
emilmont 77:869cf507173a 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 77:869cf507173a 535 {
emilmont 77:869cf507173a 536 uint32_t result;
emilmont 77:869cf507173a 537
emilmont 77:869cf507173a 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 77:869cf507173a 539 return(result);
emilmont 77:869cf507173a 540 }
emilmont 77:869cf507173a 541
emilmont 77:869cf507173a 542 #define __SMLALD(ARG1,ARG2,ARG3) \
emilmont 77:869cf507173a 543 ({ \
emilmont 77:869cf507173a 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
emilmont 77:869cf507173a 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 77:869cf507173a 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 77:869cf507173a 547 })
emilmont 77:869cf507173a 548
emilmont 77:869cf507173a 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
emilmont 77:869cf507173a 550 ({ \
emilmont 77:869cf507173a 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
emilmont 77:869cf507173a 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 77:869cf507173a 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 77:869cf507173a 554 })
emilmont 77:869cf507173a 555
emilmont 77:869cf507173a 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 557 {
emilmont 77:869cf507173a 558 uint32_t result;
emilmont 77:869cf507173a 559
emilmont 77:869cf507173a 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 561 return(result);
emilmont 77:869cf507173a 562 }
emilmont 77:869cf507173a 563
emilmont 77:869cf507173a 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 565 {
emilmont 77:869cf507173a 566 uint32_t result;
emilmont 77:869cf507173a 567
emilmont 77:869cf507173a 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 569 return(result);
emilmont 77:869cf507173a 570 }
emilmont 77:869cf507173a 571
emilmont 77:869cf507173a 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 77:869cf507173a 573 {
emilmont 77:869cf507173a 574 uint32_t result;
emilmont 77:869cf507173a 575
emilmont 77:869cf507173a 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 77:869cf507173a 577 return(result);
emilmont 77:869cf507173a 578 }
emilmont 77:869cf507173a 579
emilmont 77:869cf507173a 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
emilmont 77:869cf507173a 581 {
emilmont 77:869cf507173a 582 uint32_t result;
emilmont 77:869cf507173a 583
emilmont 77:869cf507173a 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emilmont 77:869cf507173a 585 return(result);
emilmont 77:869cf507173a 586 }
emilmont 77:869cf507173a 587
emilmont 77:869cf507173a 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
emilmont 77:869cf507173a 589 ({ \
emilmont 77:869cf507173a 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
emilmont 77:869cf507173a 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 77:869cf507173a 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 77:869cf507173a 593 })
emilmont 77:869cf507173a 594
emilmont 77:869cf507173a 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
emilmont 77:869cf507173a 596 ({ \
emilmont 77:869cf507173a 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
emilmont 77:869cf507173a 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
emilmont 77:869cf507173a 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
emilmont 77:869cf507173a 600 })
emilmont 77:869cf507173a 601
emilmont 77:869cf507173a 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 603 {
emilmont 77:869cf507173a 604 uint32_t result;
emilmont 77:869cf507173a 605
emilmont 77:869cf507173a 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 607 return(result);
emilmont 77:869cf507173a 608 }
emilmont 77:869cf507173a 609
emilmont 77:869cf507173a 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 611 {
emilmont 77:869cf507173a 612 uint32_t result;
emilmont 77:869cf507173a 613
emilmont 77:869cf507173a 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 615 return(result);
emilmont 77:869cf507173a 616 }
emilmont 77:869cf507173a 617
emilmont 77:869cf507173a 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 619 {
emilmont 77:869cf507173a 620 uint32_t result;
emilmont 77:869cf507173a 621
emilmont 77:869cf507173a 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emilmont 77:869cf507173a 623 return(result);
emilmont 77:869cf507173a 624 }
emilmont 77:869cf507173a 625
emilmont 77:869cf507173a 626 #define __PKHBT(ARG1,ARG2,ARG3) \
emilmont 77:869cf507173a 627 ({ \
emilmont 77:869cf507173a 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
emilmont 77:869cf507173a 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
emilmont 77:869cf507173a 630 __RES; \
emilmont 77:869cf507173a 631 })
emilmont 77:869cf507173a 632
emilmont 77:869cf507173a 633 #define __PKHTB(ARG1,ARG2,ARG3) \
emilmont 77:869cf507173a 634 ({ \
emilmont 77:869cf507173a 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
emilmont 77:869cf507173a 636 if (ARG3 == 0) \
emilmont 77:869cf507173a 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
emilmont 77:869cf507173a 638 else \
emilmont 77:869cf507173a 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
emilmont 77:869cf507173a 640 __RES; \
emilmont 77:869cf507173a 641 })
emilmont 77:869cf507173a 642
emilmont 77:869cf507173a 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
emilmont 77:869cf507173a 644 {
emilmont 77:869cf507173a 645 int32_t result;
emilmont 77:869cf507173a 646
emilmont 77:869cf507173a 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
emilmont 77:869cf507173a 648 return(result);
emilmont 77:869cf507173a 649 }
emilmont 77:869cf507173a 650
emilmont 77:869cf507173a 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 652
emilmont 77:869cf507173a 653
emilmont 77:869cf507173a 654
emilmont 77:869cf507173a 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 77:869cf507173a 656 /* TASKING carm specific functions */
emilmont 77:869cf507173a 657
emilmont 77:869cf507173a 658
emilmont 77:869cf507173a 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 660 /* not yet supported */
emilmont 77:869cf507173a 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
emilmont 77:869cf507173a 662
emilmont 77:869cf507173a 663
emilmont 77:869cf507173a 664 #endif
emilmont 77:869cf507173a 665
emilmont 77:869cf507173a 666 /*@} end of group CMSIS_SIMD_intrinsics */
emilmont 77:869cf507173a 667
emilmont 77:869cf507173a 668
emilmont 77:869cf507173a 669 #endif /* __CORE_CM4_SIMD_H */
emilmont 77:869cf507173a 670
emilmont 77:869cf507173a 671 #ifdef __cplusplus
emilmont 77:869cf507173a 672 }
emilmont 77:869cf507173a 673 #endif