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TARGET_EFM32PG12_STK3402/core_sc300.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_sc300.h
<> 139:856d2700e60b 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
<> 139:856d2700e60b 4 * @version V4.10
<> 139:856d2700e60b 5 * @date 18. March 2015
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #if defined ( __ICCARM__ )
<> 139:856d2700e60b 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 139:856d2700e60b 40 #endif
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 #ifndef __CORE_SC300_H_GENERIC
<> 139:856d2700e60b 43 #define __CORE_SC300_H_GENERIC
<> 139:856d2700e60b 44
<> 139:856d2700e60b 45 #ifdef __cplusplus
<> 139:856d2700e60b 46 extern "C" {
<> 139:856d2700e60b 47 #endif
<> 139:856d2700e60b 48
<> 139:856d2700e60b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 139:856d2700e60b 50 CMSIS violates the following MISRA-C:2004 rules:
<> 139:856d2700e60b 51
<> 139:856d2700e60b 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 139:856d2700e60b 53 Function definitions in header files are used to allow 'inlining'.
<> 139:856d2700e60b 54
<> 139:856d2700e60b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 139:856d2700e60b 56 Unions are used for effective representation of core registers.
<> 139:856d2700e60b 57
<> 139:856d2700e60b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 139:856d2700e60b 59 Function-like macros are used to allow more efficient code.
<> 139:856d2700e60b 60 */
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62
<> 139:856d2700e60b 63 /*******************************************************************************
<> 139:856d2700e60b 64 * CMSIS definitions
<> 139:856d2700e60b 65 ******************************************************************************/
<> 139:856d2700e60b 66 /** \ingroup SC3000
<> 139:856d2700e60b 67 @{
<> 139:856d2700e60b 68 */
<> 139:856d2700e60b 69
<> 139:856d2700e60b 70 /* CMSIS SC300 definitions */
<> 139:856d2700e60b 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 139:856d2700e60b 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 139:856d2700e60b 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
<> 139:856d2700e60b 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 139:856d2700e60b 75
<> 139:856d2700e60b 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
<> 139:856d2700e60b 77
<> 139:856d2700e60b 78
<> 139:856d2700e60b 79 #if defined ( __CC_ARM )
<> 139:856d2700e60b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 139:856d2700e60b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 139:856d2700e60b 82 #define __STATIC_INLINE static __inline
<> 139:856d2700e60b 83
<> 139:856d2700e60b 84 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 139:856d2700e60b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 139:856d2700e60b 87 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 88
<> 139:856d2700e60b 89 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 139:856d2700e60b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 139:856d2700e60b 92 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 93
<> 139:856d2700e60b 94 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 139:856d2700e60b 96 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 97
<> 139:856d2700e60b 98 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 139:856d2700e60b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 139:856d2700e60b 101 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 102
<> 139:856d2700e60b 103 #elif defined ( __CSMC__ )
<> 139:856d2700e60b 104 #define __packed
<> 139:856d2700e60b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 139:856d2700e60b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 139:856d2700e60b 107 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 108
<> 139:856d2700e60b 109 #endif
<> 139:856d2700e60b 110
<> 139:856d2700e60b 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 139:856d2700e60b 112 This core does not support an FPU at all
<> 139:856d2700e60b 113 */
<> 139:856d2700e60b 114 #define __FPU_USED 0
<> 139:856d2700e60b 115
<> 139:856d2700e60b 116 #if defined ( __CC_ARM )
<> 139:856d2700e60b 117 #if defined __TARGET_FPU_VFP
<> 139:856d2700e60b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 119 #endif
<> 139:856d2700e60b 120
<> 139:856d2700e60b 121 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 139:856d2700e60b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 124 #endif
<> 139:856d2700e60b 125
<> 139:856d2700e60b 126 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 127 #if defined __ARMVFP__
<> 139:856d2700e60b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 129 #endif
<> 139:856d2700e60b 130
<> 139:856d2700e60b 131 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 132 #if defined __TI__VFP_SUPPORT____
<> 139:856d2700e60b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 134 #endif
<> 139:856d2700e60b 135
<> 139:856d2700e60b 136 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 137 #if defined __FPU_VFP__
<> 139:856d2700e60b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 139 #endif
<> 139:856d2700e60b 140
<> 139:856d2700e60b 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 139:856d2700e60b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 139:856d2700e60b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 144 #endif
<> 139:856d2700e60b 145 #endif
<> 139:856d2700e60b 146
<> 139:856d2700e60b 147 #include <stdint.h> /* standard types definitions */
<> 139:856d2700e60b 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 139:856d2700e60b 149 #include <core_cmFunc.h> /* Core Function Access */
<> 139:856d2700e60b 150
<> 139:856d2700e60b 151 #ifdef __cplusplus
<> 139:856d2700e60b 152 }
<> 139:856d2700e60b 153 #endif
<> 139:856d2700e60b 154
<> 139:856d2700e60b 155 #endif /* __CORE_SC300_H_GENERIC */
<> 139:856d2700e60b 156
<> 139:856d2700e60b 157 #ifndef __CMSIS_GENERIC
<> 139:856d2700e60b 158
<> 139:856d2700e60b 159 #ifndef __CORE_SC300_H_DEPENDANT
<> 139:856d2700e60b 160 #define __CORE_SC300_H_DEPENDANT
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 #ifdef __cplusplus
<> 139:856d2700e60b 163 extern "C" {
<> 139:856d2700e60b 164 #endif
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 /* check device defines and use defaults */
<> 139:856d2700e60b 167 #if defined __CHECK_DEVICE_DEFINES
<> 139:856d2700e60b 168 #ifndef __SC300_REV
<> 139:856d2700e60b 169 #define __SC300_REV 0x0000
<> 139:856d2700e60b 170 #warning "__SC300_REV not defined in device header file; using default!"
<> 139:856d2700e60b 171 #endif
<> 139:856d2700e60b 172
<> 139:856d2700e60b 173 #ifndef __MPU_PRESENT
<> 139:856d2700e60b 174 #define __MPU_PRESENT 0
<> 139:856d2700e60b 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 139:856d2700e60b 176 #endif
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 #ifndef __NVIC_PRIO_BITS
<> 139:856d2700e60b 179 #define __NVIC_PRIO_BITS 4
<> 139:856d2700e60b 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 139:856d2700e60b 181 #endif
<> 139:856d2700e60b 182
<> 139:856d2700e60b 183 #ifndef __Vendor_SysTickConfig
<> 139:856d2700e60b 184 #define __Vendor_SysTickConfig 0
<> 139:856d2700e60b 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 139:856d2700e60b 186 #endif
<> 139:856d2700e60b 187 #endif
<> 139:856d2700e60b 188
<> 139:856d2700e60b 189 /* IO definitions (access restrictions to peripheral registers) */
<> 139:856d2700e60b 190 /**
<> 139:856d2700e60b 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 139:856d2700e60b 192
<> 139:856d2700e60b 193 <strong>IO Type Qualifiers</strong> are used
<> 139:856d2700e60b 194 \li to specify the access to peripheral variables.
<> 139:856d2700e60b 195 \li for automatic generation of peripheral register debug information.
<> 139:856d2700e60b 196 */
<> 139:856d2700e60b 197 #ifdef __cplusplus
<> 139:856d2700e60b 198 #define __I volatile /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 199 #else
<> 139:856d2700e60b 200 #define __I volatile const /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 201 #endif
<> 139:856d2700e60b 202 #define __O volatile /*!< Defines 'write only' permissions */
<> 139:856d2700e60b 203 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 139:856d2700e60b 204
<> 139:856d2700e60b 205 /*@} end of group SC300 */
<> 139:856d2700e60b 206
<> 139:856d2700e60b 207
<> 139:856d2700e60b 208
<> 139:856d2700e60b 209 /*******************************************************************************
<> 139:856d2700e60b 210 * Register Abstraction
<> 139:856d2700e60b 211 Core Register contain:
<> 139:856d2700e60b 212 - Core Register
<> 139:856d2700e60b 213 - Core NVIC Register
<> 139:856d2700e60b 214 - Core SCB Register
<> 139:856d2700e60b 215 - Core SysTick Register
<> 139:856d2700e60b 216 - Core Debug Register
<> 139:856d2700e60b 217 - Core MPU Register
<> 139:856d2700e60b 218 ******************************************************************************/
<> 139:856d2700e60b 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 139:856d2700e60b 220 \brief Type definitions and defines for Cortex-M processor based devices.
<> 139:856d2700e60b 221 */
<> 139:856d2700e60b 222
<> 139:856d2700e60b 223 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 224 \defgroup CMSIS_CORE Status and Control Registers
<> 139:856d2700e60b 225 \brief Core Register type definitions.
<> 139:856d2700e60b 226 @{
<> 139:856d2700e60b 227 */
<> 139:856d2700e60b 228
<> 139:856d2700e60b 229 /** \brief Union type to access the Application Program Status Register (APSR).
<> 139:856d2700e60b 230 */
<> 139:856d2700e60b 231 typedef union
<> 139:856d2700e60b 232 {
<> 139:856d2700e60b 233 struct
<> 139:856d2700e60b 234 {
<> 139:856d2700e60b 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
<> 139:856d2700e60b 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 139:856d2700e60b 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 241 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 242 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 243 } APSR_Type;
<> 139:856d2700e60b 244
<> 139:856d2700e60b 245 /* APSR Register Definitions */
<> 139:856d2700e60b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 139:856d2700e60b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 139:856d2700e60b 248
<> 139:856d2700e60b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 139:856d2700e60b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 139:856d2700e60b 251
<> 139:856d2700e60b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 139:856d2700e60b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 139:856d2700e60b 254
<> 139:856d2700e60b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 139:856d2700e60b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 139:856d2700e60b 257
<> 139:856d2700e60b 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
<> 139:856d2700e60b 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 139:856d2700e60b 260
<> 139:856d2700e60b 261
<> 139:856d2700e60b 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 139:856d2700e60b 263 */
<> 139:856d2700e60b 264 typedef union
<> 139:856d2700e60b 265 {
<> 139:856d2700e60b 266 struct
<> 139:856d2700e60b 267 {
<> 139:856d2700e60b 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 139:856d2700e60b 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 139:856d2700e60b 270 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 271 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 272 } IPSR_Type;
<> 139:856d2700e60b 273
<> 139:856d2700e60b 274 /* IPSR Register Definitions */
<> 139:856d2700e60b 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 139:856d2700e60b 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 139:856d2700e60b 277
<> 139:856d2700e60b 278
<> 139:856d2700e60b 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 139:856d2700e60b 280 */
<> 139:856d2700e60b 281 typedef union
<> 139:856d2700e60b 282 {
<> 139:856d2700e60b 283 struct
<> 139:856d2700e60b 284 {
<> 139:856d2700e60b 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 139:856d2700e60b 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 139:856d2700e60b 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 139:856d2700e60b 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
<> 139:856d2700e60b 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 139:856d2700e60b 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 294 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 295 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 296 } xPSR_Type;
<> 139:856d2700e60b 297
<> 139:856d2700e60b 298 /* xPSR Register Definitions */
<> 139:856d2700e60b 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 139:856d2700e60b 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 139:856d2700e60b 301
<> 139:856d2700e60b 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 139:856d2700e60b 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 139:856d2700e60b 304
<> 139:856d2700e60b 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 139:856d2700e60b 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 139:856d2700e60b 307
<> 139:856d2700e60b 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 139:856d2700e60b 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 139:856d2700e60b 310
<> 139:856d2700e60b 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
<> 139:856d2700e60b 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 139:856d2700e60b 313
<> 139:856d2700e60b 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
<> 139:856d2700e60b 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
<> 139:856d2700e60b 316
<> 139:856d2700e60b 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 139:856d2700e60b 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 139:856d2700e60b 319
<> 139:856d2700e60b 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 139:856d2700e60b 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 139:856d2700e60b 322
<> 139:856d2700e60b 323
<> 139:856d2700e60b 324 /** \brief Union type to access the Control Registers (CONTROL).
<> 139:856d2700e60b 325 */
<> 139:856d2700e60b 326 typedef union
<> 139:856d2700e60b 327 {
<> 139:856d2700e60b 328 struct
<> 139:856d2700e60b 329 {
<> 139:856d2700e60b 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 139:856d2700e60b 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 139:856d2700e60b 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 139:856d2700e60b 333 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 334 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 335 } CONTROL_Type;
<> 139:856d2700e60b 336
<> 139:856d2700e60b 337 /* CONTROL Register Definitions */
<> 139:856d2700e60b 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 139:856d2700e60b 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 139:856d2700e60b 340
<> 139:856d2700e60b 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 139:856d2700e60b 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 139:856d2700e60b 343
<> 139:856d2700e60b 344 /*@} end of group CMSIS_CORE */
<> 139:856d2700e60b 345
<> 139:856d2700e60b 346
<> 139:856d2700e60b 347 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 139:856d2700e60b 349 \brief Type definitions for the NVIC Registers
<> 139:856d2700e60b 350 @{
<> 139:856d2700e60b 351 */
<> 139:856d2700e60b 352
<> 139:856d2700e60b 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 139:856d2700e60b 354 */
<> 139:856d2700e60b 355 typedef struct
<> 139:856d2700e60b 356 {
<> 139:856d2700e60b 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 139:856d2700e60b 358 uint32_t RESERVED0[24];
<> 139:856d2700e60b 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 139:856d2700e60b 360 uint32_t RSERVED1[24];
<> 139:856d2700e60b 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 139:856d2700e60b 362 uint32_t RESERVED2[24];
<> 139:856d2700e60b 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 139:856d2700e60b 364 uint32_t RESERVED3[24];
<> 139:856d2700e60b 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
<> 139:856d2700e60b 366 uint32_t RESERVED4[56];
<> 139:856d2700e60b 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
<> 139:856d2700e60b 368 uint32_t RESERVED5[644];
<> 139:856d2700e60b 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 139:856d2700e60b 370 } NVIC_Type;
<> 139:856d2700e60b 371
<> 139:856d2700e60b 372 /* Software Triggered Interrupt Register Definitions */
<> 139:856d2700e60b 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
<> 139:856d2700e60b 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 139:856d2700e60b 375
<> 139:856d2700e60b 376 /*@} end of group CMSIS_NVIC */
<> 139:856d2700e60b 377
<> 139:856d2700e60b 378
<> 139:856d2700e60b 379 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 380 \defgroup CMSIS_SCB System Control Block (SCB)
<> 139:856d2700e60b 381 \brief Type definitions for the System Control Block Registers
<> 139:856d2700e60b 382 @{
<> 139:856d2700e60b 383 */
<> 139:856d2700e60b 384
<> 139:856d2700e60b 385 /** \brief Structure type to access the System Control Block (SCB).
<> 139:856d2700e60b 386 */
<> 139:856d2700e60b 387 typedef struct
<> 139:856d2700e60b 388 {
<> 139:856d2700e60b 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 139:856d2700e60b 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 139:856d2700e60b 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 139:856d2700e60b 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 139:856d2700e60b 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 139:856d2700e60b 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 139:856d2700e60b 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
<> 139:856d2700e60b 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 139:856d2700e60b 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
<> 139:856d2700e60b 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
<> 139:856d2700e60b 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
<> 139:856d2700e60b 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
<> 139:856d2700e60b 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
<> 139:856d2700e60b 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
<> 139:856d2700e60b 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
<> 139:856d2700e60b 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
<> 139:856d2700e60b 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
<> 139:856d2700e60b 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
<> 139:856d2700e60b 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
<> 139:856d2700e60b 408 uint32_t RESERVED0[5];
<> 139:856d2700e60b 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 139:856d2700e60b 410 uint32_t RESERVED1[129];
<> 139:856d2700e60b 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
<> 139:856d2700e60b 412 } SCB_Type;
<> 139:856d2700e60b 413
<> 139:856d2700e60b 414 /* SCB CPUID Register Definitions */
<> 139:856d2700e60b 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 139:856d2700e60b 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 139:856d2700e60b 417
<> 139:856d2700e60b 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 139:856d2700e60b 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 139:856d2700e60b 420
<> 139:856d2700e60b 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 139:856d2700e60b 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 139:856d2700e60b 423
<> 139:856d2700e60b 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 139:856d2700e60b 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 139:856d2700e60b 426
<> 139:856d2700e60b 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 139:856d2700e60b 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 139:856d2700e60b 429
<> 139:856d2700e60b 430 /* SCB Interrupt Control State Register Definitions */
<> 139:856d2700e60b 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 139:856d2700e60b 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 139:856d2700e60b 433
<> 139:856d2700e60b 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 139:856d2700e60b 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 139:856d2700e60b 436
<> 139:856d2700e60b 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 139:856d2700e60b 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 139:856d2700e60b 439
<> 139:856d2700e60b 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 139:856d2700e60b 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 139:856d2700e60b 442
<> 139:856d2700e60b 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 139:856d2700e60b 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 139:856d2700e60b 445
<> 139:856d2700e60b 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 139:856d2700e60b 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 139:856d2700e60b 448
<> 139:856d2700e60b 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 139:856d2700e60b 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 139:856d2700e60b 451
<> 139:856d2700e60b 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 139:856d2700e60b 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 139:856d2700e60b 454
<> 139:856d2700e60b 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
<> 139:856d2700e60b 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 139:856d2700e60b 457
<> 139:856d2700e60b 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 139:856d2700e60b 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 139:856d2700e60b 460
<> 139:856d2700e60b 461 /* SCB Vector Table Offset Register Definitions */
<> 139:856d2700e60b 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
<> 139:856d2700e60b 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
<> 139:856d2700e60b 464
<> 139:856d2700e60b 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 139:856d2700e60b 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 139:856d2700e60b 467
<> 139:856d2700e60b 468 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 139:856d2700e60b 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 139:856d2700e60b 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 139:856d2700e60b 471
<> 139:856d2700e60b 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 139:856d2700e60b 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 139:856d2700e60b 474
<> 139:856d2700e60b 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 139:856d2700e60b 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 139:856d2700e60b 477
<> 139:856d2700e60b 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
<> 139:856d2700e60b 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 139:856d2700e60b 480
<> 139:856d2700e60b 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 139:856d2700e60b 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 139:856d2700e60b 483
<> 139:856d2700e60b 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 139:856d2700e60b 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 139:856d2700e60b 486
<> 139:856d2700e60b 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
<> 139:856d2700e60b 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 139:856d2700e60b 489
<> 139:856d2700e60b 490 /* SCB System Control Register Definitions */
<> 139:856d2700e60b 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 139:856d2700e60b 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 139:856d2700e60b 493
<> 139:856d2700e60b 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 139:856d2700e60b 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 139:856d2700e60b 496
<> 139:856d2700e60b 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 139:856d2700e60b 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 139:856d2700e60b 499
<> 139:856d2700e60b 500 /* SCB Configuration Control Register Definitions */
<> 139:856d2700e60b 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 139:856d2700e60b 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 139:856d2700e60b 503
<> 139:856d2700e60b 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
<> 139:856d2700e60b 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 139:856d2700e60b 506
<> 139:856d2700e60b 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
<> 139:856d2700e60b 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 139:856d2700e60b 509
<> 139:856d2700e60b 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 139:856d2700e60b 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 139:856d2700e60b 512
<> 139:856d2700e60b 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
<> 139:856d2700e60b 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 139:856d2700e60b 515
<> 139:856d2700e60b 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
<> 139:856d2700e60b 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 139:856d2700e60b 518
<> 139:856d2700e60b 519 /* SCB System Handler Control and State Register Definitions */
<> 139:856d2700e60b 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
<> 139:856d2700e60b 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 139:856d2700e60b 522
<> 139:856d2700e60b 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
<> 139:856d2700e60b 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 139:856d2700e60b 525
<> 139:856d2700e60b 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
<> 139:856d2700e60b 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 139:856d2700e60b 528
<> 139:856d2700e60b 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 139:856d2700e60b 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 139:856d2700e60b 531
<> 139:856d2700e60b 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 139:856d2700e60b 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 139:856d2700e60b 534
<> 139:856d2700e60b 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 139:856d2700e60b 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 139:856d2700e60b 537
<> 139:856d2700e60b 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 139:856d2700e60b 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 139:856d2700e60b 540
<> 139:856d2700e60b 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
<> 139:856d2700e60b 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 139:856d2700e60b 543
<> 139:856d2700e60b 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
<> 139:856d2700e60b 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 139:856d2700e60b 546
<> 139:856d2700e60b 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
<> 139:856d2700e60b 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 139:856d2700e60b 549
<> 139:856d2700e60b 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
<> 139:856d2700e60b 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 139:856d2700e60b 552
<> 139:856d2700e60b 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
<> 139:856d2700e60b 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 139:856d2700e60b 555
<> 139:856d2700e60b 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
<> 139:856d2700e60b 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 139:856d2700e60b 558
<> 139:856d2700e60b 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
<> 139:856d2700e60b 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 139:856d2700e60b 561
<> 139:856d2700e60b 562 /* SCB Configurable Fault Status Registers Definitions */
<> 139:856d2700e60b 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
<> 139:856d2700e60b 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 139:856d2700e60b 565
<> 139:856d2700e60b 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
<> 139:856d2700e60b 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 139:856d2700e60b 568
<> 139:856d2700e60b 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 139:856d2700e60b 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 139:856d2700e60b 571
<> 139:856d2700e60b 572 /* SCB Hard Fault Status Registers Definitions */
<> 139:856d2700e60b 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
<> 139:856d2700e60b 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 139:856d2700e60b 575
<> 139:856d2700e60b 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
<> 139:856d2700e60b 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 139:856d2700e60b 578
<> 139:856d2700e60b 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
<> 139:856d2700e60b 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 139:856d2700e60b 581
<> 139:856d2700e60b 582 /* SCB Debug Fault Status Register Definitions */
<> 139:856d2700e60b 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
<> 139:856d2700e60b 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 139:856d2700e60b 585
<> 139:856d2700e60b 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
<> 139:856d2700e60b 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 139:856d2700e60b 588
<> 139:856d2700e60b 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
<> 139:856d2700e60b 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 139:856d2700e60b 591
<> 139:856d2700e60b 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
<> 139:856d2700e60b 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 139:856d2700e60b 594
<> 139:856d2700e60b 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
<> 139:856d2700e60b 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 139:856d2700e60b 597
<> 139:856d2700e60b 598 /*@} end of group CMSIS_SCB */
<> 139:856d2700e60b 599
<> 139:856d2700e60b 600
<> 139:856d2700e60b 601 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 139:856d2700e60b 603 \brief Type definitions for the System Control and ID Register not in the SCB
<> 139:856d2700e60b 604 @{
<> 139:856d2700e60b 605 */
<> 139:856d2700e60b 606
<> 139:856d2700e60b 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 139:856d2700e60b 608 */
<> 139:856d2700e60b 609 typedef struct
<> 139:856d2700e60b 610 {
<> 139:856d2700e60b 611 uint32_t RESERVED0[1];
<> 139:856d2700e60b 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
<> 139:856d2700e60b 613 uint32_t RESERVED1[1];
<> 139:856d2700e60b 614 } SCnSCB_Type;
<> 139:856d2700e60b 615
<> 139:856d2700e60b 616 /* Interrupt Controller Type Register Definitions */
<> 139:856d2700e60b 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
<> 139:856d2700e60b 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 139:856d2700e60b 619
<> 139:856d2700e60b 620 /*@} end of group CMSIS_SCnotSCB */
<> 139:856d2700e60b 621
<> 139:856d2700e60b 622
<> 139:856d2700e60b 623 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 139:856d2700e60b 625 \brief Type definitions for the System Timer Registers.
<> 139:856d2700e60b 626 @{
<> 139:856d2700e60b 627 */
<> 139:856d2700e60b 628
<> 139:856d2700e60b 629 /** \brief Structure type to access the System Timer (SysTick).
<> 139:856d2700e60b 630 */
<> 139:856d2700e60b 631 typedef struct
<> 139:856d2700e60b 632 {
<> 139:856d2700e60b 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 139:856d2700e60b 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 139:856d2700e60b 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 139:856d2700e60b 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 139:856d2700e60b 637 } SysTick_Type;
<> 139:856d2700e60b 638
<> 139:856d2700e60b 639 /* SysTick Control / Status Register Definitions */
<> 139:856d2700e60b 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 139:856d2700e60b 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 139:856d2700e60b 642
<> 139:856d2700e60b 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 139:856d2700e60b 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 139:856d2700e60b 645
<> 139:856d2700e60b 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 139:856d2700e60b 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 139:856d2700e60b 648
<> 139:856d2700e60b 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 139:856d2700e60b 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 139:856d2700e60b 651
<> 139:856d2700e60b 652 /* SysTick Reload Register Definitions */
<> 139:856d2700e60b 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 139:856d2700e60b 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 139:856d2700e60b 655
<> 139:856d2700e60b 656 /* SysTick Current Register Definitions */
<> 139:856d2700e60b 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 139:856d2700e60b 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 139:856d2700e60b 659
<> 139:856d2700e60b 660 /* SysTick Calibration Register Definitions */
<> 139:856d2700e60b 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 139:856d2700e60b 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 139:856d2700e60b 663
<> 139:856d2700e60b 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 139:856d2700e60b 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 139:856d2700e60b 666
<> 139:856d2700e60b 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 139:856d2700e60b 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 139:856d2700e60b 669
<> 139:856d2700e60b 670 /*@} end of group CMSIS_SysTick */
<> 139:856d2700e60b 671
<> 139:856d2700e60b 672
<> 139:856d2700e60b 673 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<> 139:856d2700e60b 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 139:856d2700e60b 676 @{
<> 139:856d2700e60b 677 */
<> 139:856d2700e60b 678
<> 139:856d2700e60b 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 139:856d2700e60b 680 */
<> 139:856d2700e60b 681 typedef struct
<> 139:856d2700e60b 682 {
<> 139:856d2700e60b 683 __O union
<> 139:856d2700e60b 684 {
<> 139:856d2700e60b 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
<> 139:856d2700e60b 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
<> 139:856d2700e60b 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
<> 139:856d2700e60b 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
<> 139:856d2700e60b 689 uint32_t RESERVED0[864];
<> 139:856d2700e60b 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
<> 139:856d2700e60b 691 uint32_t RESERVED1[15];
<> 139:856d2700e60b 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
<> 139:856d2700e60b 693 uint32_t RESERVED2[15];
<> 139:856d2700e60b 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
<> 139:856d2700e60b 695 uint32_t RESERVED3[29];
<> 139:856d2700e60b 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
<> 139:856d2700e60b 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
<> 139:856d2700e60b 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
<> 139:856d2700e60b 699 uint32_t RESERVED4[43];
<> 139:856d2700e60b 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
<> 139:856d2700e60b 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
<> 139:856d2700e60b 702 uint32_t RESERVED5[6];
<> 139:856d2700e60b 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
<> 139:856d2700e60b 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
<> 139:856d2700e60b 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
<> 139:856d2700e60b 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
<> 139:856d2700e60b 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
<> 139:856d2700e60b 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
<> 139:856d2700e60b 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
<> 139:856d2700e60b 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
<> 139:856d2700e60b 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
<> 139:856d2700e60b 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
<> 139:856d2700e60b 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
<> 139:856d2700e60b 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 139:856d2700e60b 715 } ITM_Type;
<> 139:856d2700e60b 716
<> 139:856d2700e60b 717 /* ITM Trace Privilege Register Definitions */
<> 139:856d2700e60b 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
<> 139:856d2700e60b 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 139:856d2700e60b 720
<> 139:856d2700e60b 721 /* ITM Trace Control Register Definitions */
<> 139:856d2700e60b 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
<> 139:856d2700e60b 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 139:856d2700e60b 724
<> 139:856d2700e60b 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
<> 139:856d2700e60b 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 139:856d2700e60b 727
<> 139:856d2700e60b 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
<> 139:856d2700e60b 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 139:856d2700e60b 730
<> 139:856d2700e60b 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
<> 139:856d2700e60b 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 139:856d2700e60b 733
<> 139:856d2700e60b 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
<> 139:856d2700e60b 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 139:856d2700e60b 736
<> 139:856d2700e60b 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
<> 139:856d2700e60b 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 139:856d2700e60b 739
<> 139:856d2700e60b 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
<> 139:856d2700e60b 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 139:856d2700e60b 742
<> 139:856d2700e60b 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
<> 139:856d2700e60b 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 139:856d2700e60b 745
<> 139:856d2700e60b 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
<> 139:856d2700e60b 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 139:856d2700e60b 748
<> 139:856d2700e60b 749 /* ITM Integration Write Register Definitions */
<> 139:856d2700e60b 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
<> 139:856d2700e60b 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 139:856d2700e60b 752
<> 139:856d2700e60b 753 /* ITM Integration Read Register Definitions */
<> 139:856d2700e60b 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
<> 139:856d2700e60b 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 139:856d2700e60b 756
<> 139:856d2700e60b 757 /* ITM Integration Mode Control Register Definitions */
<> 139:856d2700e60b 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
<> 139:856d2700e60b 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 139:856d2700e60b 760
<> 139:856d2700e60b 761 /* ITM Lock Status Register Definitions */
<> 139:856d2700e60b 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
<> 139:856d2700e60b 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 139:856d2700e60b 764
<> 139:856d2700e60b 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
<> 139:856d2700e60b 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 139:856d2700e60b 767
<> 139:856d2700e60b 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
<> 139:856d2700e60b 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 139:856d2700e60b 770
<> 139:856d2700e60b 771 /*@}*/ /* end of group CMSIS_ITM */
<> 139:856d2700e60b 772
<> 139:856d2700e60b 773
<> 139:856d2700e60b 774 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<> 139:856d2700e60b 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 139:856d2700e60b 777 @{
<> 139:856d2700e60b 778 */
<> 139:856d2700e60b 779
<> 139:856d2700e60b 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 139:856d2700e60b 781 */
<> 139:856d2700e60b 782 typedef struct
<> 139:856d2700e60b 783 {
<> 139:856d2700e60b 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
<> 139:856d2700e60b 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
<> 139:856d2700e60b 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
<> 139:856d2700e60b 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
<> 139:856d2700e60b 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
<> 139:856d2700e60b 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
<> 139:856d2700e60b 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
<> 139:856d2700e60b 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
<> 139:856d2700e60b 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
<> 139:856d2700e60b 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
<> 139:856d2700e60b 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
<> 139:856d2700e60b 795 uint32_t RESERVED0[1];
<> 139:856d2700e60b 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
<> 139:856d2700e60b 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
<> 139:856d2700e60b 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
<> 139:856d2700e60b 799 uint32_t RESERVED1[1];
<> 139:856d2700e60b 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
<> 139:856d2700e60b 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
<> 139:856d2700e60b 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
<> 139:856d2700e60b 803 uint32_t RESERVED2[1];
<> 139:856d2700e60b 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
<> 139:856d2700e60b 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
<> 139:856d2700e60b 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 139:856d2700e60b 807 } DWT_Type;
<> 139:856d2700e60b 808
<> 139:856d2700e60b 809 /* DWT Control Register Definitions */
<> 139:856d2700e60b 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
<> 139:856d2700e60b 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 139:856d2700e60b 812
<> 139:856d2700e60b 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
<> 139:856d2700e60b 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 139:856d2700e60b 815
<> 139:856d2700e60b 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
<> 139:856d2700e60b 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 139:856d2700e60b 818
<> 139:856d2700e60b 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
<> 139:856d2700e60b 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 139:856d2700e60b 821
<> 139:856d2700e60b 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
<> 139:856d2700e60b 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 139:856d2700e60b 824
<> 139:856d2700e60b 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
<> 139:856d2700e60b 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 139:856d2700e60b 827
<> 139:856d2700e60b 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
<> 139:856d2700e60b 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 139:856d2700e60b 830
<> 139:856d2700e60b 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
<> 139:856d2700e60b 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 139:856d2700e60b 833
<> 139:856d2700e60b 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
<> 139:856d2700e60b 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 139:856d2700e60b 836
<> 139:856d2700e60b 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
<> 139:856d2700e60b 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 139:856d2700e60b 839
<> 139:856d2700e60b 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
<> 139:856d2700e60b 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 139:856d2700e60b 842
<> 139:856d2700e60b 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
<> 139:856d2700e60b 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 139:856d2700e60b 845
<> 139:856d2700e60b 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
<> 139:856d2700e60b 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 139:856d2700e60b 848
<> 139:856d2700e60b 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
<> 139:856d2700e60b 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 139:856d2700e60b 851
<> 139:856d2700e60b 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
<> 139:856d2700e60b 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 139:856d2700e60b 854
<> 139:856d2700e60b 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
<> 139:856d2700e60b 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 139:856d2700e60b 857
<> 139:856d2700e60b 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
<> 139:856d2700e60b 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 139:856d2700e60b 860
<> 139:856d2700e60b 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
<> 139:856d2700e60b 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 139:856d2700e60b 863
<> 139:856d2700e60b 864 /* DWT CPI Count Register Definitions */
<> 139:856d2700e60b 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
<> 139:856d2700e60b 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 139:856d2700e60b 867
<> 139:856d2700e60b 868 /* DWT Exception Overhead Count Register Definitions */
<> 139:856d2700e60b 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
<> 139:856d2700e60b 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 139:856d2700e60b 871
<> 139:856d2700e60b 872 /* DWT Sleep Count Register Definitions */
<> 139:856d2700e60b 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 139:856d2700e60b 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 139:856d2700e60b 875
<> 139:856d2700e60b 876 /* DWT LSU Count Register Definitions */
<> 139:856d2700e60b 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
<> 139:856d2700e60b 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 139:856d2700e60b 879
<> 139:856d2700e60b 880 /* DWT Folded-instruction Count Register Definitions */
<> 139:856d2700e60b 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
<> 139:856d2700e60b 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 139:856d2700e60b 883
<> 139:856d2700e60b 884 /* DWT Comparator Mask Register Definitions */
<> 139:856d2700e60b 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
<> 139:856d2700e60b 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 139:856d2700e60b 887
<> 139:856d2700e60b 888 /* DWT Comparator Function Register Definitions */
<> 139:856d2700e60b 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
<> 139:856d2700e60b 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 139:856d2700e60b 891
<> 139:856d2700e60b 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 139:856d2700e60b 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 139:856d2700e60b 894
<> 139:856d2700e60b 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 139:856d2700e60b 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 139:856d2700e60b 897
<> 139:856d2700e60b 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
<> 139:856d2700e60b 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 139:856d2700e60b 900
<> 139:856d2700e60b 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
<> 139:856d2700e60b 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 139:856d2700e60b 903
<> 139:856d2700e60b 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
<> 139:856d2700e60b 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 139:856d2700e60b 906
<> 139:856d2700e60b 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
<> 139:856d2700e60b 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 139:856d2700e60b 909
<> 139:856d2700e60b 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
<> 139:856d2700e60b 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 139:856d2700e60b 912
<> 139:856d2700e60b 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
<> 139:856d2700e60b 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 139:856d2700e60b 915
<> 139:856d2700e60b 916 /*@}*/ /* end of group CMSIS_DWT */
<> 139:856d2700e60b 917
<> 139:856d2700e60b 918
<> 139:856d2700e60b 919 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
<> 139:856d2700e60b 921 \brief Type definitions for the Trace Port Interface (TPI)
<> 139:856d2700e60b 922 @{
<> 139:856d2700e60b 923 */
<> 139:856d2700e60b 924
<> 139:856d2700e60b 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
<> 139:856d2700e60b 926 */
<> 139:856d2700e60b 927 typedef struct
<> 139:856d2700e60b 928 {
<> 139:856d2700e60b 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
<> 139:856d2700e60b 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
<> 139:856d2700e60b 931 uint32_t RESERVED0[2];
<> 139:856d2700e60b 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
<> 139:856d2700e60b 933 uint32_t RESERVED1[55];
<> 139:856d2700e60b 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
<> 139:856d2700e60b 935 uint32_t RESERVED2[131];
<> 139:856d2700e60b 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
<> 139:856d2700e60b 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
<> 139:856d2700e60b 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
<> 139:856d2700e60b 939 uint32_t RESERVED3[759];
<> 139:856d2700e60b 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
<> 139:856d2700e60b 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
<> 139:856d2700e60b 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
<> 139:856d2700e60b 943 uint32_t RESERVED4[1];
<> 139:856d2700e60b 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
<> 139:856d2700e60b 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
<> 139:856d2700e60b 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
<> 139:856d2700e60b 947 uint32_t RESERVED5[39];
<> 139:856d2700e60b 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
<> 139:856d2700e60b 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
<> 139:856d2700e60b 950 uint32_t RESERVED7[8];
<> 139:856d2700e60b 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
<> 139:856d2700e60b 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 139:856d2700e60b 953 } TPI_Type;
<> 139:856d2700e60b 954
<> 139:856d2700e60b 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
<> 139:856d2700e60b 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
<> 139:856d2700e60b 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 139:856d2700e60b 958
<> 139:856d2700e60b 959 /* TPI Selected Pin Protocol Register Definitions */
<> 139:856d2700e60b 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
<> 139:856d2700e60b 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 139:856d2700e60b 962
<> 139:856d2700e60b 963 /* TPI Formatter and Flush Status Register Definitions */
<> 139:856d2700e60b 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
<> 139:856d2700e60b 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 139:856d2700e60b 966
<> 139:856d2700e60b 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
<> 139:856d2700e60b 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 139:856d2700e60b 969
<> 139:856d2700e60b 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
<> 139:856d2700e60b 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 139:856d2700e60b 972
<> 139:856d2700e60b 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
<> 139:856d2700e60b 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 139:856d2700e60b 975
<> 139:856d2700e60b 976 /* TPI Formatter and Flush Control Register Definitions */
<> 139:856d2700e60b 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
<> 139:856d2700e60b 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 139:856d2700e60b 979
<> 139:856d2700e60b 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
<> 139:856d2700e60b 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 139:856d2700e60b 982
<> 139:856d2700e60b 983 /* TPI TRIGGER Register Definitions */
<> 139:856d2700e60b 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
<> 139:856d2700e60b 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 139:856d2700e60b 986
<> 139:856d2700e60b 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
<> 139:856d2700e60b 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
<> 139:856d2700e60b 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 139:856d2700e60b 990
<> 139:856d2700e60b 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
<> 139:856d2700e60b 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 139:856d2700e60b 993
<> 139:856d2700e60b 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
<> 139:856d2700e60b 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 139:856d2700e60b 996
<> 139:856d2700e60b 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
<> 139:856d2700e60b 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 139:856d2700e60b 999
<> 139:856d2700e60b 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
<> 139:856d2700e60b 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 139:856d2700e60b 1002
<> 139:856d2700e60b 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
<> 139:856d2700e60b 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 139:856d2700e60b 1005
<> 139:856d2700e60b 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
<> 139:856d2700e60b 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 139:856d2700e60b 1008
<> 139:856d2700e60b 1009 /* TPI ITATBCTR2 Register Definitions */
<> 139:856d2700e60b 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
<> 139:856d2700e60b 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 139:856d2700e60b 1012
<> 139:856d2700e60b 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
<> 139:856d2700e60b 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
<> 139:856d2700e60b 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 139:856d2700e60b 1016
<> 139:856d2700e60b 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
<> 139:856d2700e60b 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 139:856d2700e60b 1019
<> 139:856d2700e60b 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
<> 139:856d2700e60b 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 139:856d2700e60b 1022
<> 139:856d2700e60b 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
<> 139:856d2700e60b 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 139:856d2700e60b 1025
<> 139:856d2700e60b 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
<> 139:856d2700e60b 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 139:856d2700e60b 1028
<> 139:856d2700e60b 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
<> 139:856d2700e60b 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 139:856d2700e60b 1031
<> 139:856d2700e60b 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
<> 139:856d2700e60b 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 139:856d2700e60b 1034
<> 139:856d2700e60b 1035 /* TPI ITATBCTR0 Register Definitions */
<> 139:856d2700e60b 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
<> 139:856d2700e60b 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 139:856d2700e60b 1038
<> 139:856d2700e60b 1039 /* TPI Integration Mode Control Register Definitions */
<> 139:856d2700e60b 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
<> 139:856d2700e60b 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 139:856d2700e60b 1042
<> 139:856d2700e60b 1043 /* TPI DEVID Register Definitions */
<> 139:856d2700e60b 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
<> 139:856d2700e60b 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 139:856d2700e60b 1046
<> 139:856d2700e60b 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
<> 139:856d2700e60b 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 139:856d2700e60b 1049
<> 139:856d2700e60b 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
<> 139:856d2700e60b 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 139:856d2700e60b 1052
<> 139:856d2700e60b 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
<> 139:856d2700e60b 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 139:856d2700e60b 1055
<> 139:856d2700e60b 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
<> 139:856d2700e60b 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 139:856d2700e60b 1058
<> 139:856d2700e60b 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
<> 139:856d2700e60b 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 139:856d2700e60b 1061
<> 139:856d2700e60b 1062 /* TPI DEVTYPE Register Definitions */
<> 139:856d2700e60b 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
<> 139:856d2700e60b 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 139:856d2700e60b 1065
<> 139:856d2700e60b 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
<> 139:856d2700e60b 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 139:856d2700e60b 1068
<> 139:856d2700e60b 1069 /*@}*/ /* end of group CMSIS_TPI */
<> 139:856d2700e60b 1070
<> 139:856d2700e60b 1071
<> 139:856d2700e60b 1072 #if (__MPU_PRESENT == 1)
<> 139:856d2700e60b 1073 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 139:856d2700e60b 1075 \brief Type definitions for the Memory Protection Unit (MPU)
<> 139:856d2700e60b 1076 @{
<> 139:856d2700e60b 1077 */
<> 139:856d2700e60b 1078
<> 139:856d2700e60b 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 139:856d2700e60b 1080 */
<> 139:856d2700e60b 1081 typedef struct
<> 139:856d2700e60b 1082 {
<> 139:856d2700e60b 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 139:856d2700e60b 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 139:856d2700e60b 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 139:856d2700e60b 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 139:856d2700e60b 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 139:856d2700e60b 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
<> 139:856d2700e60b 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
<> 139:856d2700e60b 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
<> 139:856d2700e60b 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
<> 139:856d2700e60b 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
<> 139:856d2700e60b 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 139:856d2700e60b 1094 } MPU_Type;
<> 139:856d2700e60b 1095
<> 139:856d2700e60b 1096 /* MPU Type Register */
<> 139:856d2700e60b 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 139:856d2700e60b 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 139:856d2700e60b 1099
<> 139:856d2700e60b 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 139:856d2700e60b 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 139:856d2700e60b 1102
<> 139:856d2700e60b 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 139:856d2700e60b 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 139:856d2700e60b 1105
<> 139:856d2700e60b 1106 /* MPU Control Register */
<> 139:856d2700e60b 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 139:856d2700e60b 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 139:856d2700e60b 1109
<> 139:856d2700e60b 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 139:856d2700e60b 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 139:856d2700e60b 1112
<> 139:856d2700e60b 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 139:856d2700e60b 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 139:856d2700e60b 1115
<> 139:856d2700e60b 1116 /* MPU Region Number Register */
<> 139:856d2700e60b 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 139:856d2700e60b 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 139:856d2700e60b 1119
<> 139:856d2700e60b 1120 /* MPU Region Base Address Register */
<> 139:856d2700e60b 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
<> 139:856d2700e60b 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 139:856d2700e60b 1123
<> 139:856d2700e60b 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 139:856d2700e60b 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 139:856d2700e60b 1126
<> 139:856d2700e60b 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 139:856d2700e60b 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 139:856d2700e60b 1129
<> 139:856d2700e60b 1130 /* MPU Region Attribute and Size Register */
<> 139:856d2700e60b 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 139:856d2700e60b 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 139:856d2700e60b 1133
<> 139:856d2700e60b 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 139:856d2700e60b 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 139:856d2700e60b 1136
<> 139:856d2700e60b 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 139:856d2700e60b 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 139:856d2700e60b 1139
<> 139:856d2700e60b 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 139:856d2700e60b 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 139:856d2700e60b 1142
<> 139:856d2700e60b 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 139:856d2700e60b 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 139:856d2700e60b 1145
<> 139:856d2700e60b 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 139:856d2700e60b 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 139:856d2700e60b 1148
<> 139:856d2700e60b 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 139:856d2700e60b 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 139:856d2700e60b 1151
<> 139:856d2700e60b 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 139:856d2700e60b 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 139:856d2700e60b 1154
<> 139:856d2700e60b 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 139:856d2700e60b 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 139:856d2700e60b 1157
<> 139:856d2700e60b 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 139:856d2700e60b 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 139:856d2700e60b 1160
<> 139:856d2700e60b 1161 /*@} end of group CMSIS_MPU */
<> 139:856d2700e60b 1162 #endif
<> 139:856d2700e60b 1163
<> 139:856d2700e60b 1164
<> 139:856d2700e60b 1165 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 139:856d2700e60b 1167 \brief Type definitions for the Core Debug Registers
<> 139:856d2700e60b 1168 @{
<> 139:856d2700e60b 1169 */
<> 139:856d2700e60b 1170
<> 139:856d2700e60b 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
<> 139:856d2700e60b 1172 */
<> 139:856d2700e60b 1173 typedef struct
<> 139:856d2700e60b 1174 {
<> 139:856d2700e60b 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
<> 139:856d2700e60b 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
<> 139:856d2700e60b 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
<> 139:856d2700e60b 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 139:856d2700e60b 1179 } CoreDebug_Type;
<> 139:856d2700e60b 1180
<> 139:856d2700e60b 1181 /* Debug Halting Control and Status Register */
<> 139:856d2700e60b 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
<> 139:856d2700e60b 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 139:856d2700e60b 1184
<> 139:856d2700e60b 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 139:856d2700e60b 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 139:856d2700e60b 1187
<> 139:856d2700e60b 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 139:856d2700e60b 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 139:856d2700e60b 1190
<> 139:856d2700e60b 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 139:856d2700e60b 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 139:856d2700e60b 1193
<> 139:856d2700e60b 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 139:856d2700e60b 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 139:856d2700e60b 1196
<> 139:856d2700e60b 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
<> 139:856d2700e60b 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 139:856d2700e60b 1199
<> 139:856d2700e60b 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 139:856d2700e60b 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 139:856d2700e60b 1202
<> 139:856d2700e60b 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 139:856d2700e60b 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 139:856d2700e60b 1205
<> 139:856d2700e60b 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 139:856d2700e60b 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 139:856d2700e60b 1208
<> 139:856d2700e60b 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
<> 139:856d2700e60b 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 139:856d2700e60b 1211
<> 139:856d2700e60b 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
<> 139:856d2700e60b 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 139:856d2700e60b 1214
<> 139:856d2700e60b 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 139:856d2700e60b 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 139:856d2700e60b 1217
<> 139:856d2700e60b 1218 /* Debug Core Register Selector Register */
<> 139:856d2700e60b 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
<> 139:856d2700e60b 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 139:856d2700e60b 1221
<> 139:856d2700e60b 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
<> 139:856d2700e60b 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 139:856d2700e60b 1224
<> 139:856d2700e60b 1225 /* Debug Exception and Monitor Control Register */
<> 139:856d2700e60b 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
<> 139:856d2700e60b 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 139:856d2700e60b 1228
<> 139:856d2700e60b 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
<> 139:856d2700e60b 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 139:856d2700e60b 1231
<> 139:856d2700e60b 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
<> 139:856d2700e60b 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 139:856d2700e60b 1234
<> 139:856d2700e60b 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
<> 139:856d2700e60b 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 139:856d2700e60b 1237
<> 139:856d2700e60b 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
<> 139:856d2700e60b 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 139:856d2700e60b 1240
<> 139:856d2700e60b 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 139:856d2700e60b 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 139:856d2700e60b 1243
<> 139:856d2700e60b 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 139:856d2700e60b 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 139:856d2700e60b 1246
<> 139:856d2700e60b 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 139:856d2700e60b 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 139:856d2700e60b 1249
<> 139:856d2700e60b 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 139:856d2700e60b 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 139:856d2700e60b 1252
<> 139:856d2700e60b 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 139:856d2700e60b 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 139:856d2700e60b 1255
<> 139:856d2700e60b 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 139:856d2700e60b 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 139:856d2700e60b 1258
<> 139:856d2700e60b 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 139:856d2700e60b 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 139:856d2700e60b 1261
<> 139:856d2700e60b 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 139:856d2700e60b 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 139:856d2700e60b 1264
<> 139:856d2700e60b 1265 /*@} end of group CMSIS_CoreDebug */
<> 139:856d2700e60b 1266
<> 139:856d2700e60b 1267
<> 139:856d2700e60b 1268 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 1269 \defgroup CMSIS_core_base Core Definitions
<> 139:856d2700e60b 1270 \brief Definitions for base addresses, unions, and structures.
<> 139:856d2700e60b 1271 @{
<> 139:856d2700e60b 1272 */
<> 139:856d2700e60b 1273
<> 139:856d2700e60b 1274 /* Memory mapping of Cortex-M3 Hardware */
<> 139:856d2700e60b 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 139:856d2700e60b 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
<> 139:856d2700e60b 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
<> 139:856d2700e60b 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
<> 139:856d2700e60b 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
<> 139:856d2700e60b 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 139:856d2700e60b 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 139:856d2700e60b 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 139:856d2700e60b 1283
<> 139:856d2700e60b 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 139:856d2700e60b 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 139:856d2700e60b 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 139:856d2700e60b 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 139:856d2700e60b 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
<> 139:856d2700e60b 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
<> 139:856d2700e60b 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
<> 139:856d2700e60b 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 139:856d2700e60b 1292
<> 139:856d2700e60b 1293 #if (__MPU_PRESENT == 1)
<> 139:856d2700e60b 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 139:856d2700e60b 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 139:856d2700e60b 1296 #endif
<> 139:856d2700e60b 1297
<> 139:856d2700e60b 1298 /*@} */
<> 139:856d2700e60b 1299
<> 139:856d2700e60b 1300
<> 139:856d2700e60b 1301
<> 139:856d2700e60b 1302 /*******************************************************************************
<> 139:856d2700e60b 1303 * Hardware Abstraction Layer
<> 139:856d2700e60b 1304 Core Function Interface contains:
<> 139:856d2700e60b 1305 - Core NVIC Functions
<> 139:856d2700e60b 1306 - Core SysTick Functions
<> 139:856d2700e60b 1307 - Core Debug Functions
<> 139:856d2700e60b 1308 - Core Register Access Functions
<> 139:856d2700e60b 1309 ******************************************************************************/
<> 139:856d2700e60b 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 139:856d2700e60b 1311 */
<> 139:856d2700e60b 1312
<> 139:856d2700e60b 1313
<> 139:856d2700e60b 1314
<> 139:856d2700e60b 1315 /* ########################## NVIC functions #################################### */
<> 139:856d2700e60b 1316 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 139:856d2700e60b 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 139:856d2700e60b 1319 @{
<> 139:856d2700e60b 1320 */
<> 139:856d2700e60b 1321
<> 139:856d2700e60b 1322 /** \brief Set Priority Grouping
<> 139:856d2700e60b 1323
<> 139:856d2700e60b 1324 The function sets the priority grouping field using the required unlock sequence.
<> 139:856d2700e60b 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<> 139:856d2700e60b 1326 Only values from 0..7 are used.
<> 139:856d2700e60b 1327 In case of a conflict between priority grouping and available
<> 139:856d2700e60b 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 139:856d2700e60b 1329
<> 139:856d2700e60b 1330 \param [in] PriorityGroup Priority grouping field.
<> 139:856d2700e60b 1331 */
<> 139:856d2700e60b 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 139:856d2700e60b 1333 {
<> 139:856d2700e60b 1334 uint32_t reg_value;
<> 139:856d2700e60b 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 139:856d2700e60b 1336
<> 139:856d2700e60b 1337 reg_value = SCB->AIRCR; /* read old register configuration */
<> 139:856d2700e60b 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 139:856d2700e60b 1339 reg_value = (reg_value |
<> 139:856d2700e60b 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 139:856d2700e60b 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<> 139:856d2700e60b 1342 SCB->AIRCR = reg_value;
<> 139:856d2700e60b 1343 }
<> 139:856d2700e60b 1344
<> 139:856d2700e60b 1345
<> 139:856d2700e60b 1346 /** \brief Get Priority Grouping
<> 139:856d2700e60b 1347
<> 139:856d2700e60b 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
<> 139:856d2700e60b 1349
<> 139:856d2700e60b 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 139:856d2700e60b 1351 */
<> 139:856d2700e60b 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
<> 139:856d2700e60b 1353 {
<> 139:856d2700e60b 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 139:856d2700e60b 1355 }
<> 139:856d2700e60b 1356
<> 139:856d2700e60b 1357
<> 139:856d2700e60b 1358 /** \brief Enable External Interrupt
<> 139:856d2700e60b 1359
<> 139:856d2700e60b 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 139:856d2700e60b 1361
<> 139:856d2700e60b 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 1363 */
<> 139:856d2700e60b 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 1365 {
<> 139:856d2700e60b 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 1367 }
<> 139:856d2700e60b 1368
<> 139:856d2700e60b 1369
<> 139:856d2700e60b 1370 /** \brief Disable External Interrupt
<> 139:856d2700e60b 1371
<> 139:856d2700e60b 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 139:856d2700e60b 1373
<> 139:856d2700e60b 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 1375 */
<> 139:856d2700e60b 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 1377 {
<> 139:856d2700e60b 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 1379 __DSB();
<> 139:856d2700e60b 1380 __ISB();
<> 139:856d2700e60b 1381 }
<> 139:856d2700e60b 1382
<> 139:856d2700e60b 1383
<> 139:856d2700e60b 1384 /** \brief Get Pending Interrupt
<> 139:856d2700e60b 1385
<> 139:856d2700e60b 1386 The function reads the pending register in the NVIC and returns the pending bit
<> 139:856d2700e60b 1387 for the specified interrupt.
<> 139:856d2700e60b 1388
<> 139:856d2700e60b 1389 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 1390
<> 139:856d2700e60b 1391 \return 0 Interrupt status is not pending.
<> 139:856d2700e60b 1392 \return 1 Interrupt status is pending.
<> 139:856d2700e60b 1393 */
<> 139:856d2700e60b 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 1395 {
<> 139:856d2700e60b 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 139:856d2700e60b 1397 }
<> 139:856d2700e60b 1398
<> 139:856d2700e60b 1399
<> 139:856d2700e60b 1400 /** \brief Set Pending Interrupt
<> 139:856d2700e60b 1401
<> 139:856d2700e60b 1402 The function sets the pending bit of an external interrupt.
<> 139:856d2700e60b 1403
<> 139:856d2700e60b 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 139:856d2700e60b 1405 */
<> 139:856d2700e60b 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 1407 {
<> 139:856d2700e60b 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 1409 }
<> 139:856d2700e60b 1410
<> 139:856d2700e60b 1411
<> 139:856d2700e60b 1412 /** \brief Clear Pending Interrupt
<> 139:856d2700e60b 1413
<> 139:856d2700e60b 1414 The function clears the pending bit of an external interrupt.
<> 139:856d2700e60b 1415
<> 139:856d2700e60b 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 1417 */
<> 139:856d2700e60b 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 1419 {
<> 139:856d2700e60b 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 1421 }
<> 139:856d2700e60b 1422
<> 139:856d2700e60b 1423
<> 139:856d2700e60b 1424 /** \brief Get Active Interrupt
<> 139:856d2700e60b 1425
<> 139:856d2700e60b 1426 The function reads the active register in NVIC and returns the active bit.
<> 139:856d2700e60b 1427
<> 139:856d2700e60b 1428 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 1429
<> 139:856d2700e60b 1430 \return 0 Interrupt status is not active.
<> 139:856d2700e60b 1431 \return 1 Interrupt status is active.
<> 139:856d2700e60b 1432 */
<> 139:856d2700e60b 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
<> 139:856d2700e60b 1434 {
<> 139:856d2700e60b 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 139:856d2700e60b 1436 }
<> 139:856d2700e60b 1437
<> 139:856d2700e60b 1438
<> 139:856d2700e60b 1439 /** \brief Set Interrupt Priority
<> 139:856d2700e60b 1440
<> 139:856d2700e60b 1441 The function sets the priority of an interrupt.
<> 139:856d2700e60b 1442
<> 139:856d2700e60b 1443 \note The priority cannot be set for every core interrupt.
<> 139:856d2700e60b 1444
<> 139:856d2700e60b 1445 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 1446 \param [in] priority Priority to set.
<> 139:856d2700e60b 1447 */
<> 139:856d2700e60b 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 139:856d2700e60b 1449 {
<> 139:856d2700e60b 1450 if((int32_t)IRQn < 0) {
<> 139:856d2700e60b 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 139:856d2700e60b 1452 }
<> 139:856d2700e60b 1453 else {
<> 139:856d2700e60b 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 139:856d2700e60b 1455 }
<> 139:856d2700e60b 1456 }
<> 139:856d2700e60b 1457
<> 139:856d2700e60b 1458
<> 139:856d2700e60b 1459 /** \brief Get Interrupt Priority
<> 139:856d2700e60b 1460
<> 139:856d2700e60b 1461 The function reads the priority of an interrupt. The interrupt
<> 139:856d2700e60b 1462 number can be positive to specify an external (device specific)
<> 139:856d2700e60b 1463 interrupt, or negative to specify an internal (core) interrupt.
<> 139:856d2700e60b 1464
<> 139:856d2700e60b 1465
<> 139:856d2700e60b 1466 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 139:856d2700e60b 1468 priority bits of the microcontroller.
<> 139:856d2700e60b 1469 */
<> 139:856d2700e60b 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 139:856d2700e60b 1471 {
<> 139:856d2700e60b 1472
<> 139:856d2700e60b 1473 if((int32_t)IRQn < 0) {
<> 139:856d2700e60b 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<> 139:856d2700e60b 1475 }
<> 139:856d2700e60b 1476 else {
<> 139:856d2700e60b 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<> 139:856d2700e60b 1478 }
<> 139:856d2700e60b 1479 }
<> 139:856d2700e60b 1480
<> 139:856d2700e60b 1481
<> 139:856d2700e60b 1482 /** \brief Encode Priority
<> 139:856d2700e60b 1483
<> 139:856d2700e60b 1484 The function encodes the priority for an interrupt with the given priority group,
<> 139:856d2700e60b 1485 preemptive priority value, and subpriority value.
<> 139:856d2700e60b 1486 In case of a conflict between priority grouping and available
<> 139:856d2700e60b 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 139:856d2700e60b 1488
<> 139:856d2700e60b 1489 \param [in] PriorityGroup Used priority group.
<> 139:856d2700e60b 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
<> 139:856d2700e60b 1491 \param [in] SubPriority Subpriority value (starting from 0).
<> 139:856d2700e60b 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 139:856d2700e60b 1493 */
<> 139:856d2700e60b 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 139:856d2700e60b 1495 {
<> 139:856d2700e60b 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 139:856d2700e60b 1497 uint32_t PreemptPriorityBits;
<> 139:856d2700e60b 1498 uint32_t SubPriorityBits;
<> 139:856d2700e60b 1499
<> 139:856d2700e60b 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 139:856d2700e60b 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 139:856d2700e60b 1502
<> 139:856d2700e60b 1503 return (
<> 139:856d2700e60b 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 139:856d2700e60b 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 139:856d2700e60b 1506 );
<> 139:856d2700e60b 1507 }
<> 139:856d2700e60b 1508
<> 139:856d2700e60b 1509
<> 139:856d2700e60b 1510 /** \brief Decode Priority
<> 139:856d2700e60b 1511
<> 139:856d2700e60b 1512 The function decodes an interrupt priority value with a given priority group to
<> 139:856d2700e60b 1513 preemptive priority value and subpriority value.
<> 139:856d2700e60b 1514 In case of a conflict between priority grouping and available
<> 139:856d2700e60b 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<> 139:856d2700e60b 1516
<> 139:856d2700e60b 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<> 139:856d2700e60b 1518 \param [in] PriorityGroup Used priority group.
<> 139:856d2700e60b 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
<> 139:856d2700e60b 1520 \param [out] pSubPriority Subpriority value (starting from 0).
<> 139:856d2700e60b 1521 */
<> 139:856d2700e60b 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 139:856d2700e60b 1523 {
<> 139:856d2700e60b 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 139:856d2700e60b 1525 uint32_t PreemptPriorityBits;
<> 139:856d2700e60b 1526 uint32_t SubPriorityBits;
<> 139:856d2700e60b 1527
<> 139:856d2700e60b 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 139:856d2700e60b 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 139:856d2700e60b 1530
<> 139:856d2700e60b 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 139:856d2700e60b 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 139:856d2700e60b 1533 }
<> 139:856d2700e60b 1534
<> 139:856d2700e60b 1535
<> 139:856d2700e60b 1536 /** \brief System Reset
<> 139:856d2700e60b 1537
<> 139:856d2700e60b 1538 The function initiates a system reset request to reset the MCU.
<> 139:856d2700e60b 1539 */
<> 139:856d2700e60b 1540 __STATIC_INLINE void NVIC_SystemReset(void)
<> 139:856d2700e60b 1541 {
<> 139:856d2700e60b 1542 __DSB(); /* Ensure all outstanding memory accesses included
<> 139:856d2700e60b 1543 buffered write are completed before reset */
<> 139:856d2700e60b 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 139:856d2700e60b 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 139:856d2700e60b 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 139:856d2700e60b 1547 __DSB(); /* Ensure completion of memory access */
<> 139:856d2700e60b 1548 while(1) { __NOP(); } /* wait until reset */
<> 139:856d2700e60b 1549 }
<> 139:856d2700e60b 1550
<> 139:856d2700e60b 1551 /*@} end of CMSIS_Core_NVICFunctions */
<> 139:856d2700e60b 1552
<> 139:856d2700e60b 1553
<> 139:856d2700e60b 1554
<> 139:856d2700e60b 1555 /* ################################## SysTick function ############################################ */
<> 139:856d2700e60b 1556 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 139:856d2700e60b 1558 \brief Functions that configure the System.
<> 139:856d2700e60b 1559 @{
<> 139:856d2700e60b 1560 */
<> 139:856d2700e60b 1561
<> 139:856d2700e60b 1562 #if (__Vendor_SysTickConfig == 0)
<> 139:856d2700e60b 1563
<> 139:856d2700e60b 1564 /** \brief System Tick Configuration
<> 139:856d2700e60b 1565
<> 139:856d2700e60b 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 139:856d2700e60b 1567 Counter is in free running mode to generate periodic interrupts.
<> 139:856d2700e60b 1568
<> 139:856d2700e60b 1569 \param [in] ticks Number of ticks between two interrupts.
<> 139:856d2700e60b 1570
<> 139:856d2700e60b 1571 \return 0 Function succeeded.
<> 139:856d2700e60b 1572 \return 1 Function failed.
<> 139:856d2700e60b 1573
<> 139:856d2700e60b 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 139:856d2700e60b 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 139:856d2700e60b 1576 must contain a vendor-specific implementation of this function.
<> 139:856d2700e60b 1577
<> 139:856d2700e60b 1578 */
<> 139:856d2700e60b 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 139:856d2700e60b 1580 {
<> 139:856d2700e60b 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 139:856d2700e60b 1582
<> 139:856d2700e60b 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 139:856d2700e60b 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 139:856d2700e60b 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 139:856d2700e60b 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 139:856d2700e60b 1587 SysTick_CTRL_TICKINT_Msk |
<> 139:856d2700e60b 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 139:856d2700e60b 1589 return (0UL); /* Function successful */
<> 139:856d2700e60b 1590 }
<> 139:856d2700e60b 1591
<> 139:856d2700e60b 1592 #endif
<> 139:856d2700e60b 1593
<> 139:856d2700e60b 1594 /*@} end of CMSIS_Core_SysTickFunctions */
<> 139:856d2700e60b 1595
<> 139:856d2700e60b 1596
<> 139:856d2700e60b 1597
<> 139:856d2700e60b 1598 /* ##################################### Debug In/Output function ########################################### */
<> 139:856d2700e60b 1599 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
<> 139:856d2700e60b 1601 \brief Functions that access the ITM debug interface.
<> 139:856d2700e60b 1602 @{
<> 139:856d2700e60b 1603 */
<> 139:856d2700e60b 1604
<> 139:856d2700e60b 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
<> 139:856d2700e60b 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 139:856d2700e60b 1607
<> 139:856d2700e60b 1608
<> 139:856d2700e60b 1609 /** \brief ITM Send Character
<> 139:856d2700e60b 1610
<> 139:856d2700e60b 1611 The function transmits a character via the ITM channel 0, and
<> 139:856d2700e60b 1612 \li Just returns when no debugger is connected that has booked the output.
<> 139:856d2700e60b 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<> 139:856d2700e60b 1614
<> 139:856d2700e60b 1615 \param [in] ch Character to transmit.
<> 139:856d2700e60b 1616
<> 139:856d2700e60b 1617 \returns Character to transmit.
<> 139:856d2700e60b 1618 */
<> 139:856d2700e60b 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 139:856d2700e60b 1620 {
<> 139:856d2700e60b 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 139:856d2700e60b 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 139:856d2700e60b 1623 {
<> 139:856d2700e60b 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<> 139:856d2700e60b 1625 ITM->PORT[0].u8 = (uint8_t)ch;
<> 139:856d2700e60b 1626 }
<> 139:856d2700e60b 1627 return (ch);
<> 139:856d2700e60b 1628 }
<> 139:856d2700e60b 1629
<> 139:856d2700e60b 1630
<> 139:856d2700e60b 1631 /** \brief ITM Receive Character
<> 139:856d2700e60b 1632
<> 139:856d2700e60b 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
<> 139:856d2700e60b 1634
<> 139:856d2700e60b 1635 \return Received character.
<> 139:856d2700e60b 1636 \return -1 No character pending.
<> 139:856d2700e60b 1637 */
<> 139:856d2700e60b 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<> 139:856d2700e60b 1639 int32_t ch = -1; /* no character available */
<> 139:856d2700e60b 1640
<> 139:856d2700e60b 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<> 139:856d2700e60b 1642 ch = ITM_RxBuffer;
<> 139:856d2700e60b 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 139:856d2700e60b 1644 }
<> 139:856d2700e60b 1645
<> 139:856d2700e60b 1646 return (ch);
<> 139:856d2700e60b 1647 }
<> 139:856d2700e60b 1648
<> 139:856d2700e60b 1649
<> 139:856d2700e60b 1650 /** \brief ITM Check Character
<> 139:856d2700e60b 1651
<> 139:856d2700e60b 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<> 139:856d2700e60b 1653
<> 139:856d2700e60b 1654 \return 0 No character available.
<> 139:856d2700e60b 1655 \return 1 Character available.
<> 139:856d2700e60b 1656 */
<> 139:856d2700e60b 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
<> 139:856d2700e60b 1658
<> 139:856d2700e60b 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<> 139:856d2700e60b 1660 return (0); /* no character available */
<> 139:856d2700e60b 1661 } else {
<> 139:856d2700e60b 1662 return (1); /* character available */
<> 139:856d2700e60b 1663 }
<> 139:856d2700e60b 1664 }
<> 139:856d2700e60b 1665
<> 139:856d2700e60b 1666 /*@} end of CMSIS_core_DebugFunctions */
<> 139:856d2700e60b 1667
<> 139:856d2700e60b 1668
<> 139:856d2700e60b 1669
<> 139:856d2700e60b 1670
<> 139:856d2700e60b 1671 #ifdef __cplusplus
<> 139:856d2700e60b 1672 }
<> 139:856d2700e60b 1673 #endif
<> 139:856d2700e60b 1674
<> 139:856d2700e60b 1675 #endif /* __CORE_SC300_H_DEPENDANT */
<> 139:856d2700e60b 1676
<> 139:856d2700e60b 1677 #endif /* __CMSIS_GENERIC */