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TARGET_EFM32PG12_STK3402/core_sc000.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_sc000.h
<> 139:856d2700e60b 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
<> 139:856d2700e60b 4 * @version V4.10
<> 139:856d2700e60b 5 * @date 18. March 2015
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #if defined ( __ICCARM__ )
<> 139:856d2700e60b 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 139:856d2700e60b 40 #endif
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 #ifndef __CORE_SC000_H_GENERIC
<> 139:856d2700e60b 43 #define __CORE_SC000_H_GENERIC
<> 139:856d2700e60b 44
<> 139:856d2700e60b 45 #ifdef __cplusplus
<> 139:856d2700e60b 46 extern "C" {
<> 139:856d2700e60b 47 #endif
<> 139:856d2700e60b 48
<> 139:856d2700e60b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 139:856d2700e60b 50 CMSIS violates the following MISRA-C:2004 rules:
<> 139:856d2700e60b 51
<> 139:856d2700e60b 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 139:856d2700e60b 53 Function definitions in header files are used to allow 'inlining'.
<> 139:856d2700e60b 54
<> 139:856d2700e60b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 139:856d2700e60b 56 Unions are used for effective representation of core registers.
<> 139:856d2700e60b 57
<> 139:856d2700e60b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 139:856d2700e60b 59 Function-like macros are used to allow more efficient code.
<> 139:856d2700e60b 60 */
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62
<> 139:856d2700e60b 63 /*******************************************************************************
<> 139:856d2700e60b 64 * CMSIS definitions
<> 139:856d2700e60b 65 ******************************************************************************/
<> 139:856d2700e60b 66 /** \ingroup SC000
<> 139:856d2700e60b 67 @{
<> 139:856d2700e60b 68 */
<> 139:856d2700e60b 69
<> 139:856d2700e60b 70 /* CMSIS SC000 definitions */
<> 139:856d2700e60b 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 139:856d2700e60b 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 139:856d2700e60b 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
<> 139:856d2700e60b 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 139:856d2700e60b 75
<> 139:856d2700e60b 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
<> 139:856d2700e60b 77
<> 139:856d2700e60b 78
<> 139:856d2700e60b 79 #if defined ( __CC_ARM )
<> 139:856d2700e60b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 139:856d2700e60b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 139:856d2700e60b 82 #define __STATIC_INLINE static __inline
<> 139:856d2700e60b 83
<> 139:856d2700e60b 84 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 139:856d2700e60b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 139:856d2700e60b 87 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 88
<> 139:856d2700e60b 89 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 139:856d2700e60b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 139:856d2700e60b 92 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 93
<> 139:856d2700e60b 94 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 139:856d2700e60b 96 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 97
<> 139:856d2700e60b 98 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 139:856d2700e60b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 139:856d2700e60b 101 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 102
<> 139:856d2700e60b 103 #elif defined ( __CSMC__ )
<> 139:856d2700e60b 104 #define __packed
<> 139:856d2700e60b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 139:856d2700e60b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 139:856d2700e60b 107 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 108
<> 139:856d2700e60b 109 #endif
<> 139:856d2700e60b 110
<> 139:856d2700e60b 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 139:856d2700e60b 112 This core does not support an FPU at all
<> 139:856d2700e60b 113 */
<> 139:856d2700e60b 114 #define __FPU_USED 0
<> 139:856d2700e60b 115
<> 139:856d2700e60b 116 #if defined ( __CC_ARM )
<> 139:856d2700e60b 117 #if defined __TARGET_FPU_VFP
<> 139:856d2700e60b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 119 #endif
<> 139:856d2700e60b 120
<> 139:856d2700e60b 121 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 139:856d2700e60b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 124 #endif
<> 139:856d2700e60b 125
<> 139:856d2700e60b 126 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 127 #if defined __ARMVFP__
<> 139:856d2700e60b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 129 #endif
<> 139:856d2700e60b 130
<> 139:856d2700e60b 131 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 132 #if defined __TI__VFP_SUPPORT____
<> 139:856d2700e60b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 134 #endif
<> 139:856d2700e60b 135
<> 139:856d2700e60b 136 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 137 #if defined __FPU_VFP__
<> 139:856d2700e60b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 139 #endif
<> 139:856d2700e60b 140
<> 139:856d2700e60b 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 139:856d2700e60b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 139:856d2700e60b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 144 #endif
<> 139:856d2700e60b 145 #endif
<> 139:856d2700e60b 146
<> 139:856d2700e60b 147 #include <stdint.h> /* standard types definitions */
<> 139:856d2700e60b 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 139:856d2700e60b 149 #include <core_cmFunc.h> /* Core Function Access */
<> 139:856d2700e60b 150
<> 139:856d2700e60b 151 #ifdef __cplusplus
<> 139:856d2700e60b 152 }
<> 139:856d2700e60b 153 #endif
<> 139:856d2700e60b 154
<> 139:856d2700e60b 155 #endif /* __CORE_SC000_H_GENERIC */
<> 139:856d2700e60b 156
<> 139:856d2700e60b 157 #ifndef __CMSIS_GENERIC
<> 139:856d2700e60b 158
<> 139:856d2700e60b 159 #ifndef __CORE_SC000_H_DEPENDANT
<> 139:856d2700e60b 160 #define __CORE_SC000_H_DEPENDANT
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 #ifdef __cplusplus
<> 139:856d2700e60b 163 extern "C" {
<> 139:856d2700e60b 164 #endif
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 /* check device defines and use defaults */
<> 139:856d2700e60b 167 #if defined __CHECK_DEVICE_DEFINES
<> 139:856d2700e60b 168 #ifndef __SC000_REV
<> 139:856d2700e60b 169 #define __SC000_REV 0x0000
<> 139:856d2700e60b 170 #warning "__SC000_REV not defined in device header file; using default!"
<> 139:856d2700e60b 171 #endif
<> 139:856d2700e60b 172
<> 139:856d2700e60b 173 #ifndef __MPU_PRESENT
<> 139:856d2700e60b 174 #define __MPU_PRESENT 0
<> 139:856d2700e60b 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 139:856d2700e60b 176 #endif
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 #ifndef __NVIC_PRIO_BITS
<> 139:856d2700e60b 179 #define __NVIC_PRIO_BITS 2
<> 139:856d2700e60b 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 139:856d2700e60b 181 #endif
<> 139:856d2700e60b 182
<> 139:856d2700e60b 183 #ifndef __Vendor_SysTickConfig
<> 139:856d2700e60b 184 #define __Vendor_SysTickConfig 0
<> 139:856d2700e60b 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 139:856d2700e60b 186 #endif
<> 139:856d2700e60b 187 #endif
<> 139:856d2700e60b 188
<> 139:856d2700e60b 189 /* IO definitions (access restrictions to peripheral registers) */
<> 139:856d2700e60b 190 /**
<> 139:856d2700e60b 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 139:856d2700e60b 192
<> 139:856d2700e60b 193 <strong>IO Type Qualifiers</strong> are used
<> 139:856d2700e60b 194 \li to specify the access to peripheral variables.
<> 139:856d2700e60b 195 \li for automatic generation of peripheral register debug information.
<> 139:856d2700e60b 196 */
<> 139:856d2700e60b 197 #ifdef __cplusplus
<> 139:856d2700e60b 198 #define __I volatile /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 199 #else
<> 139:856d2700e60b 200 #define __I volatile const /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 201 #endif
<> 139:856d2700e60b 202 #define __O volatile /*!< Defines 'write only' permissions */
<> 139:856d2700e60b 203 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 139:856d2700e60b 204
<> 139:856d2700e60b 205 /*@} end of group SC000 */
<> 139:856d2700e60b 206
<> 139:856d2700e60b 207
<> 139:856d2700e60b 208
<> 139:856d2700e60b 209 /*******************************************************************************
<> 139:856d2700e60b 210 * Register Abstraction
<> 139:856d2700e60b 211 Core Register contain:
<> 139:856d2700e60b 212 - Core Register
<> 139:856d2700e60b 213 - Core NVIC Register
<> 139:856d2700e60b 214 - Core SCB Register
<> 139:856d2700e60b 215 - Core SysTick Register
<> 139:856d2700e60b 216 - Core MPU Register
<> 139:856d2700e60b 217 ******************************************************************************/
<> 139:856d2700e60b 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 139:856d2700e60b 219 \brief Type definitions and defines for Cortex-M processor based devices.
<> 139:856d2700e60b 220 */
<> 139:856d2700e60b 221
<> 139:856d2700e60b 222 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 223 \defgroup CMSIS_CORE Status and Control Registers
<> 139:856d2700e60b 224 \brief Core Register type definitions.
<> 139:856d2700e60b 225 @{
<> 139:856d2700e60b 226 */
<> 139:856d2700e60b 227
<> 139:856d2700e60b 228 /** \brief Union type to access the Application Program Status Register (APSR).
<> 139:856d2700e60b 229 */
<> 139:856d2700e60b 230 typedef union
<> 139:856d2700e60b 231 {
<> 139:856d2700e60b 232 struct
<> 139:856d2700e60b 233 {
<> 139:856d2700e60b 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 139:856d2700e60b 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 239 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 240 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 241 } APSR_Type;
<> 139:856d2700e60b 242
<> 139:856d2700e60b 243 /* APSR Register Definitions */
<> 139:856d2700e60b 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 139:856d2700e60b 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 139:856d2700e60b 246
<> 139:856d2700e60b 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 139:856d2700e60b 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 139:856d2700e60b 249
<> 139:856d2700e60b 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 139:856d2700e60b 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 139:856d2700e60b 252
<> 139:856d2700e60b 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 139:856d2700e60b 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 139:856d2700e60b 255
<> 139:856d2700e60b 256
<> 139:856d2700e60b 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 139:856d2700e60b 258 */
<> 139:856d2700e60b 259 typedef union
<> 139:856d2700e60b 260 {
<> 139:856d2700e60b 261 struct
<> 139:856d2700e60b 262 {
<> 139:856d2700e60b 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 139:856d2700e60b 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 139:856d2700e60b 265 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 266 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 267 } IPSR_Type;
<> 139:856d2700e60b 268
<> 139:856d2700e60b 269 /* IPSR Register Definitions */
<> 139:856d2700e60b 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 139:856d2700e60b 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 139:856d2700e60b 272
<> 139:856d2700e60b 273
<> 139:856d2700e60b 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 139:856d2700e60b 275 */
<> 139:856d2700e60b 276 typedef union
<> 139:856d2700e60b 277 {
<> 139:856d2700e60b 278 struct
<> 139:856d2700e60b 279 {
<> 139:856d2700e60b 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 139:856d2700e60b 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 139:856d2700e60b 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 139:856d2700e60b 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 139:856d2700e60b 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 288 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 289 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 290 } xPSR_Type;
<> 139:856d2700e60b 291
<> 139:856d2700e60b 292 /* xPSR Register Definitions */
<> 139:856d2700e60b 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 139:856d2700e60b 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 139:856d2700e60b 295
<> 139:856d2700e60b 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 139:856d2700e60b 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 139:856d2700e60b 298
<> 139:856d2700e60b 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 139:856d2700e60b 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 139:856d2700e60b 301
<> 139:856d2700e60b 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 139:856d2700e60b 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 139:856d2700e60b 304
<> 139:856d2700e60b 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 139:856d2700e60b 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 139:856d2700e60b 307
<> 139:856d2700e60b 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 139:856d2700e60b 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 139:856d2700e60b 310
<> 139:856d2700e60b 311
<> 139:856d2700e60b 312 /** \brief Union type to access the Control Registers (CONTROL).
<> 139:856d2700e60b 313 */
<> 139:856d2700e60b 314 typedef union
<> 139:856d2700e60b 315 {
<> 139:856d2700e60b 316 struct
<> 139:856d2700e60b 317 {
<> 139:856d2700e60b 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
<> 139:856d2700e60b 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 139:856d2700e60b 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 139:856d2700e60b 321 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 322 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 323 } CONTROL_Type;
<> 139:856d2700e60b 324
<> 139:856d2700e60b 325 /* CONTROL Register Definitions */
<> 139:856d2700e60b 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 139:856d2700e60b 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 139:856d2700e60b 328
<> 139:856d2700e60b 329 /*@} end of group CMSIS_CORE */
<> 139:856d2700e60b 330
<> 139:856d2700e60b 331
<> 139:856d2700e60b 332 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 139:856d2700e60b 334 \brief Type definitions for the NVIC Registers
<> 139:856d2700e60b 335 @{
<> 139:856d2700e60b 336 */
<> 139:856d2700e60b 337
<> 139:856d2700e60b 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 139:856d2700e60b 339 */
<> 139:856d2700e60b 340 typedef struct
<> 139:856d2700e60b 341 {
<> 139:856d2700e60b 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 139:856d2700e60b 343 uint32_t RESERVED0[31];
<> 139:856d2700e60b 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 139:856d2700e60b 345 uint32_t RSERVED1[31];
<> 139:856d2700e60b 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 139:856d2700e60b 347 uint32_t RESERVED2[31];
<> 139:856d2700e60b 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 139:856d2700e60b 349 uint32_t RESERVED3[31];
<> 139:856d2700e60b 350 uint32_t RESERVED4[64];
<> 139:856d2700e60b 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 139:856d2700e60b 352 } NVIC_Type;
<> 139:856d2700e60b 353
<> 139:856d2700e60b 354 /*@} end of group CMSIS_NVIC */
<> 139:856d2700e60b 355
<> 139:856d2700e60b 356
<> 139:856d2700e60b 357 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 358 \defgroup CMSIS_SCB System Control Block (SCB)
<> 139:856d2700e60b 359 \brief Type definitions for the System Control Block Registers
<> 139:856d2700e60b 360 @{
<> 139:856d2700e60b 361 */
<> 139:856d2700e60b 362
<> 139:856d2700e60b 363 /** \brief Structure type to access the System Control Block (SCB).
<> 139:856d2700e60b 364 */
<> 139:856d2700e60b 365 typedef struct
<> 139:856d2700e60b 366 {
<> 139:856d2700e60b 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 139:856d2700e60b 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 139:856d2700e60b 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 139:856d2700e60b 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 139:856d2700e60b 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 139:856d2700e60b 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 139:856d2700e60b 373 uint32_t RESERVED0[1];
<> 139:856d2700e60b 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 139:856d2700e60b 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 139:856d2700e60b 376 uint32_t RESERVED1[154];
<> 139:856d2700e60b 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
<> 139:856d2700e60b 378 } SCB_Type;
<> 139:856d2700e60b 379
<> 139:856d2700e60b 380 /* SCB CPUID Register Definitions */
<> 139:856d2700e60b 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 139:856d2700e60b 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 139:856d2700e60b 383
<> 139:856d2700e60b 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 139:856d2700e60b 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 139:856d2700e60b 386
<> 139:856d2700e60b 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 139:856d2700e60b 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 139:856d2700e60b 389
<> 139:856d2700e60b 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 139:856d2700e60b 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 139:856d2700e60b 392
<> 139:856d2700e60b 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 139:856d2700e60b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 139:856d2700e60b 395
<> 139:856d2700e60b 396 /* SCB Interrupt Control State Register Definitions */
<> 139:856d2700e60b 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 139:856d2700e60b 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 139:856d2700e60b 399
<> 139:856d2700e60b 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 139:856d2700e60b 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 139:856d2700e60b 402
<> 139:856d2700e60b 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 139:856d2700e60b 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 139:856d2700e60b 405
<> 139:856d2700e60b 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 139:856d2700e60b 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 139:856d2700e60b 408
<> 139:856d2700e60b 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 139:856d2700e60b 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 139:856d2700e60b 411
<> 139:856d2700e60b 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 139:856d2700e60b 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 139:856d2700e60b 414
<> 139:856d2700e60b 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 139:856d2700e60b 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 139:856d2700e60b 417
<> 139:856d2700e60b 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 139:856d2700e60b 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 139:856d2700e60b 420
<> 139:856d2700e60b 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 139:856d2700e60b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 139:856d2700e60b 423
<> 139:856d2700e60b 424 /* SCB Interrupt Control State Register Definitions */
<> 139:856d2700e60b 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 139:856d2700e60b 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 139:856d2700e60b 427
<> 139:856d2700e60b 428 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 139:856d2700e60b 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 139:856d2700e60b 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 139:856d2700e60b 431
<> 139:856d2700e60b 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 139:856d2700e60b 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 139:856d2700e60b 434
<> 139:856d2700e60b 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 139:856d2700e60b 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 139:856d2700e60b 437
<> 139:856d2700e60b 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 139:856d2700e60b 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 139:856d2700e60b 440
<> 139:856d2700e60b 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 139:856d2700e60b 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 139:856d2700e60b 443
<> 139:856d2700e60b 444 /* SCB System Control Register Definitions */
<> 139:856d2700e60b 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 139:856d2700e60b 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 139:856d2700e60b 447
<> 139:856d2700e60b 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 139:856d2700e60b 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 139:856d2700e60b 450
<> 139:856d2700e60b 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 139:856d2700e60b 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 139:856d2700e60b 453
<> 139:856d2700e60b 454 /* SCB Configuration Control Register Definitions */
<> 139:856d2700e60b 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 139:856d2700e60b 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 139:856d2700e60b 457
<> 139:856d2700e60b 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 139:856d2700e60b 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 139:856d2700e60b 460
<> 139:856d2700e60b 461 /* SCB System Handler Control and State Register Definitions */
<> 139:856d2700e60b 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 139:856d2700e60b 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 139:856d2700e60b 464
<> 139:856d2700e60b 465 /*@} end of group CMSIS_SCB */
<> 139:856d2700e60b 466
<> 139:856d2700e60b 467
<> 139:856d2700e60b 468 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 139:856d2700e60b 470 \brief Type definitions for the System Control and ID Register not in the SCB
<> 139:856d2700e60b 471 @{
<> 139:856d2700e60b 472 */
<> 139:856d2700e60b 473
<> 139:856d2700e60b 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 139:856d2700e60b 475 */
<> 139:856d2700e60b 476 typedef struct
<> 139:856d2700e60b 477 {
<> 139:856d2700e60b 478 uint32_t RESERVED0[2];
<> 139:856d2700e60b 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
<> 139:856d2700e60b 480 } SCnSCB_Type;
<> 139:856d2700e60b 481
<> 139:856d2700e60b 482 /* Auxiliary Control Register Definitions */
<> 139:856d2700e60b 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
<> 139:856d2700e60b 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
<> 139:856d2700e60b 485
<> 139:856d2700e60b 486 /*@} end of group CMSIS_SCnotSCB */
<> 139:856d2700e60b 487
<> 139:856d2700e60b 488
<> 139:856d2700e60b 489 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 139:856d2700e60b 491 \brief Type definitions for the System Timer Registers.
<> 139:856d2700e60b 492 @{
<> 139:856d2700e60b 493 */
<> 139:856d2700e60b 494
<> 139:856d2700e60b 495 /** \brief Structure type to access the System Timer (SysTick).
<> 139:856d2700e60b 496 */
<> 139:856d2700e60b 497 typedef struct
<> 139:856d2700e60b 498 {
<> 139:856d2700e60b 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 139:856d2700e60b 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 139:856d2700e60b 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 139:856d2700e60b 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 139:856d2700e60b 503 } SysTick_Type;
<> 139:856d2700e60b 504
<> 139:856d2700e60b 505 /* SysTick Control / Status Register Definitions */
<> 139:856d2700e60b 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 139:856d2700e60b 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 139:856d2700e60b 508
<> 139:856d2700e60b 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 139:856d2700e60b 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 139:856d2700e60b 511
<> 139:856d2700e60b 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 139:856d2700e60b 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 139:856d2700e60b 514
<> 139:856d2700e60b 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 139:856d2700e60b 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 139:856d2700e60b 517
<> 139:856d2700e60b 518 /* SysTick Reload Register Definitions */
<> 139:856d2700e60b 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 139:856d2700e60b 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 139:856d2700e60b 521
<> 139:856d2700e60b 522 /* SysTick Current Register Definitions */
<> 139:856d2700e60b 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 139:856d2700e60b 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 139:856d2700e60b 525
<> 139:856d2700e60b 526 /* SysTick Calibration Register Definitions */
<> 139:856d2700e60b 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 139:856d2700e60b 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 139:856d2700e60b 529
<> 139:856d2700e60b 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 139:856d2700e60b 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 139:856d2700e60b 532
<> 139:856d2700e60b 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 139:856d2700e60b 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 139:856d2700e60b 535
<> 139:856d2700e60b 536 /*@} end of group CMSIS_SysTick */
<> 139:856d2700e60b 537
<> 139:856d2700e60b 538 #if (__MPU_PRESENT == 1)
<> 139:856d2700e60b 539 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 139:856d2700e60b 541 \brief Type definitions for the Memory Protection Unit (MPU)
<> 139:856d2700e60b 542 @{
<> 139:856d2700e60b 543 */
<> 139:856d2700e60b 544
<> 139:856d2700e60b 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 139:856d2700e60b 546 */
<> 139:856d2700e60b 547 typedef struct
<> 139:856d2700e60b 548 {
<> 139:856d2700e60b 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 139:856d2700e60b 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 139:856d2700e60b 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 139:856d2700e60b 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 139:856d2700e60b 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 139:856d2700e60b 554 } MPU_Type;
<> 139:856d2700e60b 555
<> 139:856d2700e60b 556 /* MPU Type Register */
<> 139:856d2700e60b 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 139:856d2700e60b 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 139:856d2700e60b 559
<> 139:856d2700e60b 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 139:856d2700e60b 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 139:856d2700e60b 562
<> 139:856d2700e60b 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 139:856d2700e60b 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 139:856d2700e60b 565
<> 139:856d2700e60b 566 /* MPU Control Register */
<> 139:856d2700e60b 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 139:856d2700e60b 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 139:856d2700e60b 569
<> 139:856d2700e60b 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 139:856d2700e60b 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 139:856d2700e60b 572
<> 139:856d2700e60b 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 139:856d2700e60b 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 139:856d2700e60b 575
<> 139:856d2700e60b 576 /* MPU Region Number Register */
<> 139:856d2700e60b 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 139:856d2700e60b 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 139:856d2700e60b 579
<> 139:856d2700e60b 580 /* MPU Region Base Address Register */
<> 139:856d2700e60b 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 139:856d2700e60b 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 139:856d2700e60b 583
<> 139:856d2700e60b 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 139:856d2700e60b 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 139:856d2700e60b 586
<> 139:856d2700e60b 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 139:856d2700e60b 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 139:856d2700e60b 589
<> 139:856d2700e60b 590 /* MPU Region Attribute and Size Register */
<> 139:856d2700e60b 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 139:856d2700e60b 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 139:856d2700e60b 593
<> 139:856d2700e60b 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 139:856d2700e60b 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 139:856d2700e60b 596
<> 139:856d2700e60b 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 139:856d2700e60b 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 139:856d2700e60b 599
<> 139:856d2700e60b 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 139:856d2700e60b 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 139:856d2700e60b 602
<> 139:856d2700e60b 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 139:856d2700e60b 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 139:856d2700e60b 605
<> 139:856d2700e60b 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 139:856d2700e60b 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 139:856d2700e60b 608
<> 139:856d2700e60b 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 139:856d2700e60b 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 139:856d2700e60b 611
<> 139:856d2700e60b 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 139:856d2700e60b 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 139:856d2700e60b 614
<> 139:856d2700e60b 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 139:856d2700e60b 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 139:856d2700e60b 617
<> 139:856d2700e60b 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 139:856d2700e60b 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 139:856d2700e60b 620
<> 139:856d2700e60b 621 /*@} end of group CMSIS_MPU */
<> 139:856d2700e60b 622 #endif
<> 139:856d2700e60b 623
<> 139:856d2700e60b 624
<> 139:856d2700e60b 625 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 139:856d2700e60b 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 139:856d2700e60b 628 are only accessible over DAP and not via processor. Therefore
<> 139:856d2700e60b 629 they are not covered by the Cortex-M0 header file.
<> 139:856d2700e60b 630 @{
<> 139:856d2700e60b 631 */
<> 139:856d2700e60b 632 /*@} end of group CMSIS_CoreDebug */
<> 139:856d2700e60b 633
<> 139:856d2700e60b 634
<> 139:856d2700e60b 635 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 636 \defgroup CMSIS_core_base Core Definitions
<> 139:856d2700e60b 637 \brief Definitions for base addresses, unions, and structures.
<> 139:856d2700e60b 638 @{
<> 139:856d2700e60b 639 */
<> 139:856d2700e60b 640
<> 139:856d2700e60b 641 /* Memory mapping of SC000 Hardware */
<> 139:856d2700e60b 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 139:856d2700e60b 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 139:856d2700e60b 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 139:856d2700e60b 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 139:856d2700e60b 646
<> 139:856d2700e60b 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 139:856d2700e60b 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 139:856d2700e60b 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 139:856d2700e60b 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 139:856d2700e60b 651
<> 139:856d2700e60b 652 #if (__MPU_PRESENT == 1)
<> 139:856d2700e60b 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 139:856d2700e60b 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 139:856d2700e60b 655 #endif
<> 139:856d2700e60b 656
<> 139:856d2700e60b 657 /*@} */
<> 139:856d2700e60b 658
<> 139:856d2700e60b 659
<> 139:856d2700e60b 660
<> 139:856d2700e60b 661 /*******************************************************************************
<> 139:856d2700e60b 662 * Hardware Abstraction Layer
<> 139:856d2700e60b 663 Core Function Interface contains:
<> 139:856d2700e60b 664 - Core NVIC Functions
<> 139:856d2700e60b 665 - Core SysTick Functions
<> 139:856d2700e60b 666 - Core Register Access Functions
<> 139:856d2700e60b 667 ******************************************************************************/
<> 139:856d2700e60b 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 139:856d2700e60b 669 */
<> 139:856d2700e60b 670
<> 139:856d2700e60b 671
<> 139:856d2700e60b 672
<> 139:856d2700e60b 673 /* ########################## NVIC functions #################################### */
<> 139:856d2700e60b 674 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 139:856d2700e60b 676 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 139:856d2700e60b 677 @{
<> 139:856d2700e60b 678 */
<> 139:856d2700e60b 679
<> 139:856d2700e60b 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 139:856d2700e60b 681 /* The following MACROS handle generation of the register offset and byte masks */
<> 139:856d2700e60b 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 139:856d2700e60b 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 139:856d2700e60b 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 139:856d2700e60b 685
<> 139:856d2700e60b 686
<> 139:856d2700e60b 687 /** \brief Enable External Interrupt
<> 139:856d2700e60b 688
<> 139:856d2700e60b 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 139:856d2700e60b 690
<> 139:856d2700e60b 691 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 692 */
<> 139:856d2700e60b 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 694 {
<> 139:856d2700e60b 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 696 }
<> 139:856d2700e60b 697
<> 139:856d2700e60b 698
<> 139:856d2700e60b 699 /** \brief Disable External Interrupt
<> 139:856d2700e60b 700
<> 139:856d2700e60b 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 139:856d2700e60b 702
<> 139:856d2700e60b 703 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 704 */
<> 139:856d2700e60b 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 706 {
<> 139:856d2700e60b 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 708 __DSB();
<> 139:856d2700e60b 709 __ISB();
<> 139:856d2700e60b 710 }
<> 139:856d2700e60b 711
<> 139:856d2700e60b 712
<> 139:856d2700e60b 713 /** \brief Get Pending Interrupt
<> 139:856d2700e60b 714
<> 139:856d2700e60b 715 The function reads the pending register in the NVIC and returns the pending bit
<> 139:856d2700e60b 716 for the specified interrupt.
<> 139:856d2700e60b 717
<> 139:856d2700e60b 718 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 719
<> 139:856d2700e60b 720 \return 0 Interrupt status is not pending.
<> 139:856d2700e60b 721 \return 1 Interrupt status is pending.
<> 139:856d2700e60b 722 */
<> 139:856d2700e60b 723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 724 {
<> 139:856d2700e60b 725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 139:856d2700e60b 726 }
<> 139:856d2700e60b 727
<> 139:856d2700e60b 728
<> 139:856d2700e60b 729 /** \brief Set Pending Interrupt
<> 139:856d2700e60b 730
<> 139:856d2700e60b 731 The function sets the pending bit of an external interrupt.
<> 139:856d2700e60b 732
<> 139:856d2700e60b 733 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 139:856d2700e60b 734 */
<> 139:856d2700e60b 735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 736 {
<> 139:856d2700e60b 737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 738 }
<> 139:856d2700e60b 739
<> 139:856d2700e60b 740
<> 139:856d2700e60b 741 /** \brief Clear Pending Interrupt
<> 139:856d2700e60b 742
<> 139:856d2700e60b 743 The function clears the pending bit of an external interrupt.
<> 139:856d2700e60b 744
<> 139:856d2700e60b 745 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 746 */
<> 139:856d2700e60b 747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 748 {
<> 139:856d2700e60b 749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 750 }
<> 139:856d2700e60b 751
<> 139:856d2700e60b 752
<> 139:856d2700e60b 753 /** \brief Set Interrupt Priority
<> 139:856d2700e60b 754
<> 139:856d2700e60b 755 The function sets the priority of an interrupt.
<> 139:856d2700e60b 756
<> 139:856d2700e60b 757 \note The priority cannot be set for every core interrupt.
<> 139:856d2700e60b 758
<> 139:856d2700e60b 759 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 760 \param [in] priority Priority to set.
<> 139:856d2700e60b 761 */
<> 139:856d2700e60b 762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 139:856d2700e60b 763 {
<> 139:856d2700e60b 764 if((int32_t)(IRQn) < 0) {
<> 139:856d2700e60b 765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 139:856d2700e60b 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 139:856d2700e60b 767 }
<> 139:856d2700e60b 768 else {
<> 139:856d2700e60b 769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 139:856d2700e60b 770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 139:856d2700e60b 771 }
<> 139:856d2700e60b 772 }
<> 139:856d2700e60b 773
<> 139:856d2700e60b 774
<> 139:856d2700e60b 775 /** \brief Get Interrupt Priority
<> 139:856d2700e60b 776
<> 139:856d2700e60b 777 The function reads the priority of an interrupt. The interrupt
<> 139:856d2700e60b 778 number can be positive to specify an external (device specific)
<> 139:856d2700e60b 779 interrupt, or negative to specify an internal (core) interrupt.
<> 139:856d2700e60b 780
<> 139:856d2700e60b 781
<> 139:856d2700e60b 782 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 783 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 139:856d2700e60b 784 priority bits of the microcontroller.
<> 139:856d2700e60b 785 */
<> 139:856d2700e60b 786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 139:856d2700e60b 787 {
<> 139:856d2700e60b 788
<> 139:856d2700e60b 789 if((int32_t)(IRQn) < 0) {
<> 139:856d2700e60b 790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 139:856d2700e60b 791 }
<> 139:856d2700e60b 792 else {
<> 139:856d2700e60b 793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 139:856d2700e60b 794 }
<> 139:856d2700e60b 795 }
<> 139:856d2700e60b 796
<> 139:856d2700e60b 797
<> 139:856d2700e60b 798 /** \brief System Reset
<> 139:856d2700e60b 799
<> 139:856d2700e60b 800 The function initiates a system reset request to reset the MCU.
<> 139:856d2700e60b 801 */
<> 139:856d2700e60b 802 __STATIC_INLINE void NVIC_SystemReset(void)
<> 139:856d2700e60b 803 {
<> 139:856d2700e60b 804 __DSB(); /* Ensure all outstanding memory accesses included
<> 139:856d2700e60b 805 buffered write are completed before reset */
<> 139:856d2700e60b 806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 139:856d2700e60b 807 SCB_AIRCR_SYSRESETREQ_Msk);
<> 139:856d2700e60b 808 __DSB(); /* Ensure completion of memory access */
<> 139:856d2700e60b 809 while(1) { __NOP(); } /* wait until reset */
<> 139:856d2700e60b 810 }
<> 139:856d2700e60b 811
<> 139:856d2700e60b 812 /*@} end of CMSIS_Core_NVICFunctions */
<> 139:856d2700e60b 813
<> 139:856d2700e60b 814
<> 139:856d2700e60b 815
<> 139:856d2700e60b 816 /* ################################## SysTick function ############################################ */
<> 139:856d2700e60b 817 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 139:856d2700e60b 819 \brief Functions that configure the System.
<> 139:856d2700e60b 820 @{
<> 139:856d2700e60b 821 */
<> 139:856d2700e60b 822
<> 139:856d2700e60b 823 #if (__Vendor_SysTickConfig == 0)
<> 139:856d2700e60b 824
<> 139:856d2700e60b 825 /** \brief System Tick Configuration
<> 139:856d2700e60b 826
<> 139:856d2700e60b 827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 139:856d2700e60b 828 Counter is in free running mode to generate periodic interrupts.
<> 139:856d2700e60b 829
<> 139:856d2700e60b 830 \param [in] ticks Number of ticks between two interrupts.
<> 139:856d2700e60b 831
<> 139:856d2700e60b 832 \return 0 Function succeeded.
<> 139:856d2700e60b 833 \return 1 Function failed.
<> 139:856d2700e60b 834
<> 139:856d2700e60b 835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 139:856d2700e60b 836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 139:856d2700e60b 837 must contain a vendor-specific implementation of this function.
<> 139:856d2700e60b 838
<> 139:856d2700e60b 839 */
<> 139:856d2700e60b 840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 139:856d2700e60b 841 {
<> 139:856d2700e60b 842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 139:856d2700e60b 843
<> 139:856d2700e60b 844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 139:856d2700e60b 845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 139:856d2700e60b 846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 139:856d2700e60b 847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 139:856d2700e60b 848 SysTick_CTRL_TICKINT_Msk |
<> 139:856d2700e60b 849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 139:856d2700e60b 850 return (0UL); /* Function successful */
<> 139:856d2700e60b 851 }
<> 139:856d2700e60b 852
<> 139:856d2700e60b 853 #endif
<> 139:856d2700e60b 854
<> 139:856d2700e60b 855 /*@} end of CMSIS_Core_SysTickFunctions */
<> 139:856d2700e60b 856
<> 139:856d2700e60b 857
<> 139:856d2700e60b 858
<> 139:856d2700e60b 859
<> 139:856d2700e60b 860 #ifdef __cplusplus
<> 139:856d2700e60b 861 }
<> 139:856d2700e60b 862 #endif
<> 139:856d2700e60b 863
<> 139:856d2700e60b 864 #endif /* __CORE_SC000_H_DEPENDANT */
<> 139:856d2700e60b 865
<> 139:856d2700e60b 866 #endif /* __CMSIS_GENERIC */