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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/core_cmInstr.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_cmInstr.h
<> 139:856d2700e60b 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
<> 139:856d2700e60b 4 * @version V4.10
<> 139:856d2700e60b 5 * @date 18. March 2015
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #ifndef __CORE_CMINSTR_H
<> 139:856d2700e60b 39 #define __CORE_CMINSTR_H
<> 139:856d2700e60b 40
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 /* ########################## Core Instruction Access ######################### */
<> 139:856d2700e60b 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
<> 139:856d2700e60b 44 Access to dedicated instructions
<> 139:856d2700e60b 45 @{
<> 139:856d2700e60b 46 */
<> 139:856d2700e60b 47
<> 139:856d2700e60b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 139:856d2700e60b 49 /* ARM armcc specific functions */
<> 139:856d2700e60b 50
<> 139:856d2700e60b 51 #if (__ARMCC_VERSION < 400677)
<> 139:856d2700e60b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 139:856d2700e60b 53 #endif
<> 139:856d2700e60b 54
<> 139:856d2700e60b 55
<> 139:856d2700e60b 56 /** \brief No Operation
<> 139:856d2700e60b 57
<> 139:856d2700e60b 58 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 139:856d2700e60b 59 */
<> 139:856d2700e60b 60 #define __NOP __nop
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62
<> 139:856d2700e60b 63 /** \brief Wait For Interrupt
<> 139:856d2700e60b 64
<> 139:856d2700e60b 65 Wait For Interrupt is a hint instruction that suspends execution
<> 139:856d2700e60b 66 until one of a number of events occurs.
<> 139:856d2700e60b 67 */
<> 139:856d2700e60b 68 #define __WFI __wfi
<> 139:856d2700e60b 69
<> 139:856d2700e60b 70
<> 139:856d2700e60b 71 /** \brief Wait For Event
<> 139:856d2700e60b 72
<> 139:856d2700e60b 73 Wait For Event is a hint instruction that permits the processor to enter
<> 139:856d2700e60b 74 a low-power state until one of a number of events occurs.
<> 139:856d2700e60b 75 */
<> 139:856d2700e60b 76 #define __WFE __wfe
<> 139:856d2700e60b 77
<> 139:856d2700e60b 78
<> 139:856d2700e60b 79 /** \brief Send Event
<> 139:856d2700e60b 80
<> 139:856d2700e60b 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 139:856d2700e60b 82 */
<> 139:856d2700e60b 83 #define __SEV __sev
<> 139:856d2700e60b 84
<> 139:856d2700e60b 85
<> 139:856d2700e60b 86 /** \brief Instruction Synchronization Barrier
<> 139:856d2700e60b 87
<> 139:856d2700e60b 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 139:856d2700e60b 89 so that all instructions following the ISB are fetched from cache or
<> 139:856d2700e60b 90 memory, after the instruction has been completed.
<> 139:856d2700e60b 91 */
<> 139:856d2700e60b 92 #define __ISB() do {\
<> 139:856d2700e60b 93 __schedule_barrier();\
<> 139:856d2700e60b 94 __isb(0xF);\
<> 139:856d2700e60b 95 __schedule_barrier();\
<> 139:856d2700e60b 96 } while (0)
<> 139:856d2700e60b 97
<> 139:856d2700e60b 98 /** \brief Data Synchronization Barrier
<> 139:856d2700e60b 99
<> 139:856d2700e60b 100 This function acts as a special kind of Data Memory Barrier.
<> 139:856d2700e60b 101 It completes when all explicit memory accesses before this instruction complete.
<> 139:856d2700e60b 102 */
<> 139:856d2700e60b 103 #define __DSB() do {\
<> 139:856d2700e60b 104 __schedule_barrier();\
<> 139:856d2700e60b 105 __dsb(0xF);\
<> 139:856d2700e60b 106 __schedule_barrier();\
<> 139:856d2700e60b 107 } while (0)
<> 139:856d2700e60b 108
<> 139:856d2700e60b 109 /** \brief Data Memory Barrier
<> 139:856d2700e60b 110
<> 139:856d2700e60b 111 This function ensures the apparent order of the explicit memory operations before
<> 139:856d2700e60b 112 and after the instruction, without ensuring their completion.
<> 139:856d2700e60b 113 */
<> 139:856d2700e60b 114 #define __DMB() do {\
<> 139:856d2700e60b 115 __schedule_barrier();\
<> 139:856d2700e60b 116 __dmb(0xF);\
<> 139:856d2700e60b 117 __schedule_barrier();\
<> 139:856d2700e60b 118 } while (0)
<> 139:856d2700e60b 119
<> 139:856d2700e60b 120 /** \brief Reverse byte order (32 bit)
<> 139:856d2700e60b 121
<> 139:856d2700e60b 122 This function reverses the byte order in integer value.
<> 139:856d2700e60b 123
<> 139:856d2700e60b 124 \param [in] value Value to reverse
<> 139:856d2700e60b 125 \return Reversed value
<> 139:856d2700e60b 126 */
<> 139:856d2700e60b 127 #define __REV __rev
<> 139:856d2700e60b 128
<> 139:856d2700e60b 129
<> 139:856d2700e60b 130 /** \brief Reverse byte order (16 bit)
<> 139:856d2700e60b 131
<> 139:856d2700e60b 132 This function reverses the byte order in two unsigned short values.
<> 139:856d2700e60b 133
<> 139:856d2700e60b 134 \param [in] value Value to reverse
<> 139:856d2700e60b 135 \return Reversed value
<> 139:856d2700e60b 136 */
<> 139:856d2700e60b 137 #ifndef __NO_EMBEDDED_ASM
<> 139:856d2700e60b 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
<> 139:856d2700e60b 139 {
<> 139:856d2700e60b 140 rev16 r0, r0
<> 139:856d2700e60b 141 bx lr
<> 139:856d2700e60b 142 }
<> 139:856d2700e60b 143 #endif
<> 139:856d2700e60b 144
<> 139:856d2700e60b 145 /** \brief Reverse byte order in signed short value
<> 139:856d2700e60b 146
<> 139:856d2700e60b 147 This function reverses the byte order in a signed short value with sign extension to integer.
<> 139:856d2700e60b 148
<> 139:856d2700e60b 149 \param [in] value Value to reverse
<> 139:856d2700e60b 150 \return Reversed value
<> 139:856d2700e60b 151 */
<> 139:856d2700e60b 152 #ifndef __NO_EMBEDDED_ASM
<> 139:856d2700e60b 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
<> 139:856d2700e60b 154 {
<> 139:856d2700e60b 155 revsh r0, r0
<> 139:856d2700e60b 156 bx lr
<> 139:856d2700e60b 157 }
<> 139:856d2700e60b 158 #endif
<> 139:856d2700e60b 159
<> 139:856d2700e60b 160
<> 139:856d2700e60b 161 /** \brief Rotate Right in unsigned value (32 bit)
<> 139:856d2700e60b 162
<> 139:856d2700e60b 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 139:856d2700e60b 164
<> 139:856d2700e60b 165 \param [in] value Value to rotate
<> 139:856d2700e60b 166 \param [in] value Number of Bits to rotate
<> 139:856d2700e60b 167 \return Rotated value
<> 139:856d2700e60b 168 */
<> 139:856d2700e60b 169 #define __ROR __ror
<> 139:856d2700e60b 170
<> 139:856d2700e60b 171
<> 139:856d2700e60b 172 /** \brief Breakpoint
<> 139:856d2700e60b 173
<> 139:856d2700e60b 174 This function causes the processor to enter Debug state.
<> 139:856d2700e60b 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 139:856d2700e60b 176
<> 139:856d2700e60b 177 \param [in] value is ignored by the processor.
<> 139:856d2700e60b 178 If required, a debugger can use it to store additional information about the breakpoint.
<> 139:856d2700e60b 179 */
<> 139:856d2700e60b 180 #define __BKPT(value) __breakpoint(value)
<> 139:856d2700e60b 181
<> 139:856d2700e60b 182
<> 139:856d2700e60b 183 /** \brief Reverse bit order of value
<> 139:856d2700e60b 184
<> 139:856d2700e60b 185 This function reverses the bit order of the given value.
<> 139:856d2700e60b 186
<> 139:856d2700e60b 187 \param [in] value Value to reverse
<> 139:856d2700e60b 188 \return Reversed value
<> 139:856d2700e60b 189 */
<> 139:856d2700e60b 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 139:856d2700e60b 191 #define __RBIT __rbit
<> 139:856d2700e60b 192 #else
<> 139:856d2700e60b 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 139:856d2700e60b 194 {
<> 139:856d2700e60b 195 uint32_t result;
<> 139:856d2700e60b 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 139:856d2700e60b 197
<> 139:856d2700e60b 198 result = value; // r will be reversed bits of v; first get LSB of v
<> 139:856d2700e60b 199 for (value >>= 1; value; value >>= 1)
<> 139:856d2700e60b 200 {
<> 139:856d2700e60b 201 result <<= 1;
<> 139:856d2700e60b 202 result |= value & 1;
<> 139:856d2700e60b 203 s--;
<> 139:856d2700e60b 204 }
<> 139:856d2700e60b 205 result <<= s; // shift when v's highest bits are zero
<> 139:856d2700e60b 206 return(result);
<> 139:856d2700e60b 207 }
<> 139:856d2700e60b 208 #endif
<> 139:856d2700e60b 209
<> 139:856d2700e60b 210
<> 139:856d2700e60b 211 /** \brief Count leading zeros
<> 139:856d2700e60b 212
<> 139:856d2700e60b 213 This function counts the number of leading zeros of a data value.
<> 139:856d2700e60b 214
<> 139:856d2700e60b 215 \param [in] value Value to count the leading zeros
<> 139:856d2700e60b 216 \return number of leading zeros in value
<> 139:856d2700e60b 217 */
<> 139:856d2700e60b 218 #define __CLZ __clz
<> 139:856d2700e60b 219
<> 139:856d2700e60b 220
<> 139:856d2700e60b 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 139:856d2700e60b 222
<> 139:856d2700e60b 223 /** \brief LDR Exclusive (8 bit)
<> 139:856d2700e60b 224
<> 139:856d2700e60b 225 This function executes a exclusive LDR instruction for 8 bit value.
<> 139:856d2700e60b 226
<> 139:856d2700e60b 227 \param [in] ptr Pointer to data
<> 139:856d2700e60b 228 \return value of type uint8_t at (*ptr)
<> 139:856d2700e60b 229 */
<> 139:856d2700e60b 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
<> 139:856d2700e60b 231
<> 139:856d2700e60b 232
<> 139:856d2700e60b 233 /** \brief LDR Exclusive (16 bit)
<> 139:856d2700e60b 234
<> 139:856d2700e60b 235 This function executes a exclusive LDR instruction for 16 bit values.
<> 139:856d2700e60b 236
<> 139:856d2700e60b 237 \param [in] ptr Pointer to data
<> 139:856d2700e60b 238 \return value of type uint16_t at (*ptr)
<> 139:856d2700e60b 239 */
<> 139:856d2700e60b 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
<> 139:856d2700e60b 241
<> 139:856d2700e60b 242
<> 139:856d2700e60b 243 /** \brief LDR Exclusive (32 bit)
<> 139:856d2700e60b 244
<> 139:856d2700e60b 245 This function executes a exclusive LDR instruction for 32 bit values.
<> 139:856d2700e60b 246
<> 139:856d2700e60b 247 \param [in] ptr Pointer to data
<> 139:856d2700e60b 248 \return value of type uint32_t at (*ptr)
<> 139:856d2700e60b 249 */
<> 139:856d2700e60b 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
<> 139:856d2700e60b 251
<> 139:856d2700e60b 252
<> 139:856d2700e60b 253 /** \brief STR Exclusive (8 bit)
<> 139:856d2700e60b 254
<> 139:856d2700e60b 255 This function executes a exclusive STR instruction for 8 bit values.
<> 139:856d2700e60b 256
<> 139:856d2700e60b 257 \param [in] value Value to store
<> 139:856d2700e60b 258 \param [in] ptr Pointer to location
<> 139:856d2700e60b 259 \return 0 Function succeeded
<> 139:856d2700e60b 260 \return 1 Function failed
<> 139:856d2700e60b 261 */
<> 139:856d2700e60b 262 #define __STREXB(value, ptr) __strex(value, ptr)
<> 139:856d2700e60b 263
<> 139:856d2700e60b 264
<> 139:856d2700e60b 265 /** \brief STR Exclusive (16 bit)
<> 139:856d2700e60b 266
<> 139:856d2700e60b 267 This function executes a exclusive STR instruction for 16 bit values.
<> 139:856d2700e60b 268
<> 139:856d2700e60b 269 \param [in] value Value to store
<> 139:856d2700e60b 270 \param [in] ptr Pointer to location
<> 139:856d2700e60b 271 \return 0 Function succeeded
<> 139:856d2700e60b 272 \return 1 Function failed
<> 139:856d2700e60b 273 */
<> 139:856d2700e60b 274 #define __STREXH(value, ptr) __strex(value, ptr)
<> 139:856d2700e60b 275
<> 139:856d2700e60b 276
<> 139:856d2700e60b 277 /** \brief STR Exclusive (32 bit)
<> 139:856d2700e60b 278
<> 139:856d2700e60b 279 This function executes a exclusive STR instruction for 32 bit values.
<> 139:856d2700e60b 280
<> 139:856d2700e60b 281 \param [in] value Value to store
<> 139:856d2700e60b 282 \param [in] ptr Pointer to location
<> 139:856d2700e60b 283 \return 0 Function succeeded
<> 139:856d2700e60b 284 \return 1 Function failed
<> 139:856d2700e60b 285 */
<> 139:856d2700e60b 286 #define __STREXW(value, ptr) __strex(value, ptr)
<> 139:856d2700e60b 287
<> 139:856d2700e60b 288
<> 139:856d2700e60b 289 /** \brief Remove the exclusive lock
<> 139:856d2700e60b 290
<> 139:856d2700e60b 291 This function removes the exclusive lock which is created by LDREX.
<> 139:856d2700e60b 292
<> 139:856d2700e60b 293 */
<> 139:856d2700e60b 294 #define __CLREX __clrex
<> 139:856d2700e60b 295
<> 139:856d2700e60b 296
<> 139:856d2700e60b 297 /** \brief Signed Saturate
<> 139:856d2700e60b 298
<> 139:856d2700e60b 299 This function saturates a signed value.
<> 139:856d2700e60b 300
<> 139:856d2700e60b 301 \param [in] value Value to be saturated
<> 139:856d2700e60b 302 \param [in] sat Bit position to saturate to (1..32)
<> 139:856d2700e60b 303 \return Saturated value
<> 139:856d2700e60b 304 */
<> 139:856d2700e60b 305 #define __SSAT __ssat
<> 139:856d2700e60b 306
<> 139:856d2700e60b 307
<> 139:856d2700e60b 308 /** \brief Unsigned Saturate
<> 139:856d2700e60b 309
<> 139:856d2700e60b 310 This function saturates an unsigned value.
<> 139:856d2700e60b 311
<> 139:856d2700e60b 312 \param [in] value Value to be saturated
<> 139:856d2700e60b 313 \param [in] sat Bit position to saturate to (0..31)
<> 139:856d2700e60b 314 \return Saturated value
<> 139:856d2700e60b 315 */
<> 139:856d2700e60b 316 #define __USAT __usat
<> 139:856d2700e60b 317
<> 139:856d2700e60b 318
<> 139:856d2700e60b 319 /** \brief Rotate Right with Extend (32 bit)
<> 139:856d2700e60b 320
<> 139:856d2700e60b 321 This function moves each bit of a bitstring right by one bit.
<> 139:856d2700e60b 322 The carry input is shifted in at the left end of the bitstring.
<> 139:856d2700e60b 323
<> 139:856d2700e60b 324 \param [in] value Value to rotate
<> 139:856d2700e60b 325 \return Rotated value
<> 139:856d2700e60b 326 */
<> 139:856d2700e60b 327 #ifndef __NO_EMBEDDED_ASM
<> 139:856d2700e60b 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
<> 139:856d2700e60b 329 {
<> 139:856d2700e60b 330 rrx r0, r0
<> 139:856d2700e60b 331 bx lr
<> 139:856d2700e60b 332 }
<> 139:856d2700e60b 333 #endif
<> 139:856d2700e60b 334
<> 139:856d2700e60b 335
<> 139:856d2700e60b 336 /** \brief LDRT Unprivileged (8 bit)
<> 139:856d2700e60b 337
<> 139:856d2700e60b 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 139:856d2700e60b 339
<> 139:856d2700e60b 340 \param [in] ptr Pointer to data
<> 139:856d2700e60b 341 \return value of type uint8_t at (*ptr)
<> 139:856d2700e60b 342 */
<> 139:856d2700e60b 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<> 139:856d2700e60b 344
<> 139:856d2700e60b 345
<> 139:856d2700e60b 346 /** \brief LDRT Unprivileged (16 bit)
<> 139:856d2700e60b 347
<> 139:856d2700e60b 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 139:856d2700e60b 349
<> 139:856d2700e60b 350 \param [in] ptr Pointer to data
<> 139:856d2700e60b 351 \return value of type uint16_t at (*ptr)
<> 139:856d2700e60b 352 */
<> 139:856d2700e60b 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<> 139:856d2700e60b 354
<> 139:856d2700e60b 355
<> 139:856d2700e60b 356 /** \brief LDRT Unprivileged (32 bit)
<> 139:856d2700e60b 357
<> 139:856d2700e60b 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 139:856d2700e60b 359
<> 139:856d2700e60b 360 \param [in] ptr Pointer to data
<> 139:856d2700e60b 361 \return value of type uint32_t at (*ptr)
<> 139:856d2700e60b 362 */
<> 139:856d2700e60b 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<> 139:856d2700e60b 364
<> 139:856d2700e60b 365
<> 139:856d2700e60b 366 /** \brief STRT Unprivileged (8 bit)
<> 139:856d2700e60b 367
<> 139:856d2700e60b 368 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 139:856d2700e60b 369
<> 139:856d2700e60b 370 \param [in] value Value to store
<> 139:856d2700e60b 371 \param [in] ptr Pointer to location
<> 139:856d2700e60b 372 */
<> 139:856d2700e60b 373 #define __STRBT(value, ptr) __strt(value, ptr)
<> 139:856d2700e60b 374
<> 139:856d2700e60b 375
<> 139:856d2700e60b 376 /** \brief STRT Unprivileged (16 bit)
<> 139:856d2700e60b 377
<> 139:856d2700e60b 378 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 139:856d2700e60b 379
<> 139:856d2700e60b 380 \param [in] value Value to store
<> 139:856d2700e60b 381 \param [in] ptr Pointer to location
<> 139:856d2700e60b 382 */
<> 139:856d2700e60b 383 #define __STRHT(value, ptr) __strt(value, ptr)
<> 139:856d2700e60b 384
<> 139:856d2700e60b 385
<> 139:856d2700e60b 386 /** \brief STRT Unprivileged (32 bit)
<> 139:856d2700e60b 387
<> 139:856d2700e60b 388 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 139:856d2700e60b 389
<> 139:856d2700e60b 390 \param [in] value Value to store
<> 139:856d2700e60b 391 \param [in] ptr Pointer to location
<> 139:856d2700e60b 392 */
<> 139:856d2700e60b 393 #define __STRT(value, ptr) __strt(value, ptr)
<> 139:856d2700e60b 394
<> 139:856d2700e60b 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 139:856d2700e60b 396
<> 139:856d2700e60b 397
<> 139:856d2700e60b 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 139:856d2700e60b 399 /* GNU gcc specific functions */
<> 139:856d2700e60b 400
<> 139:856d2700e60b 401 /* Define macros for porting to both thumb1 and thumb2.
<> 139:856d2700e60b 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
<> 139:856d2700e60b 403 * Otherwise, use general registers, specified by constrant "r" */
<> 139:856d2700e60b 404 #if defined (__thumb__) && !defined (__thumb2__)
<> 139:856d2700e60b 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
<> 139:856d2700e60b 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
<> 139:856d2700e60b 407 #else
<> 139:856d2700e60b 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
<> 139:856d2700e60b 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
<> 139:856d2700e60b 410 #endif
<> 139:856d2700e60b 411
<> 139:856d2700e60b 412 /** \brief No Operation
<> 139:856d2700e60b 413
<> 139:856d2700e60b 414 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 139:856d2700e60b 415 */
<> 139:856d2700e60b 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
<> 139:856d2700e60b 417 {
<> 139:856d2700e60b 418 __ASM volatile ("nop");
<> 139:856d2700e60b 419 }
<> 139:856d2700e60b 420
<> 139:856d2700e60b 421
<> 139:856d2700e60b 422 /** \brief Wait For Interrupt
<> 139:856d2700e60b 423
<> 139:856d2700e60b 424 Wait For Interrupt is a hint instruction that suspends execution
<> 139:856d2700e60b 425 until one of a number of events occurs.
<> 139:856d2700e60b 426 */
<> 139:856d2700e60b 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
<> 139:856d2700e60b 428 {
<> 139:856d2700e60b 429 __ASM volatile ("wfi");
<> 139:856d2700e60b 430 }
<> 139:856d2700e60b 431
<> 139:856d2700e60b 432
<> 139:856d2700e60b 433 /** \brief Wait For Event
<> 139:856d2700e60b 434
<> 139:856d2700e60b 435 Wait For Event is a hint instruction that permits the processor to enter
<> 139:856d2700e60b 436 a low-power state until one of a number of events occurs.
<> 139:856d2700e60b 437 */
<> 139:856d2700e60b 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
<> 139:856d2700e60b 439 {
<> 139:856d2700e60b 440 __ASM volatile ("wfe");
<> 139:856d2700e60b 441 }
<> 139:856d2700e60b 442
<> 139:856d2700e60b 443
<> 139:856d2700e60b 444 /** \brief Send Event
<> 139:856d2700e60b 445
<> 139:856d2700e60b 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 139:856d2700e60b 447 */
<> 139:856d2700e60b 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
<> 139:856d2700e60b 449 {
<> 139:856d2700e60b 450 __ASM volatile ("sev");
<> 139:856d2700e60b 451 }
<> 139:856d2700e60b 452
<> 139:856d2700e60b 453
<> 139:856d2700e60b 454 /** \brief Instruction Synchronization Barrier
<> 139:856d2700e60b 455
<> 139:856d2700e60b 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 139:856d2700e60b 457 so that all instructions following the ISB are fetched from cache or
<> 139:856d2700e60b 458 memory, after the instruction has been completed.
<> 139:856d2700e60b 459 */
<> 139:856d2700e60b 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
<> 139:856d2700e60b 461 {
<> 139:856d2700e60b 462 __ASM volatile ("isb 0xF":::"memory");
<> 139:856d2700e60b 463 }
<> 139:856d2700e60b 464
<> 139:856d2700e60b 465
<> 139:856d2700e60b 466 /** \brief Data Synchronization Barrier
<> 139:856d2700e60b 467
<> 139:856d2700e60b 468 This function acts as a special kind of Data Memory Barrier.
<> 139:856d2700e60b 469 It completes when all explicit memory accesses before this instruction complete.
<> 139:856d2700e60b 470 */
<> 139:856d2700e60b 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
<> 139:856d2700e60b 472 {
<> 139:856d2700e60b 473 __ASM volatile ("dsb 0xF":::"memory");
<> 139:856d2700e60b 474 }
<> 139:856d2700e60b 475
<> 139:856d2700e60b 476
<> 139:856d2700e60b 477 /** \brief Data Memory Barrier
<> 139:856d2700e60b 478
<> 139:856d2700e60b 479 This function ensures the apparent order of the explicit memory operations before
<> 139:856d2700e60b 480 and after the instruction, without ensuring their completion.
<> 139:856d2700e60b 481 */
<> 139:856d2700e60b 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
<> 139:856d2700e60b 483 {
<> 139:856d2700e60b 484 __ASM volatile ("dmb 0xF":::"memory");
<> 139:856d2700e60b 485 }
<> 139:856d2700e60b 486
<> 139:856d2700e60b 487
<> 139:856d2700e60b 488 /** \brief Reverse byte order (32 bit)
<> 139:856d2700e60b 489
<> 139:856d2700e60b 490 This function reverses the byte order in integer value.
<> 139:856d2700e60b 491
<> 139:856d2700e60b 492 \param [in] value Value to reverse
<> 139:856d2700e60b 493 \return Reversed value
<> 139:856d2700e60b 494 */
<> 139:856d2700e60b 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
<> 139:856d2700e60b 496 {
<> 139:856d2700e60b 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
<> 139:856d2700e60b 498 return __builtin_bswap32(value);
<> 139:856d2700e60b 499 #else
<> 139:856d2700e60b 500 uint32_t result;
<> 139:856d2700e60b 501
<> 139:856d2700e60b 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 139:856d2700e60b 503 return(result);
<> 139:856d2700e60b 504 #endif
<> 139:856d2700e60b 505 }
<> 139:856d2700e60b 506
<> 139:856d2700e60b 507
<> 139:856d2700e60b 508 /** \brief Reverse byte order (16 bit)
<> 139:856d2700e60b 509
<> 139:856d2700e60b 510 This function reverses the byte order in two unsigned short values.
<> 139:856d2700e60b 511
<> 139:856d2700e60b 512 \param [in] value Value to reverse
<> 139:856d2700e60b 513 \return Reversed value
<> 139:856d2700e60b 514 */
<> 139:856d2700e60b 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
<> 139:856d2700e60b 516 {
<> 139:856d2700e60b 517 uint32_t result;
<> 139:856d2700e60b 518
<> 139:856d2700e60b 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 139:856d2700e60b 520 return(result);
<> 139:856d2700e60b 521 }
<> 139:856d2700e60b 522
<> 139:856d2700e60b 523
<> 139:856d2700e60b 524 /** \brief Reverse byte order in signed short value
<> 139:856d2700e60b 525
<> 139:856d2700e60b 526 This function reverses the byte order in a signed short value with sign extension to integer.
<> 139:856d2700e60b 527
<> 139:856d2700e60b 528 \param [in] value Value to reverse
<> 139:856d2700e60b 529 \return Reversed value
<> 139:856d2700e60b 530 */
<> 139:856d2700e60b 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
<> 139:856d2700e60b 532 {
<> 139:856d2700e60b 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 139:856d2700e60b 534 return (short)__builtin_bswap16(value);
<> 139:856d2700e60b 535 #else
<> 139:856d2700e60b 536 uint32_t result;
<> 139:856d2700e60b 537
<> 139:856d2700e60b 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 139:856d2700e60b 539 return(result);
<> 139:856d2700e60b 540 #endif
<> 139:856d2700e60b 541 }
<> 139:856d2700e60b 542
<> 139:856d2700e60b 543
<> 139:856d2700e60b 544 /** \brief Rotate Right in unsigned value (32 bit)
<> 139:856d2700e60b 545
<> 139:856d2700e60b 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 139:856d2700e60b 547
<> 139:856d2700e60b 548 \param [in] value Value to rotate
<> 139:856d2700e60b 549 \param [in] value Number of Bits to rotate
<> 139:856d2700e60b 550 \return Rotated value
<> 139:856d2700e60b 551 */
<> 139:856d2700e60b 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 553 {
<> 139:856d2700e60b 554 return (op1 >> op2) | (op1 << (32 - op2));
<> 139:856d2700e60b 555 }
<> 139:856d2700e60b 556
<> 139:856d2700e60b 557
<> 139:856d2700e60b 558 /** \brief Breakpoint
<> 139:856d2700e60b 559
<> 139:856d2700e60b 560 This function causes the processor to enter Debug state.
<> 139:856d2700e60b 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 139:856d2700e60b 562
<> 139:856d2700e60b 563 \param [in] value is ignored by the processor.
<> 139:856d2700e60b 564 If required, a debugger can use it to store additional information about the breakpoint.
<> 139:856d2700e60b 565 */
<> 139:856d2700e60b 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
<> 139:856d2700e60b 567
<> 139:856d2700e60b 568
<> 139:856d2700e60b 569 /** \brief Reverse bit order of value
<> 139:856d2700e60b 570
<> 139:856d2700e60b 571 This function reverses the bit order of the given value.
<> 139:856d2700e60b 572
<> 139:856d2700e60b 573 \param [in] value Value to reverse
<> 139:856d2700e60b 574 \return Reversed value
<> 139:856d2700e60b 575 */
<> 139:856d2700e60b 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 139:856d2700e60b 577 {
<> 139:856d2700e60b 578 uint32_t result;
<> 139:856d2700e60b 579
<> 139:856d2700e60b 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 139:856d2700e60b 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
<> 139:856d2700e60b 582 #else
<> 139:856d2700e60b 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 139:856d2700e60b 584
<> 139:856d2700e60b 585 result = value; // r will be reversed bits of v; first get LSB of v
<> 139:856d2700e60b 586 for (value >>= 1; value; value >>= 1)
<> 139:856d2700e60b 587 {
<> 139:856d2700e60b 588 result <<= 1;
<> 139:856d2700e60b 589 result |= value & 1;
<> 139:856d2700e60b 590 s--;
<> 139:856d2700e60b 591 }
<> 139:856d2700e60b 592 result <<= s; // shift when v's highest bits are zero
<> 139:856d2700e60b 593 #endif
<> 139:856d2700e60b 594 return(result);
<> 139:856d2700e60b 595 }
<> 139:856d2700e60b 596
<> 139:856d2700e60b 597
<> 139:856d2700e60b 598 /** \brief Count leading zeros
<> 139:856d2700e60b 599
<> 139:856d2700e60b 600 This function counts the number of leading zeros of a data value.
<> 139:856d2700e60b 601
<> 139:856d2700e60b 602 \param [in] value Value to count the leading zeros
<> 139:856d2700e60b 603 \return number of leading zeros in value
<> 139:856d2700e60b 604 */
<> 139:856d2700e60b 605 #define __CLZ __builtin_clz
<> 139:856d2700e60b 606
<> 139:856d2700e60b 607
<> 139:856d2700e60b 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 139:856d2700e60b 609
<> 139:856d2700e60b 610 /** \brief LDR Exclusive (8 bit)
<> 139:856d2700e60b 611
<> 139:856d2700e60b 612 This function executes a exclusive LDR instruction for 8 bit value.
<> 139:856d2700e60b 613
<> 139:856d2700e60b 614 \param [in] ptr Pointer to data
<> 139:856d2700e60b 615 \return value of type uint8_t at (*ptr)
<> 139:856d2700e60b 616 */
<> 139:856d2700e60b 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
<> 139:856d2700e60b 618 {
<> 139:856d2700e60b 619 uint32_t result;
<> 139:856d2700e60b 620
<> 139:856d2700e60b 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 139:856d2700e60b 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
<> 139:856d2700e60b 623 #else
<> 139:856d2700e60b 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 139:856d2700e60b 625 accepted by assembler. So has to use following less efficient pattern.
<> 139:856d2700e60b 626 */
<> 139:856d2700e60b 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 139:856d2700e60b 628 #endif
<> 139:856d2700e60b 629 return ((uint8_t) result); /* Add explicit type cast here */
<> 139:856d2700e60b 630 }
<> 139:856d2700e60b 631
<> 139:856d2700e60b 632
<> 139:856d2700e60b 633 /** \brief LDR Exclusive (16 bit)
<> 139:856d2700e60b 634
<> 139:856d2700e60b 635 This function executes a exclusive LDR instruction for 16 bit values.
<> 139:856d2700e60b 636
<> 139:856d2700e60b 637 \param [in] ptr Pointer to data
<> 139:856d2700e60b 638 \return value of type uint16_t at (*ptr)
<> 139:856d2700e60b 639 */
<> 139:856d2700e60b 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
<> 139:856d2700e60b 641 {
<> 139:856d2700e60b 642 uint32_t result;
<> 139:856d2700e60b 643
<> 139:856d2700e60b 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 139:856d2700e60b 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
<> 139:856d2700e60b 646 #else
<> 139:856d2700e60b 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 139:856d2700e60b 648 accepted by assembler. So has to use following less efficient pattern.
<> 139:856d2700e60b 649 */
<> 139:856d2700e60b 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 139:856d2700e60b 651 #endif
<> 139:856d2700e60b 652 return ((uint16_t) result); /* Add explicit type cast here */
<> 139:856d2700e60b 653 }
<> 139:856d2700e60b 654
<> 139:856d2700e60b 655
<> 139:856d2700e60b 656 /** \brief LDR Exclusive (32 bit)
<> 139:856d2700e60b 657
<> 139:856d2700e60b 658 This function executes a exclusive LDR instruction for 32 bit values.
<> 139:856d2700e60b 659
<> 139:856d2700e60b 660 \param [in] ptr Pointer to data
<> 139:856d2700e60b 661 \return value of type uint32_t at (*ptr)
<> 139:856d2700e60b 662 */
<> 139:856d2700e60b 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
<> 139:856d2700e60b 664 {
<> 139:856d2700e60b 665 uint32_t result;
<> 139:856d2700e60b 666
<> 139:856d2700e60b 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
<> 139:856d2700e60b 668 return(result);
<> 139:856d2700e60b 669 }
<> 139:856d2700e60b 670
<> 139:856d2700e60b 671
<> 139:856d2700e60b 672 /** \brief STR Exclusive (8 bit)
<> 139:856d2700e60b 673
<> 139:856d2700e60b 674 This function executes a exclusive STR instruction for 8 bit values.
<> 139:856d2700e60b 675
<> 139:856d2700e60b 676 \param [in] value Value to store
<> 139:856d2700e60b 677 \param [in] ptr Pointer to location
<> 139:856d2700e60b 678 \return 0 Function succeeded
<> 139:856d2700e60b 679 \return 1 Function failed
<> 139:856d2700e60b 680 */
<> 139:856d2700e60b 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
<> 139:856d2700e60b 682 {
<> 139:856d2700e60b 683 uint32_t result;
<> 139:856d2700e60b 684
<> 139:856d2700e60b 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 139:856d2700e60b 686 return(result);
<> 139:856d2700e60b 687 }
<> 139:856d2700e60b 688
<> 139:856d2700e60b 689
<> 139:856d2700e60b 690 /** \brief STR Exclusive (16 bit)
<> 139:856d2700e60b 691
<> 139:856d2700e60b 692 This function executes a exclusive STR instruction for 16 bit values.
<> 139:856d2700e60b 693
<> 139:856d2700e60b 694 \param [in] value Value to store
<> 139:856d2700e60b 695 \param [in] ptr Pointer to location
<> 139:856d2700e60b 696 \return 0 Function succeeded
<> 139:856d2700e60b 697 \return 1 Function failed
<> 139:856d2700e60b 698 */
<> 139:856d2700e60b 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
<> 139:856d2700e60b 700 {
<> 139:856d2700e60b 701 uint32_t result;
<> 139:856d2700e60b 702
<> 139:856d2700e60b 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 139:856d2700e60b 704 return(result);
<> 139:856d2700e60b 705 }
<> 139:856d2700e60b 706
<> 139:856d2700e60b 707
<> 139:856d2700e60b 708 /** \brief STR Exclusive (32 bit)
<> 139:856d2700e60b 709
<> 139:856d2700e60b 710 This function executes a exclusive STR instruction for 32 bit values.
<> 139:856d2700e60b 711
<> 139:856d2700e60b 712 \param [in] value Value to store
<> 139:856d2700e60b 713 \param [in] ptr Pointer to location
<> 139:856d2700e60b 714 \return 0 Function succeeded
<> 139:856d2700e60b 715 \return 1 Function failed
<> 139:856d2700e60b 716 */
<> 139:856d2700e60b 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
<> 139:856d2700e60b 718 {
<> 139:856d2700e60b 719 uint32_t result;
<> 139:856d2700e60b 720
<> 139:856d2700e60b 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
<> 139:856d2700e60b 722 return(result);
<> 139:856d2700e60b 723 }
<> 139:856d2700e60b 724
<> 139:856d2700e60b 725
<> 139:856d2700e60b 726 /** \brief Remove the exclusive lock
<> 139:856d2700e60b 727
<> 139:856d2700e60b 728 This function removes the exclusive lock which is created by LDREX.
<> 139:856d2700e60b 729
<> 139:856d2700e60b 730 */
<> 139:856d2700e60b 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
<> 139:856d2700e60b 732 {
<> 139:856d2700e60b 733 __ASM volatile ("clrex" ::: "memory");
<> 139:856d2700e60b 734 }
<> 139:856d2700e60b 735
<> 139:856d2700e60b 736
<> 139:856d2700e60b 737 /** \brief Signed Saturate
<> 139:856d2700e60b 738
<> 139:856d2700e60b 739 This function saturates a signed value.
<> 139:856d2700e60b 740
<> 139:856d2700e60b 741 \param [in] value Value to be saturated
<> 139:856d2700e60b 742 \param [in] sat Bit position to saturate to (1..32)
<> 139:856d2700e60b 743 \return Saturated value
<> 139:856d2700e60b 744 */
<> 139:856d2700e60b 745 #define __SSAT(ARG1,ARG2) \
<> 139:856d2700e60b 746 ({ \
<> 139:856d2700e60b 747 uint32_t __RES, __ARG1 = (ARG1); \
<> 139:856d2700e60b 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 139:856d2700e60b 749 __RES; \
<> 139:856d2700e60b 750 })
<> 139:856d2700e60b 751
<> 139:856d2700e60b 752
<> 139:856d2700e60b 753 /** \brief Unsigned Saturate
<> 139:856d2700e60b 754
<> 139:856d2700e60b 755 This function saturates an unsigned value.
<> 139:856d2700e60b 756
<> 139:856d2700e60b 757 \param [in] value Value to be saturated
<> 139:856d2700e60b 758 \param [in] sat Bit position to saturate to (0..31)
<> 139:856d2700e60b 759 \return Saturated value
<> 139:856d2700e60b 760 */
<> 139:856d2700e60b 761 #define __USAT(ARG1,ARG2) \
<> 139:856d2700e60b 762 ({ \
<> 139:856d2700e60b 763 uint32_t __RES, __ARG1 = (ARG1); \
<> 139:856d2700e60b 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 139:856d2700e60b 765 __RES; \
<> 139:856d2700e60b 766 })
<> 139:856d2700e60b 767
<> 139:856d2700e60b 768
<> 139:856d2700e60b 769 /** \brief Rotate Right with Extend (32 bit)
<> 139:856d2700e60b 770
<> 139:856d2700e60b 771 This function moves each bit of a bitstring right by one bit.
<> 139:856d2700e60b 772 The carry input is shifted in at the left end of the bitstring.
<> 139:856d2700e60b 773
<> 139:856d2700e60b 774 \param [in] value Value to rotate
<> 139:856d2700e60b 775 \return Rotated value
<> 139:856d2700e60b 776 */
<> 139:856d2700e60b 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
<> 139:856d2700e60b 778 {
<> 139:856d2700e60b 779 uint32_t result;
<> 139:856d2700e60b 780
<> 139:856d2700e60b 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 139:856d2700e60b 782 return(result);
<> 139:856d2700e60b 783 }
<> 139:856d2700e60b 784
<> 139:856d2700e60b 785
<> 139:856d2700e60b 786 /** \brief LDRT Unprivileged (8 bit)
<> 139:856d2700e60b 787
<> 139:856d2700e60b 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 139:856d2700e60b 789
<> 139:856d2700e60b 790 \param [in] ptr Pointer to data
<> 139:856d2700e60b 791 \return value of type uint8_t at (*ptr)
<> 139:856d2700e60b 792 */
<> 139:856d2700e60b 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
<> 139:856d2700e60b 794 {
<> 139:856d2700e60b 795 uint32_t result;
<> 139:856d2700e60b 796
<> 139:856d2700e60b 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 139:856d2700e60b 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 139:856d2700e60b 799 #else
<> 139:856d2700e60b 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 139:856d2700e60b 801 accepted by assembler. So has to use following less efficient pattern.
<> 139:856d2700e60b 802 */
<> 139:856d2700e60b 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 139:856d2700e60b 804 #endif
<> 139:856d2700e60b 805 return ((uint8_t) result); /* Add explicit type cast here */
<> 139:856d2700e60b 806 }
<> 139:856d2700e60b 807
<> 139:856d2700e60b 808
<> 139:856d2700e60b 809 /** \brief LDRT Unprivileged (16 bit)
<> 139:856d2700e60b 810
<> 139:856d2700e60b 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 139:856d2700e60b 812
<> 139:856d2700e60b 813 \param [in] ptr Pointer to data
<> 139:856d2700e60b 814 \return value of type uint16_t at (*ptr)
<> 139:856d2700e60b 815 */
<> 139:856d2700e60b 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
<> 139:856d2700e60b 817 {
<> 139:856d2700e60b 818 uint32_t result;
<> 139:856d2700e60b 819
<> 139:856d2700e60b 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 139:856d2700e60b 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
<> 139:856d2700e60b 822 #else
<> 139:856d2700e60b 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 139:856d2700e60b 824 accepted by assembler. So has to use following less efficient pattern.
<> 139:856d2700e60b 825 */
<> 139:856d2700e60b 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 139:856d2700e60b 827 #endif
<> 139:856d2700e60b 828 return ((uint16_t) result); /* Add explicit type cast here */
<> 139:856d2700e60b 829 }
<> 139:856d2700e60b 830
<> 139:856d2700e60b 831
<> 139:856d2700e60b 832 /** \brief LDRT Unprivileged (32 bit)
<> 139:856d2700e60b 833
<> 139:856d2700e60b 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 139:856d2700e60b 835
<> 139:856d2700e60b 836 \param [in] ptr Pointer to data
<> 139:856d2700e60b 837 \return value of type uint32_t at (*ptr)
<> 139:856d2700e60b 838 */
<> 139:856d2700e60b 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
<> 139:856d2700e60b 840 {
<> 139:856d2700e60b 841 uint32_t result;
<> 139:856d2700e60b 842
<> 139:856d2700e60b 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 139:856d2700e60b 844 return(result);
<> 139:856d2700e60b 845 }
<> 139:856d2700e60b 846
<> 139:856d2700e60b 847
<> 139:856d2700e60b 848 /** \brief STRT Unprivileged (8 bit)
<> 139:856d2700e60b 849
<> 139:856d2700e60b 850 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 139:856d2700e60b 851
<> 139:856d2700e60b 852 \param [in] value Value to store
<> 139:856d2700e60b 853 \param [in] ptr Pointer to location
<> 139:856d2700e60b 854 */
<> 139:856d2700e60b 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
<> 139:856d2700e60b 856 {
<> 139:856d2700e60b 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 139:856d2700e60b 858 }
<> 139:856d2700e60b 859
<> 139:856d2700e60b 860
<> 139:856d2700e60b 861 /** \brief STRT Unprivileged (16 bit)
<> 139:856d2700e60b 862
<> 139:856d2700e60b 863 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 139:856d2700e60b 864
<> 139:856d2700e60b 865 \param [in] value Value to store
<> 139:856d2700e60b 866 \param [in] ptr Pointer to location
<> 139:856d2700e60b 867 */
<> 139:856d2700e60b 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
<> 139:856d2700e60b 869 {
<> 139:856d2700e60b 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 139:856d2700e60b 871 }
<> 139:856d2700e60b 872
<> 139:856d2700e60b 873
<> 139:856d2700e60b 874 /** \brief STRT Unprivileged (32 bit)
<> 139:856d2700e60b 875
<> 139:856d2700e60b 876 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 139:856d2700e60b 877
<> 139:856d2700e60b 878 \param [in] value Value to store
<> 139:856d2700e60b 879 \param [in] ptr Pointer to location
<> 139:856d2700e60b 880 */
<> 139:856d2700e60b 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
<> 139:856d2700e60b 882 {
<> 139:856d2700e60b 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
<> 139:856d2700e60b 884 }
<> 139:856d2700e60b 885
<> 139:856d2700e60b 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 139:856d2700e60b 887
<> 139:856d2700e60b 888
<> 139:856d2700e60b 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 139:856d2700e60b 890 /* IAR iccarm specific functions */
<> 139:856d2700e60b 891 #include <cmsis_iar.h>
<> 139:856d2700e60b 892
<> 139:856d2700e60b 893
<> 139:856d2700e60b 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 139:856d2700e60b 895 /* TI CCS specific functions */
<> 139:856d2700e60b 896 #include <cmsis_ccs.h>
<> 139:856d2700e60b 897
<> 139:856d2700e60b 898
<> 139:856d2700e60b 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 139:856d2700e60b 900 /* TASKING carm specific functions */
<> 139:856d2700e60b 901 /*
<> 139:856d2700e60b 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 139:856d2700e60b 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 139:856d2700e60b 904 * Including the CMSIS ones.
<> 139:856d2700e60b 905 */
<> 139:856d2700e60b 906
<> 139:856d2700e60b 907
<> 139:856d2700e60b 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 139:856d2700e60b 909 /* Cosmic specific functions */
<> 139:856d2700e60b 910 #include <cmsis_csm.h>
<> 139:856d2700e60b 911
<> 139:856d2700e60b 912 #endif
<> 139:856d2700e60b 913
<> 139:856d2700e60b 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
<> 139:856d2700e60b 915
<> 139:856d2700e60b 916 #endif /* __CORE_CMINSTR_H */