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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/core_cmFunc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_cmFunc.h
<> 139:856d2700e60b 3 * @brief CMSIS Cortex-M Core Function Access Header File
<> 139:856d2700e60b 4 * @version V4.10
<> 139:856d2700e60b 5 * @date 18. March 2015
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #ifndef __CORE_CMFUNC_H
<> 139:856d2700e60b 39 #define __CORE_CMFUNC_H
<> 139:856d2700e60b 40
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 /* ########################### Core Function Access ########################### */
<> 139:856d2700e60b 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 139:856d2700e60b 45 @{
<> 139:856d2700e60b 46 */
<> 139:856d2700e60b 47
<> 139:856d2700e60b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 139:856d2700e60b 49 /* ARM armcc specific functions */
<> 139:856d2700e60b 50
<> 139:856d2700e60b 51 #if (__ARMCC_VERSION < 400677)
<> 139:856d2700e60b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 139:856d2700e60b 53 #endif
<> 139:856d2700e60b 54
<> 139:856d2700e60b 55 /* intrinsic void __enable_irq(); */
<> 139:856d2700e60b 56 /* intrinsic void __disable_irq(); */
<> 139:856d2700e60b 57
<> 139:856d2700e60b 58 /** \brief Get Control Register
<> 139:856d2700e60b 59
<> 139:856d2700e60b 60 This function returns the content of the Control Register.
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62 \return Control Register value
<> 139:856d2700e60b 63 */
<> 139:856d2700e60b 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 139:856d2700e60b 65 {
<> 139:856d2700e60b 66 register uint32_t __regControl __ASM("control");
<> 139:856d2700e60b 67 return(__regControl);
<> 139:856d2700e60b 68 }
<> 139:856d2700e60b 69
<> 139:856d2700e60b 70
<> 139:856d2700e60b 71 /** \brief Set Control Register
<> 139:856d2700e60b 72
<> 139:856d2700e60b 73 This function writes the given value to the Control Register.
<> 139:856d2700e60b 74
<> 139:856d2700e60b 75 \param [in] control Control Register value to set
<> 139:856d2700e60b 76 */
<> 139:856d2700e60b 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 139:856d2700e60b 78 {
<> 139:856d2700e60b 79 register uint32_t __regControl __ASM("control");
<> 139:856d2700e60b 80 __regControl = control;
<> 139:856d2700e60b 81 }
<> 139:856d2700e60b 82
<> 139:856d2700e60b 83
<> 139:856d2700e60b 84 /** \brief Get IPSR Register
<> 139:856d2700e60b 85
<> 139:856d2700e60b 86 This function returns the content of the IPSR Register.
<> 139:856d2700e60b 87
<> 139:856d2700e60b 88 \return IPSR Register value
<> 139:856d2700e60b 89 */
<> 139:856d2700e60b 90 __STATIC_INLINE uint32_t __get_IPSR(void)
<> 139:856d2700e60b 91 {
<> 139:856d2700e60b 92 register uint32_t __regIPSR __ASM("ipsr");
<> 139:856d2700e60b 93 return(__regIPSR);
<> 139:856d2700e60b 94 }
<> 139:856d2700e60b 95
<> 139:856d2700e60b 96
<> 139:856d2700e60b 97 /** \brief Get APSR Register
<> 139:856d2700e60b 98
<> 139:856d2700e60b 99 This function returns the content of the APSR Register.
<> 139:856d2700e60b 100
<> 139:856d2700e60b 101 \return APSR Register value
<> 139:856d2700e60b 102 */
<> 139:856d2700e60b 103 __STATIC_INLINE uint32_t __get_APSR(void)
<> 139:856d2700e60b 104 {
<> 139:856d2700e60b 105 register uint32_t __regAPSR __ASM("apsr");
<> 139:856d2700e60b 106 return(__regAPSR);
<> 139:856d2700e60b 107 }
<> 139:856d2700e60b 108
<> 139:856d2700e60b 109
<> 139:856d2700e60b 110 /** \brief Get xPSR Register
<> 139:856d2700e60b 111
<> 139:856d2700e60b 112 This function returns the content of the xPSR Register.
<> 139:856d2700e60b 113
<> 139:856d2700e60b 114 \return xPSR Register value
<> 139:856d2700e60b 115 */
<> 139:856d2700e60b 116 __STATIC_INLINE uint32_t __get_xPSR(void)
<> 139:856d2700e60b 117 {
<> 139:856d2700e60b 118 register uint32_t __regXPSR __ASM("xpsr");
<> 139:856d2700e60b 119 return(__regXPSR);
<> 139:856d2700e60b 120 }
<> 139:856d2700e60b 121
<> 139:856d2700e60b 122
<> 139:856d2700e60b 123 /** \brief Get Process Stack Pointer
<> 139:856d2700e60b 124
<> 139:856d2700e60b 125 This function returns the current value of the Process Stack Pointer (PSP).
<> 139:856d2700e60b 126
<> 139:856d2700e60b 127 \return PSP Register value
<> 139:856d2700e60b 128 */
<> 139:856d2700e60b 129 __STATIC_INLINE uint32_t __get_PSP(void)
<> 139:856d2700e60b 130 {
<> 139:856d2700e60b 131 register uint32_t __regProcessStackPointer __ASM("psp");
<> 139:856d2700e60b 132 return(__regProcessStackPointer);
<> 139:856d2700e60b 133 }
<> 139:856d2700e60b 134
<> 139:856d2700e60b 135
<> 139:856d2700e60b 136 /** \brief Set Process Stack Pointer
<> 139:856d2700e60b 137
<> 139:856d2700e60b 138 This function assigns the given value to the Process Stack Pointer (PSP).
<> 139:856d2700e60b 139
<> 139:856d2700e60b 140 \param [in] topOfProcStack Process Stack Pointer value to set
<> 139:856d2700e60b 141 */
<> 139:856d2700e60b 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 139:856d2700e60b 143 {
<> 139:856d2700e60b 144 register uint32_t __regProcessStackPointer __ASM("psp");
<> 139:856d2700e60b 145 __regProcessStackPointer = topOfProcStack;
<> 139:856d2700e60b 146 }
<> 139:856d2700e60b 147
<> 139:856d2700e60b 148
<> 139:856d2700e60b 149 /** \brief Get Main Stack Pointer
<> 139:856d2700e60b 150
<> 139:856d2700e60b 151 This function returns the current value of the Main Stack Pointer (MSP).
<> 139:856d2700e60b 152
<> 139:856d2700e60b 153 \return MSP Register value
<> 139:856d2700e60b 154 */
<> 139:856d2700e60b 155 __STATIC_INLINE uint32_t __get_MSP(void)
<> 139:856d2700e60b 156 {
<> 139:856d2700e60b 157 register uint32_t __regMainStackPointer __ASM("msp");
<> 139:856d2700e60b 158 return(__regMainStackPointer);
<> 139:856d2700e60b 159 }
<> 139:856d2700e60b 160
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 /** \brief Set Main Stack Pointer
<> 139:856d2700e60b 163
<> 139:856d2700e60b 164 This function assigns the given value to the Main Stack Pointer (MSP).
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 \param [in] topOfMainStack Main Stack Pointer value to set
<> 139:856d2700e60b 167 */
<> 139:856d2700e60b 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 139:856d2700e60b 169 {
<> 139:856d2700e60b 170 register uint32_t __regMainStackPointer __ASM("msp");
<> 139:856d2700e60b 171 __regMainStackPointer = topOfMainStack;
<> 139:856d2700e60b 172 }
<> 139:856d2700e60b 173
<> 139:856d2700e60b 174
<> 139:856d2700e60b 175 /** \brief Get Priority Mask
<> 139:856d2700e60b 176
<> 139:856d2700e60b 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 139:856d2700e60b 178
<> 139:856d2700e60b 179 \return Priority Mask value
<> 139:856d2700e60b 180 */
<> 139:856d2700e60b 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 139:856d2700e60b 182 {
<> 139:856d2700e60b 183 register uint32_t __regPriMask __ASM("primask");
<> 139:856d2700e60b 184 return(__regPriMask);
<> 139:856d2700e60b 185 }
<> 139:856d2700e60b 186
<> 139:856d2700e60b 187
<> 139:856d2700e60b 188 /** \brief Set Priority Mask
<> 139:856d2700e60b 189
<> 139:856d2700e60b 190 This function assigns the given value to the Priority Mask Register.
<> 139:856d2700e60b 191
<> 139:856d2700e60b 192 \param [in] priMask Priority Mask
<> 139:856d2700e60b 193 */
<> 139:856d2700e60b 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 139:856d2700e60b 195 {
<> 139:856d2700e60b 196 register uint32_t __regPriMask __ASM("primask");
<> 139:856d2700e60b 197 __regPriMask = (priMask);
<> 139:856d2700e60b 198 }
<> 139:856d2700e60b 199
<> 139:856d2700e60b 200
<> 139:856d2700e60b 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 139:856d2700e60b 202
<> 139:856d2700e60b 203 /** \brief Enable FIQ
<> 139:856d2700e60b 204
<> 139:856d2700e60b 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 139:856d2700e60b 206 Can only be executed in Privileged modes.
<> 139:856d2700e60b 207 */
<> 139:856d2700e60b 208 #define __enable_fault_irq __enable_fiq
<> 139:856d2700e60b 209
<> 139:856d2700e60b 210
<> 139:856d2700e60b 211 /** \brief Disable FIQ
<> 139:856d2700e60b 212
<> 139:856d2700e60b 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 139:856d2700e60b 214 Can only be executed in Privileged modes.
<> 139:856d2700e60b 215 */
<> 139:856d2700e60b 216 #define __disable_fault_irq __disable_fiq
<> 139:856d2700e60b 217
<> 139:856d2700e60b 218
<> 139:856d2700e60b 219 /** \brief Get Base Priority
<> 139:856d2700e60b 220
<> 139:856d2700e60b 221 This function returns the current value of the Base Priority register.
<> 139:856d2700e60b 222
<> 139:856d2700e60b 223 \return Base Priority register value
<> 139:856d2700e60b 224 */
<> 139:856d2700e60b 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 139:856d2700e60b 226 {
<> 139:856d2700e60b 227 register uint32_t __regBasePri __ASM("basepri");
<> 139:856d2700e60b 228 return(__regBasePri);
<> 139:856d2700e60b 229 }
<> 139:856d2700e60b 230
<> 139:856d2700e60b 231
<> 139:856d2700e60b 232 /** \brief Set Base Priority
<> 139:856d2700e60b 233
<> 139:856d2700e60b 234 This function assigns the given value to the Base Priority register.
<> 139:856d2700e60b 235
<> 139:856d2700e60b 236 \param [in] basePri Base Priority value to set
<> 139:856d2700e60b 237 */
<> 139:856d2700e60b 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
<> 139:856d2700e60b 239 {
<> 139:856d2700e60b 240 register uint32_t __regBasePri __ASM("basepri");
<> 139:856d2700e60b 241 __regBasePri = (basePri & 0xff);
<> 139:856d2700e60b 242 }
<> 139:856d2700e60b 243
<> 139:856d2700e60b 244
<> 139:856d2700e60b 245 /** \brief Set Base Priority with condition
<> 139:856d2700e60b 246
<> 139:856d2700e60b 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 139:856d2700e60b 248 or the new value increases the BASEPRI priority level.
<> 139:856d2700e60b 249
<> 139:856d2700e60b 250 \param [in] basePri Base Priority value to set
<> 139:856d2700e60b 251 */
<> 139:856d2700e60b 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
<> 139:856d2700e60b 253 {
<> 139:856d2700e60b 254 register uint32_t __regBasePriMax __ASM("basepri_max");
<> 139:856d2700e60b 255 __regBasePriMax = (basePri & 0xff);
<> 139:856d2700e60b 256 }
<> 139:856d2700e60b 257
<> 139:856d2700e60b 258
<> 139:856d2700e60b 259 /** \brief Get Fault Mask
<> 139:856d2700e60b 260
<> 139:856d2700e60b 261 This function returns the current value of the Fault Mask register.
<> 139:856d2700e60b 262
<> 139:856d2700e60b 263 \return Fault Mask register value
<> 139:856d2700e60b 264 */
<> 139:856d2700e60b 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 139:856d2700e60b 266 {
<> 139:856d2700e60b 267 register uint32_t __regFaultMask __ASM("faultmask");
<> 139:856d2700e60b 268 return(__regFaultMask);
<> 139:856d2700e60b 269 }
<> 139:856d2700e60b 270
<> 139:856d2700e60b 271
<> 139:856d2700e60b 272 /** \brief Set Fault Mask
<> 139:856d2700e60b 273
<> 139:856d2700e60b 274 This function assigns the given value to the Fault Mask register.
<> 139:856d2700e60b 275
<> 139:856d2700e60b 276 \param [in] faultMask Fault Mask value to set
<> 139:856d2700e60b 277 */
<> 139:856d2700e60b 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 139:856d2700e60b 279 {
<> 139:856d2700e60b 280 register uint32_t __regFaultMask __ASM("faultmask");
<> 139:856d2700e60b 281 __regFaultMask = (faultMask & (uint32_t)1);
<> 139:856d2700e60b 282 }
<> 139:856d2700e60b 283
<> 139:856d2700e60b 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 139:856d2700e60b 285
<> 139:856d2700e60b 286
<> 139:856d2700e60b 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 139:856d2700e60b 288
<> 139:856d2700e60b 289 /** \brief Get FPSCR
<> 139:856d2700e60b 290
<> 139:856d2700e60b 291 This function returns the current value of the Floating Point Status/Control register.
<> 139:856d2700e60b 292
<> 139:856d2700e60b 293 \return Floating Point Status/Control register value
<> 139:856d2700e60b 294 */
<> 139:856d2700e60b 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 139:856d2700e60b 296 {
<> 139:856d2700e60b 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 139:856d2700e60b 298 register uint32_t __regfpscr __ASM("fpscr");
<> 139:856d2700e60b 299 return(__regfpscr);
<> 139:856d2700e60b 300 #else
<> 139:856d2700e60b 301 return(0);
<> 139:856d2700e60b 302 #endif
<> 139:856d2700e60b 303 }
<> 139:856d2700e60b 304
<> 139:856d2700e60b 305
<> 139:856d2700e60b 306 /** \brief Set FPSCR
<> 139:856d2700e60b 307
<> 139:856d2700e60b 308 This function assigns the given value to the Floating Point Status/Control register.
<> 139:856d2700e60b 309
<> 139:856d2700e60b 310 \param [in] fpscr Floating Point Status/Control value to set
<> 139:856d2700e60b 311 */
<> 139:856d2700e60b 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 139:856d2700e60b 313 {
<> 139:856d2700e60b 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 139:856d2700e60b 315 register uint32_t __regfpscr __ASM("fpscr");
<> 139:856d2700e60b 316 __regfpscr = (fpscr);
<> 139:856d2700e60b 317 #endif
<> 139:856d2700e60b 318 }
<> 139:856d2700e60b 319
<> 139:856d2700e60b 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 139:856d2700e60b 321
<> 139:856d2700e60b 322
<> 139:856d2700e60b 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 139:856d2700e60b 324 /* GNU gcc specific functions */
<> 139:856d2700e60b 325
<> 139:856d2700e60b 326 /** \brief Enable IRQ Interrupts
<> 139:856d2700e60b 327
<> 139:856d2700e60b 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
<> 139:856d2700e60b 329 Can only be executed in Privileged modes.
<> 139:856d2700e60b 330 */
<> 139:856d2700e60b 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 139:856d2700e60b 332 {
<> 139:856d2700e60b 333 __ASM volatile ("cpsie i" : : : "memory");
<> 139:856d2700e60b 334 }
<> 139:856d2700e60b 335
<> 139:856d2700e60b 336
<> 139:856d2700e60b 337 /** \brief Disable IRQ Interrupts
<> 139:856d2700e60b 338
<> 139:856d2700e60b 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 139:856d2700e60b 340 Can only be executed in Privileged modes.
<> 139:856d2700e60b 341 */
<> 139:856d2700e60b 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
<> 139:856d2700e60b 343 {
<> 139:856d2700e60b 344 __ASM volatile ("cpsid i" : : : "memory");
<> 139:856d2700e60b 345 }
<> 139:856d2700e60b 346
<> 139:856d2700e60b 347
<> 139:856d2700e60b 348 /** \brief Get Control Register
<> 139:856d2700e60b 349
<> 139:856d2700e60b 350 This function returns the content of the Control Register.
<> 139:856d2700e60b 351
<> 139:856d2700e60b 352 \return Control Register value
<> 139:856d2700e60b 353 */
<> 139:856d2700e60b 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 139:856d2700e60b 355 {
<> 139:856d2700e60b 356 uint32_t result;
<> 139:856d2700e60b 357
<> 139:856d2700e60b 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
<> 139:856d2700e60b 359 return(result);
<> 139:856d2700e60b 360 }
<> 139:856d2700e60b 361
<> 139:856d2700e60b 362
<> 139:856d2700e60b 363 /** \brief Set Control Register
<> 139:856d2700e60b 364
<> 139:856d2700e60b 365 This function writes the given value to the Control Register.
<> 139:856d2700e60b 366
<> 139:856d2700e60b 367 \param [in] control Control Register value to set
<> 139:856d2700e60b 368 */
<> 139:856d2700e60b 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 139:856d2700e60b 370 {
<> 139:856d2700e60b 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
<> 139:856d2700e60b 372 }
<> 139:856d2700e60b 373
<> 139:856d2700e60b 374
<> 139:856d2700e60b 375 /** \brief Get IPSR Register
<> 139:856d2700e60b 376
<> 139:856d2700e60b 377 This function returns the content of the IPSR Register.
<> 139:856d2700e60b 378
<> 139:856d2700e60b 379 \return IPSR Register value
<> 139:856d2700e60b 380 */
<> 139:856d2700e60b 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
<> 139:856d2700e60b 382 {
<> 139:856d2700e60b 383 uint32_t result;
<> 139:856d2700e60b 384
<> 139:856d2700e60b 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
<> 139:856d2700e60b 386 return(result);
<> 139:856d2700e60b 387 }
<> 139:856d2700e60b 388
<> 139:856d2700e60b 389
<> 139:856d2700e60b 390 /** \brief Get APSR Register
<> 139:856d2700e60b 391
<> 139:856d2700e60b 392 This function returns the content of the APSR Register.
<> 139:856d2700e60b 393
<> 139:856d2700e60b 394 \return APSR Register value
<> 139:856d2700e60b 395 */
<> 139:856d2700e60b 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 139:856d2700e60b 397 {
<> 139:856d2700e60b 398 uint32_t result;
<> 139:856d2700e60b 399
<> 139:856d2700e60b 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
<> 139:856d2700e60b 401 return(result);
<> 139:856d2700e60b 402 }
<> 139:856d2700e60b 403
<> 139:856d2700e60b 404
<> 139:856d2700e60b 405 /** \brief Get xPSR Register
<> 139:856d2700e60b 406
<> 139:856d2700e60b 407 This function returns the content of the xPSR Register.
<> 139:856d2700e60b 408
<> 139:856d2700e60b 409 \return xPSR Register value
<> 139:856d2700e60b 410 */
<> 139:856d2700e60b 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
<> 139:856d2700e60b 412 {
<> 139:856d2700e60b 413 uint32_t result;
<> 139:856d2700e60b 414
<> 139:856d2700e60b 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
<> 139:856d2700e60b 416 return(result);
<> 139:856d2700e60b 417 }
<> 139:856d2700e60b 418
<> 139:856d2700e60b 419
<> 139:856d2700e60b 420 /** \brief Get Process Stack Pointer
<> 139:856d2700e60b 421
<> 139:856d2700e60b 422 This function returns the current value of the Process Stack Pointer (PSP).
<> 139:856d2700e60b 423
<> 139:856d2700e60b 424 \return PSP Register value
<> 139:856d2700e60b 425 */
<> 139:856d2700e60b 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
<> 139:856d2700e60b 427 {
<> 139:856d2700e60b 428 register uint32_t result;
<> 139:856d2700e60b 429
<> 139:856d2700e60b 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
<> 139:856d2700e60b 431 return(result);
<> 139:856d2700e60b 432 }
<> 139:856d2700e60b 433
<> 139:856d2700e60b 434
<> 139:856d2700e60b 435 /** \brief Set Process Stack Pointer
<> 139:856d2700e60b 436
<> 139:856d2700e60b 437 This function assigns the given value to the Process Stack Pointer (PSP).
<> 139:856d2700e60b 438
<> 139:856d2700e60b 439 \param [in] topOfProcStack Process Stack Pointer value to set
<> 139:856d2700e60b 440 */
<> 139:856d2700e60b 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 139:856d2700e60b 442 {
<> 139:856d2700e60b 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
<> 139:856d2700e60b 444 }
<> 139:856d2700e60b 445
<> 139:856d2700e60b 446
<> 139:856d2700e60b 447 /** \brief Get Main Stack Pointer
<> 139:856d2700e60b 448
<> 139:856d2700e60b 449 This function returns the current value of the Main Stack Pointer (MSP).
<> 139:856d2700e60b 450
<> 139:856d2700e60b 451 \return MSP Register value
<> 139:856d2700e60b 452 */
<> 139:856d2700e60b 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
<> 139:856d2700e60b 454 {
<> 139:856d2700e60b 455 register uint32_t result;
<> 139:856d2700e60b 456
<> 139:856d2700e60b 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
<> 139:856d2700e60b 458 return(result);
<> 139:856d2700e60b 459 }
<> 139:856d2700e60b 460
<> 139:856d2700e60b 461
<> 139:856d2700e60b 462 /** \brief Set Main Stack Pointer
<> 139:856d2700e60b 463
<> 139:856d2700e60b 464 This function assigns the given value to the Main Stack Pointer (MSP).
<> 139:856d2700e60b 465
<> 139:856d2700e60b 466 \param [in] topOfMainStack Main Stack Pointer value to set
<> 139:856d2700e60b 467 */
<> 139:856d2700e60b 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 139:856d2700e60b 469 {
<> 139:856d2700e60b 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
<> 139:856d2700e60b 471 }
<> 139:856d2700e60b 472
<> 139:856d2700e60b 473
<> 139:856d2700e60b 474 /** \brief Get Priority Mask
<> 139:856d2700e60b 475
<> 139:856d2700e60b 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 139:856d2700e60b 477
<> 139:856d2700e60b 478 \return Priority Mask value
<> 139:856d2700e60b 479 */
<> 139:856d2700e60b 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 139:856d2700e60b 481 {
<> 139:856d2700e60b 482 uint32_t result;
<> 139:856d2700e60b 483
<> 139:856d2700e60b 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
<> 139:856d2700e60b 485 return(result);
<> 139:856d2700e60b 486 }
<> 139:856d2700e60b 487
<> 139:856d2700e60b 488
<> 139:856d2700e60b 489 /** \brief Set Priority Mask
<> 139:856d2700e60b 490
<> 139:856d2700e60b 491 This function assigns the given value to the Priority Mask Register.
<> 139:856d2700e60b 492
<> 139:856d2700e60b 493 \param [in] priMask Priority Mask
<> 139:856d2700e60b 494 */
<> 139:856d2700e60b 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 139:856d2700e60b 496 {
<> 139:856d2700e60b 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
<> 139:856d2700e60b 498 }
<> 139:856d2700e60b 499
<> 139:856d2700e60b 500
<> 139:856d2700e60b 501 #if (__CORTEX_M >= 0x03)
<> 139:856d2700e60b 502
<> 139:856d2700e60b 503 /** \brief Enable FIQ
<> 139:856d2700e60b 504
<> 139:856d2700e60b 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 139:856d2700e60b 506 Can only be executed in Privileged modes.
<> 139:856d2700e60b 507 */
<> 139:856d2700e60b 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
<> 139:856d2700e60b 509 {
<> 139:856d2700e60b 510 __ASM volatile ("cpsie f" : : : "memory");
<> 139:856d2700e60b 511 }
<> 139:856d2700e60b 512
<> 139:856d2700e60b 513
<> 139:856d2700e60b 514 /** \brief Disable FIQ
<> 139:856d2700e60b 515
<> 139:856d2700e60b 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 139:856d2700e60b 517 Can only be executed in Privileged modes.
<> 139:856d2700e60b 518 */
<> 139:856d2700e60b 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
<> 139:856d2700e60b 520 {
<> 139:856d2700e60b 521 __ASM volatile ("cpsid f" : : : "memory");
<> 139:856d2700e60b 522 }
<> 139:856d2700e60b 523
<> 139:856d2700e60b 524
<> 139:856d2700e60b 525 /** \brief Get Base Priority
<> 139:856d2700e60b 526
<> 139:856d2700e60b 527 This function returns the current value of the Base Priority register.
<> 139:856d2700e60b 528
<> 139:856d2700e60b 529 \return Base Priority register value
<> 139:856d2700e60b 530 */
<> 139:856d2700e60b 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 139:856d2700e60b 532 {
<> 139:856d2700e60b 533 uint32_t result;
<> 139:856d2700e60b 534
<> 139:856d2700e60b 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
<> 139:856d2700e60b 536 return(result);
<> 139:856d2700e60b 537 }
<> 139:856d2700e60b 538
<> 139:856d2700e60b 539
<> 139:856d2700e60b 540 /** \brief Set Base Priority
<> 139:856d2700e60b 541
<> 139:856d2700e60b 542 This function assigns the given value to the Base Priority register.
<> 139:856d2700e60b 543
<> 139:856d2700e60b 544 \param [in] basePri Base Priority value to set
<> 139:856d2700e60b 545 */
<> 139:856d2700e60b 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
<> 139:856d2700e60b 547 {
<> 139:856d2700e60b 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
<> 139:856d2700e60b 549 }
<> 139:856d2700e60b 550
<> 139:856d2700e60b 551
<> 139:856d2700e60b 552 /** \brief Set Base Priority with condition
<> 139:856d2700e60b 553
<> 139:856d2700e60b 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 139:856d2700e60b 555 or the new value increases the BASEPRI priority level.
<> 139:856d2700e60b 556
<> 139:856d2700e60b 557 \param [in] basePri Base Priority value to set
<> 139:856d2700e60b 558 */
<> 139:856d2700e60b 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
<> 139:856d2700e60b 560 {
<> 139:856d2700e60b 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
<> 139:856d2700e60b 562 }
<> 139:856d2700e60b 563
<> 139:856d2700e60b 564
<> 139:856d2700e60b 565 /** \brief Get Fault Mask
<> 139:856d2700e60b 566
<> 139:856d2700e60b 567 This function returns the current value of the Fault Mask register.
<> 139:856d2700e60b 568
<> 139:856d2700e60b 569 \return Fault Mask register value
<> 139:856d2700e60b 570 */
<> 139:856d2700e60b 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 139:856d2700e60b 572 {
<> 139:856d2700e60b 573 uint32_t result;
<> 139:856d2700e60b 574
<> 139:856d2700e60b 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
<> 139:856d2700e60b 576 return(result);
<> 139:856d2700e60b 577 }
<> 139:856d2700e60b 578
<> 139:856d2700e60b 579
<> 139:856d2700e60b 580 /** \brief Set Fault Mask
<> 139:856d2700e60b 581
<> 139:856d2700e60b 582 This function assigns the given value to the Fault Mask register.
<> 139:856d2700e60b 583
<> 139:856d2700e60b 584 \param [in] faultMask Fault Mask value to set
<> 139:856d2700e60b 585 */
<> 139:856d2700e60b 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 139:856d2700e60b 587 {
<> 139:856d2700e60b 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
<> 139:856d2700e60b 589 }
<> 139:856d2700e60b 590
<> 139:856d2700e60b 591 #endif /* (__CORTEX_M >= 0x03) */
<> 139:856d2700e60b 592
<> 139:856d2700e60b 593
<> 139:856d2700e60b 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 139:856d2700e60b 595
<> 139:856d2700e60b 596 /** \brief Get FPSCR
<> 139:856d2700e60b 597
<> 139:856d2700e60b 598 This function returns the current value of the Floating Point Status/Control register.
<> 139:856d2700e60b 599
<> 139:856d2700e60b 600 \return Floating Point Status/Control register value
<> 139:856d2700e60b 601 */
<> 139:856d2700e60b 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 139:856d2700e60b 603 {
<> 139:856d2700e60b 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 139:856d2700e60b 605 uint32_t result;
<> 139:856d2700e60b 606
<> 139:856d2700e60b 607 /* Empty asm statement works as a scheduling barrier */
<> 139:856d2700e60b 608 __ASM volatile ("");
<> 139:856d2700e60b 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
<> 139:856d2700e60b 610 __ASM volatile ("");
<> 139:856d2700e60b 611 return(result);
<> 139:856d2700e60b 612 #else
<> 139:856d2700e60b 613 return(0);
<> 139:856d2700e60b 614 #endif
<> 139:856d2700e60b 615 }
<> 139:856d2700e60b 616
<> 139:856d2700e60b 617
<> 139:856d2700e60b 618 /** \brief Set FPSCR
<> 139:856d2700e60b 619
<> 139:856d2700e60b 620 This function assigns the given value to the Floating Point Status/Control register.
<> 139:856d2700e60b 621
<> 139:856d2700e60b 622 \param [in] fpscr Floating Point Status/Control value to set
<> 139:856d2700e60b 623 */
<> 139:856d2700e60b 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 139:856d2700e60b 625 {
<> 139:856d2700e60b 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 139:856d2700e60b 627 /* Empty asm statement works as a scheduling barrier */
<> 139:856d2700e60b 628 __ASM volatile ("");
<> 139:856d2700e60b 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
<> 139:856d2700e60b 630 __ASM volatile ("");
<> 139:856d2700e60b 631 #endif
<> 139:856d2700e60b 632 }
<> 139:856d2700e60b 633
<> 139:856d2700e60b 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 139:856d2700e60b 635
<> 139:856d2700e60b 636
<> 139:856d2700e60b 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 139:856d2700e60b 638 /* IAR iccarm specific functions */
<> 139:856d2700e60b 639 #include <cmsis_iar.h>
<> 139:856d2700e60b 640
<> 139:856d2700e60b 641
<> 139:856d2700e60b 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 139:856d2700e60b 643 /* TI CCS specific functions */
<> 139:856d2700e60b 644 #include <cmsis_ccs.h>
<> 139:856d2700e60b 645
<> 139:856d2700e60b 646
<> 139:856d2700e60b 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 139:856d2700e60b 648 /* TASKING carm specific functions */
<> 139:856d2700e60b 649 /*
<> 139:856d2700e60b 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 139:856d2700e60b 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 139:856d2700e60b 652 * Including the CMSIS ones.
<> 139:856d2700e60b 653 */
<> 139:856d2700e60b 654
<> 139:856d2700e60b 655
<> 139:856d2700e60b 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 139:856d2700e60b 657 /* Cosmic specific functions */
<> 139:856d2700e60b 658 #include <cmsis_csm.h>
<> 139:856d2700e60b 659
<> 139:856d2700e60b 660 #endif
<> 139:856d2700e60b 661
<> 139:856d2700e60b 662 /*@} end of CMSIS_Core_RegAccFunctions */
<> 139:856d2700e60b 663
<> 139:856d2700e60b 664 #endif /* __CORE_CMFUNC_H */