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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/core_cm4_simd.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_cm4_simd.h
<> 139:856d2700e60b 3 * @brief CMSIS Cortex-M4 SIMD Header File
<> 139:856d2700e60b 4 * @version V3.20
<> 139:856d2700e60b 5 * @date 25. February 2013
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #ifdef __cplusplus
<> 139:856d2700e60b 39 extern "C" {
<> 139:856d2700e60b 40 #endif
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 #ifndef __CORE_CM4_SIMD_H
<> 139:856d2700e60b 43 #define __CORE_CM4_SIMD_H
<> 139:856d2700e60b 44
<> 139:856d2700e60b 45
<> 139:856d2700e60b 46 /*******************************************************************************
<> 139:856d2700e60b 47 * Hardware Abstraction Layer
<> 139:856d2700e60b 48 ******************************************************************************/
<> 139:856d2700e60b 49
<> 139:856d2700e60b 50
<> 139:856d2700e60b 51 /* ################### Compiler specific Intrinsics ########################### */
<> 139:856d2700e60b 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
<> 139:856d2700e60b 53 Access to dedicated SIMD instructions
<> 139:856d2700e60b 54 @{
<> 139:856d2700e60b 55 */
<> 139:856d2700e60b 56
<> 139:856d2700e60b 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 139:856d2700e60b 58 /* ARM armcc specific functions */
<> 139:856d2700e60b 59
<> 139:856d2700e60b 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 61 #define __SADD8 __sadd8
<> 139:856d2700e60b 62 #define __QADD8 __qadd8
<> 139:856d2700e60b 63 #define __SHADD8 __shadd8
<> 139:856d2700e60b 64 #define __UADD8 __uadd8
<> 139:856d2700e60b 65 #define __UQADD8 __uqadd8
<> 139:856d2700e60b 66 #define __UHADD8 __uhadd8
<> 139:856d2700e60b 67 #define __SSUB8 __ssub8
<> 139:856d2700e60b 68 #define __QSUB8 __qsub8
<> 139:856d2700e60b 69 #define __SHSUB8 __shsub8
<> 139:856d2700e60b 70 #define __USUB8 __usub8
<> 139:856d2700e60b 71 #define __UQSUB8 __uqsub8
<> 139:856d2700e60b 72 #define __UHSUB8 __uhsub8
<> 139:856d2700e60b 73 #define __SADD16 __sadd16
<> 139:856d2700e60b 74 #define __QADD16 __qadd16
<> 139:856d2700e60b 75 #define __SHADD16 __shadd16
<> 139:856d2700e60b 76 #define __UADD16 __uadd16
<> 139:856d2700e60b 77 #define __UQADD16 __uqadd16
<> 139:856d2700e60b 78 #define __UHADD16 __uhadd16
<> 139:856d2700e60b 79 #define __SSUB16 __ssub16
<> 139:856d2700e60b 80 #define __QSUB16 __qsub16
<> 139:856d2700e60b 81 #define __SHSUB16 __shsub16
<> 139:856d2700e60b 82 #define __USUB16 __usub16
<> 139:856d2700e60b 83 #define __UQSUB16 __uqsub16
<> 139:856d2700e60b 84 #define __UHSUB16 __uhsub16
<> 139:856d2700e60b 85 #define __SASX __sasx
<> 139:856d2700e60b 86 #define __QASX __qasx
<> 139:856d2700e60b 87 #define __SHASX __shasx
<> 139:856d2700e60b 88 #define __UASX __uasx
<> 139:856d2700e60b 89 #define __UQASX __uqasx
<> 139:856d2700e60b 90 #define __UHASX __uhasx
<> 139:856d2700e60b 91 #define __SSAX __ssax
<> 139:856d2700e60b 92 #define __QSAX __qsax
<> 139:856d2700e60b 93 #define __SHSAX __shsax
<> 139:856d2700e60b 94 #define __USAX __usax
<> 139:856d2700e60b 95 #define __UQSAX __uqsax
<> 139:856d2700e60b 96 #define __UHSAX __uhsax
<> 139:856d2700e60b 97 #define __USAD8 __usad8
<> 139:856d2700e60b 98 #define __USADA8 __usada8
<> 139:856d2700e60b 99 #define __SSAT16 __ssat16
<> 139:856d2700e60b 100 #define __USAT16 __usat16
<> 139:856d2700e60b 101 #define __UXTB16 __uxtb16
<> 139:856d2700e60b 102 #define __UXTAB16 __uxtab16
<> 139:856d2700e60b 103 #define __SXTB16 __sxtb16
<> 139:856d2700e60b 104 #define __SXTAB16 __sxtab16
<> 139:856d2700e60b 105 #define __SMUAD __smuad
<> 139:856d2700e60b 106 #define __SMUADX __smuadx
<> 139:856d2700e60b 107 #define __SMLAD __smlad
<> 139:856d2700e60b 108 #define __SMLADX __smladx
<> 139:856d2700e60b 109 #define __SMLALD __smlald
<> 139:856d2700e60b 110 #define __SMLALDX __smlaldx
<> 139:856d2700e60b 111 #define __SMUSD __smusd
<> 139:856d2700e60b 112 #define __SMUSDX __smusdx
<> 139:856d2700e60b 113 #define __SMLSD __smlsd
<> 139:856d2700e60b 114 #define __SMLSDX __smlsdx
<> 139:856d2700e60b 115 #define __SMLSLD __smlsld
<> 139:856d2700e60b 116 #define __SMLSLDX __smlsldx
<> 139:856d2700e60b 117 #define __SEL __sel
<> 139:856d2700e60b 118 #define __QADD __qadd
<> 139:856d2700e60b 119 #define __QSUB __qsub
<> 139:856d2700e60b 120
<> 139:856d2700e60b 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
<> 139:856d2700e60b 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<> 139:856d2700e60b 123
<> 139:856d2700e60b 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
<> 139:856d2700e60b 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<> 139:856d2700e60b 126
<> 139:856d2700e60b 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
<> 139:856d2700e60b 128 ((int64_t)(ARG3) << 32) ) >> 32))
<> 139:856d2700e60b 129
<> 139:856d2700e60b 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 131
<> 139:856d2700e60b 132
<> 139:856d2700e60b 133
<> 139:856d2700e60b 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 139:856d2700e60b 135 /* IAR iccarm specific functions */
<> 139:856d2700e60b 136
<> 139:856d2700e60b 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 138 #include <cmsis_iar.h>
<> 139:856d2700e60b 139
<> 139:856d2700e60b 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 141
<> 139:856d2700e60b 142
<> 139:856d2700e60b 143
<> 139:856d2700e60b 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 139:856d2700e60b 145 /* TI CCS specific functions */
<> 139:856d2700e60b 146
<> 139:856d2700e60b 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 148 #include <cmsis_ccs.h>
<> 139:856d2700e60b 149
<> 139:856d2700e60b 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 151
<> 139:856d2700e60b 152
<> 139:856d2700e60b 153
<> 139:856d2700e60b 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 139:856d2700e60b 155 /* GNU gcc specific functions */
<> 139:856d2700e60b 156
<> 139:856d2700e60b 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 159 {
<> 139:856d2700e60b 160 uint32_t result;
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 163 return(result);
<> 139:856d2700e60b 164 }
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 167 {
<> 139:856d2700e60b 168 uint32_t result;
<> 139:856d2700e60b 169
<> 139:856d2700e60b 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 171 return(result);
<> 139:856d2700e60b 172 }
<> 139:856d2700e60b 173
<> 139:856d2700e60b 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 175 {
<> 139:856d2700e60b 176 uint32_t result;
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 179 return(result);
<> 139:856d2700e60b 180 }
<> 139:856d2700e60b 181
<> 139:856d2700e60b 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 183 {
<> 139:856d2700e60b 184 uint32_t result;
<> 139:856d2700e60b 185
<> 139:856d2700e60b 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 187 return(result);
<> 139:856d2700e60b 188 }
<> 139:856d2700e60b 189
<> 139:856d2700e60b 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 191 {
<> 139:856d2700e60b 192 uint32_t result;
<> 139:856d2700e60b 193
<> 139:856d2700e60b 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 195 return(result);
<> 139:856d2700e60b 196 }
<> 139:856d2700e60b 197
<> 139:856d2700e60b 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 199 {
<> 139:856d2700e60b 200 uint32_t result;
<> 139:856d2700e60b 201
<> 139:856d2700e60b 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 203 return(result);
<> 139:856d2700e60b 204 }
<> 139:856d2700e60b 205
<> 139:856d2700e60b 206
<> 139:856d2700e60b 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 208 {
<> 139:856d2700e60b 209 uint32_t result;
<> 139:856d2700e60b 210
<> 139:856d2700e60b 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 212 return(result);
<> 139:856d2700e60b 213 }
<> 139:856d2700e60b 214
<> 139:856d2700e60b 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 216 {
<> 139:856d2700e60b 217 uint32_t result;
<> 139:856d2700e60b 218
<> 139:856d2700e60b 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 220 return(result);
<> 139:856d2700e60b 221 }
<> 139:856d2700e60b 222
<> 139:856d2700e60b 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 224 {
<> 139:856d2700e60b 225 uint32_t result;
<> 139:856d2700e60b 226
<> 139:856d2700e60b 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 228 return(result);
<> 139:856d2700e60b 229 }
<> 139:856d2700e60b 230
<> 139:856d2700e60b 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 232 {
<> 139:856d2700e60b 233 uint32_t result;
<> 139:856d2700e60b 234
<> 139:856d2700e60b 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 236 return(result);
<> 139:856d2700e60b 237 }
<> 139:856d2700e60b 238
<> 139:856d2700e60b 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 240 {
<> 139:856d2700e60b 241 uint32_t result;
<> 139:856d2700e60b 242
<> 139:856d2700e60b 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 244 return(result);
<> 139:856d2700e60b 245 }
<> 139:856d2700e60b 246
<> 139:856d2700e60b 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 248 {
<> 139:856d2700e60b 249 uint32_t result;
<> 139:856d2700e60b 250
<> 139:856d2700e60b 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 252 return(result);
<> 139:856d2700e60b 253 }
<> 139:856d2700e60b 254
<> 139:856d2700e60b 255
<> 139:856d2700e60b 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 257 {
<> 139:856d2700e60b 258 uint32_t result;
<> 139:856d2700e60b 259
<> 139:856d2700e60b 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 261 return(result);
<> 139:856d2700e60b 262 }
<> 139:856d2700e60b 263
<> 139:856d2700e60b 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 265 {
<> 139:856d2700e60b 266 uint32_t result;
<> 139:856d2700e60b 267
<> 139:856d2700e60b 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 269 return(result);
<> 139:856d2700e60b 270 }
<> 139:856d2700e60b 271
<> 139:856d2700e60b 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 273 {
<> 139:856d2700e60b 274 uint32_t result;
<> 139:856d2700e60b 275
<> 139:856d2700e60b 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 277 return(result);
<> 139:856d2700e60b 278 }
<> 139:856d2700e60b 279
<> 139:856d2700e60b 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 281 {
<> 139:856d2700e60b 282 uint32_t result;
<> 139:856d2700e60b 283
<> 139:856d2700e60b 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 285 return(result);
<> 139:856d2700e60b 286 }
<> 139:856d2700e60b 287
<> 139:856d2700e60b 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 289 {
<> 139:856d2700e60b 290 uint32_t result;
<> 139:856d2700e60b 291
<> 139:856d2700e60b 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 293 return(result);
<> 139:856d2700e60b 294 }
<> 139:856d2700e60b 295
<> 139:856d2700e60b 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 297 {
<> 139:856d2700e60b 298 uint32_t result;
<> 139:856d2700e60b 299
<> 139:856d2700e60b 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 301 return(result);
<> 139:856d2700e60b 302 }
<> 139:856d2700e60b 303
<> 139:856d2700e60b 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 305 {
<> 139:856d2700e60b 306 uint32_t result;
<> 139:856d2700e60b 307
<> 139:856d2700e60b 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 309 return(result);
<> 139:856d2700e60b 310 }
<> 139:856d2700e60b 311
<> 139:856d2700e60b 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 313 {
<> 139:856d2700e60b 314 uint32_t result;
<> 139:856d2700e60b 315
<> 139:856d2700e60b 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 317 return(result);
<> 139:856d2700e60b 318 }
<> 139:856d2700e60b 319
<> 139:856d2700e60b 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 321 {
<> 139:856d2700e60b 322 uint32_t result;
<> 139:856d2700e60b 323
<> 139:856d2700e60b 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 325 return(result);
<> 139:856d2700e60b 326 }
<> 139:856d2700e60b 327
<> 139:856d2700e60b 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 329 {
<> 139:856d2700e60b 330 uint32_t result;
<> 139:856d2700e60b 331
<> 139:856d2700e60b 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 333 return(result);
<> 139:856d2700e60b 334 }
<> 139:856d2700e60b 335
<> 139:856d2700e60b 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 337 {
<> 139:856d2700e60b 338 uint32_t result;
<> 139:856d2700e60b 339
<> 139:856d2700e60b 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 341 return(result);
<> 139:856d2700e60b 342 }
<> 139:856d2700e60b 343
<> 139:856d2700e60b 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 345 {
<> 139:856d2700e60b 346 uint32_t result;
<> 139:856d2700e60b 347
<> 139:856d2700e60b 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 349 return(result);
<> 139:856d2700e60b 350 }
<> 139:856d2700e60b 351
<> 139:856d2700e60b 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 353 {
<> 139:856d2700e60b 354 uint32_t result;
<> 139:856d2700e60b 355
<> 139:856d2700e60b 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 357 return(result);
<> 139:856d2700e60b 358 }
<> 139:856d2700e60b 359
<> 139:856d2700e60b 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 361 {
<> 139:856d2700e60b 362 uint32_t result;
<> 139:856d2700e60b 363
<> 139:856d2700e60b 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 365 return(result);
<> 139:856d2700e60b 366 }
<> 139:856d2700e60b 367
<> 139:856d2700e60b 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 369 {
<> 139:856d2700e60b 370 uint32_t result;
<> 139:856d2700e60b 371
<> 139:856d2700e60b 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 373 return(result);
<> 139:856d2700e60b 374 }
<> 139:856d2700e60b 375
<> 139:856d2700e60b 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 377 {
<> 139:856d2700e60b 378 uint32_t result;
<> 139:856d2700e60b 379
<> 139:856d2700e60b 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 381 return(result);
<> 139:856d2700e60b 382 }
<> 139:856d2700e60b 383
<> 139:856d2700e60b 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 385 {
<> 139:856d2700e60b 386 uint32_t result;
<> 139:856d2700e60b 387
<> 139:856d2700e60b 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 389 return(result);
<> 139:856d2700e60b 390 }
<> 139:856d2700e60b 391
<> 139:856d2700e60b 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 393 {
<> 139:856d2700e60b 394 uint32_t result;
<> 139:856d2700e60b 395
<> 139:856d2700e60b 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 397 return(result);
<> 139:856d2700e60b 398 }
<> 139:856d2700e60b 399
<> 139:856d2700e60b 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 401 {
<> 139:856d2700e60b 402 uint32_t result;
<> 139:856d2700e60b 403
<> 139:856d2700e60b 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 405 return(result);
<> 139:856d2700e60b 406 }
<> 139:856d2700e60b 407
<> 139:856d2700e60b 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 409 {
<> 139:856d2700e60b 410 uint32_t result;
<> 139:856d2700e60b 411
<> 139:856d2700e60b 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 413 return(result);
<> 139:856d2700e60b 414 }
<> 139:856d2700e60b 415
<> 139:856d2700e60b 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 417 {
<> 139:856d2700e60b 418 uint32_t result;
<> 139:856d2700e60b 419
<> 139:856d2700e60b 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 421 return(result);
<> 139:856d2700e60b 422 }
<> 139:856d2700e60b 423
<> 139:856d2700e60b 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 425 {
<> 139:856d2700e60b 426 uint32_t result;
<> 139:856d2700e60b 427
<> 139:856d2700e60b 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 429 return(result);
<> 139:856d2700e60b 430 }
<> 139:856d2700e60b 431
<> 139:856d2700e60b 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 433 {
<> 139:856d2700e60b 434 uint32_t result;
<> 139:856d2700e60b 435
<> 139:856d2700e60b 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 437 return(result);
<> 139:856d2700e60b 438 }
<> 139:856d2700e60b 439
<> 139:856d2700e60b 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 441 {
<> 139:856d2700e60b 442 uint32_t result;
<> 139:856d2700e60b 443
<> 139:856d2700e60b 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 445 return(result);
<> 139:856d2700e60b 446 }
<> 139:856d2700e60b 447
<> 139:856d2700e60b 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 449 {
<> 139:856d2700e60b 450 uint32_t result;
<> 139:856d2700e60b 451
<> 139:856d2700e60b 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 453 return(result);
<> 139:856d2700e60b 454 }
<> 139:856d2700e60b 455
<> 139:856d2700e60b 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
<> 139:856d2700e60b 457 {
<> 139:856d2700e60b 458 uint32_t result;
<> 139:856d2700e60b 459
<> 139:856d2700e60b 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 139:856d2700e60b 461 return(result);
<> 139:856d2700e60b 462 }
<> 139:856d2700e60b 463
<> 139:856d2700e60b 464 #define __SSAT16(ARG1,ARG2) \
<> 139:856d2700e60b 465 ({ \
<> 139:856d2700e60b 466 uint32_t __RES, __ARG1 = (ARG1); \
<> 139:856d2700e60b 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 139:856d2700e60b 468 __RES; \
<> 139:856d2700e60b 469 })
<> 139:856d2700e60b 470
<> 139:856d2700e60b 471 #define __USAT16(ARG1,ARG2) \
<> 139:856d2700e60b 472 ({ \
<> 139:856d2700e60b 473 uint32_t __RES, __ARG1 = (ARG1); \
<> 139:856d2700e60b 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 139:856d2700e60b 475 __RES; \
<> 139:856d2700e60b 476 })
<> 139:856d2700e60b 477
<> 139:856d2700e60b 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
<> 139:856d2700e60b 479 {
<> 139:856d2700e60b 480 uint32_t result;
<> 139:856d2700e60b 481
<> 139:856d2700e60b 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 139:856d2700e60b 483 return(result);
<> 139:856d2700e60b 484 }
<> 139:856d2700e60b 485
<> 139:856d2700e60b 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 487 {
<> 139:856d2700e60b 488 uint32_t result;
<> 139:856d2700e60b 489
<> 139:856d2700e60b 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 491 return(result);
<> 139:856d2700e60b 492 }
<> 139:856d2700e60b 493
<> 139:856d2700e60b 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
<> 139:856d2700e60b 495 {
<> 139:856d2700e60b 496 uint32_t result;
<> 139:856d2700e60b 497
<> 139:856d2700e60b 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 139:856d2700e60b 499 return(result);
<> 139:856d2700e60b 500 }
<> 139:856d2700e60b 501
<> 139:856d2700e60b 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 503 {
<> 139:856d2700e60b 504 uint32_t result;
<> 139:856d2700e60b 505
<> 139:856d2700e60b 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 507 return(result);
<> 139:856d2700e60b 508 }
<> 139:856d2700e60b 509
<> 139:856d2700e60b 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 511 {
<> 139:856d2700e60b 512 uint32_t result;
<> 139:856d2700e60b 513
<> 139:856d2700e60b 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 515 return(result);
<> 139:856d2700e60b 516 }
<> 139:856d2700e60b 517
<> 139:856d2700e60b 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 519 {
<> 139:856d2700e60b 520 uint32_t result;
<> 139:856d2700e60b 521
<> 139:856d2700e60b 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 523 return(result);
<> 139:856d2700e60b 524 }
<> 139:856d2700e60b 525
<> 139:856d2700e60b 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 139:856d2700e60b 527 {
<> 139:856d2700e60b 528 uint32_t result;
<> 139:856d2700e60b 529
<> 139:856d2700e60b 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 139:856d2700e60b 531 return(result);
<> 139:856d2700e60b 532 }
<> 139:856d2700e60b 533
<> 139:856d2700e60b 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 139:856d2700e60b 535 {
<> 139:856d2700e60b 536 uint32_t result;
<> 139:856d2700e60b 537
<> 139:856d2700e60b 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 139:856d2700e60b 539 return(result);
<> 139:856d2700e60b 540 }
<> 139:856d2700e60b 541
<> 139:856d2700e60b 542 #define __SMLALD(ARG1,ARG2,ARG3) \
<> 139:856d2700e60b 543 ({ \
<> 139:856d2700e60b 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
<> 139:856d2700e60b 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 139:856d2700e60b 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 139:856d2700e60b 547 })
<> 139:856d2700e60b 548
<> 139:856d2700e60b 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
<> 139:856d2700e60b 550 ({ \
<> 139:856d2700e60b 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
<> 139:856d2700e60b 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 139:856d2700e60b 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 139:856d2700e60b 554 })
<> 139:856d2700e60b 555
<> 139:856d2700e60b 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 557 {
<> 139:856d2700e60b 558 uint32_t result;
<> 139:856d2700e60b 559
<> 139:856d2700e60b 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 561 return(result);
<> 139:856d2700e60b 562 }
<> 139:856d2700e60b 563
<> 139:856d2700e60b 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 565 {
<> 139:856d2700e60b 566 uint32_t result;
<> 139:856d2700e60b 567
<> 139:856d2700e60b 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 569 return(result);
<> 139:856d2700e60b 570 }
<> 139:856d2700e60b 571
<> 139:856d2700e60b 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 139:856d2700e60b 573 {
<> 139:856d2700e60b 574 uint32_t result;
<> 139:856d2700e60b 575
<> 139:856d2700e60b 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 139:856d2700e60b 577 return(result);
<> 139:856d2700e60b 578 }
<> 139:856d2700e60b 579
<> 139:856d2700e60b 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 139:856d2700e60b 581 {
<> 139:856d2700e60b 582 uint32_t result;
<> 139:856d2700e60b 583
<> 139:856d2700e60b 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 139:856d2700e60b 585 return(result);
<> 139:856d2700e60b 586 }
<> 139:856d2700e60b 587
<> 139:856d2700e60b 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
<> 139:856d2700e60b 589 ({ \
<> 139:856d2700e60b 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
<> 139:856d2700e60b 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 139:856d2700e60b 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 139:856d2700e60b 593 })
<> 139:856d2700e60b 594
<> 139:856d2700e60b 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
<> 139:856d2700e60b 596 ({ \
<> 139:856d2700e60b 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
<> 139:856d2700e60b 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 139:856d2700e60b 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 139:856d2700e60b 600 })
<> 139:856d2700e60b 601
<> 139:856d2700e60b 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 603 {
<> 139:856d2700e60b 604 uint32_t result;
<> 139:856d2700e60b 605
<> 139:856d2700e60b 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 607 return(result);
<> 139:856d2700e60b 608 }
<> 139:856d2700e60b 609
<> 139:856d2700e60b 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 611 {
<> 139:856d2700e60b 612 uint32_t result;
<> 139:856d2700e60b 613
<> 139:856d2700e60b 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 615 return(result);
<> 139:856d2700e60b 616 }
<> 139:856d2700e60b 617
<> 139:856d2700e60b 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
<> 139:856d2700e60b 619 {
<> 139:856d2700e60b 620 uint32_t result;
<> 139:856d2700e60b 621
<> 139:856d2700e60b 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 139:856d2700e60b 623 return(result);
<> 139:856d2700e60b 624 }
<> 139:856d2700e60b 625
<> 139:856d2700e60b 626 #define __PKHBT(ARG1,ARG2,ARG3) \
<> 139:856d2700e60b 627 ({ \
<> 139:856d2700e60b 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 139:856d2700e60b 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 139:856d2700e60b 630 __RES; \
<> 139:856d2700e60b 631 })
<> 139:856d2700e60b 632
<> 139:856d2700e60b 633 #define __PKHTB(ARG1,ARG2,ARG3) \
<> 139:856d2700e60b 634 ({ \
<> 139:856d2700e60b 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 139:856d2700e60b 636 if (ARG3 == 0) \
<> 139:856d2700e60b 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
<> 139:856d2700e60b 638 else \
<> 139:856d2700e60b 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 139:856d2700e60b 640 __RES; \
<> 139:856d2700e60b 641 })
<> 139:856d2700e60b 642
<> 139:856d2700e60b 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
<> 139:856d2700e60b 644 {
<> 139:856d2700e60b 645 int32_t result;
<> 139:856d2700e60b 646
<> 139:856d2700e60b 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
<> 139:856d2700e60b 648 return(result);
<> 139:856d2700e60b 649 }
<> 139:856d2700e60b 650
<> 139:856d2700e60b 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 652
<> 139:856d2700e60b 653
<> 139:856d2700e60b 654
<> 139:856d2700e60b 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 139:856d2700e60b 656 /* TASKING carm specific functions */
<> 139:856d2700e60b 657
<> 139:856d2700e60b 658
<> 139:856d2700e60b 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 660 /* not yet supported */
<> 139:856d2700e60b 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 139:856d2700e60b 662
<> 139:856d2700e60b 663
<> 139:856d2700e60b 664 #endif
<> 139:856d2700e60b 665
<> 139:856d2700e60b 666 /*@} end of group CMSIS_SIMD_intrinsics */
<> 139:856d2700e60b 667
<> 139:856d2700e60b 668
<> 139:856d2700e60b 669 #endif /* __CORE_CM4_SIMD_H */
<> 139:856d2700e60b 670
<> 139:856d2700e60b 671 #ifdef __cplusplus
<> 139:856d2700e60b 672 }
<> 139:856d2700e60b 673 #endif