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mbed 2

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TARGET_EFM32PG12_STK3402/core_cm0.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_cm0.h
<> 139:856d2700e60b 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
<> 139:856d2700e60b 4 * @version V4.10
<> 139:856d2700e60b 5 * @date 18. March 2015
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #if defined ( __ICCARM__ )
<> 139:856d2700e60b 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 139:856d2700e60b 40 #endif
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 #ifndef __CORE_CM0_H_GENERIC
<> 139:856d2700e60b 43 #define __CORE_CM0_H_GENERIC
<> 139:856d2700e60b 44
<> 139:856d2700e60b 45 #ifdef __cplusplus
<> 139:856d2700e60b 46 extern "C" {
<> 139:856d2700e60b 47 #endif
<> 139:856d2700e60b 48
<> 139:856d2700e60b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 139:856d2700e60b 50 CMSIS violates the following MISRA-C:2004 rules:
<> 139:856d2700e60b 51
<> 139:856d2700e60b 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 139:856d2700e60b 53 Function definitions in header files are used to allow 'inlining'.
<> 139:856d2700e60b 54
<> 139:856d2700e60b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 139:856d2700e60b 56 Unions are used for effective representation of core registers.
<> 139:856d2700e60b 57
<> 139:856d2700e60b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 139:856d2700e60b 59 Function-like macros are used to allow more efficient code.
<> 139:856d2700e60b 60 */
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62
<> 139:856d2700e60b 63 /*******************************************************************************
<> 139:856d2700e60b 64 * CMSIS definitions
<> 139:856d2700e60b 65 ******************************************************************************/
<> 139:856d2700e60b 66 /** \ingroup Cortex_M0
<> 139:856d2700e60b 67 @{
<> 139:856d2700e60b 68 */
<> 139:856d2700e60b 69
<> 139:856d2700e60b 70 /* CMSIS CM0 definitions */
<> 139:856d2700e60b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 139:856d2700e60b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 139:856d2700e60b 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
<> 139:856d2700e60b 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 139:856d2700e60b 75
<> 139:856d2700e60b 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 139:856d2700e60b 77
<> 139:856d2700e60b 78
<> 139:856d2700e60b 79 #if defined ( __CC_ARM )
<> 139:856d2700e60b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 139:856d2700e60b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 139:856d2700e60b 82 #define __STATIC_INLINE static __inline
<> 139:856d2700e60b 83
<> 139:856d2700e60b 84 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 139:856d2700e60b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 139:856d2700e60b 87 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 88
<> 139:856d2700e60b 89 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 139:856d2700e60b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 139:856d2700e60b 92 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 93
<> 139:856d2700e60b 94 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 139:856d2700e60b 96 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 97
<> 139:856d2700e60b 98 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 139:856d2700e60b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 139:856d2700e60b 101 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 102
<> 139:856d2700e60b 103 #elif defined ( __CSMC__ )
<> 139:856d2700e60b 104 #define __packed
<> 139:856d2700e60b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 139:856d2700e60b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 139:856d2700e60b 107 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 108
<> 139:856d2700e60b 109 #endif
<> 139:856d2700e60b 110
<> 139:856d2700e60b 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 139:856d2700e60b 112 This core does not support an FPU at all
<> 139:856d2700e60b 113 */
<> 139:856d2700e60b 114 #define __FPU_USED 0
<> 139:856d2700e60b 115
<> 139:856d2700e60b 116 #if defined ( __CC_ARM )
<> 139:856d2700e60b 117 #if defined __TARGET_FPU_VFP
<> 139:856d2700e60b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 119 #endif
<> 139:856d2700e60b 120
<> 139:856d2700e60b 121 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 139:856d2700e60b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 124 #endif
<> 139:856d2700e60b 125
<> 139:856d2700e60b 126 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 127 #if defined __ARMVFP__
<> 139:856d2700e60b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 129 #endif
<> 139:856d2700e60b 130
<> 139:856d2700e60b 131 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 132 #if defined __TI__VFP_SUPPORT____
<> 139:856d2700e60b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 134 #endif
<> 139:856d2700e60b 135
<> 139:856d2700e60b 136 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 137 #if defined __FPU_VFP__
<> 139:856d2700e60b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 139 #endif
<> 139:856d2700e60b 140
<> 139:856d2700e60b 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 139:856d2700e60b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 139:856d2700e60b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 144 #endif
<> 139:856d2700e60b 145 #endif
<> 139:856d2700e60b 146
<> 139:856d2700e60b 147 #include <stdint.h> /* standard types definitions */
<> 139:856d2700e60b 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 139:856d2700e60b 149 #include <core_cmFunc.h> /* Core Function Access */
<> 139:856d2700e60b 150
<> 139:856d2700e60b 151 #ifdef __cplusplus
<> 139:856d2700e60b 152 }
<> 139:856d2700e60b 153 #endif
<> 139:856d2700e60b 154
<> 139:856d2700e60b 155 #endif /* __CORE_CM0_H_GENERIC */
<> 139:856d2700e60b 156
<> 139:856d2700e60b 157 #ifndef __CMSIS_GENERIC
<> 139:856d2700e60b 158
<> 139:856d2700e60b 159 #ifndef __CORE_CM0_H_DEPENDANT
<> 139:856d2700e60b 160 #define __CORE_CM0_H_DEPENDANT
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 #ifdef __cplusplus
<> 139:856d2700e60b 163 extern "C" {
<> 139:856d2700e60b 164 #endif
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 /* check device defines and use defaults */
<> 139:856d2700e60b 167 #if defined __CHECK_DEVICE_DEFINES
<> 139:856d2700e60b 168 #ifndef __CM0_REV
<> 139:856d2700e60b 169 #define __CM0_REV 0x0000
<> 139:856d2700e60b 170 #warning "__CM0_REV not defined in device header file; using default!"
<> 139:856d2700e60b 171 #endif
<> 139:856d2700e60b 172
<> 139:856d2700e60b 173 #ifndef __NVIC_PRIO_BITS
<> 139:856d2700e60b 174 #define __NVIC_PRIO_BITS 2
<> 139:856d2700e60b 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 139:856d2700e60b 176 #endif
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 #ifndef __Vendor_SysTickConfig
<> 139:856d2700e60b 179 #define __Vendor_SysTickConfig 0
<> 139:856d2700e60b 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 139:856d2700e60b 181 #endif
<> 139:856d2700e60b 182 #endif
<> 139:856d2700e60b 183
<> 139:856d2700e60b 184 /* IO definitions (access restrictions to peripheral registers) */
<> 139:856d2700e60b 185 /**
<> 139:856d2700e60b 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 139:856d2700e60b 187
<> 139:856d2700e60b 188 <strong>IO Type Qualifiers</strong> are used
<> 139:856d2700e60b 189 \li to specify the access to peripheral variables.
<> 139:856d2700e60b 190 \li for automatic generation of peripheral register debug information.
<> 139:856d2700e60b 191 */
<> 139:856d2700e60b 192 #ifdef __cplusplus
<> 139:856d2700e60b 193 #define __I volatile /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 194 #else
<> 139:856d2700e60b 195 #define __I volatile const /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 196 #endif
<> 139:856d2700e60b 197 #define __O volatile /*!< Defines 'write only' permissions */
<> 139:856d2700e60b 198 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 139:856d2700e60b 199
<> 139:856d2700e60b 200 #ifdef __cplusplus
<> 139:856d2700e60b 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 202 #else
<> 139:856d2700e60b 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 204 #endif
<> 139:856d2700e60b 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 139:856d2700e60b 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 139:856d2700e60b 207
<> 139:856d2700e60b 208 /*@} end of group Cortex_M0 */
<> 139:856d2700e60b 209
<> 139:856d2700e60b 210
<> 139:856d2700e60b 211
<> 139:856d2700e60b 212 /*******************************************************************************
<> 139:856d2700e60b 213 * Register Abstraction
<> 139:856d2700e60b 214 Core Register contain:
<> 139:856d2700e60b 215 - Core Register
<> 139:856d2700e60b 216 - Core NVIC Register
<> 139:856d2700e60b 217 - Core SCB Register
<> 139:856d2700e60b 218 - Core SysTick Register
<> 139:856d2700e60b 219 ******************************************************************************/
<> 139:856d2700e60b 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 139:856d2700e60b 221 \brief Type definitions and defines for Cortex-M processor based devices.
<> 139:856d2700e60b 222 */
<> 139:856d2700e60b 223
<> 139:856d2700e60b 224 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 225 \defgroup CMSIS_CORE Status and Control Registers
<> 139:856d2700e60b 226 \brief Core Register type definitions.
<> 139:856d2700e60b 227 @{
<> 139:856d2700e60b 228 */
<> 139:856d2700e60b 229
<> 139:856d2700e60b 230 /** \brief Union type to access the Application Program Status Register (APSR).
<> 139:856d2700e60b 231 */
<> 139:856d2700e60b 232 typedef union
<> 139:856d2700e60b 233 {
<> 139:856d2700e60b 234 struct
<> 139:856d2700e60b 235 {
<> 139:856d2700e60b 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 139:856d2700e60b 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 241 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 242 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 243 } APSR_Type;
<> 139:856d2700e60b 244
<> 139:856d2700e60b 245 /* APSR Register Definitions */
<> 139:856d2700e60b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 139:856d2700e60b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 139:856d2700e60b 248
<> 139:856d2700e60b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 139:856d2700e60b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 139:856d2700e60b 251
<> 139:856d2700e60b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 139:856d2700e60b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 139:856d2700e60b 254
<> 139:856d2700e60b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 139:856d2700e60b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 139:856d2700e60b 257
<> 139:856d2700e60b 258
<> 139:856d2700e60b 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 139:856d2700e60b 260 */
<> 139:856d2700e60b 261 typedef union
<> 139:856d2700e60b 262 {
<> 139:856d2700e60b 263 struct
<> 139:856d2700e60b 264 {
<> 139:856d2700e60b 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 139:856d2700e60b 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 139:856d2700e60b 267 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 268 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 269 } IPSR_Type;
<> 139:856d2700e60b 270
<> 139:856d2700e60b 271 /* IPSR Register Definitions */
<> 139:856d2700e60b 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 139:856d2700e60b 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 139:856d2700e60b 274
<> 139:856d2700e60b 275
<> 139:856d2700e60b 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 139:856d2700e60b 277 */
<> 139:856d2700e60b 278 typedef union
<> 139:856d2700e60b 279 {
<> 139:856d2700e60b 280 struct
<> 139:856d2700e60b 281 {
<> 139:856d2700e60b 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 139:856d2700e60b 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 139:856d2700e60b 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 139:856d2700e60b 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 139:856d2700e60b 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 290 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 291 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 292 } xPSR_Type;
<> 139:856d2700e60b 293
<> 139:856d2700e60b 294 /* xPSR Register Definitions */
<> 139:856d2700e60b 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 139:856d2700e60b 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 139:856d2700e60b 297
<> 139:856d2700e60b 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 139:856d2700e60b 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 139:856d2700e60b 300
<> 139:856d2700e60b 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 139:856d2700e60b 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 139:856d2700e60b 303
<> 139:856d2700e60b 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 139:856d2700e60b 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 139:856d2700e60b 306
<> 139:856d2700e60b 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 139:856d2700e60b 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 139:856d2700e60b 309
<> 139:856d2700e60b 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 139:856d2700e60b 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 139:856d2700e60b 312
<> 139:856d2700e60b 313
<> 139:856d2700e60b 314 /** \brief Union type to access the Control Registers (CONTROL).
<> 139:856d2700e60b 315 */
<> 139:856d2700e60b 316 typedef union
<> 139:856d2700e60b 317 {
<> 139:856d2700e60b 318 struct
<> 139:856d2700e60b 319 {
<> 139:856d2700e60b 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
<> 139:856d2700e60b 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 139:856d2700e60b 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 139:856d2700e60b 323 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 324 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 325 } CONTROL_Type;
<> 139:856d2700e60b 326
<> 139:856d2700e60b 327 /* CONTROL Register Definitions */
<> 139:856d2700e60b 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 139:856d2700e60b 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 139:856d2700e60b 330
<> 139:856d2700e60b 331 /*@} end of group CMSIS_CORE */
<> 139:856d2700e60b 332
<> 139:856d2700e60b 333
<> 139:856d2700e60b 334 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 139:856d2700e60b 336 \brief Type definitions for the NVIC Registers
<> 139:856d2700e60b 337 @{
<> 139:856d2700e60b 338 */
<> 139:856d2700e60b 339
<> 139:856d2700e60b 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 139:856d2700e60b 341 */
<> 139:856d2700e60b 342 typedef struct
<> 139:856d2700e60b 343 {
<> 139:856d2700e60b 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 139:856d2700e60b 345 uint32_t RESERVED0[31];
<> 139:856d2700e60b 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 139:856d2700e60b 347 uint32_t RSERVED1[31];
<> 139:856d2700e60b 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 139:856d2700e60b 349 uint32_t RESERVED2[31];
<> 139:856d2700e60b 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 139:856d2700e60b 351 uint32_t RESERVED3[31];
<> 139:856d2700e60b 352 uint32_t RESERVED4[64];
<> 139:856d2700e60b 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 139:856d2700e60b 354 } NVIC_Type;
<> 139:856d2700e60b 355
<> 139:856d2700e60b 356 /*@} end of group CMSIS_NVIC */
<> 139:856d2700e60b 357
<> 139:856d2700e60b 358
<> 139:856d2700e60b 359 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 360 \defgroup CMSIS_SCB System Control Block (SCB)
<> 139:856d2700e60b 361 \brief Type definitions for the System Control Block Registers
<> 139:856d2700e60b 362 @{
<> 139:856d2700e60b 363 */
<> 139:856d2700e60b 364
<> 139:856d2700e60b 365 /** \brief Structure type to access the System Control Block (SCB).
<> 139:856d2700e60b 366 */
<> 139:856d2700e60b 367 typedef struct
<> 139:856d2700e60b 368 {
<> 139:856d2700e60b 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 139:856d2700e60b 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 139:856d2700e60b 371 uint32_t RESERVED0;
<> 139:856d2700e60b 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 139:856d2700e60b 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 139:856d2700e60b 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 139:856d2700e60b 375 uint32_t RESERVED1;
<> 139:856d2700e60b 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 139:856d2700e60b 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 139:856d2700e60b 378 } SCB_Type;
<> 139:856d2700e60b 379
<> 139:856d2700e60b 380 /* SCB CPUID Register Definitions */
<> 139:856d2700e60b 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 139:856d2700e60b 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 139:856d2700e60b 383
<> 139:856d2700e60b 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 139:856d2700e60b 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 139:856d2700e60b 386
<> 139:856d2700e60b 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 139:856d2700e60b 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 139:856d2700e60b 389
<> 139:856d2700e60b 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 139:856d2700e60b 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 139:856d2700e60b 392
<> 139:856d2700e60b 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 139:856d2700e60b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 139:856d2700e60b 395
<> 139:856d2700e60b 396 /* SCB Interrupt Control State Register Definitions */
<> 139:856d2700e60b 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 139:856d2700e60b 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 139:856d2700e60b 399
<> 139:856d2700e60b 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 139:856d2700e60b 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 139:856d2700e60b 402
<> 139:856d2700e60b 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 139:856d2700e60b 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 139:856d2700e60b 405
<> 139:856d2700e60b 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 139:856d2700e60b 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 139:856d2700e60b 408
<> 139:856d2700e60b 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 139:856d2700e60b 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 139:856d2700e60b 411
<> 139:856d2700e60b 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 139:856d2700e60b 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 139:856d2700e60b 414
<> 139:856d2700e60b 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 139:856d2700e60b 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 139:856d2700e60b 417
<> 139:856d2700e60b 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 139:856d2700e60b 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 139:856d2700e60b 420
<> 139:856d2700e60b 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 139:856d2700e60b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 139:856d2700e60b 423
<> 139:856d2700e60b 424 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 139:856d2700e60b 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 139:856d2700e60b 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 139:856d2700e60b 427
<> 139:856d2700e60b 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 139:856d2700e60b 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 139:856d2700e60b 430
<> 139:856d2700e60b 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 139:856d2700e60b 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 139:856d2700e60b 433
<> 139:856d2700e60b 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 139:856d2700e60b 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 139:856d2700e60b 436
<> 139:856d2700e60b 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 139:856d2700e60b 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 139:856d2700e60b 439
<> 139:856d2700e60b 440 /* SCB System Control Register Definitions */
<> 139:856d2700e60b 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 139:856d2700e60b 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 139:856d2700e60b 443
<> 139:856d2700e60b 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 139:856d2700e60b 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 139:856d2700e60b 446
<> 139:856d2700e60b 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 139:856d2700e60b 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 139:856d2700e60b 449
<> 139:856d2700e60b 450 /* SCB Configuration Control Register Definitions */
<> 139:856d2700e60b 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 139:856d2700e60b 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 139:856d2700e60b 453
<> 139:856d2700e60b 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 139:856d2700e60b 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 139:856d2700e60b 456
<> 139:856d2700e60b 457 /* SCB System Handler Control and State Register Definitions */
<> 139:856d2700e60b 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 139:856d2700e60b 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 139:856d2700e60b 460
<> 139:856d2700e60b 461 /*@} end of group CMSIS_SCB */
<> 139:856d2700e60b 462
<> 139:856d2700e60b 463
<> 139:856d2700e60b 464 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 139:856d2700e60b 466 \brief Type definitions for the System Timer Registers.
<> 139:856d2700e60b 467 @{
<> 139:856d2700e60b 468 */
<> 139:856d2700e60b 469
<> 139:856d2700e60b 470 /** \brief Structure type to access the System Timer (SysTick).
<> 139:856d2700e60b 471 */
<> 139:856d2700e60b 472 typedef struct
<> 139:856d2700e60b 473 {
<> 139:856d2700e60b 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 139:856d2700e60b 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 139:856d2700e60b 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 139:856d2700e60b 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 139:856d2700e60b 478 } SysTick_Type;
<> 139:856d2700e60b 479
<> 139:856d2700e60b 480 /* SysTick Control / Status Register Definitions */
<> 139:856d2700e60b 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 139:856d2700e60b 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 139:856d2700e60b 483
<> 139:856d2700e60b 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 139:856d2700e60b 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 139:856d2700e60b 486
<> 139:856d2700e60b 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 139:856d2700e60b 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 139:856d2700e60b 489
<> 139:856d2700e60b 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 139:856d2700e60b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 139:856d2700e60b 492
<> 139:856d2700e60b 493 /* SysTick Reload Register Definitions */
<> 139:856d2700e60b 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 139:856d2700e60b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 139:856d2700e60b 496
<> 139:856d2700e60b 497 /* SysTick Current Register Definitions */
<> 139:856d2700e60b 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 139:856d2700e60b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 139:856d2700e60b 500
<> 139:856d2700e60b 501 /* SysTick Calibration Register Definitions */
<> 139:856d2700e60b 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 139:856d2700e60b 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 139:856d2700e60b 504
<> 139:856d2700e60b 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 139:856d2700e60b 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 139:856d2700e60b 507
<> 139:856d2700e60b 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 139:856d2700e60b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 139:856d2700e60b 510
<> 139:856d2700e60b 511 /*@} end of group CMSIS_SysTick */
<> 139:856d2700e60b 512
<> 139:856d2700e60b 513
<> 139:856d2700e60b 514 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 139:856d2700e60b 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 139:856d2700e60b 517 are only accessible over DAP and not via processor. Therefore
<> 139:856d2700e60b 518 they are not covered by the Cortex-M0 header file.
<> 139:856d2700e60b 519 @{
<> 139:856d2700e60b 520 */
<> 139:856d2700e60b 521 /*@} end of group CMSIS_CoreDebug */
<> 139:856d2700e60b 522
<> 139:856d2700e60b 523
<> 139:856d2700e60b 524 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 525 \defgroup CMSIS_core_base Core Definitions
<> 139:856d2700e60b 526 \brief Definitions for base addresses, unions, and structures.
<> 139:856d2700e60b 527 @{
<> 139:856d2700e60b 528 */
<> 139:856d2700e60b 529
<> 139:856d2700e60b 530 /* Memory mapping of Cortex-M0 Hardware */
<> 139:856d2700e60b 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 139:856d2700e60b 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 139:856d2700e60b 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 139:856d2700e60b 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 139:856d2700e60b 535
<> 139:856d2700e60b 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 139:856d2700e60b 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 139:856d2700e60b 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 139:856d2700e60b 539
<> 139:856d2700e60b 540
<> 139:856d2700e60b 541 /*@} */
<> 139:856d2700e60b 542
<> 139:856d2700e60b 543
<> 139:856d2700e60b 544
<> 139:856d2700e60b 545 /*******************************************************************************
<> 139:856d2700e60b 546 * Hardware Abstraction Layer
<> 139:856d2700e60b 547 Core Function Interface contains:
<> 139:856d2700e60b 548 - Core NVIC Functions
<> 139:856d2700e60b 549 - Core SysTick Functions
<> 139:856d2700e60b 550 - Core Register Access Functions
<> 139:856d2700e60b 551 ******************************************************************************/
<> 139:856d2700e60b 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 139:856d2700e60b 553 */
<> 139:856d2700e60b 554
<> 139:856d2700e60b 555
<> 139:856d2700e60b 556
<> 139:856d2700e60b 557 /* ########################## NVIC functions #################################### */
<> 139:856d2700e60b 558 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 139:856d2700e60b 560 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 139:856d2700e60b 561 @{
<> 139:856d2700e60b 562 */
<> 139:856d2700e60b 563
<> 139:856d2700e60b 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 139:856d2700e60b 565 /* The following MACROS handle generation of the register offset and byte masks */
<> 139:856d2700e60b 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 139:856d2700e60b 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 139:856d2700e60b 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 139:856d2700e60b 569
<> 139:856d2700e60b 570
<> 139:856d2700e60b 571 /** \brief Enable External Interrupt
<> 139:856d2700e60b 572
<> 139:856d2700e60b 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 139:856d2700e60b 574
<> 139:856d2700e60b 575 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 576 */
<> 139:856d2700e60b 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 578 {
<> 139:856d2700e60b 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 580 }
<> 139:856d2700e60b 581
<> 139:856d2700e60b 582
<> 139:856d2700e60b 583 /** \brief Disable External Interrupt
<> 139:856d2700e60b 584
<> 139:856d2700e60b 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 139:856d2700e60b 586
<> 139:856d2700e60b 587 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 588 */
<> 139:856d2700e60b 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 590 {
<> 139:856d2700e60b 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 592 __DSB();
<> 139:856d2700e60b 593 __ISB();
<> 139:856d2700e60b 594 }
<> 139:856d2700e60b 595
<> 139:856d2700e60b 596
<> 139:856d2700e60b 597 /** \brief Get Pending Interrupt
<> 139:856d2700e60b 598
<> 139:856d2700e60b 599 The function reads the pending register in the NVIC and returns the pending bit
<> 139:856d2700e60b 600 for the specified interrupt.
<> 139:856d2700e60b 601
<> 139:856d2700e60b 602 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 603
<> 139:856d2700e60b 604 \return 0 Interrupt status is not pending.
<> 139:856d2700e60b 605 \return 1 Interrupt status is pending.
<> 139:856d2700e60b 606 */
<> 139:856d2700e60b 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 608 {
<> 139:856d2700e60b 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 139:856d2700e60b 610 }
<> 139:856d2700e60b 611
<> 139:856d2700e60b 612
<> 139:856d2700e60b 613 /** \brief Set Pending Interrupt
<> 139:856d2700e60b 614
<> 139:856d2700e60b 615 The function sets the pending bit of an external interrupt.
<> 139:856d2700e60b 616
<> 139:856d2700e60b 617 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 139:856d2700e60b 618 */
<> 139:856d2700e60b 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 620 {
<> 139:856d2700e60b 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 622 }
<> 139:856d2700e60b 623
<> 139:856d2700e60b 624
<> 139:856d2700e60b 625 /** \brief Clear Pending Interrupt
<> 139:856d2700e60b 626
<> 139:856d2700e60b 627 The function clears the pending bit of an external interrupt.
<> 139:856d2700e60b 628
<> 139:856d2700e60b 629 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 139:856d2700e60b 630 */
<> 139:856d2700e60b 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 139:856d2700e60b 632 {
<> 139:856d2700e60b 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 139:856d2700e60b 634 }
<> 139:856d2700e60b 635
<> 139:856d2700e60b 636
<> 139:856d2700e60b 637 /** \brief Set Interrupt Priority
<> 139:856d2700e60b 638
<> 139:856d2700e60b 639 The function sets the priority of an interrupt.
<> 139:856d2700e60b 640
<> 139:856d2700e60b 641 \note The priority cannot be set for every core interrupt.
<> 139:856d2700e60b 642
<> 139:856d2700e60b 643 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 644 \param [in] priority Priority to set.
<> 139:856d2700e60b 645 */
<> 139:856d2700e60b 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 139:856d2700e60b 647 {
<> 139:856d2700e60b 648 if((int32_t)(IRQn) < 0) {
<> 139:856d2700e60b 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 139:856d2700e60b 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 139:856d2700e60b 651 }
<> 139:856d2700e60b 652 else {
<> 139:856d2700e60b 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 139:856d2700e60b 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 139:856d2700e60b 655 }
<> 139:856d2700e60b 656 }
<> 139:856d2700e60b 657
<> 139:856d2700e60b 658
<> 139:856d2700e60b 659 /** \brief Get Interrupt Priority
<> 139:856d2700e60b 660
<> 139:856d2700e60b 661 The function reads the priority of an interrupt. The interrupt
<> 139:856d2700e60b 662 number can be positive to specify an external (device specific)
<> 139:856d2700e60b 663 interrupt, or negative to specify an internal (core) interrupt.
<> 139:856d2700e60b 664
<> 139:856d2700e60b 665
<> 139:856d2700e60b 666 \param [in] IRQn Interrupt number.
<> 139:856d2700e60b 667 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 139:856d2700e60b 668 priority bits of the microcontroller.
<> 139:856d2700e60b 669 */
<> 139:856d2700e60b 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 139:856d2700e60b 671 {
<> 139:856d2700e60b 672
<> 139:856d2700e60b 673 if((int32_t)(IRQn) < 0) {
<> 139:856d2700e60b 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 139:856d2700e60b 675 }
<> 139:856d2700e60b 676 else {
<> 139:856d2700e60b 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 139:856d2700e60b 678 }
<> 139:856d2700e60b 679 }
<> 139:856d2700e60b 680
<> 139:856d2700e60b 681
<> 139:856d2700e60b 682 /** \brief System Reset
<> 139:856d2700e60b 683
<> 139:856d2700e60b 684 The function initiates a system reset request to reset the MCU.
<> 139:856d2700e60b 685 */
<> 139:856d2700e60b 686 __STATIC_INLINE void NVIC_SystemReset(void)
<> 139:856d2700e60b 687 {
<> 139:856d2700e60b 688 __DSB(); /* Ensure all outstanding memory accesses included
<> 139:856d2700e60b 689 buffered write are completed before reset */
<> 139:856d2700e60b 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 139:856d2700e60b 691 SCB_AIRCR_SYSRESETREQ_Msk);
<> 139:856d2700e60b 692 __DSB(); /* Ensure completion of memory access */
<> 139:856d2700e60b 693 while(1) { __NOP(); } /* wait until reset */
<> 139:856d2700e60b 694 }
<> 139:856d2700e60b 695
<> 139:856d2700e60b 696 /*@} end of CMSIS_Core_NVICFunctions */
<> 139:856d2700e60b 697
<> 139:856d2700e60b 698
<> 139:856d2700e60b 699
<> 139:856d2700e60b 700 /* ################################## SysTick function ############################################ */
<> 139:856d2700e60b 701 /** \ingroup CMSIS_Core_FunctionInterface
<> 139:856d2700e60b 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 139:856d2700e60b 703 \brief Functions that configure the System.
<> 139:856d2700e60b 704 @{
<> 139:856d2700e60b 705 */
<> 139:856d2700e60b 706
<> 139:856d2700e60b 707 #if (__Vendor_SysTickConfig == 0)
<> 139:856d2700e60b 708
<> 139:856d2700e60b 709 /** \brief System Tick Configuration
<> 139:856d2700e60b 710
<> 139:856d2700e60b 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 139:856d2700e60b 712 Counter is in free running mode to generate periodic interrupts.
<> 139:856d2700e60b 713
<> 139:856d2700e60b 714 \param [in] ticks Number of ticks between two interrupts.
<> 139:856d2700e60b 715
<> 139:856d2700e60b 716 \return 0 Function succeeded.
<> 139:856d2700e60b 717 \return 1 Function failed.
<> 139:856d2700e60b 718
<> 139:856d2700e60b 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 139:856d2700e60b 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 139:856d2700e60b 721 must contain a vendor-specific implementation of this function.
<> 139:856d2700e60b 722
<> 139:856d2700e60b 723 */
<> 139:856d2700e60b 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 139:856d2700e60b 725 {
<> 139:856d2700e60b 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 139:856d2700e60b 727
<> 139:856d2700e60b 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 139:856d2700e60b 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 139:856d2700e60b 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 139:856d2700e60b 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 139:856d2700e60b 732 SysTick_CTRL_TICKINT_Msk |
<> 139:856d2700e60b 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 139:856d2700e60b 734 return (0UL); /* Function successful */
<> 139:856d2700e60b 735 }
<> 139:856d2700e60b 736
<> 139:856d2700e60b 737 #endif
<> 139:856d2700e60b 738
<> 139:856d2700e60b 739 /*@} end of CMSIS_Core_SysTickFunctions */
<> 139:856d2700e60b 740
<> 139:856d2700e60b 741
<> 139:856d2700e60b 742
<> 139:856d2700e60b 743
<> 139:856d2700e60b 744 #ifdef __cplusplus
<> 139:856d2700e60b 745 }
<> 139:856d2700e60b 746 #endif
<> 139:856d2700e60b 747
<> 139:856d2700e60b 748 #endif /* __CORE_CM0_H_DEPENDANT */
<> 139:856d2700e60b 749
<> 139:856d2700e60b 750 #endif /* __CMSIS_GENERIC */