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TARGET_EFM32PG12_STK3402/core_ca_mmu.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 ;/**************************************************************************//**
<> 139:856d2700e60b 2 ; * @file core_ca_mmu.h
<> 139:856d2700e60b 3 ; * @brief MMU Startup File for A9_MP Device Series
<> 139:856d2700e60b 4 ; * @version V1.01
<> 139:856d2700e60b 5 ; * @date 10 Sept 2014
<> 139:856d2700e60b 6 ; *
<> 139:856d2700e60b 7 ; * @note
<> 139:856d2700e60b 8 ; *
<> 139:856d2700e60b 9 ; ******************************************************************************/
<> 139:856d2700e60b 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
<> 139:856d2700e60b 11 ;
<> 139:856d2700e60b 12 ; All rights reserved.
<> 139:856d2700e60b 13 ; Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 ; modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 ; - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 ; notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 ; - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 ; notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 ; documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 ; - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 ; to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 ; specific prior written permission.
<> 139:856d2700e60b 23 ; *
<> 139:856d2700e60b 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 ; POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ; ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37 #ifdef __cplusplus
<> 139:856d2700e60b 38 extern "C" {
<> 139:856d2700e60b 39 #endif
<> 139:856d2700e60b 40
<> 139:856d2700e60b 41 #ifndef _MMU_FUNC_H
<> 139:856d2700e60b 42 #define _MMU_FUNC_H
<> 139:856d2700e60b 43
<> 139:856d2700e60b 44 #define SECTION_DESCRIPTOR (0x2)
<> 139:856d2700e60b 45 #define SECTION_MASK (0xFFFFFFFC)
<> 139:856d2700e60b 46
<> 139:856d2700e60b 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
<> 139:856d2700e60b 48 #define SECTION_B_SHIFT (2)
<> 139:856d2700e60b 49 #define SECTION_C_SHIFT (3)
<> 139:856d2700e60b 50 #define SECTION_TEX0_SHIFT (12)
<> 139:856d2700e60b 51 #define SECTION_TEX1_SHIFT (13)
<> 139:856d2700e60b 52 #define SECTION_TEX2_SHIFT (14)
<> 139:856d2700e60b 53
<> 139:856d2700e60b 54 #define SECTION_XN_MASK (0xFFFFFFEF)
<> 139:856d2700e60b 55 #define SECTION_XN_SHIFT (4)
<> 139:856d2700e60b 56
<> 139:856d2700e60b 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
<> 139:856d2700e60b 58 #define SECTION_DOMAIN_SHIFT (5)
<> 139:856d2700e60b 59
<> 139:856d2700e60b 60 #define SECTION_P_MASK (0xFFFFFDFF)
<> 139:856d2700e60b 61 #define SECTION_P_SHIFT (9)
<> 139:856d2700e60b 62
<> 139:856d2700e60b 63 #define SECTION_AP_MASK (0xFFFF73FF)
<> 139:856d2700e60b 64 #define SECTION_AP_SHIFT (10)
<> 139:856d2700e60b 65 #define SECTION_AP2_SHIFT (15)
<> 139:856d2700e60b 66
<> 139:856d2700e60b 67 #define SECTION_S_MASK (0xFFFEFFFF)
<> 139:856d2700e60b 68 #define SECTION_S_SHIFT (16)
<> 139:856d2700e60b 69
<> 139:856d2700e60b 70 #define SECTION_NG_MASK (0xFFFDFFFF)
<> 139:856d2700e60b 71 #define SECTION_NG_SHIFT (17)
<> 139:856d2700e60b 72
<> 139:856d2700e60b 73 #define SECTION_NS_MASK (0xFFF7FFFF)
<> 139:856d2700e60b 74 #define SECTION_NS_SHIFT (19)
<> 139:856d2700e60b 75
<> 139:856d2700e60b 76
<> 139:856d2700e60b 77 #define PAGE_L1_DESCRIPTOR (0x1)
<> 139:856d2700e60b 78 #define PAGE_L1_MASK (0xFFFFFFFC)
<> 139:856d2700e60b 79
<> 139:856d2700e60b 80 #define PAGE_L2_4K_DESC (0x2)
<> 139:856d2700e60b 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
<> 139:856d2700e60b 82
<> 139:856d2700e60b 83 #define PAGE_L2_64K_DESC (0x1)
<> 139:856d2700e60b 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
<> 139:856d2700e60b 85
<> 139:856d2700e60b 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
<> 139:856d2700e60b 87 #define PAGE_4K_B_SHIFT (2)
<> 139:856d2700e60b 88 #define PAGE_4K_C_SHIFT (3)
<> 139:856d2700e60b 89 #define PAGE_4K_TEX0_SHIFT (6)
<> 139:856d2700e60b 90 #define PAGE_4K_TEX1_SHIFT (7)
<> 139:856d2700e60b 91 #define PAGE_4K_TEX2_SHIFT (8)
<> 139:856d2700e60b 92
<> 139:856d2700e60b 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
<> 139:856d2700e60b 94 #define PAGE_64K_B_SHIFT (2)
<> 139:856d2700e60b 95 #define PAGE_64K_C_SHIFT (3)
<> 139:856d2700e60b 96 #define PAGE_64K_TEX0_SHIFT (12)
<> 139:856d2700e60b 97 #define PAGE_64K_TEX1_SHIFT (13)
<> 139:856d2700e60b 98 #define PAGE_64K_TEX2_SHIFT (14)
<> 139:856d2700e60b 99
<> 139:856d2700e60b 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
<> 139:856d2700e60b 101 #define PAGE_B_SHIFT (2)
<> 139:856d2700e60b 102 #define PAGE_C_SHIFT (3)
<> 139:856d2700e60b 103 #define PAGE_TEX_SHIFT (12)
<> 139:856d2700e60b 104
<> 139:856d2700e60b 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
<> 139:856d2700e60b 106 #define PAGE_XN_4K_SHIFT (0)
<> 139:856d2700e60b 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
<> 139:856d2700e60b 108 #define PAGE_XN_64K_SHIFT (15)
<> 139:856d2700e60b 109
<> 139:856d2700e60b 110
<> 139:856d2700e60b 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
<> 139:856d2700e60b 112 #define PAGE_DOMAIN_SHIFT (5)
<> 139:856d2700e60b 113
<> 139:856d2700e60b 114 #define PAGE_P_MASK (0xFFFFFDFF)
<> 139:856d2700e60b 115 #define PAGE_P_SHIFT (9)
<> 139:856d2700e60b 116
<> 139:856d2700e60b 117 #define PAGE_AP_MASK (0xFFFFFDCF)
<> 139:856d2700e60b 118 #define PAGE_AP_SHIFT (4)
<> 139:856d2700e60b 119 #define PAGE_AP2_SHIFT (9)
<> 139:856d2700e60b 120
<> 139:856d2700e60b 121 #define PAGE_S_MASK (0xFFFFFBFF)
<> 139:856d2700e60b 122 #define PAGE_S_SHIFT (10)
<> 139:856d2700e60b 123
<> 139:856d2700e60b 124 #define PAGE_NG_MASK (0xFFFFF7FF)
<> 139:856d2700e60b 125 #define PAGE_NG_SHIFT (11)
<> 139:856d2700e60b 126
<> 139:856d2700e60b 127 #define PAGE_NS_MASK (0xFFFFFFF7)
<> 139:856d2700e60b 128 #define PAGE_NS_SHIFT (3)
<> 139:856d2700e60b 129
<> 139:856d2700e60b 130 #define OFFSET_1M (0x00100000)
<> 139:856d2700e60b 131 #define OFFSET_64K (0x00010000)
<> 139:856d2700e60b 132 #define OFFSET_4K (0x00001000)
<> 139:856d2700e60b 133
<> 139:856d2700e60b 134 #define DESCRIPTOR_FAULT (0x00000000)
<> 139:856d2700e60b 135
<> 139:856d2700e60b 136 /* ########################### MMU Function Access ########################### */
<> 139:856d2700e60b 137 /** \ingroup MMU_FunctionInterface
<> 139:856d2700e60b 138 \defgroup MMU_Functions MMU Functions Interface
<> 139:856d2700e60b 139 @{
<> 139:856d2700e60b 140 */
<> 139:856d2700e60b 141
<> 139:856d2700e60b 142 /* Attributes enumerations */
<> 139:856d2700e60b 143
<> 139:856d2700e60b 144 /* Region size attributes */
<> 139:856d2700e60b 145 typedef enum
<> 139:856d2700e60b 146 {
<> 139:856d2700e60b 147 SECTION,
<> 139:856d2700e60b 148 PAGE_4k,
<> 139:856d2700e60b 149 PAGE_64k,
<> 139:856d2700e60b 150 } mmu_region_size_Type;
<> 139:856d2700e60b 151
<> 139:856d2700e60b 152 /* Region type attributes */
<> 139:856d2700e60b 153 typedef enum
<> 139:856d2700e60b 154 {
<> 139:856d2700e60b 155 NORMAL,
<> 139:856d2700e60b 156 DEVICE,
<> 139:856d2700e60b 157 SHARED_DEVICE,
<> 139:856d2700e60b 158 NON_SHARED_DEVICE,
<> 139:856d2700e60b 159 STRONGLY_ORDERED
<> 139:856d2700e60b 160 } mmu_memory_Type;
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 /* Region cacheability attributes */
<> 139:856d2700e60b 163 typedef enum
<> 139:856d2700e60b 164 {
<> 139:856d2700e60b 165 NON_CACHEABLE,
<> 139:856d2700e60b 166 WB_WA,
<> 139:856d2700e60b 167 WT,
<> 139:856d2700e60b 168 WB_NO_WA,
<> 139:856d2700e60b 169 } mmu_cacheability_Type;
<> 139:856d2700e60b 170
<> 139:856d2700e60b 171 /* Region parity check attributes */
<> 139:856d2700e60b 172 typedef enum
<> 139:856d2700e60b 173 {
<> 139:856d2700e60b 174 ECC_DISABLED,
<> 139:856d2700e60b 175 ECC_ENABLED,
<> 139:856d2700e60b 176 } mmu_ecc_check_Type;
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 /* Region execution attributes */
<> 139:856d2700e60b 179 typedef enum
<> 139:856d2700e60b 180 {
<> 139:856d2700e60b 181 EXECUTE,
<> 139:856d2700e60b 182 NON_EXECUTE,
<> 139:856d2700e60b 183 } mmu_execute_Type;
<> 139:856d2700e60b 184
<> 139:856d2700e60b 185 /* Region global attributes */
<> 139:856d2700e60b 186 typedef enum
<> 139:856d2700e60b 187 {
<> 139:856d2700e60b 188 GLOBAL,
<> 139:856d2700e60b 189 NON_GLOBAL,
<> 139:856d2700e60b 190 } mmu_global_Type;
<> 139:856d2700e60b 191
<> 139:856d2700e60b 192 /* Region shareability attributes */
<> 139:856d2700e60b 193 typedef enum
<> 139:856d2700e60b 194 {
<> 139:856d2700e60b 195 NON_SHARED,
<> 139:856d2700e60b 196 SHARED,
<> 139:856d2700e60b 197 } mmu_shared_Type;
<> 139:856d2700e60b 198
<> 139:856d2700e60b 199 /* Region security attributes */
<> 139:856d2700e60b 200 typedef enum
<> 139:856d2700e60b 201 {
<> 139:856d2700e60b 202 SECURE,
<> 139:856d2700e60b 203 NON_SECURE,
<> 139:856d2700e60b 204 } mmu_secure_Type;
<> 139:856d2700e60b 205
<> 139:856d2700e60b 206 /* Region access attributes */
<> 139:856d2700e60b 207 typedef enum
<> 139:856d2700e60b 208 {
<> 139:856d2700e60b 209 NO_ACCESS,
<> 139:856d2700e60b 210 RW,
<> 139:856d2700e60b 211 READ,
<> 139:856d2700e60b 212 } mmu_access_Type;
<> 139:856d2700e60b 213
<> 139:856d2700e60b 214 /* Memory Region definition */
<> 139:856d2700e60b 215 typedef struct RegionStruct {
<> 139:856d2700e60b 216 mmu_region_size_Type rg_t;
<> 139:856d2700e60b 217 mmu_memory_Type mem_t;
<> 139:856d2700e60b 218 uint8_t domain;
<> 139:856d2700e60b 219 mmu_cacheability_Type inner_norm_t;
<> 139:856d2700e60b 220 mmu_cacheability_Type outer_norm_t;
<> 139:856d2700e60b 221 mmu_ecc_check_Type e_t;
<> 139:856d2700e60b 222 mmu_execute_Type xn_t;
<> 139:856d2700e60b 223 mmu_global_Type g_t;
<> 139:856d2700e60b 224 mmu_secure_Type sec_t;
<> 139:856d2700e60b 225 mmu_access_Type priv_t;
<> 139:856d2700e60b 226 mmu_access_Type user_t;
<> 139:856d2700e60b 227 mmu_shared_Type sh_t;
<> 139:856d2700e60b 228
<> 139:856d2700e60b 229 } mmu_region_attributes_Type;
<> 139:856d2700e60b 230
<> 139:856d2700e60b 231 /** \brief Set section execution-never attribute
<> 139:856d2700e60b 232
<> 139:856d2700e60b 233 The function sets section execution-never attribute
<> 139:856d2700e60b 234
<> 139:856d2700e60b 235 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
<> 139:856d2700e60b 237
<> 139:856d2700e60b 238 \return 0
<> 139:856d2700e60b 239 */
<> 139:856d2700e60b 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
<> 139:856d2700e60b 241 {
<> 139:856d2700e60b 242 *descriptor_l1 &= SECTION_XN_MASK;
<> 139:856d2700e60b 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
<> 139:856d2700e60b 244 return 0;
<> 139:856d2700e60b 245 }
<> 139:856d2700e60b 246
<> 139:856d2700e60b 247 /** \brief Set section domain
<> 139:856d2700e60b 248
<> 139:856d2700e60b 249 The function sets section domain
<> 139:856d2700e60b 250
<> 139:856d2700e60b 251 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 252 \param [in] domain Section domain
<> 139:856d2700e60b 253
<> 139:856d2700e60b 254 \return 0
<> 139:856d2700e60b 255 */
<> 139:856d2700e60b 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
<> 139:856d2700e60b 257 {
<> 139:856d2700e60b 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
<> 139:856d2700e60b 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
<> 139:856d2700e60b 260 return 0;
<> 139:856d2700e60b 261 }
<> 139:856d2700e60b 262
<> 139:856d2700e60b 263 /** \brief Set section parity check
<> 139:856d2700e60b 264
<> 139:856d2700e60b 265 The function sets section parity check
<> 139:856d2700e60b 266
<> 139:856d2700e60b 267 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 139:856d2700e60b 269
<> 139:856d2700e60b 270 \return 0
<> 139:856d2700e60b 271 */
<> 139:856d2700e60b 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 139:856d2700e60b 273 {
<> 139:856d2700e60b 274 *descriptor_l1 &= SECTION_P_MASK;
<> 139:856d2700e60b 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 139:856d2700e60b 276 return 0;
<> 139:856d2700e60b 277 }
<> 139:856d2700e60b 278
<> 139:856d2700e60b 279 /** \brief Set section access privileges
<> 139:856d2700e60b 280
<> 139:856d2700e60b 281 The function sets section access privileges
<> 139:856d2700e60b 282
<> 139:856d2700e60b 283 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 139:856d2700e60b 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 139:856d2700e60b 286 \param [in] afe Access flag enable
<> 139:856d2700e60b 287
<> 139:856d2700e60b 288 \return 0
<> 139:856d2700e60b 289 */
<> 139:856d2700e60b 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 139:856d2700e60b 291 {
<> 139:856d2700e60b 292 uint32_t ap = 0;
<> 139:856d2700e60b 293
<> 139:856d2700e60b 294 if (afe == 0) { //full access
<> 139:856d2700e60b 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 139:856d2700e60b 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 139:856d2700e60b 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 139:856d2700e60b 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 139:856d2700e60b 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 139:856d2700e60b 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 139:856d2700e60b 301 }
<> 139:856d2700e60b 302
<> 139:856d2700e60b 303 else { //Simplified access
<> 139:856d2700e60b 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 139:856d2700e60b 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 139:856d2700e60b 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 139:856d2700e60b 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 139:856d2700e60b 308 }
<> 139:856d2700e60b 309
<> 139:856d2700e60b 310 *descriptor_l1 &= SECTION_AP_MASK;
<> 139:856d2700e60b 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
<> 139:856d2700e60b 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
<> 139:856d2700e60b 313
<> 139:856d2700e60b 314 return 0;
<> 139:856d2700e60b 315 }
<> 139:856d2700e60b 316
<> 139:856d2700e60b 317 /** \brief Set section shareability
<> 139:856d2700e60b 318
<> 139:856d2700e60b 319 The function sets section shareability
<> 139:856d2700e60b 320
<> 139:856d2700e60b 321 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
<> 139:856d2700e60b 323
<> 139:856d2700e60b 324 \return 0
<> 139:856d2700e60b 325 */
<> 139:856d2700e60b 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
<> 139:856d2700e60b 327 {
<> 139:856d2700e60b 328 *descriptor_l1 &= SECTION_S_MASK;
<> 139:856d2700e60b 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
<> 139:856d2700e60b 330 return 0;
<> 139:856d2700e60b 331 }
<> 139:856d2700e60b 332
<> 139:856d2700e60b 333 /** \brief Set section Global attribute
<> 139:856d2700e60b 334
<> 139:856d2700e60b 335 The function sets section Global attribute
<> 139:856d2700e60b 336
<> 139:856d2700e60b 337 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
<> 139:856d2700e60b 339
<> 139:856d2700e60b 340 \return 0
<> 139:856d2700e60b 341 */
<> 139:856d2700e60b 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
<> 139:856d2700e60b 343 {
<> 139:856d2700e60b 344 *descriptor_l1 &= SECTION_NG_MASK;
<> 139:856d2700e60b 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
<> 139:856d2700e60b 346 return 0;
<> 139:856d2700e60b 347 }
<> 139:856d2700e60b 348
<> 139:856d2700e60b 349 /** \brief Set section Security attribute
<> 139:856d2700e60b 350
<> 139:856d2700e60b 351 The function sets section Global attribute
<> 139:856d2700e60b 352
<> 139:856d2700e60b 353 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
<> 139:856d2700e60b 355
<> 139:856d2700e60b 356 \return 0
<> 139:856d2700e60b 357 */
<> 139:856d2700e60b 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 139:856d2700e60b 359 {
<> 139:856d2700e60b 360 *descriptor_l1 &= SECTION_NS_MASK;
<> 139:856d2700e60b 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
<> 139:856d2700e60b 362 return 0;
<> 139:856d2700e60b 363 }
<> 139:856d2700e60b 364
<> 139:856d2700e60b 365 /* Page 4k or 64k */
<> 139:856d2700e60b 366 /** \brief Set 4k/64k page execution-never attribute
<> 139:856d2700e60b 367
<> 139:856d2700e60b 368 The function sets 4k/64k page execution-never attribute
<> 139:856d2700e60b 369
<> 139:856d2700e60b 370 \param [out] descriptor_l2 L2 descriptor.
<> 139:856d2700e60b 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
<> 139:856d2700e60b 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
<> 139:856d2700e60b 373
<> 139:856d2700e60b 374 \return 0
<> 139:856d2700e60b 375 */
<> 139:856d2700e60b 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
<> 139:856d2700e60b 377 {
<> 139:856d2700e60b 378 if (page == PAGE_4k)
<> 139:856d2700e60b 379 {
<> 139:856d2700e60b 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
<> 139:856d2700e60b 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
<> 139:856d2700e60b 382 }
<> 139:856d2700e60b 383 else
<> 139:856d2700e60b 384 {
<> 139:856d2700e60b 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
<> 139:856d2700e60b 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
<> 139:856d2700e60b 387 }
<> 139:856d2700e60b 388 return 0;
<> 139:856d2700e60b 389 }
<> 139:856d2700e60b 390
<> 139:856d2700e60b 391 /** \brief Set 4k/64k page domain
<> 139:856d2700e60b 392
<> 139:856d2700e60b 393 The function sets 4k/64k page domain
<> 139:856d2700e60b 394
<> 139:856d2700e60b 395 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 396 \param [in] domain Page domain
<> 139:856d2700e60b 397
<> 139:856d2700e60b 398 \return 0
<> 139:856d2700e60b 399 */
<> 139:856d2700e60b 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
<> 139:856d2700e60b 401 {
<> 139:856d2700e60b 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
<> 139:856d2700e60b 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
<> 139:856d2700e60b 404 return 0;
<> 139:856d2700e60b 405 }
<> 139:856d2700e60b 406
<> 139:856d2700e60b 407 /** \brief Set 4k/64k page parity check
<> 139:856d2700e60b 408
<> 139:856d2700e60b 409 The function sets 4k/64k page parity check
<> 139:856d2700e60b 410
<> 139:856d2700e60b 411 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 139:856d2700e60b 413
<> 139:856d2700e60b 414 \return 0
<> 139:856d2700e60b 415 */
<> 139:856d2700e60b 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 139:856d2700e60b 417 {
<> 139:856d2700e60b 418 *descriptor_l1 &= SECTION_P_MASK;
<> 139:856d2700e60b 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 139:856d2700e60b 420 return 0;
<> 139:856d2700e60b 421 }
<> 139:856d2700e60b 422
<> 139:856d2700e60b 423 /** \brief Set 4k/64k page access privileges
<> 139:856d2700e60b 424
<> 139:856d2700e60b 425 The function sets 4k/64k page access privileges
<> 139:856d2700e60b 426
<> 139:856d2700e60b 427 \param [out] descriptor_l2 L2 descriptor.
<> 139:856d2700e60b 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 139:856d2700e60b 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 139:856d2700e60b 430 \param [in] afe Access flag enable
<> 139:856d2700e60b 431
<> 139:856d2700e60b 432 \return 0
<> 139:856d2700e60b 433 */
<> 139:856d2700e60b 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 139:856d2700e60b 435 {
<> 139:856d2700e60b 436 uint32_t ap = 0;
<> 139:856d2700e60b 437
<> 139:856d2700e60b 438 if (afe == 0) { //full access
<> 139:856d2700e60b 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 139:856d2700e60b 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 139:856d2700e60b 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 139:856d2700e60b 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 139:856d2700e60b 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 139:856d2700e60b 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
<> 139:856d2700e60b 445 }
<> 139:856d2700e60b 446
<> 139:856d2700e60b 447 else { //Simplified access
<> 139:856d2700e60b 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 139:856d2700e60b 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 139:856d2700e60b 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 139:856d2700e60b 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 139:856d2700e60b 452 }
<> 139:856d2700e60b 453
<> 139:856d2700e60b 454 *descriptor_l2 &= PAGE_AP_MASK;
<> 139:856d2700e60b 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
<> 139:856d2700e60b 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
<> 139:856d2700e60b 457
<> 139:856d2700e60b 458 return 0;
<> 139:856d2700e60b 459 }
<> 139:856d2700e60b 460
<> 139:856d2700e60b 461 /** \brief Set 4k/64k page shareability
<> 139:856d2700e60b 462
<> 139:856d2700e60b 463 The function sets 4k/64k page shareability
<> 139:856d2700e60b 464
<> 139:856d2700e60b 465 \param [out] descriptor_l2 L2 descriptor.
<> 139:856d2700e60b 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
<> 139:856d2700e60b 467
<> 139:856d2700e60b 468 \return 0
<> 139:856d2700e60b 469 */
<> 139:856d2700e60b 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
<> 139:856d2700e60b 471 {
<> 139:856d2700e60b 472 *descriptor_l2 &= PAGE_S_MASK;
<> 139:856d2700e60b 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
<> 139:856d2700e60b 474 return 0;
<> 139:856d2700e60b 475 }
<> 139:856d2700e60b 476
<> 139:856d2700e60b 477 /** \brief Set 4k/64k page Global attribute
<> 139:856d2700e60b 478
<> 139:856d2700e60b 479 The function sets 4k/64k page Global attribute
<> 139:856d2700e60b 480
<> 139:856d2700e60b 481 \param [out] descriptor_l2 L2 descriptor.
<> 139:856d2700e60b 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
<> 139:856d2700e60b 483
<> 139:856d2700e60b 484 \return 0
<> 139:856d2700e60b 485 */
<> 139:856d2700e60b 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
<> 139:856d2700e60b 487 {
<> 139:856d2700e60b 488 *descriptor_l2 &= PAGE_NG_MASK;
<> 139:856d2700e60b 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
<> 139:856d2700e60b 490 return 0;
<> 139:856d2700e60b 491 }
<> 139:856d2700e60b 492
<> 139:856d2700e60b 493 /** \brief Set 4k/64k page Security attribute
<> 139:856d2700e60b 494
<> 139:856d2700e60b 495 The function sets 4k/64k page Global attribute
<> 139:856d2700e60b 496
<> 139:856d2700e60b 497 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
<> 139:856d2700e60b 499
<> 139:856d2700e60b 500 \return 0
<> 139:856d2700e60b 501 */
<> 139:856d2700e60b 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 139:856d2700e60b 503 {
<> 139:856d2700e60b 504 *descriptor_l1 &= PAGE_NS_MASK;
<> 139:856d2700e60b 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
<> 139:856d2700e60b 506 return 0;
<> 139:856d2700e60b 507 }
<> 139:856d2700e60b 508
<> 139:856d2700e60b 509
<> 139:856d2700e60b 510 /** \brief Set Section memory attributes
<> 139:856d2700e60b 511
<> 139:856d2700e60b 512 The function sets section memory attributes
<> 139:856d2700e60b 513
<> 139:856d2700e60b 514 \param [out] descriptor_l1 L1 descriptor.
<> 139:856d2700e60b 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 139:856d2700e60b 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 139:856d2700e60b 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 139:856d2700e60b 518
<> 139:856d2700e60b 519 \return 0
<> 139:856d2700e60b 520 */
<> 139:856d2700e60b 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
<> 139:856d2700e60b 522 {
<> 139:856d2700e60b 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
<> 139:856d2700e60b 524
<> 139:856d2700e60b 525 if (STRONGLY_ORDERED == mem)
<> 139:856d2700e60b 526 {
<> 139:856d2700e60b 527 return 0;
<> 139:856d2700e60b 528 }
<> 139:856d2700e60b 529 else if (SHARED_DEVICE == mem)
<> 139:856d2700e60b 530 {
<> 139:856d2700e60b 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 139:856d2700e60b 532 }
<> 139:856d2700e60b 533 else if (NON_SHARED_DEVICE == mem)
<> 139:856d2700e60b 534 {
<> 139:856d2700e60b 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
<> 139:856d2700e60b 536 }
<> 139:856d2700e60b 537 else if (NORMAL == mem)
<> 139:856d2700e60b 538 {
<> 139:856d2700e60b 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
<> 139:856d2700e60b 540 switch(inner)
<> 139:856d2700e60b 541 {
<> 139:856d2700e60b 542 case NON_CACHEABLE:
<> 139:856d2700e60b 543 break;
<> 139:856d2700e60b 544 case WB_WA:
<> 139:856d2700e60b 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 139:856d2700e60b 546 break;
<> 139:856d2700e60b 547 case WT:
<> 139:856d2700e60b 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
<> 139:856d2700e60b 549 break;
<> 139:856d2700e60b 550 case WB_NO_WA:
<> 139:856d2700e60b 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
<> 139:856d2700e60b 552 break;
<> 139:856d2700e60b 553 }
<> 139:856d2700e60b 554 switch(outer)
<> 139:856d2700e60b 555 {
<> 139:856d2700e60b 556 case NON_CACHEABLE:
<> 139:856d2700e60b 557 break;
<> 139:856d2700e60b 558 case WB_WA:
<> 139:856d2700e60b 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
<> 139:856d2700e60b 560 break;
<> 139:856d2700e60b 561 case WT:
<> 139:856d2700e60b 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
<> 139:856d2700e60b 563 break;
<> 139:856d2700e60b 564 case WB_NO_WA:
<> 139:856d2700e60b 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
<> 139:856d2700e60b 566 break;
<> 139:856d2700e60b 567 }
<> 139:856d2700e60b 568 }
<> 139:856d2700e60b 569
<> 139:856d2700e60b 570 return 0;
<> 139:856d2700e60b 571 }
<> 139:856d2700e60b 572
<> 139:856d2700e60b 573 /** \brief Set 4k/64k page memory attributes
<> 139:856d2700e60b 574
<> 139:856d2700e60b 575 The function sets 4k/64k page memory attributes
<> 139:856d2700e60b 576
<> 139:856d2700e60b 577 \param [out] descriptor_l2 L2 descriptor.
<> 139:856d2700e60b 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 139:856d2700e60b 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 139:856d2700e60b 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 139:856d2700e60b 581
<> 139:856d2700e60b 582 \return 0
<> 139:856d2700e60b 583 */
<> 139:856d2700e60b 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
<> 139:856d2700e60b 585 {
<> 139:856d2700e60b 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
<> 139:856d2700e60b 587
<> 139:856d2700e60b 588 if (page == PAGE_64k)
<> 139:856d2700e60b 589 {
<> 139:856d2700e60b 590 //same as section
<> 139:856d2700e60b 591 __memory_section(descriptor_l2, mem, outer, inner);
<> 139:856d2700e60b 592 }
<> 139:856d2700e60b 593 else
<> 139:856d2700e60b 594 {
<> 139:856d2700e60b 595 if (STRONGLY_ORDERED == mem)
<> 139:856d2700e60b 596 {
<> 139:856d2700e60b 597 return 0;
<> 139:856d2700e60b 598 }
<> 139:856d2700e60b 599 else if (SHARED_DEVICE == mem)
<> 139:856d2700e60b 600 {
<> 139:856d2700e60b 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 139:856d2700e60b 602 }
<> 139:856d2700e60b 603 else if (NON_SHARED_DEVICE == mem)
<> 139:856d2700e60b 604 {
<> 139:856d2700e60b 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
<> 139:856d2700e60b 606 }
<> 139:856d2700e60b 607 else if (NORMAL == mem)
<> 139:856d2700e60b 608 {
<> 139:856d2700e60b 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
<> 139:856d2700e60b 610 switch(inner)
<> 139:856d2700e60b 611 {
<> 139:856d2700e60b 612 case NON_CACHEABLE:
<> 139:856d2700e60b 613 break;
<> 139:856d2700e60b 614 case WB_WA:
<> 139:856d2700e60b 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 139:856d2700e60b 616 break;
<> 139:856d2700e60b 617 case WT:
<> 139:856d2700e60b 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
<> 139:856d2700e60b 619 break;
<> 139:856d2700e60b 620 case WB_NO_WA:
<> 139:856d2700e60b 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
<> 139:856d2700e60b 622 break;
<> 139:856d2700e60b 623 }
<> 139:856d2700e60b 624 switch(outer)
<> 139:856d2700e60b 625 {
<> 139:856d2700e60b 626 case NON_CACHEABLE:
<> 139:856d2700e60b 627 break;
<> 139:856d2700e60b 628 case WB_WA:
<> 139:856d2700e60b 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
<> 139:856d2700e60b 630 break;
<> 139:856d2700e60b 631 case WT:
<> 139:856d2700e60b 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
<> 139:856d2700e60b 633 break;
<> 139:856d2700e60b 634 case WB_NO_WA:
<> 139:856d2700e60b 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
<> 139:856d2700e60b 636 break;
<> 139:856d2700e60b 637 }
<> 139:856d2700e60b 638 }
<> 139:856d2700e60b 639 }
<> 139:856d2700e60b 640
<> 139:856d2700e60b 641 return 0;
<> 139:856d2700e60b 642 }
<> 139:856d2700e60b 643
<> 139:856d2700e60b 644 /** \brief Create a L1 section descriptor
<> 139:856d2700e60b 645
<> 139:856d2700e60b 646 The function creates a section descriptor.
<> 139:856d2700e60b 647
<> 139:856d2700e60b 648 Assumptions:
<> 139:856d2700e60b 649 - 16MB super sections not supported
<> 139:856d2700e60b 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 139:856d2700e60b 651 - Functions always return 0
<> 139:856d2700e60b 652
<> 139:856d2700e60b 653 \param [out] descriptor L1 descriptor
<> 139:856d2700e60b 654 \param [out] descriptor2 L2 descriptor
<> 139:856d2700e60b 655 \param [in] reg Section attributes
<> 139:856d2700e60b 656
<> 139:856d2700e60b 657 \return 0
<> 139:856d2700e60b 658 */
<> 139:856d2700e60b 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
<> 139:856d2700e60b 660 {
<> 139:856d2700e60b 661 *descriptor = 0;
<> 139:856d2700e60b 662
<> 139:856d2700e60b 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
<> 139:856d2700e60b 664 __xn_section(descriptor,reg.xn_t);
<> 139:856d2700e60b 665 __domain_section(descriptor, reg.domain);
<> 139:856d2700e60b 666 __p_section(descriptor, reg.e_t);
<> 139:856d2700e60b 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
<> 139:856d2700e60b 668 __shared_section(descriptor,reg.sh_t);
<> 139:856d2700e60b 669 __global_section(descriptor,reg.g_t);
<> 139:856d2700e60b 670 __secure_section(descriptor,reg.sec_t);
<> 139:856d2700e60b 671 *descriptor &= SECTION_MASK;
<> 139:856d2700e60b 672 *descriptor |= SECTION_DESCRIPTOR;
<> 139:856d2700e60b 673
<> 139:856d2700e60b 674 return 0;
<> 139:856d2700e60b 675
<> 139:856d2700e60b 676 }
<> 139:856d2700e60b 677
<> 139:856d2700e60b 678
<> 139:856d2700e60b 679 /** \brief Create a L1 and L2 4k/64k page descriptor
<> 139:856d2700e60b 680
<> 139:856d2700e60b 681 The function creates a 4k/64k page descriptor.
<> 139:856d2700e60b 682 Assumptions:
<> 139:856d2700e60b 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 139:856d2700e60b 684 - Functions always return 0
<> 139:856d2700e60b 685
<> 139:856d2700e60b 686 \param [out] descriptor L1 descriptor
<> 139:856d2700e60b 687 \param [out] descriptor2 L2 descriptor
<> 139:856d2700e60b 688 \param [in] reg 4k/64k page attributes
<> 139:856d2700e60b 689
<> 139:856d2700e60b 690 \return 0
<> 139:856d2700e60b 691 */
<> 139:856d2700e60b 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
<> 139:856d2700e60b 693 {
<> 139:856d2700e60b 694 *descriptor = 0;
<> 139:856d2700e60b 695 *descriptor2 = 0;
<> 139:856d2700e60b 696
<> 139:856d2700e60b 697 switch (reg.rg_t)
<> 139:856d2700e60b 698 {
<> 139:856d2700e60b 699 case PAGE_4k:
<> 139:856d2700e60b 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
<> 139:856d2700e60b 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
<> 139:856d2700e60b 702 __domain_page(descriptor, reg.domain);
<> 139:856d2700e60b 703 __p_page(descriptor, reg.e_t);
<> 139:856d2700e60b 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 139:856d2700e60b 705 __shared_page(descriptor2,reg.sh_t);
<> 139:856d2700e60b 706 __global_page(descriptor2,reg.g_t);
<> 139:856d2700e60b 707 __secure_page(descriptor,reg.sec_t);
<> 139:856d2700e60b 708 *descriptor &= PAGE_L1_MASK;
<> 139:856d2700e60b 709 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 139:856d2700e60b 710 *descriptor2 &= PAGE_L2_4K_MASK;
<> 139:856d2700e60b 711 *descriptor2 |= PAGE_L2_4K_DESC;
<> 139:856d2700e60b 712 break;
<> 139:856d2700e60b 713
<> 139:856d2700e60b 714 case PAGE_64k:
<> 139:856d2700e60b 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
<> 139:856d2700e60b 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
<> 139:856d2700e60b 717 __domain_page(descriptor, reg.domain);
<> 139:856d2700e60b 718 __p_page(descriptor, reg.e_t);
<> 139:856d2700e60b 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 139:856d2700e60b 720 __shared_page(descriptor2,reg.sh_t);
<> 139:856d2700e60b 721 __global_page(descriptor2,reg.g_t);
<> 139:856d2700e60b 722 __secure_page(descriptor,reg.sec_t);
<> 139:856d2700e60b 723 *descriptor &= PAGE_L1_MASK;
<> 139:856d2700e60b 724 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 139:856d2700e60b 725 *descriptor2 &= PAGE_L2_64K_MASK;
<> 139:856d2700e60b 726 *descriptor2 |= PAGE_L2_64K_DESC;
<> 139:856d2700e60b 727 break;
<> 139:856d2700e60b 728
<> 139:856d2700e60b 729 case SECTION:
<> 139:856d2700e60b 730 //error
<> 139:856d2700e60b 731 break;
<> 139:856d2700e60b 732
<> 139:856d2700e60b 733 }
<> 139:856d2700e60b 734
<> 139:856d2700e60b 735 return 0;
<> 139:856d2700e60b 736
<> 139:856d2700e60b 737 }
<> 139:856d2700e60b 738
<> 139:856d2700e60b 739 /** \brief Create a 1MB Section
<> 139:856d2700e60b 740
<> 139:856d2700e60b 741 \param [in] ttb Translation table base address
<> 139:856d2700e60b 742 \param [in] base_address Section base address
<> 139:856d2700e60b 743 \param [in] count Number of sections to create
<> 139:856d2700e60b 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 139:856d2700e60b 745
<> 139:856d2700e60b 746 */
<> 139:856d2700e60b 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
<> 139:856d2700e60b 748 {
<> 139:856d2700e60b 749 uint32_t offset;
<> 139:856d2700e60b 750 uint32_t entry;
<> 139:856d2700e60b 751 uint32_t i;
<> 139:856d2700e60b 752
<> 139:856d2700e60b 753 offset = base_address >> 20;
<> 139:856d2700e60b 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
<> 139:856d2700e60b 755
<> 139:856d2700e60b 756 //4 bytes aligned
<> 139:856d2700e60b 757 ttb = ttb + offset;
<> 139:856d2700e60b 758
<> 139:856d2700e60b 759 for (i = 0; i < count; i++ )
<> 139:856d2700e60b 760 {
<> 139:856d2700e60b 761 //4 bytes aligned
<> 139:856d2700e60b 762 *ttb++ = entry;
<> 139:856d2700e60b 763 entry += OFFSET_1M;
<> 139:856d2700e60b 764 }
<> 139:856d2700e60b 765 }
<> 139:856d2700e60b 766
<> 139:856d2700e60b 767 /** \brief Create a 4k page entry
<> 139:856d2700e60b 768
<> 139:856d2700e60b 769 \param [in] ttb L1 table base address
<> 139:856d2700e60b 770 \param [in] base_address 4k base address
<> 139:856d2700e60b 771 \param [in] count Number of 4k pages to create
<> 139:856d2700e60b 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 139:856d2700e60b 773 \param [in] ttb_l2 L2 table base address
<> 139:856d2700e60b 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 139:856d2700e60b 775
<> 139:856d2700e60b 776 */
<> 139:856d2700e60b 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 139:856d2700e60b 778 {
<> 139:856d2700e60b 779
<> 139:856d2700e60b 780 uint32_t offset, offset2;
<> 139:856d2700e60b 781 uint32_t entry, entry2;
<> 139:856d2700e60b 782 uint32_t i;
<> 139:856d2700e60b 783
<> 139:856d2700e60b 784
<> 139:856d2700e60b 785 offset = base_address >> 20;
<> 139:856d2700e60b 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 139:856d2700e60b 787
<> 139:856d2700e60b 788 //4 bytes aligned
<> 139:856d2700e60b 789 ttb += offset;
<> 139:856d2700e60b 790 //create l1_entry
<> 139:856d2700e60b 791 *ttb = entry;
<> 139:856d2700e60b 792
<> 139:856d2700e60b 793 offset2 = (base_address & 0xff000) >> 12;
<> 139:856d2700e60b 794 ttb_l2 += offset2;
<> 139:856d2700e60b 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
<> 139:856d2700e60b 796 for (i = 0; i < count; i++ )
<> 139:856d2700e60b 797 {
<> 139:856d2700e60b 798 //4 bytes aligned
<> 139:856d2700e60b 799 *ttb_l2++ = entry2;
<> 139:856d2700e60b 800 entry2 += OFFSET_4K;
<> 139:856d2700e60b 801 }
<> 139:856d2700e60b 802 }
<> 139:856d2700e60b 803
<> 139:856d2700e60b 804 /** \brief Create a 64k page entry
<> 139:856d2700e60b 805
<> 139:856d2700e60b 806 \param [in] ttb L1 table base address
<> 139:856d2700e60b 807 \param [in] base_address 64k base address
<> 139:856d2700e60b 808 \param [in] count Number of 64k pages to create
<> 139:856d2700e60b 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 139:856d2700e60b 810 \param [in] ttb_l2 L2 table base address
<> 139:856d2700e60b 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 139:856d2700e60b 812
<> 139:856d2700e60b 813 */
<> 139:856d2700e60b 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 139:856d2700e60b 815 {
<> 139:856d2700e60b 816 uint32_t offset, offset2;
<> 139:856d2700e60b 817 uint32_t entry, entry2;
<> 139:856d2700e60b 818 uint32_t i,j;
<> 139:856d2700e60b 819
<> 139:856d2700e60b 820
<> 139:856d2700e60b 821 offset = base_address >> 20;
<> 139:856d2700e60b 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 139:856d2700e60b 823
<> 139:856d2700e60b 824 //4 bytes aligned
<> 139:856d2700e60b 825 ttb += offset;
<> 139:856d2700e60b 826 //create l1_entry
<> 139:856d2700e60b 827 *ttb = entry;
<> 139:856d2700e60b 828
<> 139:856d2700e60b 829 offset2 = (base_address & 0xff000) >> 12;
<> 139:856d2700e60b 830 ttb_l2 += offset2;
<> 139:856d2700e60b 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
<> 139:856d2700e60b 832 for (i = 0; i < count; i++ )
<> 139:856d2700e60b 833 {
<> 139:856d2700e60b 834 //create 16 entries
<> 139:856d2700e60b 835 for (j = 0; j < 16; j++)
<> 139:856d2700e60b 836 //4 bytes aligned
<> 139:856d2700e60b 837 *ttb_l2++ = entry2;
<> 139:856d2700e60b 838 entry2 += OFFSET_64K;
<> 139:856d2700e60b 839 }
<> 139:856d2700e60b 840 }
<> 139:856d2700e60b 841
<> 139:856d2700e60b 842 /*@} end of MMU_Functions */
<> 139:856d2700e60b 843 #endif
<> 139:856d2700e60b 844
<> 139:856d2700e60b 845 #ifdef __cplusplus
<> 139:856d2700e60b 846 }
<> 139:856d2700e60b 847 #endif