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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/core_ca9.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
139:856d2700e60b 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file core_ca9.h
<> 139:856d2700e60b 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 139:856d2700e60b 4 * @version
<> 139:856d2700e60b 5 * @date 25 March 2013
<> 139:856d2700e60b 6 *
<> 139:856d2700e60b 7 * @note
<> 139:856d2700e60b 8 *
<> 139:856d2700e60b 9 ******************************************************************************/
<> 139:856d2700e60b 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 139:856d2700e60b 11
<> 139:856d2700e60b 12 All rights reserved.
<> 139:856d2700e60b 13 Redistribution and use in source and binary forms, with or without
<> 139:856d2700e60b 14 modification, are permitted provided that the following conditions are met:
<> 139:856d2700e60b 15 - Redistributions of source code must retain the above copyright
<> 139:856d2700e60b 16 notice, this list of conditions and the following disclaimer.
<> 139:856d2700e60b 17 - Redistributions in binary form must reproduce the above copyright
<> 139:856d2700e60b 18 notice, this list of conditions and the following disclaimer in the
<> 139:856d2700e60b 19 documentation and/or other materials provided with the distribution.
<> 139:856d2700e60b 20 - Neither the name of ARM nor the names of its contributors may be used
<> 139:856d2700e60b 21 to endorse or promote products derived from this software without
<> 139:856d2700e60b 22 specific prior written permission.
<> 139:856d2700e60b 23 *
<> 139:856d2700e60b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 139:856d2700e60b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 139:856d2700e60b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 139:856d2700e60b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 139:856d2700e60b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 139:856d2700e60b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 139:856d2700e60b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 139:856d2700e60b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 139:856d2700e60b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 139:856d2700e60b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 139:856d2700e60b 34 POSSIBILITY OF SUCH DAMAGE.
<> 139:856d2700e60b 35 ---------------------------------------------------------------------------*/
<> 139:856d2700e60b 36
<> 139:856d2700e60b 37
<> 139:856d2700e60b 38 #if defined ( __ICCARM__ )
<> 139:856d2700e60b 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 139:856d2700e60b 40 #endif
<> 139:856d2700e60b 41
<> 139:856d2700e60b 42 #ifdef __cplusplus
<> 139:856d2700e60b 43 extern "C" {
<> 139:856d2700e60b 44 #endif
<> 139:856d2700e60b 45
<> 139:856d2700e60b 46 #ifndef __CORE_CA9_H_GENERIC
<> 139:856d2700e60b 47 #define __CORE_CA9_H_GENERIC
<> 139:856d2700e60b 48
<> 139:856d2700e60b 49
<> 139:856d2700e60b 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 139:856d2700e60b 51 CMSIS violates the following MISRA-C:2004 rules:
<> 139:856d2700e60b 52
<> 139:856d2700e60b 53 \li Required Rule 8.5, object/function definition in header file.<br>
<> 139:856d2700e60b 54 Function definitions in header files are used to allow 'inlining'.
<> 139:856d2700e60b 55
<> 139:856d2700e60b 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 139:856d2700e60b 57 Unions are used for effective representation of core registers.
<> 139:856d2700e60b 58
<> 139:856d2700e60b 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 139:856d2700e60b 60 Function-like macros are used to allow more efficient code.
<> 139:856d2700e60b 61 */
<> 139:856d2700e60b 62
<> 139:856d2700e60b 63
<> 139:856d2700e60b 64 /*******************************************************************************
<> 139:856d2700e60b 65 * CMSIS definitions
<> 139:856d2700e60b 66 ******************************************************************************/
<> 139:856d2700e60b 67 /** \ingroup Cortex_A9
<> 139:856d2700e60b 68 @{
<> 139:856d2700e60b 69 */
<> 139:856d2700e60b 70
<> 139:856d2700e60b 71 /* CMSIS CA9 definitions */
<> 139:856d2700e60b 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
<> 139:856d2700e60b 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
<> 139:856d2700e60b 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
<> 139:856d2700e60b 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 139:856d2700e60b 76
<> 139:856d2700e60b 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
<> 139:856d2700e60b 78
<> 139:856d2700e60b 79
<> 139:856d2700e60b 80 #if defined ( __CC_ARM )
<> 139:856d2700e60b 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 139:856d2700e60b 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 139:856d2700e60b 83 #define __STATIC_INLINE static __inline
<> 139:856d2700e60b 84 #define __STATIC_ASM static __asm
<> 139:856d2700e60b 85
<> 139:856d2700e60b 86 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 139:856d2700e60b 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 139:856d2700e60b 89 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 90 #define __STATIC_ASM static __asm
<> 139:856d2700e60b 91
<> 139:856d2700e60b 92 #include <stdint.h>
<> 139:856d2700e60b 93 inline uint32_t __get_PSR(void) {
<> 139:856d2700e60b 94 __ASM("mrs r0, cpsr");
<> 139:856d2700e60b 95 }
<> 139:856d2700e60b 96
<> 139:856d2700e60b 97 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 139:856d2700e60b 99 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 100 #define __STATIC_ASM static __asm
<> 139:856d2700e60b 101
<> 139:856d2700e60b 102 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 139:856d2700e60b 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 139:856d2700e60b 105 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 106 #define __STATIC_ASM static __asm
<> 139:856d2700e60b 107
<> 139:856d2700e60b 108 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 139:856d2700e60b 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 139:856d2700e60b 111 #define __STATIC_INLINE static inline
<> 139:856d2700e60b 112 #define __STATIC_ASM static __asm
<> 139:856d2700e60b 113
<> 139:856d2700e60b 114 #endif
<> 139:856d2700e60b 115
<> 139:856d2700e60b 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 139:856d2700e60b 117 */
<> 139:856d2700e60b 118 #if defined ( __CC_ARM )
<> 139:856d2700e60b 119 #if defined __TARGET_FPU_VFP
<> 139:856d2700e60b 120 #if (__FPU_PRESENT == 1)
<> 139:856d2700e60b 121 #define __FPU_USED 1
<> 139:856d2700e60b 122 #else
<> 139:856d2700e60b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 124 #define __FPU_USED 0
<> 139:856d2700e60b 125 #endif
<> 139:856d2700e60b 126 #else
<> 139:856d2700e60b 127 #define __FPU_USED 0
<> 139:856d2700e60b 128 #endif
<> 139:856d2700e60b 129
<> 139:856d2700e60b 130 #elif defined ( __ICCARM__ )
<> 139:856d2700e60b 131 #if defined __ARMVFP__
<> 139:856d2700e60b 132 #if (__FPU_PRESENT == 1)
<> 139:856d2700e60b 133 #define __FPU_USED 1
<> 139:856d2700e60b 134 #else
<> 139:856d2700e60b 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 136 #define __FPU_USED 0
<> 139:856d2700e60b 137 #endif
<> 139:856d2700e60b 138 #else
<> 139:856d2700e60b 139 #define __FPU_USED 0
<> 139:856d2700e60b 140 #endif
<> 139:856d2700e60b 141
<> 139:856d2700e60b 142 #elif defined ( __TMS470__ )
<> 139:856d2700e60b 143 #if defined __TI_VFP_SUPPORT__
<> 139:856d2700e60b 144 #if (__FPU_PRESENT == 1)
<> 139:856d2700e60b 145 #define __FPU_USED 1
<> 139:856d2700e60b 146 #else
<> 139:856d2700e60b 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 148 #define __FPU_USED 0
<> 139:856d2700e60b 149 #endif
<> 139:856d2700e60b 150 #else
<> 139:856d2700e60b 151 #define __FPU_USED 0
<> 139:856d2700e60b 152 #endif
<> 139:856d2700e60b 153
<> 139:856d2700e60b 154 #elif defined ( __GNUC__ )
<> 139:856d2700e60b 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 139:856d2700e60b 156 #if (__FPU_PRESENT == 1)
<> 139:856d2700e60b 157 #define __FPU_USED 1
<> 139:856d2700e60b 158 #else
<> 139:856d2700e60b 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 160 #define __FPU_USED 0
<> 139:856d2700e60b 161 #endif
<> 139:856d2700e60b 162 #else
<> 139:856d2700e60b 163 #define __FPU_USED 0
<> 139:856d2700e60b 164 #endif
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 #elif defined ( __TASKING__ )
<> 139:856d2700e60b 167 #if defined __FPU_VFP__
<> 139:856d2700e60b 168 #if (__FPU_PRESENT == 1)
<> 139:856d2700e60b 169 #define __FPU_USED 1
<> 139:856d2700e60b 170 #else
<> 139:856d2700e60b 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 139:856d2700e60b 172 #define __FPU_USED 0
<> 139:856d2700e60b 173 #endif
<> 139:856d2700e60b 174 #else
<> 139:856d2700e60b 175 #define __FPU_USED 0
<> 139:856d2700e60b 176 #endif
<> 139:856d2700e60b 177 #endif
<> 139:856d2700e60b 178
<> 139:856d2700e60b 179 #include <stdint.h> /*!< standard types definitions */
<> 139:856d2700e60b 180 #include "core_caInstr.h" /*!< Core Instruction Access */
<> 139:856d2700e60b 181 #include "core_caFunc.h" /*!< Core Function Access */
<> 139:856d2700e60b 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
<> 139:856d2700e60b 183
<> 139:856d2700e60b 184 #endif /* __CORE_CA9_H_GENERIC */
<> 139:856d2700e60b 185
<> 139:856d2700e60b 186 #ifndef __CMSIS_GENERIC
<> 139:856d2700e60b 187
<> 139:856d2700e60b 188 #ifndef __CORE_CA9_H_DEPENDANT
<> 139:856d2700e60b 189 #define __CORE_CA9_H_DEPENDANT
<> 139:856d2700e60b 190
<> 139:856d2700e60b 191 /* check device defines and use defaults */
<> 139:856d2700e60b 192 #if defined __CHECK_DEVICE_DEFINES
<> 139:856d2700e60b 193 #ifndef __CA9_REV
<> 139:856d2700e60b 194 #define __CA9_REV 0x0000
<> 139:856d2700e60b 195 #warning "__CA9_REV not defined in device header file; using default!"
<> 139:856d2700e60b 196 #endif
<> 139:856d2700e60b 197
<> 139:856d2700e60b 198 #ifndef __FPU_PRESENT
<> 139:856d2700e60b 199 #define __FPU_PRESENT 1
<> 139:856d2700e60b 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 139:856d2700e60b 201 #endif
<> 139:856d2700e60b 202
<> 139:856d2700e60b 203 #ifndef __Vendor_SysTickConfig
<> 139:856d2700e60b 204 #define __Vendor_SysTickConfig 1
<> 139:856d2700e60b 205 #endif
<> 139:856d2700e60b 206
<> 139:856d2700e60b 207 #if __Vendor_SysTickConfig == 0
<> 139:856d2700e60b 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
<> 139:856d2700e60b 209 #endif
<> 139:856d2700e60b 210 #endif
<> 139:856d2700e60b 211
<> 139:856d2700e60b 212 /* IO definitions (access restrictions to peripheral registers) */
<> 139:856d2700e60b 213 /**
<> 139:856d2700e60b 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 139:856d2700e60b 215
<> 139:856d2700e60b 216 <strong>IO Type Qualifiers</strong> are used
<> 139:856d2700e60b 217 \li to specify the access to peripheral variables.
<> 139:856d2700e60b 218 \li for automatic generation of peripheral register debug information.
<> 139:856d2700e60b 219 */
<> 139:856d2700e60b 220 #ifdef __cplusplus
<> 139:856d2700e60b 221 #define __I volatile /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 222 #else
<> 139:856d2700e60b 223 #define __I volatile const /*!< Defines 'read only' permissions */
<> 139:856d2700e60b 224 #endif
<> 139:856d2700e60b 225 #define __O volatile /*!< Defines 'write only' permissions */
<> 139:856d2700e60b 226 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 139:856d2700e60b 227
<> 139:856d2700e60b 228 /*@} end of group Cortex_A9 */
<> 139:856d2700e60b 229
<> 139:856d2700e60b 230
<> 139:856d2700e60b 231 /*******************************************************************************
<> 139:856d2700e60b 232 * Register Abstraction
<> 139:856d2700e60b 233 ******************************************************************************/
<> 139:856d2700e60b 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 139:856d2700e60b 235 \brief Type definitions and defines for Cortex-A processor based devices.
<> 139:856d2700e60b 236 */
<> 139:856d2700e60b 237
<> 139:856d2700e60b 238 /** \ingroup CMSIS_core_register
<> 139:856d2700e60b 239 \defgroup CMSIS_CORE Status and Control Registers
<> 139:856d2700e60b 240 \brief Core Register type definitions.
<> 139:856d2700e60b 241 @{
<> 139:856d2700e60b 242 */
<> 139:856d2700e60b 243
<> 139:856d2700e60b 244 /** \brief Union type to access the Application Program Status Register (APSR).
<> 139:856d2700e60b 245 */
<> 139:856d2700e60b 246 typedef union
<> 139:856d2700e60b 247 {
<> 139:856d2700e60b 248 struct
<> 139:856d2700e60b 249 {
<> 139:856d2700e60b 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 139:856d2700e60b 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 139:856d2700e60b 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
<> 139:856d2700e60b 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 139:856d2700e60b 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 139:856d2700e60b 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 139:856d2700e60b 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 139:856d2700e60b 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 139:856d2700e60b 258 } b; /*!< Structure used for bit access */
<> 139:856d2700e60b 259 uint32_t w; /*!< Type used for word access */
<> 139:856d2700e60b 260 } APSR_Type;
<> 139:856d2700e60b 261
<> 139:856d2700e60b 262
<> 139:856d2700e60b 263 /*@} end of group CMSIS_CORE */
<> 139:856d2700e60b 264
<> 139:856d2700e60b 265 /*@} end of CMSIS_Core_FPUFunctions */
<> 139:856d2700e60b 266
<> 139:856d2700e60b 267
<> 139:856d2700e60b 268 #endif /* __CORE_CA9_H_GENERIC */
<> 139:856d2700e60b 269
<> 139:856d2700e60b 270 #endif /* __CMSIS_GENERIC */
<> 139:856d2700e60b 271
<> 139:856d2700e60b 272 #ifdef __cplusplus
<> 139:856d2700e60b 273 }
<> 139:856d2700e60b 274
<> 139:856d2700e60b 275
<> 139:856d2700e60b 276 #endif