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mbed 2

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TARGET_DISCO_L476VG/core_cm0.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 107:4f6c30876dfa 1 /**************************************************************************//**
Kojto 107:4f6c30876dfa 2 * @file core_cm0.h
Kojto 107:4f6c30876dfa 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 107:4f6c30876dfa 6 *
Kojto 107:4f6c30876dfa 7 * @note
Kojto 107:4f6c30876dfa 8 *
Kojto 107:4f6c30876dfa 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 107:4f6c30876dfa 11
Kojto 107:4f6c30876dfa 12 All rights reserved.
Kojto 107:4f6c30876dfa 13 Redistribution and use in source and binary forms, with or without
Kojto 107:4f6c30876dfa 14 modification, are permitted provided that the following conditions are met:
Kojto 107:4f6c30876dfa 15 - Redistributions of source code must retain the above copyright
Kojto 107:4f6c30876dfa 16 notice, this list of conditions and the following disclaimer.
Kojto 107:4f6c30876dfa 17 - Redistributions in binary form must reproduce the above copyright
Kojto 107:4f6c30876dfa 18 notice, this list of conditions and the following disclaimer in the
Kojto 107:4f6c30876dfa 19 documentation and/or other materials provided with the distribution.
Kojto 107:4f6c30876dfa 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 107:4f6c30876dfa 21 to endorse or promote products derived from this software without
Kojto 107:4f6c30876dfa 22 specific prior written permission.
Kojto 107:4f6c30876dfa 23 *
Kojto 107:4f6c30876dfa 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 107:4f6c30876dfa 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 107:4f6c30876dfa 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 107:4f6c30876dfa 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 107:4f6c30876dfa 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 107:4f6c30876dfa 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 107:4f6c30876dfa 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 107:4f6c30876dfa 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 107:4f6c30876dfa 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 107:4f6c30876dfa 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 107:4f6c30876dfa 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 107:4f6c30876dfa 35 ---------------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 36
Kojto 107:4f6c30876dfa 37
Kojto 107:4f6c30876dfa 38 #if defined ( __ICCARM__ )
Kojto 107:4f6c30876dfa 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 107:4f6c30876dfa 40 #endif
Kojto 107:4f6c30876dfa 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 107:4f6c30876dfa 45 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 46 extern "C" {
Kojto 107:4f6c30876dfa 47 #endif
Kojto 107:4f6c30876dfa 48
Kojto 107:4f6c30876dfa 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 107:4f6c30876dfa 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 107:4f6c30876dfa 51
Kojto 107:4f6c30876dfa 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 107:4f6c30876dfa 53 Function definitions in header files are used to allow 'inlining'.
Kojto 107:4f6c30876dfa 54
Kojto 107:4f6c30876dfa 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 107:4f6c30876dfa 56 Unions are used for effective representation of core registers.
Kojto 107:4f6c30876dfa 57
Kojto 107:4f6c30876dfa 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 107:4f6c30876dfa 59 Function-like macros are used to allow more efficient code.
Kojto 107:4f6c30876dfa 60 */
Kojto 107:4f6c30876dfa 61
Kojto 107:4f6c30876dfa 62
Kojto 107:4f6c30876dfa 63 /*******************************************************************************
Kojto 107:4f6c30876dfa 64 * CMSIS definitions
Kojto 107:4f6c30876dfa 65 ******************************************************************************/
Kojto 107:4f6c30876dfa 66 /** \ingroup Cortex_M0
Kojto 107:4f6c30876dfa 67 @{
Kojto 107:4f6c30876dfa 68 */
Kojto 107:4f6c30876dfa 69
Kojto 107:4f6c30876dfa 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 107:4f6c30876dfa 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 107:4f6c30876dfa 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 107:4f6c30876dfa 75
Kojto 107:4f6c30876dfa 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 107:4f6c30876dfa 77
Kojto 107:4f6c30876dfa 78
Kojto 107:4f6c30876dfa 79 #if defined ( __CC_ARM )
Kojto 107:4f6c30876dfa 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 107:4f6c30876dfa 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 107:4f6c30876dfa 82 #define __STATIC_INLINE static __inline
Kojto 107:4f6c30876dfa 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 107:4f6c30876dfa 89 #elif defined ( __ICCARM__ )
Kojto 107:4f6c30876dfa 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 107:4f6c30876dfa 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 107:4f6c30876dfa 92 #define __STATIC_INLINE static inline
Kojto 107:4f6c30876dfa 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 107:4f6c30876dfa 96 #define __STATIC_INLINE static inline
Kojto 107:4f6c30876dfa 97
Kojto 107:4f6c30876dfa 98 #elif defined ( __TASKING__ )
Kojto 107:4f6c30876dfa 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 107:4f6c30876dfa 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 107:4f6c30876dfa 101 #define __STATIC_INLINE static inline
Kojto 107:4f6c30876dfa 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 107:4f6c30876dfa 109 #endif
Kojto 107:4f6c30876dfa 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 107:4f6c30876dfa 113 */
Kojto 107:4f6c30876dfa 114 #define __FPU_USED 0
Kojto 107:4f6c30876dfa 115
Kojto 107:4f6c30876dfa 116 #if defined ( __CC_ARM )
Kojto 107:4f6c30876dfa 117 #if defined __TARGET_FPU_VFP
Kojto 107:4f6c30876dfa 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 119 #endif
Kojto 107:4f6c30876dfa 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 107:4f6c30876dfa 126 #elif defined ( __ICCARM__ )
Kojto 107:4f6c30876dfa 127 #if defined __ARMVFP__
Kojto 107:4f6c30876dfa 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 129 #endif
Kojto 107:4f6c30876dfa 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 107:4f6c30876dfa 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 134 #endif
Kojto 107:4f6c30876dfa 135
Kojto 107:4f6c30876dfa 136 #elif defined ( __TASKING__ )
Kojto 107:4f6c30876dfa 137 #if defined __FPU_VFP__
Kojto 107:4f6c30876dfa 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 107:4f6c30876dfa 145 #endif
Kojto 107:4f6c30876dfa 146
Kojto 107:4f6c30876dfa 147 #include <stdint.h> /* standard types definitions */
Kojto 107:4f6c30876dfa 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 107:4f6c30876dfa 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 107:4f6c30876dfa 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 107:4f6c30876dfa 155 #endif /* __CORE_CM0_H_GENERIC */
Kojto 107:4f6c30876dfa 156
Kojto 107:4f6c30876dfa 157 #ifndef __CMSIS_GENERIC
Kojto 107:4f6c30876dfa 158
Kojto 107:4f6c30876dfa 159 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 107:4f6c30876dfa 160 #define __CORE_CM0_H_DEPENDANT
Kojto 107:4f6c30876dfa 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 107:4f6c30876dfa 166 /* check device defines and use defaults */
Kojto 107:4f6c30876dfa 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 107:4f6c30876dfa 168 #ifndef __CM0_REV
Kojto 107:4f6c30876dfa 169 #define __CM0_REV 0x0000
Kojto 107:4f6c30876dfa 170 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 107:4f6c30876dfa 171 #endif
Kojto 107:4f6c30876dfa 172
Kojto 107:4f6c30876dfa 173 #ifndef __NVIC_PRIO_BITS
Kojto 107:4f6c30876dfa 174 #define __NVIC_PRIO_BITS 2
Kojto 107:4f6c30876dfa 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 107:4f6c30876dfa 176 #endif
Kojto 107:4f6c30876dfa 177
Kojto 107:4f6c30876dfa 178 #ifndef __Vendor_SysTickConfig
Kojto 107:4f6c30876dfa 179 #define __Vendor_SysTickConfig 0
Kojto 107:4f6c30876dfa 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 107:4f6c30876dfa 181 #endif
Kojto 107:4f6c30876dfa 182 #endif
Kojto 107:4f6c30876dfa 183
Kojto 107:4f6c30876dfa 184 /* IO definitions (access restrictions to peripheral registers) */
Kojto 107:4f6c30876dfa 185 /**
Kojto 107:4f6c30876dfa 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 107:4f6c30876dfa 187
Kojto 107:4f6c30876dfa 188 <strong>IO Type Qualifiers</strong> are used
Kojto 107:4f6c30876dfa 189 \li to specify the access to peripheral variables.
Kojto 107:4f6c30876dfa 190 \li for automatic generation of peripheral register debug information.
Kojto 107:4f6c30876dfa 191 */
Kojto 107:4f6c30876dfa 192 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 193 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 107:4f6c30876dfa 194 #else
Kojto 107:4f6c30876dfa 195 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 107:4f6c30876dfa 196 #endif
Kojto 107:4f6c30876dfa 197 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 107:4f6c30876dfa 198 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 107:4f6c30876dfa 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
Kojto 107:4f6c30876dfa 208 /*@} end of group Cortex_M0 */
Kojto 107:4f6c30876dfa 209
Kojto 107:4f6c30876dfa 210
Kojto 107:4f6c30876dfa 211
Kojto 107:4f6c30876dfa 212 /*******************************************************************************
Kojto 107:4f6c30876dfa 213 * Register Abstraction
Kojto 107:4f6c30876dfa 214 Core Register contain:
Kojto 107:4f6c30876dfa 215 - Core Register
Kojto 107:4f6c30876dfa 216 - Core NVIC Register
Kojto 107:4f6c30876dfa 217 - Core SCB Register
Kojto 107:4f6c30876dfa 218 - Core SysTick Register
Kojto 107:4f6c30876dfa 219 ******************************************************************************/
Kojto 107:4f6c30876dfa 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 107:4f6c30876dfa 221 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 107:4f6c30876dfa 222 */
Kojto 107:4f6c30876dfa 223
Kojto 107:4f6c30876dfa 224 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 225 \defgroup CMSIS_CORE Status and Control Registers
Kojto 107:4f6c30876dfa 226 \brief Core Register type definitions.
Kojto 107:4f6c30876dfa 227 @{
Kojto 107:4f6c30876dfa 228 */
Kojto 107:4f6c30876dfa 229
Kojto 107:4f6c30876dfa 230 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 107:4f6c30876dfa 231 */
Kojto 107:4f6c30876dfa 232 typedef union
Kojto 107:4f6c30876dfa 233 {
Kojto 107:4f6c30876dfa 234 struct
Kojto 107:4f6c30876dfa 235 {
Kojto 110:165afa46840b 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 107:4f6c30876dfa 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 107:4f6c30876dfa 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 107:4f6c30876dfa 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 107:4f6c30876dfa 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 107:4f6c30876dfa 241 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 242 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 243 } APSR_Type;
Kojto 107:4f6c30876dfa 244
Kojto 110:165afa46840b 245 /* APSR Register Definitions */
Kojto 110:165afa46840b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 248
Kojto 110:165afa46840b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 257
Kojto 107:4f6c30876dfa 258
Kojto 107:4f6c30876dfa 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 107:4f6c30876dfa 260 */
Kojto 107:4f6c30876dfa 261 typedef union
Kojto 107:4f6c30876dfa 262 {
Kojto 107:4f6c30876dfa 263 struct
Kojto 107:4f6c30876dfa 264 {
Kojto 107:4f6c30876dfa 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 107:4f6c30876dfa 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 107:4f6c30876dfa 267 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 268 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 269 } IPSR_Type;
Kojto 107:4f6c30876dfa 270
Kojto 110:165afa46840b 271 /* IPSR Register Definitions */
Kojto 110:165afa46840b 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 274
Kojto 107:4f6c30876dfa 275
Kojto 107:4f6c30876dfa 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 107:4f6c30876dfa 277 */
Kojto 107:4f6c30876dfa 278 typedef union
Kojto 107:4f6c30876dfa 279 {
Kojto 107:4f6c30876dfa 280 struct
Kojto 107:4f6c30876dfa 281 {
Kojto 107:4f6c30876dfa 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 107:4f6c30876dfa 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 107:4f6c30876dfa 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 107:4f6c30876dfa 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 107:4f6c30876dfa 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 107:4f6c30876dfa 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 107:4f6c30876dfa 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 107:4f6c30876dfa 290 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 291 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 292 } xPSR_Type;
Kojto 107:4f6c30876dfa 293
Kojto 110:165afa46840b 294 /* xPSR Register Definitions */
Kojto 110:165afa46840b 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 297
Kojto 110:165afa46840b 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 312
Kojto 107:4f6c30876dfa 313
Kojto 107:4f6c30876dfa 314 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 107:4f6c30876dfa 315 */
Kojto 107:4f6c30876dfa 316 typedef union
Kojto 107:4f6c30876dfa 317 {
Kojto 107:4f6c30876dfa 318 struct
Kojto 107:4f6c30876dfa 319 {
Kojto 110:165afa46840b 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 107:4f6c30876dfa 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 107:4f6c30876dfa 323 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 324 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 325 } CONTROL_Type;
Kojto 107:4f6c30876dfa 326
Kojto 110:165afa46840b 327 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 330
Kojto 107:4f6c30876dfa 331 /*@} end of group CMSIS_CORE */
Kojto 107:4f6c30876dfa 332
Kojto 107:4f6c30876dfa 333
Kojto 107:4f6c30876dfa 334 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 107:4f6c30876dfa 336 \brief Type definitions for the NVIC Registers
Kojto 107:4f6c30876dfa 337 @{
Kojto 107:4f6c30876dfa 338 */
Kojto 107:4f6c30876dfa 339
Kojto 107:4f6c30876dfa 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 107:4f6c30876dfa 341 */
Kojto 107:4f6c30876dfa 342 typedef struct
Kojto 107:4f6c30876dfa 343 {
Kojto 107:4f6c30876dfa 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 107:4f6c30876dfa 345 uint32_t RESERVED0[31];
Kojto 107:4f6c30876dfa 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 107:4f6c30876dfa 347 uint32_t RSERVED1[31];
Kojto 107:4f6c30876dfa 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 107:4f6c30876dfa 349 uint32_t RESERVED2[31];
Kojto 107:4f6c30876dfa 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 107:4f6c30876dfa 351 uint32_t RESERVED3[31];
Kojto 107:4f6c30876dfa 352 uint32_t RESERVED4[64];
Kojto 107:4f6c30876dfa 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 107:4f6c30876dfa 354 } NVIC_Type;
Kojto 107:4f6c30876dfa 355
Kojto 107:4f6c30876dfa 356 /*@} end of group CMSIS_NVIC */
Kojto 107:4f6c30876dfa 357
Kojto 107:4f6c30876dfa 358
Kojto 107:4f6c30876dfa 359 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 360 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 107:4f6c30876dfa 361 \brief Type definitions for the System Control Block Registers
Kojto 107:4f6c30876dfa 362 @{
Kojto 107:4f6c30876dfa 363 */
Kojto 107:4f6c30876dfa 364
Kojto 107:4f6c30876dfa 365 /** \brief Structure type to access the System Control Block (SCB).
Kojto 107:4f6c30876dfa 366 */
Kojto 107:4f6c30876dfa 367 typedef struct
Kojto 107:4f6c30876dfa 368 {
Kojto 107:4f6c30876dfa 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 107:4f6c30876dfa 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 107:4f6c30876dfa 371 uint32_t RESERVED0;
Kojto 107:4f6c30876dfa 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 107:4f6c30876dfa 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 107:4f6c30876dfa 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 107:4f6c30876dfa 375 uint32_t RESERVED1;
Kojto 107:4f6c30876dfa 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 107:4f6c30876dfa 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 107:4f6c30876dfa 378 } SCB_Type;
Kojto 107:4f6c30876dfa 379
Kojto 107:4f6c30876dfa 380 /* SCB CPUID Register Definitions */
Kojto 107:4f6c30876dfa 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 107:4f6c30876dfa 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 107:4f6c30876dfa 383
Kojto 107:4f6c30876dfa 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 107:4f6c30876dfa 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 107:4f6c30876dfa 386
Kojto 107:4f6c30876dfa 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 107:4f6c30876dfa 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 107:4f6c30876dfa 389
Kojto 107:4f6c30876dfa 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 107:4f6c30876dfa 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 107:4f6c30876dfa 392
Kojto 107:4f6c30876dfa 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 107:4f6c30876dfa 395
Kojto 107:4f6c30876dfa 396 /* SCB Interrupt Control State Register Definitions */
Kojto 107:4f6c30876dfa 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 107:4f6c30876dfa 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 107:4f6c30876dfa 399
Kojto 107:4f6c30876dfa 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 107:4f6c30876dfa 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 107:4f6c30876dfa 402
Kojto 107:4f6c30876dfa 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 107:4f6c30876dfa 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 107:4f6c30876dfa 405
Kojto 107:4f6c30876dfa 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 107:4f6c30876dfa 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 107:4f6c30876dfa 408
Kojto 107:4f6c30876dfa 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 107:4f6c30876dfa 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 107:4f6c30876dfa 411
Kojto 107:4f6c30876dfa 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 107:4f6c30876dfa 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 107:4f6c30876dfa 414
Kojto 107:4f6c30876dfa 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 107:4f6c30876dfa 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 107:4f6c30876dfa 417
Kojto 107:4f6c30876dfa 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 107:4f6c30876dfa 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 107:4f6c30876dfa 420
Kojto 107:4f6c30876dfa 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 107:4f6c30876dfa 423
Kojto 107:4f6c30876dfa 424 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 107:4f6c30876dfa 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 107:4f6c30876dfa 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 107:4f6c30876dfa 427
Kojto 107:4f6c30876dfa 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 107:4f6c30876dfa 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 107:4f6c30876dfa 430
Kojto 107:4f6c30876dfa 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 107:4f6c30876dfa 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 107:4f6c30876dfa 433
Kojto 107:4f6c30876dfa 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 107:4f6c30876dfa 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 107:4f6c30876dfa 436
Kojto 107:4f6c30876dfa 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 107:4f6c30876dfa 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 107:4f6c30876dfa 439
Kojto 107:4f6c30876dfa 440 /* SCB System Control Register Definitions */
Kojto 107:4f6c30876dfa 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 107:4f6c30876dfa 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 107:4f6c30876dfa 443
Kojto 107:4f6c30876dfa 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 107:4f6c30876dfa 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 107:4f6c30876dfa 446
Kojto 107:4f6c30876dfa 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 107:4f6c30876dfa 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 107:4f6c30876dfa 449
Kojto 107:4f6c30876dfa 450 /* SCB Configuration Control Register Definitions */
Kojto 107:4f6c30876dfa 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 107:4f6c30876dfa 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 107:4f6c30876dfa 453
Kojto 107:4f6c30876dfa 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 107:4f6c30876dfa 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 107:4f6c30876dfa 456
Kojto 107:4f6c30876dfa 457 /* SCB System Handler Control and State Register Definitions */
Kojto 107:4f6c30876dfa 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 107:4f6c30876dfa 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 107:4f6c30876dfa 460
Kojto 107:4f6c30876dfa 461 /*@} end of group CMSIS_SCB */
Kojto 107:4f6c30876dfa 462
Kojto 107:4f6c30876dfa 463
Kojto 107:4f6c30876dfa 464 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 107:4f6c30876dfa 466 \brief Type definitions for the System Timer Registers.
Kojto 107:4f6c30876dfa 467 @{
Kojto 107:4f6c30876dfa 468 */
Kojto 107:4f6c30876dfa 469
Kojto 107:4f6c30876dfa 470 /** \brief Structure type to access the System Timer (SysTick).
Kojto 107:4f6c30876dfa 471 */
Kojto 107:4f6c30876dfa 472 typedef struct
Kojto 107:4f6c30876dfa 473 {
Kojto 107:4f6c30876dfa 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 107:4f6c30876dfa 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 107:4f6c30876dfa 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 107:4f6c30876dfa 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 107:4f6c30876dfa 478 } SysTick_Type;
Kojto 107:4f6c30876dfa 479
Kojto 107:4f6c30876dfa 480 /* SysTick Control / Status Register Definitions */
Kojto 107:4f6c30876dfa 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 107:4f6c30876dfa 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 107:4f6c30876dfa 483
Kojto 107:4f6c30876dfa 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 107:4f6c30876dfa 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 107:4f6c30876dfa 486
Kojto 107:4f6c30876dfa 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 107:4f6c30876dfa 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 107:4f6c30876dfa 489
Kojto 107:4f6c30876dfa 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 107:4f6c30876dfa 492
Kojto 107:4f6c30876dfa 493 /* SysTick Reload Register Definitions */
Kojto 107:4f6c30876dfa 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 107:4f6c30876dfa 496
Kojto 107:4f6c30876dfa 497 /* SysTick Current Register Definitions */
Kojto 107:4f6c30876dfa 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 107:4f6c30876dfa 500
Kojto 107:4f6c30876dfa 501 /* SysTick Calibration Register Definitions */
Kojto 107:4f6c30876dfa 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 107:4f6c30876dfa 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 107:4f6c30876dfa 504
Kojto 107:4f6c30876dfa 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 107:4f6c30876dfa 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 107:4f6c30876dfa 507
Kojto 107:4f6c30876dfa 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 107:4f6c30876dfa 510
Kojto 107:4f6c30876dfa 511 /*@} end of group CMSIS_SysTick */
Kojto 107:4f6c30876dfa 512
Kojto 107:4f6c30876dfa 513
Kojto 107:4f6c30876dfa 514 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 107:4f6c30876dfa 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 107:4f6c30876dfa 517 are only accessible over DAP and not via processor. Therefore
Kojto 107:4f6c30876dfa 518 they are not covered by the Cortex-M0 header file.
Kojto 107:4f6c30876dfa 519 @{
Kojto 107:4f6c30876dfa 520 */
Kojto 107:4f6c30876dfa 521 /*@} end of group CMSIS_CoreDebug */
Kojto 107:4f6c30876dfa 522
Kojto 107:4f6c30876dfa 523
Kojto 107:4f6c30876dfa 524 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 525 \defgroup CMSIS_core_base Core Definitions
Kojto 107:4f6c30876dfa 526 \brief Definitions for base addresses, unions, and structures.
Kojto 107:4f6c30876dfa 527 @{
Kojto 107:4f6c30876dfa 528 */
Kojto 107:4f6c30876dfa 529
Kojto 107:4f6c30876dfa 530 /* Memory mapping of Cortex-M0 Hardware */
Kojto 107:4f6c30876dfa 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 107:4f6c30876dfa 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 107:4f6c30876dfa 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 107:4f6c30876dfa 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 107:4f6c30876dfa 535
Kojto 107:4f6c30876dfa 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 107:4f6c30876dfa 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 107:4f6c30876dfa 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 107:4f6c30876dfa 539
Kojto 107:4f6c30876dfa 540
Kojto 107:4f6c30876dfa 541 /*@} */
Kojto 107:4f6c30876dfa 542
Kojto 107:4f6c30876dfa 543
Kojto 107:4f6c30876dfa 544
Kojto 107:4f6c30876dfa 545 /*******************************************************************************
Kojto 107:4f6c30876dfa 546 * Hardware Abstraction Layer
Kojto 107:4f6c30876dfa 547 Core Function Interface contains:
Kojto 107:4f6c30876dfa 548 - Core NVIC Functions
Kojto 107:4f6c30876dfa 549 - Core SysTick Functions
Kojto 107:4f6c30876dfa 550 - Core Register Access Functions
Kojto 107:4f6c30876dfa 551 ******************************************************************************/
Kojto 107:4f6c30876dfa 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 107:4f6c30876dfa 553 */
Kojto 107:4f6c30876dfa 554
Kojto 107:4f6c30876dfa 555
Kojto 107:4f6c30876dfa 556
Kojto 107:4f6c30876dfa 557 /* ########################## NVIC functions #################################### */
Kojto 107:4f6c30876dfa 558 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 107:4f6c30876dfa 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 107:4f6c30876dfa 560 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 107:4f6c30876dfa 561 @{
Kojto 107:4f6c30876dfa 562 */
Kojto 107:4f6c30876dfa 563
Kojto 107:4f6c30876dfa 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 107:4f6c30876dfa 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 107:4f6c30876dfa 569
Kojto 107:4f6c30876dfa 570
Kojto 107:4f6c30876dfa 571 /** \brief Enable External Interrupt
Kojto 107:4f6c30876dfa 572
Kojto 107:4f6c30876dfa 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 107:4f6c30876dfa 574
Kojto 107:4f6c30876dfa 575 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 576 */
Kojto 107:4f6c30876dfa 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 578 {
Kojto 110:165afa46840b 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 107:4f6c30876dfa 580 }
Kojto 107:4f6c30876dfa 581
Kojto 107:4f6c30876dfa 582
Kojto 107:4f6c30876dfa 583 /** \brief Disable External Interrupt
Kojto 107:4f6c30876dfa 584
Kojto 107:4f6c30876dfa 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 107:4f6c30876dfa 586
Kojto 107:4f6c30876dfa 587 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 588 */
Kojto 107:4f6c30876dfa 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 590 {
Kojto 110:165afa46840b 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
Kojto 107:4f6c30876dfa 594 }
Kojto 107:4f6c30876dfa 595
Kojto 107:4f6c30876dfa 596
Kojto 107:4f6c30876dfa 597 /** \brief Get Pending Interrupt
Kojto 107:4f6c30876dfa 598
Kojto 107:4f6c30876dfa 599 The function reads the pending register in the NVIC and returns the pending bit
Kojto 107:4f6c30876dfa 600 for the specified interrupt.
Kojto 107:4f6c30876dfa 601
Kojto 107:4f6c30876dfa 602 \param [in] IRQn Interrupt number.
Kojto 107:4f6c30876dfa 603
Kojto 107:4f6c30876dfa 604 \return 0 Interrupt status is not pending.
Kojto 107:4f6c30876dfa 605 \return 1 Interrupt status is pending.
Kojto 107:4f6c30876dfa 606 */
Kojto 107:4f6c30876dfa 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 608 {
Kojto 110:165afa46840b 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 107:4f6c30876dfa 610 }
Kojto 107:4f6c30876dfa 611
Kojto 107:4f6c30876dfa 612
Kojto 107:4f6c30876dfa 613 /** \brief Set Pending Interrupt
Kojto 107:4f6c30876dfa 614
Kojto 107:4f6c30876dfa 615 The function sets the pending bit of an external interrupt.
Kojto 107:4f6c30876dfa 616
Kojto 107:4f6c30876dfa 617 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 618 */
Kojto 107:4f6c30876dfa 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 620 {
Kojto 110:165afa46840b 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 107:4f6c30876dfa 622 }
Kojto 107:4f6c30876dfa 623
Kojto 107:4f6c30876dfa 624
Kojto 107:4f6c30876dfa 625 /** \brief Clear Pending Interrupt
Kojto 107:4f6c30876dfa 626
Kojto 107:4f6c30876dfa 627 The function clears the pending bit of an external interrupt.
Kojto 107:4f6c30876dfa 628
Kojto 107:4f6c30876dfa 629 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 630 */
Kojto 107:4f6c30876dfa 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 632 {
Kojto 110:165afa46840b 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 107:4f6c30876dfa 634 }
Kojto 107:4f6c30876dfa 635
Kojto 107:4f6c30876dfa 636
Kojto 107:4f6c30876dfa 637 /** \brief Set Interrupt Priority
Kojto 107:4f6c30876dfa 638
Kojto 107:4f6c30876dfa 639 The function sets the priority of an interrupt.
Kojto 107:4f6c30876dfa 640
Kojto 107:4f6c30876dfa 641 \note The priority cannot be set for every core interrupt.
Kojto 107:4f6c30876dfa 642
Kojto 107:4f6c30876dfa 643 \param [in] IRQn Interrupt number.
Kojto 107:4f6c30876dfa 644 \param [in] priority Priority to set.
Kojto 107:4f6c30876dfa 645 */
Kojto 107:4f6c30876dfa 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 107:4f6c30876dfa 647 {
Kojto 110:165afa46840b 648 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 651 }
Kojto 107:4f6c30876dfa 652 else {
Kojto 110:165afa46840b 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 655 }
Kojto 107:4f6c30876dfa 656 }
Kojto 107:4f6c30876dfa 657
Kojto 107:4f6c30876dfa 658
Kojto 107:4f6c30876dfa 659 /** \brief Get Interrupt Priority
Kojto 107:4f6c30876dfa 660
Kojto 107:4f6c30876dfa 661 The function reads the priority of an interrupt. The interrupt
Kojto 107:4f6c30876dfa 662 number can be positive to specify an external (device specific)
Kojto 107:4f6c30876dfa 663 interrupt, or negative to specify an internal (core) interrupt.
Kojto 107:4f6c30876dfa 664
Kojto 107:4f6c30876dfa 665
Kojto 107:4f6c30876dfa 666 \param [in] IRQn Interrupt number.
Kojto 107:4f6c30876dfa 667 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 107:4f6c30876dfa 668 priority bits of the microcontroller.
Kojto 107:4f6c30876dfa 669 */
Kojto 107:4f6c30876dfa 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 671 {
Kojto 107:4f6c30876dfa 672
Kojto 110:165afa46840b 673 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 675 }
Kojto 107:4f6c30876dfa 676 else {
Kojto 110:165afa46840b 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 678 }
Kojto 107:4f6c30876dfa 679 }
Kojto 107:4f6c30876dfa 680
Kojto 107:4f6c30876dfa 681
Kojto 107:4f6c30876dfa 682 /** \brief System Reset
Kojto 107:4f6c30876dfa 683
Kojto 107:4f6c30876dfa 684 The function initiates a system reset request to reset the MCU.
Kojto 107:4f6c30876dfa 685 */
Kojto 107:4f6c30876dfa 686 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 107:4f6c30876dfa 687 {
Kojto 107:4f6c30876dfa 688 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 107:4f6c30876dfa 689 buffered write are completed before reset */
Kojto 110:165afa46840b 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 107:4f6c30876dfa 691 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 107:4f6c30876dfa 692 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 693 while(1) { __NOP(); } /* wait until reset */
Kojto 107:4f6c30876dfa 694 }
Kojto 107:4f6c30876dfa 695
Kojto 107:4f6c30876dfa 696 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 107:4f6c30876dfa 697
Kojto 107:4f6c30876dfa 698
Kojto 107:4f6c30876dfa 699
Kojto 107:4f6c30876dfa 700 /* ################################## SysTick function ############################################ */
Kojto 107:4f6c30876dfa 701 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 107:4f6c30876dfa 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 107:4f6c30876dfa 703 \brief Functions that configure the System.
Kojto 107:4f6c30876dfa 704 @{
Kojto 107:4f6c30876dfa 705 */
Kojto 107:4f6c30876dfa 706
Kojto 107:4f6c30876dfa 707 #if (__Vendor_SysTickConfig == 0)
Kojto 107:4f6c30876dfa 708
Kojto 107:4f6c30876dfa 709 /** \brief System Tick Configuration
Kojto 107:4f6c30876dfa 710
Kojto 107:4f6c30876dfa 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 107:4f6c30876dfa 712 Counter is in free running mode to generate periodic interrupts.
Kojto 107:4f6c30876dfa 713
Kojto 107:4f6c30876dfa 714 \param [in] ticks Number of ticks between two interrupts.
Kojto 107:4f6c30876dfa 715
Kojto 107:4f6c30876dfa 716 \return 0 Function succeeded.
Kojto 107:4f6c30876dfa 717 \return 1 Function failed.
Kojto 107:4f6c30876dfa 718
Kojto 107:4f6c30876dfa 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 107:4f6c30876dfa 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 107:4f6c30876dfa 721 must contain a vendor-specific implementation of this function.
Kojto 107:4f6c30876dfa 722
Kojto 107:4f6c30876dfa 723 */
Kojto 107:4f6c30876dfa 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 107:4f6c30876dfa 725 {
Kojto 110:165afa46840b 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 107:4f6c30876dfa 727
Kojto 110:165afa46840b 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 107:4f6c30876dfa 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 107:4f6c30876dfa 732 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 734 return (0UL); /* Function successful */
Kojto 107:4f6c30876dfa 735 }
Kojto 107:4f6c30876dfa 736
Kojto 107:4f6c30876dfa 737 #endif
Kojto 107:4f6c30876dfa 738
Kojto 107:4f6c30876dfa 739 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 107:4f6c30876dfa 740
Kojto 107:4f6c30876dfa 741
Kojto 107:4f6c30876dfa 742
Kojto 107:4f6c30876dfa 743
Kojto 110:165afa46840b 744 #ifdef __cplusplus
Kojto 110:165afa46840b 745 }
Kojto 110:165afa46840b 746 #endif
Kojto 110:165afa46840b 747
Kojto 107:4f6c30876dfa 748 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 107:4f6c30876dfa 749
Kojto 107:4f6c30876dfa 750 #endif /* __CMSIS_GENERIC */