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mbed 2

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TARGET_DISCO_L072CZ_LRWAN1/core_sc300.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**************************************************************************//**
AnnaBridge 143:86740a56073b 2 * @file core_sc300.h
AnnaBridge 143:86740a56073b 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
AnnaBridge 143:86740a56073b 4 * @version V4.10
AnnaBridge 143:86740a56073b 5 * @date 18. March 2015
AnnaBridge 143:86740a56073b 6 *
AnnaBridge 143:86740a56073b 7 * @note
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 ******************************************************************************/
AnnaBridge 143:86740a56073b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 143:86740a56073b 11
AnnaBridge 143:86740a56073b 12 All rights reserved.
AnnaBridge 143:86740a56073b 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 143:86740a56073b 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 15 - Redistributions of source code must retain the above copyright
AnnaBridge 143:86740a56073b 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 143:86740a56073b 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 143:86740a56073b 19 documentation and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 143:86740a56073b 21 to endorse or promote products derived from this software without
AnnaBridge 143:86740a56073b 22 specific prior written permission.
AnnaBridge 143:86740a56073b 23 *
AnnaBridge 143:86740a56073b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 143:86740a56073b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 143:86740a56073b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 143:86740a56073b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 143:86740a56073b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 143:86740a56073b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 143:86740a56073b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 143:86740a56073b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 143:86740a56073b 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 35 ---------------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 36
AnnaBridge 143:86740a56073b 37
AnnaBridge 143:86740a56073b 38 #if defined ( __ICCARM__ )
AnnaBridge 143:86740a56073b 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 143:86740a56073b 40 #endif
AnnaBridge 143:86740a56073b 41
AnnaBridge 143:86740a56073b 42 #ifndef __CORE_SC300_H_GENERIC
AnnaBridge 143:86740a56073b 43 #define __CORE_SC300_H_GENERIC
AnnaBridge 143:86740a56073b 44
AnnaBridge 143:86740a56073b 45 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 46 extern "C" {
AnnaBridge 143:86740a56073b 47 #endif
AnnaBridge 143:86740a56073b 48
AnnaBridge 143:86740a56073b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 143:86740a56073b 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 143:86740a56073b 51
AnnaBridge 143:86740a56073b 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 143:86740a56073b 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 143:86740a56073b 54
AnnaBridge 143:86740a56073b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 143:86740a56073b 56 Unions are used for effective representation of core registers.
AnnaBridge 143:86740a56073b 57
AnnaBridge 143:86740a56073b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 143:86740a56073b 59 Function-like macros are used to allow more efficient code.
AnnaBridge 143:86740a56073b 60 */
AnnaBridge 143:86740a56073b 61
AnnaBridge 143:86740a56073b 62
AnnaBridge 143:86740a56073b 63 /*******************************************************************************
AnnaBridge 143:86740a56073b 64 * CMSIS definitions
AnnaBridge 143:86740a56073b 65 ******************************************************************************/
AnnaBridge 143:86740a56073b 66 /** \ingroup SC3000
AnnaBridge 143:86740a56073b 67 @{
AnnaBridge 143:86740a56073b 68 */
AnnaBridge 143:86740a56073b 69
AnnaBridge 143:86740a56073b 70 /* CMSIS SC300 definitions */
AnnaBridge 143:86740a56073b 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 143:86740a56073b 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 143:86740a56073b 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 143:86740a56073b 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 143:86740a56073b 75
AnnaBridge 143:86740a56073b 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
AnnaBridge 143:86740a56073b 77
AnnaBridge 143:86740a56073b 78
AnnaBridge 143:86740a56073b 79 #if defined ( __CC_ARM )
AnnaBridge 143:86740a56073b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 143:86740a56073b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 143:86740a56073b 82 #define __STATIC_INLINE static __inline
AnnaBridge 143:86740a56073b 83
AnnaBridge 143:86740a56073b 84 #elif defined ( __GNUC__ )
AnnaBridge 143:86740a56073b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 143:86740a56073b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 143:86740a56073b 87 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 88
AnnaBridge 143:86740a56073b 89 #elif defined ( __ICCARM__ )
AnnaBridge 143:86740a56073b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 143:86740a56073b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 143:86740a56073b 92 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 93
AnnaBridge 143:86740a56073b 94 #elif defined ( __TMS470__ )
AnnaBridge 143:86740a56073b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 143:86740a56073b 96 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 97
AnnaBridge 143:86740a56073b 98 #elif defined ( __TASKING__ )
AnnaBridge 143:86740a56073b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 143:86740a56073b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 143:86740a56073b 101 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 102
AnnaBridge 143:86740a56073b 103 #elif defined ( __CSMC__ )
AnnaBridge 143:86740a56073b 104 #define __packed
AnnaBridge 143:86740a56073b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 143:86740a56073b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 143:86740a56073b 107 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 108
AnnaBridge 143:86740a56073b 109 #endif
AnnaBridge 143:86740a56073b 110
AnnaBridge 143:86740a56073b 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 143:86740a56073b 112 This core does not support an FPU at all
AnnaBridge 143:86740a56073b 113 */
AnnaBridge 143:86740a56073b 114 #define __FPU_USED 0
AnnaBridge 143:86740a56073b 115
AnnaBridge 143:86740a56073b 116 #if defined ( __CC_ARM )
AnnaBridge 143:86740a56073b 117 #if defined __TARGET_FPU_VFP
AnnaBridge 143:86740a56073b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 119 #endif
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 #elif defined ( __GNUC__ )
AnnaBridge 143:86740a56073b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 143:86740a56073b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 124 #endif
AnnaBridge 143:86740a56073b 125
AnnaBridge 143:86740a56073b 126 #elif defined ( __ICCARM__ )
AnnaBridge 143:86740a56073b 127 #if defined __ARMVFP__
AnnaBridge 143:86740a56073b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 129 #endif
AnnaBridge 143:86740a56073b 130
AnnaBridge 143:86740a56073b 131 #elif defined ( __TMS470__ )
AnnaBridge 143:86740a56073b 132 #if defined __TI__VFP_SUPPORT____
AnnaBridge 143:86740a56073b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 134 #endif
AnnaBridge 143:86740a56073b 135
AnnaBridge 143:86740a56073b 136 #elif defined ( __TASKING__ )
AnnaBridge 143:86740a56073b 137 #if defined __FPU_VFP__
AnnaBridge 143:86740a56073b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 139 #endif
AnnaBridge 143:86740a56073b 140
AnnaBridge 143:86740a56073b 141 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 143:86740a56073b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 143:86740a56073b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 144 #endif
AnnaBridge 143:86740a56073b 145 #endif
AnnaBridge 143:86740a56073b 146
AnnaBridge 143:86740a56073b 147 #include <stdint.h> /* standard types definitions */
AnnaBridge 143:86740a56073b 148 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 143:86740a56073b 149 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 143:86740a56073b 150
AnnaBridge 143:86740a56073b 151 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 152 }
AnnaBridge 143:86740a56073b 153 #endif
AnnaBridge 143:86740a56073b 154
AnnaBridge 143:86740a56073b 155 #endif /* __CORE_SC300_H_GENERIC */
AnnaBridge 143:86740a56073b 156
AnnaBridge 143:86740a56073b 157 #ifndef __CMSIS_GENERIC
AnnaBridge 143:86740a56073b 158
AnnaBridge 143:86740a56073b 159 #ifndef __CORE_SC300_H_DEPENDANT
AnnaBridge 143:86740a56073b 160 #define __CORE_SC300_H_DEPENDANT
AnnaBridge 143:86740a56073b 161
AnnaBridge 143:86740a56073b 162 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 163 extern "C" {
AnnaBridge 143:86740a56073b 164 #endif
AnnaBridge 143:86740a56073b 165
AnnaBridge 143:86740a56073b 166 /* check device defines and use defaults */
AnnaBridge 143:86740a56073b 167 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 143:86740a56073b 168 #ifndef __SC300_REV
AnnaBridge 143:86740a56073b 169 #define __SC300_REV 0x0000
AnnaBridge 143:86740a56073b 170 #warning "__SC300_REV not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 171 #endif
AnnaBridge 143:86740a56073b 172
AnnaBridge 143:86740a56073b 173 #ifndef __MPU_PRESENT
AnnaBridge 143:86740a56073b 174 #define __MPU_PRESENT 0
AnnaBridge 143:86740a56073b 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 176 #endif
AnnaBridge 143:86740a56073b 177
AnnaBridge 143:86740a56073b 178 #ifndef __NVIC_PRIO_BITS
AnnaBridge 143:86740a56073b 179 #define __NVIC_PRIO_BITS 4
AnnaBridge 143:86740a56073b 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 181 #endif
AnnaBridge 143:86740a56073b 182
AnnaBridge 143:86740a56073b 183 #ifndef __Vendor_SysTickConfig
AnnaBridge 143:86740a56073b 184 #define __Vendor_SysTickConfig 0
AnnaBridge 143:86740a56073b 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 186 #endif
AnnaBridge 143:86740a56073b 187 #endif
AnnaBridge 143:86740a56073b 188
AnnaBridge 143:86740a56073b 189 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 143:86740a56073b 190 /**
AnnaBridge 143:86740a56073b 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 143:86740a56073b 192
AnnaBridge 143:86740a56073b 193 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 143:86740a56073b 194 \li to specify the access to peripheral variables.
AnnaBridge 143:86740a56073b 195 \li for automatic generation of peripheral register debug information.
AnnaBridge 143:86740a56073b 196 */
AnnaBridge 143:86740a56073b 197 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 198 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 143:86740a56073b 199 #else
AnnaBridge 143:86740a56073b 200 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 143:86740a56073b 201 #endif
AnnaBridge 143:86740a56073b 202 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 143:86740a56073b 203 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 143:86740a56073b 204
AnnaBridge 143:86740a56073b 205 /*@} end of group SC300 */
AnnaBridge 143:86740a56073b 206
AnnaBridge 143:86740a56073b 207
AnnaBridge 143:86740a56073b 208
AnnaBridge 143:86740a56073b 209 /*******************************************************************************
AnnaBridge 143:86740a56073b 210 * Register Abstraction
AnnaBridge 143:86740a56073b 211 Core Register contain:
AnnaBridge 143:86740a56073b 212 - Core Register
AnnaBridge 143:86740a56073b 213 - Core NVIC Register
AnnaBridge 143:86740a56073b 214 - Core SCB Register
AnnaBridge 143:86740a56073b 215 - Core SysTick Register
AnnaBridge 143:86740a56073b 216 - Core Debug Register
AnnaBridge 143:86740a56073b 217 - Core MPU Register
AnnaBridge 143:86740a56073b 218 ******************************************************************************/
AnnaBridge 143:86740a56073b 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 143:86740a56073b 220 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 143:86740a56073b 221 */
AnnaBridge 143:86740a56073b 222
AnnaBridge 143:86740a56073b 223 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 224 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 143:86740a56073b 225 \brief Core Register type definitions.
AnnaBridge 143:86740a56073b 226 @{
AnnaBridge 143:86740a56073b 227 */
AnnaBridge 143:86740a56073b 228
AnnaBridge 143:86740a56073b 229 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 143:86740a56073b 230 */
AnnaBridge 143:86740a56073b 231 typedef union
AnnaBridge 143:86740a56073b 232 {
AnnaBridge 143:86740a56073b 233 struct
AnnaBridge 143:86740a56073b 234 {
AnnaBridge 143:86740a56073b 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 143:86740a56073b 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 143:86740a56073b 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 143:86740a56073b 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 143:86740a56073b 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 143:86740a56073b 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 143:86740a56073b 241 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 242 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 243 } APSR_Type;
AnnaBridge 143:86740a56073b 244
AnnaBridge 143:86740a56073b 245 /* APSR Register Definitions */
AnnaBridge 143:86740a56073b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 143:86740a56073b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 143:86740a56073b 248
AnnaBridge 143:86740a56073b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 143:86740a56073b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 143:86740a56073b 251
AnnaBridge 143:86740a56073b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 143:86740a56073b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 143:86740a56073b 254
AnnaBridge 143:86740a56073b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 143:86740a56073b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 143:86740a56073b 257
AnnaBridge 143:86740a56073b 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
AnnaBridge 143:86740a56073b 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 143:86740a56073b 260
AnnaBridge 143:86740a56073b 261
AnnaBridge 143:86740a56073b 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 143:86740a56073b 263 */
AnnaBridge 143:86740a56073b 264 typedef union
AnnaBridge 143:86740a56073b 265 {
AnnaBridge 143:86740a56073b 266 struct
AnnaBridge 143:86740a56073b 267 {
AnnaBridge 143:86740a56073b 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 143:86740a56073b 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 143:86740a56073b 270 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 271 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 272 } IPSR_Type;
AnnaBridge 143:86740a56073b 273
AnnaBridge 143:86740a56073b 274 /* IPSR Register Definitions */
AnnaBridge 143:86740a56073b 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 143:86740a56073b 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 143:86740a56073b 277
AnnaBridge 143:86740a56073b 278
AnnaBridge 143:86740a56073b 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 143:86740a56073b 280 */
AnnaBridge 143:86740a56073b 281 typedef union
AnnaBridge 143:86740a56073b 282 {
AnnaBridge 143:86740a56073b 283 struct
AnnaBridge 143:86740a56073b 284 {
AnnaBridge 143:86740a56073b 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 143:86740a56073b 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 143:86740a56073b 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 143:86740a56073b 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
AnnaBridge 143:86740a56073b 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 143:86740a56073b 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 143:86740a56073b 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 143:86740a56073b 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 143:86740a56073b 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 143:86740a56073b 294 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 295 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 296 } xPSR_Type;
AnnaBridge 143:86740a56073b 297
AnnaBridge 143:86740a56073b 298 /* xPSR Register Definitions */
AnnaBridge 143:86740a56073b 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 143:86740a56073b 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 143:86740a56073b 301
AnnaBridge 143:86740a56073b 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 143:86740a56073b 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 143:86740a56073b 304
AnnaBridge 143:86740a56073b 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 143:86740a56073b 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 143:86740a56073b 307
AnnaBridge 143:86740a56073b 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 143:86740a56073b 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 143:86740a56073b 310
AnnaBridge 143:86740a56073b 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
AnnaBridge 143:86740a56073b 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 143:86740a56073b 313
AnnaBridge 143:86740a56073b 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
AnnaBridge 143:86740a56073b 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
AnnaBridge 143:86740a56073b 316
AnnaBridge 143:86740a56073b 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 143:86740a56073b 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 143:86740a56073b 319
AnnaBridge 143:86740a56073b 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 143:86740a56073b 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 143:86740a56073b 322
AnnaBridge 143:86740a56073b 323
AnnaBridge 143:86740a56073b 324 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 143:86740a56073b 325 */
AnnaBridge 143:86740a56073b 326 typedef union
AnnaBridge 143:86740a56073b 327 {
AnnaBridge 143:86740a56073b 328 struct
AnnaBridge 143:86740a56073b 329 {
AnnaBridge 143:86740a56073b 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 143:86740a56073b 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 143:86740a56073b 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 143:86740a56073b 333 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 334 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 335 } CONTROL_Type;
AnnaBridge 143:86740a56073b 336
AnnaBridge 143:86740a56073b 337 /* CONTROL Register Definitions */
AnnaBridge 143:86740a56073b 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 143:86740a56073b 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 143:86740a56073b 340
AnnaBridge 143:86740a56073b 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
AnnaBridge 143:86740a56073b 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 143:86740a56073b 343
AnnaBridge 143:86740a56073b 344 /*@} end of group CMSIS_CORE */
AnnaBridge 143:86740a56073b 345
AnnaBridge 143:86740a56073b 346
AnnaBridge 143:86740a56073b 347 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 143:86740a56073b 349 \brief Type definitions for the NVIC Registers
AnnaBridge 143:86740a56073b 350 @{
AnnaBridge 143:86740a56073b 351 */
AnnaBridge 143:86740a56073b 352
AnnaBridge 143:86740a56073b 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 143:86740a56073b 354 */
AnnaBridge 143:86740a56073b 355 typedef struct
AnnaBridge 143:86740a56073b 356 {
AnnaBridge 143:86740a56073b 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 143:86740a56073b 358 uint32_t RESERVED0[24];
AnnaBridge 143:86740a56073b 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 143:86740a56073b 360 uint32_t RSERVED1[24];
AnnaBridge 143:86740a56073b 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 143:86740a56073b 362 uint32_t RESERVED2[24];
AnnaBridge 143:86740a56073b 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 143:86740a56073b 364 uint32_t RESERVED3[24];
AnnaBridge 143:86740a56073b 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 143:86740a56073b 366 uint32_t RESERVED4[56];
AnnaBridge 143:86740a56073b 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 143:86740a56073b 368 uint32_t RESERVED5[644];
AnnaBridge 143:86740a56073b 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 143:86740a56073b 370 } NVIC_Type;
AnnaBridge 143:86740a56073b 371
AnnaBridge 143:86740a56073b 372 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 143:86740a56073b 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
AnnaBridge 143:86740a56073b 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 143:86740a56073b 375
AnnaBridge 143:86740a56073b 376 /*@} end of group CMSIS_NVIC */
AnnaBridge 143:86740a56073b 377
AnnaBridge 143:86740a56073b 378
AnnaBridge 143:86740a56073b 379 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 380 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 143:86740a56073b 381 \brief Type definitions for the System Control Block Registers
AnnaBridge 143:86740a56073b 382 @{
AnnaBridge 143:86740a56073b 383 */
AnnaBridge 143:86740a56073b 384
AnnaBridge 143:86740a56073b 385 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 143:86740a56073b 386 */
AnnaBridge 143:86740a56073b 387 typedef struct
AnnaBridge 143:86740a56073b 388 {
AnnaBridge 143:86740a56073b 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 143:86740a56073b 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 143:86740a56073b 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 143:86740a56073b 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 143:86740a56073b 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 143:86740a56073b 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 143:86740a56073b 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 143:86740a56073b 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 143:86740a56073b 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 143:86740a56073b 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 143:86740a56073b 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 143:86740a56073b 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 143:86740a56073b 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 143:86740a56073b 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 143:86740a56073b 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 143:86740a56073b 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 143:86740a56073b 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 143:86740a56073b 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 143:86740a56073b 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 143:86740a56073b 408 uint32_t RESERVED0[5];
AnnaBridge 143:86740a56073b 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 143:86740a56073b 410 uint32_t RESERVED1[129];
AnnaBridge 143:86740a56073b 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 143:86740a56073b 412 } SCB_Type;
AnnaBridge 143:86740a56073b 413
AnnaBridge 143:86740a56073b 414 /* SCB CPUID Register Definitions */
AnnaBridge 143:86740a56073b 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 143:86740a56073b 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 143:86740a56073b 417
AnnaBridge 143:86740a56073b 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 143:86740a56073b 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 143:86740a56073b 420
AnnaBridge 143:86740a56073b 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 143:86740a56073b 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 143:86740a56073b 423
AnnaBridge 143:86740a56073b 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 143:86740a56073b 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 143:86740a56073b 426
AnnaBridge 143:86740a56073b 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 143:86740a56073b 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 143:86740a56073b 429
AnnaBridge 143:86740a56073b 430 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 143:86740a56073b 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 143:86740a56073b 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 143:86740a56073b 433
AnnaBridge 143:86740a56073b 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 143:86740a56073b 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 143:86740a56073b 436
AnnaBridge 143:86740a56073b 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 143:86740a56073b 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 143:86740a56073b 439
AnnaBridge 143:86740a56073b 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 143:86740a56073b 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 143:86740a56073b 442
AnnaBridge 143:86740a56073b 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 143:86740a56073b 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 143:86740a56073b 445
AnnaBridge 143:86740a56073b 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 143:86740a56073b 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 143:86740a56073b 448
AnnaBridge 143:86740a56073b 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 143:86740a56073b 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 143:86740a56073b 451
AnnaBridge 143:86740a56073b 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 143:86740a56073b 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 143:86740a56073b 454
AnnaBridge 143:86740a56073b 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 143:86740a56073b 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 143:86740a56073b 457
AnnaBridge 143:86740a56073b 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 143:86740a56073b 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 143:86740a56073b 460
AnnaBridge 143:86740a56073b 461 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 143:86740a56073b 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
AnnaBridge 143:86740a56073b 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
AnnaBridge 143:86740a56073b 464
AnnaBridge 143:86740a56073b 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 143:86740a56073b 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 143:86740a56073b 467
AnnaBridge 143:86740a56073b 468 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 143:86740a56073b 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 143:86740a56073b 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 143:86740a56073b 471
AnnaBridge 143:86740a56073b 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 143:86740a56073b 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 143:86740a56073b 474
AnnaBridge 143:86740a56073b 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 143:86740a56073b 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 143:86740a56073b 477
AnnaBridge 143:86740a56073b 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 143:86740a56073b 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 143:86740a56073b 480
AnnaBridge 143:86740a56073b 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 143:86740a56073b 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 143:86740a56073b 483
AnnaBridge 143:86740a56073b 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 143:86740a56073b 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 143:86740a56073b 486
AnnaBridge 143:86740a56073b 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 143:86740a56073b 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 143:86740a56073b 489
AnnaBridge 143:86740a56073b 490 /* SCB System Control Register Definitions */
AnnaBridge 143:86740a56073b 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 143:86740a56073b 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 143:86740a56073b 493
AnnaBridge 143:86740a56073b 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 143:86740a56073b 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 143:86740a56073b 496
AnnaBridge 143:86740a56073b 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 143:86740a56073b 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 143:86740a56073b 499
AnnaBridge 143:86740a56073b 500 /* SCB Configuration Control Register Definitions */
AnnaBridge 143:86740a56073b 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 143:86740a56073b 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 143:86740a56073b 503
AnnaBridge 143:86740a56073b 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 143:86740a56073b 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 143:86740a56073b 506
AnnaBridge 143:86740a56073b 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 143:86740a56073b 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 143:86740a56073b 509
AnnaBridge 143:86740a56073b 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 143:86740a56073b 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 143:86740a56073b 512
AnnaBridge 143:86740a56073b 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 143:86740a56073b 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 143:86740a56073b 515
AnnaBridge 143:86740a56073b 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 143:86740a56073b 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 143:86740a56073b 518
AnnaBridge 143:86740a56073b 519 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 143:86740a56073b 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 143:86740a56073b 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 143:86740a56073b 522
AnnaBridge 143:86740a56073b 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 143:86740a56073b 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 143:86740a56073b 525
AnnaBridge 143:86740a56073b 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 143:86740a56073b 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 143:86740a56073b 528
AnnaBridge 143:86740a56073b 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 143:86740a56073b 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 143:86740a56073b 531
AnnaBridge 143:86740a56073b 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 143:86740a56073b 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 143:86740a56073b 534
AnnaBridge 143:86740a56073b 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 143:86740a56073b 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 143:86740a56073b 537
AnnaBridge 143:86740a56073b 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 143:86740a56073b 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 143:86740a56073b 540
AnnaBridge 143:86740a56073b 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 143:86740a56073b 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 143:86740a56073b 543
AnnaBridge 143:86740a56073b 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 143:86740a56073b 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 143:86740a56073b 546
AnnaBridge 143:86740a56073b 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 143:86740a56073b 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 143:86740a56073b 549
AnnaBridge 143:86740a56073b 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 143:86740a56073b 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 143:86740a56073b 552
AnnaBridge 143:86740a56073b 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 143:86740a56073b 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 143:86740a56073b 555
AnnaBridge 143:86740a56073b 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 143:86740a56073b 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 143:86740a56073b 558
AnnaBridge 143:86740a56073b 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 143:86740a56073b 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 143:86740a56073b 561
AnnaBridge 143:86740a56073b 562 /* SCB Configurable Fault Status Registers Definitions */
AnnaBridge 143:86740a56073b 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 143:86740a56073b 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 143:86740a56073b 565
AnnaBridge 143:86740a56073b 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 143:86740a56073b 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 143:86740a56073b 568
AnnaBridge 143:86740a56073b 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 143:86740a56073b 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 143:86740a56073b 571
AnnaBridge 143:86740a56073b 572 /* SCB Hard Fault Status Registers Definitions */
AnnaBridge 143:86740a56073b 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 143:86740a56073b 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 143:86740a56073b 575
AnnaBridge 143:86740a56073b 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
AnnaBridge 143:86740a56073b 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 143:86740a56073b 578
AnnaBridge 143:86740a56073b 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 143:86740a56073b 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 143:86740a56073b 581
AnnaBridge 143:86740a56073b 582 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 143:86740a56073b 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 143:86740a56073b 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 143:86740a56073b 585
AnnaBridge 143:86740a56073b 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
AnnaBridge 143:86740a56073b 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 143:86740a56073b 588
AnnaBridge 143:86740a56073b 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 143:86740a56073b 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 143:86740a56073b 591
AnnaBridge 143:86740a56073b 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
AnnaBridge 143:86740a56073b 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 143:86740a56073b 594
AnnaBridge 143:86740a56073b 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
AnnaBridge 143:86740a56073b 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 143:86740a56073b 597
AnnaBridge 143:86740a56073b 598 /*@} end of group CMSIS_SCB */
AnnaBridge 143:86740a56073b 599
AnnaBridge 143:86740a56073b 600
AnnaBridge 143:86740a56073b 601 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 143:86740a56073b 603 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 143:86740a56073b 604 @{
AnnaBridge 143:86740a56073b 605 */
AnnaBridge 143:86740a56073b 606
AnnaBridge 143:86740a56073b 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 143:86740a56073b 608 */
AnnaBridge 143:86740a56073b 609 typedef struct
AnnaBridge 143:86740a56073b 610 {
AnnaBridge 143:86740a56073b 611 uint32_t RESERVED0[1];
AnnaBridge 143:86740a56073b 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 143:86740a56073b 613 uint32_t RESERVED1[1];
AnnaBridge 143:86740a56073b 614 } SCnSCB_Type;
AnnaBridge 143:86740a56073b 615
AnnaBridge 143:86740a56073b 616 /* Interrupt Controller Type Register Definitions */
AnnaBridge 143:86740a56073b 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
AnnaBridge 143:86740a56073b 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 143:86740a56073b 619
AnnaBridge 143:86740a56073b 620 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 143:86740a56073b 621
AnnaBridge 143:86740a56073b 622
AnnaBridge 143:86740a56073b 623 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 143:86740a56073b 625 \brief Type definitions for the System Timer Registers.
AnnaBridge 143:86740a56073b 626 @{
AnnaBridge 143:86740a56073b 627 */
AnnaBridge 143:86740a56073b 628
AnnaBridge 143:86740a56073b 629 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 143:86740a56073b 630 */
AnnaBridge 143:86740a56073b 631 typedef struct
AnnaBridge 143:86740a56073b 632 {
AnnaBridge 143:86740a56073b 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 143:86740a56073b 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 143:86740a56073b 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 143:86740a56073b 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 143:86740a56073b 637 } SysTick_Type;
AnnaBridge 143:86740a56073b 638
AnnaBridge 143:86740a56073b 639 /* SysTick Control / Status Register Definitions */
AnnaBridge 143:86740a56073b 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 143:86740a56073b 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 143:86740a56073b 642
AnnaBridge 143:86740a56073b 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 143:86740a56073b 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 143:86740a56073b 645
AnnaBridge 143:86740a56073b 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 143:86740a56073b 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 143:86740a56073b 648
AnnaBridge 143:86740a56073b 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 143:86740a56073b 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 143:86740a56073b 651
AnnaBridge 143:86740a56073b 652 /* SysTick Reload Register Definitions */
AnnaBridge 143:86740a56073b 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 143:86740a56073b 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 143:86740a56073b 655
AnnaBridge 143:86740a56073b 656 /* SysTick Current Register Definitions */
AnnaBridge 143:86740a56073b 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 143:86740a56073b 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 143:86740a56073b 659
AnnaBridge 143:86740a56073b 660 /* SysTick Calibration Register Definitions */
AnnaBridge 143:86740a56073b 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 143:86740a56073b 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 143:86740a56073b 663
AnnaBridge 143:86740a56073b 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 143:86740a56073b 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 143:86740a56073b 666
AnnaBridge 143:86740a56073b 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 143:86740a56073b 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 143:86740a56073b 669
AnnaBridge 143:86740a56073b 670 /*@} end of group CMSIS_SysTick */
AnnaBridge 143:86740a56073b 671
AnnaBridge 143:86740a56073b 672
AnnaBridge 143:86740a56073b 673 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 143:86740a56073b 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 143:86740a56073b 676 @{
AnnaBridge 143:86740a56073b 677 */
AnnaBridge 143:86740a56073b 678
AnnaBridge 143:86740a56073b 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 143:86740a56073b 680 */
AnnaBridge 143:86740a56073b 681 typedef struct
AnnaBridge 143:86740a56073b 682 {
AnnaBridge 143:86740a56073b 683 __O union
AnnaBridge 143:86740a56073b 684 {
AnnaBridge 143:86740a56073b 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 143:86740a56073b 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 143:86740a56073b 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 143:86740a56073b 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 143:86740a56073b 689 uint32_t RESERVED0[864];
AnnaBridge 143:86740a56073b 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 143:86740a56073b 691 uint32_t RESERVED1[15];
AnnaBridge 143:86740a56073b 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 143:86740a56073b 693 uint32_t RESERVED2[15];
AnnaBridge 143:86740a56073b 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 143:86740a56073b 695 uint32_t RESERVED3[29];
AnnaBridge 143:86740a56073b 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 143:86740a56073b 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 143:86740a56073b 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 143:86740a56073b 699 uint32_t RESERVED4[43];
AnnaBridge 143:86740a56073b 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 143:86740a56073b 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 143:86740a56073b 702 uint32_t RESERVED5[6];
AnnaBridge 143:86740a56073b 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 143:86740a56073b 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 143:86740a56073b 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 143:86740a56073b 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 143:86740a56073b 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 143:86740a56073b 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 143:86740a56073b 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 143:86740a56073b 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 143:86740a56073b 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 143:86740a56073b 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 143:86740a56073b 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 143:86740a56073b 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 143:86740a56073b 715 } ITM_Type;
AnnaBridge 143:86740a56073b 716
AnnaBridge 143:86740a56073b 717 /* ITM Trace Privilege Register Definitions */
AnnaBridge 143:86740a56073b 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 143:86740a56073b 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 143:86740a56073b 720
AnnaBridge 143:86740a56073b 721 /* ITM Trace Control Register Definitions */
AnnaBridge 143:86740a56073b 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
AnnaBridge 143:86740a56073b 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 143:86740a56073b 724
AnnaBridge 143:86740a56073b 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
AnnaBridge 143:86740a56073b 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 143:86740a56073b 727
AnnaBridge 143:86740a56073b 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 143:86740a56073b 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 143:86740a56073b 730
AnnaBridge 143:86740a56073b 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
AnnaBridge 143:86740a56073b 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 143:86740a56073b 733
AnnaBridge 143:86740a56073b 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
AnnaBridge 143:86740a56073b 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 143:86740a56073b 736
AnnaBridge 143:86740a56073b 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
AnnaBridge 143:86740a56073b 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 143:86740a56073b 739
AnnaBridge 143:86740a56073b 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
AnnaBridge 143:86740a56073b 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 143:86740a56073b 742
AnnaBridge 143:86740a56073b 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
AnnaBridge 143:86740a56073b 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 143:86740a56073b 745
AnnaBridge 143:86740a56073b 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 143:86740a56073b 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 143:86740a56073b 748
AnnaBridge 143:86740a56073b 749 /* ITM Integration Write Register Definitions */
AnnaBridge 143:86740a56073b 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 143:86740a56073b 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 143:86740a56073b 752
AnnaBridge 143:86740a56073b 753 /* ITM Integration Read Register Definitions */
AnnaBridge 143:86740a56073b 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
AnnaBridge 143:86740a56073b 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 143:86740a56073b 756
AnnaBridge 143:86740a56073b 757 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 143:86740a56073b 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 143:86740a56073b 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 143:86740a56073b 760
AnnaBridge 143:86740a56073b 761 /* ITM Lock Status Register Definitions */
AnnaBridge 143:86740a56073b 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
AnnaBridge 143:86740a56073b 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 143:86740a56073b 764
AnnaBridge 143:86740a56073b 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
AnnaBridge 143:86740a56073b 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 143:86740a56073b 767
AnnaBridge 143:86740a56073b 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
AnnaBridge 143:86740a56073b 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 143:86740a56073b 770
AnnaBridge 143:86740a56073b 771 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 143:86740a56073b 772
AnnaBridge 143:86740a56073b 773
AnnaBridge 143:86740a56073b 774 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 143:86740a56073b 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 143:86740a56073b 777 @{
AnnaBridge 143:86740a56073b 778 */
AnnaBridge 143:86740a56073b 779
AnnaBridge 143:86740a56073b 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 143:86740a56073b 781 */
AnnaBridge 143:86740a56073b 782 typedef struct
AnnaBridge 143:86740a56073b 783 {
AnnaBridge 143:86740a56073b 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 143:86740a56073b 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 143:86740a56073b 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 143:86740a56073b 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 143:86740a56073b 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 143:86740a56073b 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 143:86740a56073b 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 143:86740a56073b 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 143:86740a56073b 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 143:86740a56073b 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 143:86740a56073b 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 143:86740a56073b 795 uint32_t RESERVED0[1];
AnnaBridge 143:86740a56073b 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 143:86740a56073b 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 143:86740a56073b 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 143:86740a56073b 799 uint32_t RESERVED1[1];
AnnaBridge 143:86740a56073b 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 143:86740a56073b 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 143:86740a56073b 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 143:86740a56073b 803 uint32_t RESERVED2[1];
AnnaBridge 143:86740a56073b 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 143:86740a56073b 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 143:86740a56073b 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 143:86740a56073b 807 } DWT_Type;
AnnaBridge 143:86740a56073b 808
AnnaBridge 143:86740a56073b 809 /* DWT Control Register Definitions */
AnnaBridge 143:86740a56073b 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 143:86740a56073b 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 143:86740a56073b 812
AnnaBridge 143:86740a56073b 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 143:86740a56073b 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 143:86740a56073b 815
AnnaBridge 143:86740a56073b 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 143:86740a56073b 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 143:86740a56073b 818
AnnaBridge 143:86740a56073b 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 143:86740a56073b 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 143:86740a56073b 821
AnnaBridge 143:86740a56073b 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 143:86740a56073b 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 143:86740a56073b 824
AnnaBridge 143:86740a56073b 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 143:86740a56073b 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 143:86740a56073b 827
AnnaBridge 143:86740a56073b 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 143:86740a56073b 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 143:86740a56073b 830
AnnaBridge 143:86740a56073b 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 143:86740a56073b 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 143:86740a56073b 833
AnnaBridge 143:86740a56073b 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 143:86740a56073b 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 143:86740a56073b 836
AnnaBridge 143:86740a56073b 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 143:86740a56073b 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 143:86740a56073b 839
AnnaBridge 143:86740a56073b 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 143:86740a56073b 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 143:86740a56073b 842
AnnaBridge 143:86740a56073b 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 143:86740a56073b 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 143:86740a56073b 845
AnnaBridge 143:86740a56073b 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 143:86740a56073b 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 143:86740a56073b 848
AnnaBridge 143:86740a56073b 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 143:86740a56073b 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 143:86740a56073b 851
AnnaBridge 143:86740a56073b 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 143:86740a56073b 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 143:86740a56073b 854
AnnaBridge 143:86740a56073b 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 143:86740a56073b 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 143:86740a56073b 857
AnnaBridge 143:86740a56073b 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 143:86740a56073b 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 143:86740a56073b 860
AnnaBridge 143:86740a56073b 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 143:86740a56073b 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 143:86740a56073b 863
AnnaBridge 143:86740a56073b 864 /* DWT CPI Count Register Definitions */
AnnaBridge 143:86740a56073b 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 143:86740a56073b 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 143:86740a56073b 867
AnnaBridge 143:86740a56073b 868 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 143:86740a56073b 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 143:86740a56073b 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 143:86740a56073b 871
AnnaBridge 143:86740a56073b 872 /* DWT Sleep Count Register Definitions */
AnnaBridge 143:86740a56073b 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 143:86740a56073b 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 143:86740a56073b 875
AnnaBridge 143:86740a56073b 876 /* DWT LSU Count Register Definitions */
AnnaBridge 143:86740a56073b 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 143:86740a56073b 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 143:86740a56073b 879
AnnaBridge 143:86740a56073b 880 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 143:86740a56073b 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 143:86740a56073b 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 143:86740a56073b 883
AnnaBridge 143:86740a56073b 884 /* DWT Comparator Mask Register Definitions */
AnnaBridge 143:86740a56073b 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
AnnaBridge 143:86740a56073b 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 143:86740a56073b 887
AnnaBridge 143:86740a56073b 888 /* DWT Comparator Function Register Definitions */
AnnaBridge 143:86740a56073b 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 143:86740a56073b 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 143:86740a56073b 891
AnnaBridge 143:86740a56073b 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 143:86740a56073b 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 143:86740a56073b 894
AnnaBridge 143:86740a56073b 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 143:86740a56073b 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 143:86740a56073b 897
AnnaBridge 143:86740a56073b 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 143:86740a56073b 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 143:86740a56073b 900
AnnaBridge 143:86740a56073b 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 143:86740a56073b 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 143:86740a56073b 903
AnnaBridge 143:86740a56073b 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 143:86740a56073b 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 143:86740a56073b 906
AnnaBridge 143:86740a56073b 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 143:86740a56073b 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 143:86740a56073b 909
AnnaBridge 143:86740a56073b 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 143:86740a56073b 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 143:86740a56073b 912
AnnaBridge 143:86740a56073b 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 143:86740a56073b 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 143:86740a56073b 915
AnnaBridge 143:86740a56073b 916 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 143:86740a56073b 917
AnnaBridge 143:86740a56073b 918
AnnaBridge 143:86740a56073b 919 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 143:86740a56073b 921 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 143:86740a56073b 922 @{
AnnaBridge 143:86740a56073b 923 */
AnnaBridge 143:86740a56073b 924
AnnaBridge 143:86740a56073b 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 143:86740a56073b 926 */
AnnaBridge 143:86740a56073b 927 typedef struct
AnnaBridge 143:86740a56073b 928 {
AnnaBridge 143:86740a56073b 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 143:86740a56073b 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 143:86740a56073b 931 uint32_t RESERVED0[2];
AnnaBridge 143:86740a56073b 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 143:86740a56073b 933 uint32_t RESERVED1[55];
AnnaBridge 143:86740a56073b 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 143:86740a56073b 935 uint32_t RESERVED2[131];
AnnaBridge 143:86740a56073b 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 143:86740a56073b 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 143:86740a56073b 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 143:86740a56073b 939 uint32_t RESERVED3[759];
AnnaBridge 143:86740a56073b 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 143:86740a56073b 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 143:86740a56073b 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 143:86740a56073b 943 uint32_t RESERVED4[1];
AnnaBridge 143:86740a56073b 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 143:86740a56073b 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 143:86740a56073b 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 143:86740a56073b 947 uint32_t RESERVED5[39];
AnnaBridge 143:86740a56073b 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 143:86740a56073b 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 143:86740a56073b 950 uint32_t RESERVED7[8];
AnnaBridge 143:86740a56073b 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 143:86740a56073b 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 143:86740a56073b 953 } TPI_Type;
AnnaBridge 143:86740a56073b 954
AnnaBridge 143:86740a56073b 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 143:86740a56073b 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 143:86740a56073b 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 143:86740a56073b 958
AnnaBridge 143:86740a56073b 959 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 143:86740a56073b 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
AnnaBridge 143:86740a56073b 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 143:86740a56073b 962
AnnaBridge 143:86740a56073b 963 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 143:86740a56073b 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 143:86740a56073b 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 143:86740a56073b 966
AnnaBridge 143:86740a56073b 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
AnnaBridge 143:86740a56073b 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 143:86740a56073b 969
AnnaBridge 143:86740a56073b 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
AnnaBridge 143:86740a56073b 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 143:86740a56073b 972
AnnaBridge 143:86740a56073b 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
AnnaBridge 143:86740a56073b 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 143:86740a56073b 975
AnnaBridge 143:86740a56073b 976 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 143:86740a56073b 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
AnnaBridge 143:86740a56073b 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 143:86740a56073b 979
AnnaBridge 143:86740a56073b 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
AnnaBridge 143:86740a56073b 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 143:86740a56073b 982
AnnaBridge 143:86740a56073b 983 /* TPI TRIGGER Register Definitions */
AnnaBridge 143:86740a56073b 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 143:86740a56073b 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 143:86740a56073b 986
AnnaBridge 143:86740a56073b 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 143:86740a56073b 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 143:86740a56073b 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 143:86740a56073b 990
AnnaBridge 143:86740a56073b 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 143:86740a56073b 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 143:86740a56073b 993
AnnaBridge 143:86740a56073b 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 143:86740a56073b 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 143:86740a56073b 996
AnnaBridge 143:86740a56073b 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 143:86740a56073b 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 143:86740a56073b 999
AnnaBridge 143:86740a56073b 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 143:86740a56073b 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 143:86740a56073b 1002
AnnaBridge 143:86740a56073b 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 143:86740a56073b 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 143:86740a56073b 1005
AnnaBridge 143:86740a56073b 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 143:86740a56073b 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 143:86740a56073b 1008
AnnaBridge 143:86740a56073b 1009 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 143:86740a56073b 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 143:86740a56073b 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 143:86740a56073b 1012
AnnaBridge 143:86740a56073b 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 143:86740a56073b 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 143:86740a56073b 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 143:86740a56073b 1016
AnnaBridge 143:86740a56073b 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 143:86740a56073b 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 143:86740a56073b 1019
AnnaBridge 143:86740a56073b 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 143:86740a56073b 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 143:86740a56073b 1022
AnnaBridge 143:86740a56073b 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 143:86740a56073b 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 143:86740a56073b 1025
AnnaBridge 143:86740a56073b 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 143:86740a56073b 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 143:86740a56073b 1028
AnnaBridge 143:86740a56073b 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 143:86740a56073b 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 143:86740a56073b 1031
AnnaBridge 143:86740a56073b 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 143:86740a56073b 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 143:86740a56073b 1034
AnnaBridge 143:86740a56073b 1035 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 143:86740a56073b 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 143:86740a56073b 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 143:86740a56073b 1038
AnnaBridge 143:86740a56073b 1039 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 143:86740a56073b 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
AnnaBridge 143:86740a56073b 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 143:86740a56073b 1042
AnnaBridge 143:86740a56073b 1043 /* TPI DEVID Register Definitions */
AnnaBridge 143:86740a56073b 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 143:86740a56073b 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 143:86740a56073b 1046
AnnaBridge 143:86740a56073b 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 143:86740a56073b 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 143:86740a56073b 1049
AnnaBridge 143:86740a56073b 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 143:86740a56073b 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 143:86740a56073b 1052
AnnaBridge 143:86740a56073b 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 143:86740a56073b 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 143:86740a56073b 1055
AnnaBridge 143:86740a56073b 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 143:86740a56073b 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 143:86740a56073b 1058
AnnaBridge 143:86740a56073b 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 143:86740a56073b 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 143:86740a56073b 1061
AnnaBridge 143:86740a56073b 1062 /* TPI DEVTYPE Register Definitions */
AnnaBridge 143:86740a56073b 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 143:86740a56073b 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 143:86740a56073b 1065
AnnaBridge 143:86740a56073b 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 143:86740a56073b 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 143:86740a56073b 1068
AnnaBridge 143:86740a56073b 1069 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 143:86740a56073b 1070
AnnaBridge 143:86740a56073b 1071
AnnaBridge 143:86740a56073b 1072 #if (__MPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 1073 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 143:86740a56073b 1075 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 143:86740a56073b 1076 @{
AnnaBridge 143:86740a56073b 1077 */
AnnaBridge 143:86740a56073b 1078
AnnaBridge 143:86740a56073b 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 143:86740a56073b 1080 */
AnnaBridge 143:86740a56073b 1081 typedef struct
AnnaBridge 143:86740a56073b 1082 {
AnnaBridge 143:86740a56073b 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 143:86740a56073b 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 143:86740a56073b 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 143:86740a56073b 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 143:86740a56073b 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 143:86740a56073b 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 143:86740a56073b 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 143:86740a56073b 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 1094 } MPU_Type;
AnnaBridge 143:86740a56073b 1095
AnnaBridge 143:86740a56073b 1096 /* MPU Type Register */
AnnaBridge 143:86740a56073b 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
AnnaBridge 143:86740a56073b 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 143:86740a56073b 1099
AnnaBridge 143:86740a56073b 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
AnnaBridge 143:86740a56073b 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 143:86740a56073b 1102
AnnaBridge 143:86740a56073b 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 143:86740a56073b 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 143:86740a56073b 1105
AnnaBridge 143:86740a56073b 1106 /* MPU Control Register */
AnnaBridge 143:86740a56073b 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 143:86740a56073b 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 143:86740a56073b 1109
AnnaBridge 143:86740a56073b 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 143:86740a56073b 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 143:86740a56073b 1112
AnnaBridge 143:86740a56073b 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
AnnaBridge 143:86740a56073b 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 143:86740a56073b 1115
AnnaBridge 143:86740a56073b 1116 /* MPU Region Number Register */
AnnaBridge 143:86740a56073b 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
AnnaBridge 143:86740a56073b 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 143:86740a56073b 1119
AnnaBridge 143:86740a56073b 1120 /* MPU Region Base Address Register */
AnnaBridge 143:86740a56073b 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
AnnaBridge 143:86740a56073b 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 143:86740a56073b 1123
AnnaBridge 143:86740a56073b 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
AnnaBridge 143:86740a56073b 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 143:86740a56073b 1126
AnnaBridge 143:86740a56073b 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
AnnaBridge 143:86740a56073b 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 143:86740a56073b 1129
AnnaBridge 143:86740a56073b 1130 /* MPU Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 143:86740a56073b 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 143:86740a56073b 1133
AnnaBridge 143:86740a56073b 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 143:86740a56073b 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 143:86740a56073b 1136
AnnaBridge 143:86740a56073b 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 143:86740a56073b 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 143:86740a56073b 1139
AnnaBridge 143:86740a56073b 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 143:86740a56073b 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 143:86740a56073b 1142
AnnaBridge 143:86740a56073b 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 143:86740a56073b 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 143:86740a56073b 1145
AnnaBridge 143:86740a56073b 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 143:86740a56073b 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 143:86740a56073b 1148
AnnaBridge 143:86740a56073b 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 143:86740a56073b 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 143:86740a56073b 1151
AnnaBridge 143:86740a56073b 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 143:86740a56073b 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 143:86740a56073b 1154
AnnaBridge 143:86740a56073b 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
AnnaBridge 143:86740a56073b 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 143:86740a56073b 1157
AnnaBridge 143:86740a56073b 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
AnnaBridge 143:86740a56073b 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 143:86740a56073b 1160
AnnaBridge 143:86740a56073b 1161 /*@} end of group CMSIS_MPU */
AnnaBridge 143:86740a56073b 1162 #endif
AnnaBridge 143:86740a56073b 1163
AnnaBridge 143:86740a56073b 1164
AnnaBridge 143:86740a56073b 1165 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 143:86740a56073b 1167 \brief Type definitions for the Core Debug Registers
AnnaBridge 143:86740a56073b 1168 @{
AnnaBridge 143:86740a56073b 1169 */
AnnaBridge 143:86740a56073b 1170
AnnaBridge 143:86740a56073b 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 143:86740a56073b 1172 */
AnnaBridge 143:86740a56073b 1173 typedef struct
AnnaBridge 143:86740a56073b 1174 {
AnnaBridge 143:86740a56073b 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 143:86740a56073b 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 143:86740a56073b 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 143:86740a56073b 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 143:86740a56073b 1179 } CoreDebug_Type;
AnnaBridge 143:86740a56073b 1180
AnnaBridge 143:86740a56073b 1181 /* Debug Halting Control and Status Register */
AnnaBridge 143:86740a56073b 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 143:86740a56073b 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 143:86740a56073b 1184
AnnaBridge 143:86740a56073b 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 143:86740a56073b 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 143:86740a56073b 1187
AnnaBridge 143:86740a56073b 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 143:86740a56073b 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 143:86740a56073b 1190
AnnaBridge 143:86740a56073b 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 143:86740a56073b 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 143:86740a56073b 1193
AnnaBridge 143:86740a56073b 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 143:86740a56073b 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 143:86740a56073b 1196
AnnaBridge 143:86740a56073b 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 143:86740a56073b 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 143:86740a56073b 1199
AnnaBridge 143:86740a56073b 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 143:86740a56073b 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 143:86740a56073b 1202
AnnaBridge 143:86740a56073b 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 143:86740a56073b 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 143:86740a56073b 1205
AnnaBridge 143:86740a56073b 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 143:86740a56073b 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 143:86740a56073b 1208
AnnaBridge 143:86740a56073b 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 143:86740a56073b 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 143:86740a56073b 1211
AnnaBridge 143:86740a56073b 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 143:86740a56073b 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 143:86740a56073b 1214
AnnaBridge 143:86740a56073b 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 143:86740a56073b 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 143:86740a56073b 1217
AnnaBridge 143:86740a56073b 1218 /* Debug Core Register Selector Register */
AnnaBridge 143:86740a56073b 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 143:86740a56073b 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 143:86740a56073b 1221
AnnaBridge 143:86740a56073b 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 143:86740a56073b 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 143:86740a56073b 1224
AnnaBridge 143:86740a56073b 1225 /* Debug Exception and Monitor Control Register */
AnnaBridge 143:86740a56073b 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 143:86740a56073b 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 143:86740a56073b 1228
AnnaBridge 143:86740a56073b 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 143:86740a56073b 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 143:86740a56073b 1231
AnnaBridge 143:86740a56073b 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 143:86740a56073b 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 143:86740a56073b 1234
AnnaBridge 143:86740a56073b 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 143:86740a56073b 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 143:86740a56073b 1237
AnnaBridge 143:86740a56073b 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 143:86740a56073b 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 143:86740a56073b 1240
AnnaBridge 143:86740a56073b 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 143:86740a56073b 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 143:86740a56073b 1243
AnnaBridge 143:86740a56073b 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 143:86740a56073b 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 143:86740a56073b 1246
AnnaBridge 143:86740a56073b 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 143:86740a56073b 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 143:86740a56073b 1249
AnnaBridge 143:86740a56073b 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 143:86740a56073b 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 143:86740a56073b 1252
AnnaBridge 143:86740a56073b 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 143:86740a56073b 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 143:86740a56073b 1255
AnnaBridge 143:86740a56073b 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 143:86740a56073b 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 143:86740a56073b 1258
AnnaBridge 143:86740a56073b 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 143:86740a56073b 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 143:86740a56073b 1261
AnnaBridge 143:86740a56073b 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 143:86740a56073b 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 143:86740a56073b 1264
AnnaBridge 143:86740a56073b 1265 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 143:86740a56073b 1266
AnnaBridge 143:86740a56073b 1267
AnnaBridge 143:86740a56073b 1268 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 1269 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 143:86740a56073b 1270 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 143:86740a56073b 1271 @{
AnnaBridge 143:86740a56073b 1272 */
AnnaBridge 143:86740a56073b 1273
AnnaBridge 143:86740a56073b 1274 /* Memory mapping of Cortex-M3 Hardware */
AnnaBridge 143:86740a56073b 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 143:86740a56073b 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 143:86740a56073b 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 143:86740a56073b 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 143:86740a56073b 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 143:86740a56073b 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 143:86740a56073b 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 143:86740a56073b 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 143:86740a56073b 1283
AnnaBridge 143:86740a56073b 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 143:86740a56073b 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 143:86740a56073b 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 143:86740a56073b 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 143:86740a56073b 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 143:86740a56073b 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 143:86740a56073b 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 143:86740a56073b 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 143:86740a56073b 1292
AnnaBridge 143:86740a56073b 1293 #if (__MPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 143:86740a56073b 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 143:86740a56073b 1296 #endif
AnnaBridge 143:86740a56073b 1297
AnnaBridge 143:86740a56073b 1298 /*@} */
AnnaBridge 143:86740a56073b 1299
AnnaBridge 143:86740a56073b 1300
AnnaBridge 143:86740a56073b 1301
AnnaBridge 143:86740a56073b 1302 /*******************************************************************************
AnnaBridge 143:86740a56073b 1303 * Hardware Abstraction Layer
AnnaBridge 143:86740a56073b 1304 Core Function Interface contains:
AnnaBridge 143:86740a56073b 1305 - Core NVIC Functions
AnnaBridge 143:86740a56073b 1306 - Core SysTick Functions
AnnaBridge 143:86740a56073b 1307 - Core Debug Functions
AnnaBridge 143:86740a56073b 1308 - Core Register Access Functions
AnnaBridge 143:86740a56073b 1309 ******************************************************************************/
AnnaBridge 143:86740a56073b 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 143:86740a56073b 1311 */
AnnaBridge 143:86740a56073b 1312
AnnaBridge 143:86740a56073b 1313
AnnaBridge 143:86740a56073b 1314
AnnaBridge 143:86740a56073b 1315 /* ########################## NVIC functions #################################### */
AnnaBridge 143:86740a56073b 1316 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 143:86740a56073b 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 143:86740a56073b 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 143:86740a56073b 1319 @{
AnnaBridge 143:86740a56073b 1320 */
AnnaBridge 143:86740a56073b 1321
AnnaBridge 143:86740a56073b 1322 /** \brief Set Priority Grouping
AnnaBridge 143:86740a56073b 1323
AnnaBridge 143:86740a56073b 1324 The function sets the priority grouping field using the required unlock sequence.
AnnaBridge 143:86740a56073b 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 143:86740a56073b 1326 Only values from 0..7 are used.
AnnaBridge 143:86740a56073b 1327 In case of a conflict between priority grouping and available
AnnaBridge 143:86740a56073b 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 143:86740a56073b 1329
AnnaBridge 143:86740a56073b 1330 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 143:86740a56073b 1331 */
AnnaBridge 143:86740a56073b 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 143:86740a56073b 1333 {
AnnaBridge 143:86740a56073b 1334 uint32_t reg_value;
AnnaBridge 143:86740a56073b 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 143:86740a56073b 1336
AnnaBridge 143:86740a56073b 1337 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 143:86740a56073b 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 143:86740a56073b 1339 reg_value = (reg_value |
AnnaBridge 143:86740a56073b 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 143:86740a56073b 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
AnnaBridge 143:86740a56073b 1342 SCB->AIRCR = reg_value;
AnnaBridge 143:86740a56073b 1343 }
AnnaBridge 143:86740a56073b 1344
AnnaBridge 143:86740a56073b 1345
AnnaBridge 143:86740a56073b 1346 /** \brief Get Priority Grouping
AnnaBridge 143:86740a56073b 1347
AnnaBridge 143:86740a56073b 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 143:86740a56073b 1349
AnnaBridge 143:86740a56073b 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 143:86740a56073b 1351 */
AnnaBridge 143:86740a56073b 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
AnnaBridge 143:86740a56073b 1353 {
AnnaBridge 143:86740a56073b 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 143:86740a56073b 1355 }
AnnaBridge 143:86740a56073b 1356
AnnaBridge 143:86740a56073b 1357
AnnaBridge 143:86740a56073b 1358 /** \brief Enable External Interrupt
AnnaBridge 143:86740a56073b 1359
AnnaBridge 143:86740a56073b 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 143:86740a56073b 1361
AnnaBridge 143:86740a56073b 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 1363 */
AnnaBridge 143:86740a56073b 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1365 {
AnnaBridge 143:86740a56073b 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 1367 }
AnnaBridge 143:86740a56073b 1368
AnnaBridge 143:86740a56073b 1369
AnnaBridge 143:86740a56073b 1370 /** \brief Disable External Interrupt
AnnaBridge 143:86740a56073b 1371
AnnaBridge 143:86740a56073b 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 143:86740a56073b 1373
AnnaBridge 143:86740a56073b 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 1375 */
AnnaBridge 143:86740a56073b 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1377 {
AnnaBridge 143:86740a56073b 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 1379 __DSB();
AnnaBridge 143:86740a56073b 1380 __ISB();
AnnaBridge 143:86740a56073b 1381 }
AnnaBridge 143:86740a56073b 1382
AnnaBridge 143:86740a56073b 1383
AnnaBridge 143:86740a56073b 1384 /** \brief Get Pending Interrupt
AnnaBridge 143:86740a56073b 1385
AnnaBridge 143:86740a56073b 1386 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 143:86740a56073b 1387 for the specified interrupt.
AnnaBridge 143:86740a56073b 1388
AnnaBridge 143:86740a56073b 1389 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 1390
AnnaBridge 143:86740a56073b 1391 \return 0 Interrupt status is not pending.
AnnaBridge 143:86740a56073b 1392 \return 1 Interrupt status is pending.
AnnaBridge 143:86740a56073b 1393 */
AnnaBridge 143:86740a56073b 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1395 {
AnnaBridge 143:86740a56073b 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 143:86740a56073b 1397 }
AnnaBridge 143:86740a56073b 1398
AnnaBridge 143:86740a56073b 1399
AnnaBridge 143:86740a56073b 1400 /** \brief Set Pending Interrupt
AnnaBridge 143:86740a56073b 1401
AnnaBridge 143:86740a56073b 1402 The function sets the pending bit of an external interrupt.
AnnaBridge 143:86740a56073b 1403
AnnaBridge 143:86740a56073b 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 1405 */
AnnaBridge 143:86740a56073b 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1407 {
AnnaBridge 143:86740a56073b 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 1409 }
AnnaBridge 143:86740a56073b 1410
AnnaBridge 143:86740a56073b 1411
AnnaBridge 143:86740a56073b 1412 /** \brief Clear Pending Interrupt
AnnaBridge 143:86740a56073b 1413
AnnaBridge 143:86740a56073b 1414 The function clears the pending bit of an external interrupt.
AnnaBridge 143:86740a56073b 1415
AnnaBridge 143:86740a56073b 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 1417 */
AnnaBridge 143:86740a56073b 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1419 {
AnnaBridge 143:86740a56073b 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 1421 }
AnnaBridge 143:86740a56073b 1422
AnnaBridge 143:86740a56073b 1423
AnnaBridge 143:86740a56073b 1424 /** \brief Get Active Interrupt
AnnaBridge 143:86740a56073b 1425
AnnaBridge 143:86740a56073b 1426 The function reads the active register in NVIC and returns the active bit.
AnnaBridge 143:86740a56073b 1427
AnnaBridge 143:86740a56073b 1428 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 1429
AnnaBridge 143:86740a56073b 1430 \return 0 Interrupt status is not active.
AnnaBridge 143:86740a56073b 1431 \return 1 Interrupt status is active.
AnnaBridge 143:86740a56073b 1432 */
AnnaBridge 143:86740a56073b 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1434 {
AnnaBridge 143:86740a56073b 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 143:86740a56073b 1436 }
AnnaBridge 143:86740a56073b 1437
AnnaBridge 143:86740a56073b 1438
AnnaBridge 143:86740a56073b 1439 /** \brief Set Interrupt Priority
AnnaBridge 143:86740a56073b 1440
AnnaBridge 143:86740a56073b 1441 The function sets the priority of an interrupt.
AnnaBridge 143:86740a56073b 1442
AnnaBridge 143:86740a56073b 1443 \note The priority cannot be set for every core interrupt.
AnnaBridge 143:86740a56073b 1444
AnnaBridge 143:86740a56073b 1445 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 1446 \param [in] priority Priority to set.
AnnaBridge 143:86740a56073b 1447 */
AnnaBridge 143:86740a56073b 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 143:86740a56073b 1449 {
AnnaBridge 143:86740a56073b 1450 if((int32_t)IRQn < 0) {
AnnaBridge 143:86740a56073b 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 143:86740a56073b 1452 }
AnnaBridge 143:86740a56073b 1453 else {
AnnaBridge 143:86740a56073b 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 143:86740a56073b 1455 }
AnnaBridge 143:86740a56073b 1456 }
AnnaBridge 143:86740a56073b 1457
AnnaBridge 143:86740a56073b 1458
AnnaBridge 143:86740a56073b 1459 /** \brief Get Interrupt Priority
AnnaBridge 143:86740a56073b 1460
AnnaBridge 143:86740a56073b 1461 The function reads the priority of an interrupt. The interrupt
AnnaBridge 143:86740a56073b 1462 number can be positive to specify an external (device specific)
AnnaBridge 143:86740a56073b 1463 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 143:86740a56073b 1464
AnnaBridge 143:86740a56073b 1465
AnnaBridge 143:86740a56073b 1466 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 143:86740a56073b 1468 priority bits of the microcontroller.
AnnaBridge 143:86740a56073b 1469 */
AnnaBridge 143:86740a56073b 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 1471 {
AnnaBridge 143:86740a56073b 1472
AnnaBridge 143:86740a56073b 1473 if((int32_t)IRQn < 0) {
AnnaBridge 143:86740a56073b 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 143:86740a56073b 1475 }
AnnaBridge 143:86740a56073b 1476 else {
AnnaBridge 143:86740a56073b 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 143:86740a56073b 1478 }
AnnaBridge 143:86740a56073b 1479 }
AnnaBridge 143:86740a56073b 1480
AnnaBridge 143:86740a56073b 1481
AnnaBridge 143:86740a56073b 1482 /** \brief Encode Priority
AnnaBridge 143:86740a56073b 1483
AnnaBridge 143:86740a56073b 1484 The function encodes the priority for an interrupt with the given priority group,
AnnaBridge 143:86740a56073b 1485 preemptive priority value, and subpriority value.
AnnaBridge 143:86740a56073b 1486 In case of a conflict between priority grouping and available
AnnaBridge 143:86740a56073b 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 143:86740a56073b 1488
AnnaBridge 143:86740a56073b 1489 \param [in] PriorityGroup Used priority group.
AnnaBridge 143:86740a56073b 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 143:86740a56073b 1491 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 143:86740a56073b 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 143:86740a56073b 1493 */
AnnaBridge 143:86740a56073b 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 143:86740a56073b 1495 {
AnnaBridge 143:86740a56073b 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 143:86740a56073b 1497 uint32_t PreemptPriorityBits;
AnnaBridge 143:86740a56073b 1498 uint32_t SubPriorityBits;
AnnaBridge 143:86740a56073b 1499
AnnaBridge 143:86740a56073b 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 143:86740a56073b 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 143:86740a56073b 1502
AnnaBridge 143:86740a56073b 1503 return (
AnnaBridge 143:86740a56073b 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 143:86740a56073b 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 143:86740a56073b 1506 );
AnnaBridge 143:86740a56073b 1507 }
AnnaBridge 143:86740a56073b 1508
AnnaBridge 143:86740a56073b 1509
AnnaBridge 143:86740a56073b 1510 /** \brief Decode Priority
AnnaBridge 143:86740a56073b 1511
AnnaBridge 143:86740a56073b 1512 The function decodes an interrupt priority value with a given priority group to
AnnaBridge 143:86740a56073b 1513 preemptive priority value and subpriority value.
AnnaBridge 143:86740a56073b 1514 In case of a conflict between priority grouping and available
AnnaBridge 143:86740a56073b 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 143:86740a56073b 1516
AnnaBridge 143:86740a56073b 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 143:86740a56073b 1518 \param [in] PriorityGroup Used priority group.
AnnaBridge 143:86740a56073b 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 143:86740a56073b 1520 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 143:86740a56073b 1521 */
AnnaBridge 143:86740a56073b 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
AnnaBridge 143:86740a56073b 1523 {
AnnaBridge 143:86740a56073b 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 143:86740a56073b 1525 uint32_t PreemptPriorityBits;
AnnaBridge 143:86740a56073b 1526 uint32_t SubPriorityBits;
AnnaBridge 143:86740a56073b 1527
AnnaBridge 143:86740a56073b 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 143:86740a56073b 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 143:86740a56073b 1530
AnnaBridge 143:86740a56073b 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 143:86740a56073b 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 143:86740a56073b 1533 }
AnnaBridge 143:86740a56073b 1534
AnnaBridge 143:86740a56073b 1535
AnnaBridge 143:86740a56073b 1536 /** \brief System Reset
AnnaBridge 143:86740a56073b 1537
AnnaBridge 143:86740a56073b 1538 The function initiates a system reset request to reset the MCU.
AnnaBridge 143:86740a56073b 1539 */
AnnaBridge 143:86740a56073b 1540 __STATIC_INLINE void NVIC_SystemReset(void)
AnnaBridge 143:86740a56073b 1541 {
AnnaBridge 143:86740a56073b 1542 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 143:86740a56073b 1543 buffered write are completed before reset */
AnnaBridge 143:86740a56073b 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 143:86740a56073b 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 143:86740a56073b 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 143:86740a56073b 1547 __DSB(); /* Ensure completion of memory access */
AnnaBridge 143:86740a56073b 1548 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 143:86740a56073b 1549 }
AnnaBridge 143:86740a56073b 1550
AnnaBridge 143:86740a56073b 1551 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 143:86740a56073b 1552
AnnaBridge 143:86740a56073b 1553
AnnaBridge 143:86740a56073b 1554
AnnaBridge 143:86740a56073b 1555 /* ################################## SysTick function ############################################ */
AnnaBridge 143:86740a56073b 1556 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 143:86740a56073b 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 143:86740a56073b 1558 \brief Functions that configure the System.
AnnaBridge 143:86740a56073b 1559 @{
AnnaBridge 143:86740a56073b 1560 */
AnnaBridge 143:86740a56073b 1561
AnnaBridge 143:86740a56073b 1562 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 143:86740a56073b 1563
AnnaBridge 143:86740a56073b 1564 /** \brief System Tick Configuration
AnnaBridge 143:86740a56073b 1565
AnnaBridge 143:86740a56073b 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 143:86740a56073b 1567 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 143:86740a56073b 1568
AnnaBridge 143:86740a56073b 1569 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 143:86740a56073b 1570
AnnaBridge 143:86740a56073b 1571 \return 0 Function succeeded.
AnnaBridge 143:86740a56073b 1572 \return 1 Function failed.
AnnaBridge 143:86740a56073b 1573
AnnaBridge 143:86740a56073b 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 143:86740a56073b 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 143:86740a56073b 1576 must contain a vendor-specific implementation of this function.
AnnaBridge 143:86740a56073b 1577
AnnaBridge 143:86740a56073b 1578 */
AnnaBridge 143:86740a56073b 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 143:86740a56073b 1580 {
AnnaBridge 143:86740a56073b 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
AnnaBridge 143:86740a56073b 1582
AnnaBridge 143:86740a56073b 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 143:86740a56073b 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 143:86740a56073b 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 143:86740a56073b 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 143:86740a56073b 1587 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 143:86740a56073b 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 143:86740a56073b 1589 return (0UL); /* Function successful */
AnnaBridge 143:86740a56073b 1590 }
AnnaBridge 143:86740a56073b 1591
AnnaBridge 143:86740a56073b 1592 #endif
AnnaBridge 143:86740a56073b 1593
AnnaBridge 143:86740a56073b 1594 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 143:86740a56073b 1595
AnnaBridge 143:86740a56073b 1596
AnnaBridge 143:86740a56073b 1597
AnnaBridge 143:86740a56073b 1598 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 143:86740a56073b 1599 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 143:86740a56073b 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 143:86740a56073b 1601 \brief Functions that access the ITM debug interface.
AnnaBridge 143:86740a56073b 1602 @{
AnnaBridge 143:86740a56073b 1603 */
AnnaBridge 143:86740a56073b 1604
AnnaBridge 143:86740a56073b 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 143:86740a56073b 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 143:86740a56073b 1607
AnnaBridge 143:86740a56073b 1608
AnnaBridge 143:86740a56073b 1609 /** \brief ITM Send Character
AnnaBridge 143:86740a56073b 1610
AnnaBridge 143:86740a56073b 1611 The function transmits a character via the ITM channel 0, and
AnnaBridge 143:86740a56073b 1612 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 143:86740a56073b 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 143:86740a56073b 1614
AnnaBridge 143:86740a56073b 1615 \param [in] ch Character to transmit.
AnnaBridge 143:86740a56073b 1616
AnnaBridge 143:86740a56073b 1617 \returns Character to transmit.
AnnaBridge 143:86740a56073b 1618 */
AnnaBridge 143:86740a56073b 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 143:86740a56073b 1620 {
AnnaBridge 143:86740a56073b 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 143:86740a56073b 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 143:86740a56073b 1623 {
AnnaBridge 143:86740a56073b 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
AnnaBridge 143:86740a56073b 1625 ITM->PORT[0].u8 = (uint8_t)ch;
AnnaBridge 143:86740a56073b 1626 }
AnnaBridge 143:86740a56073b 1627 return (ch);
AnnaBridge 143:86740a56073b 1628 }
AnnaBridge 143:86740a56073b 1629
AnnaBridge 143:86740a56073b 1630
AnnaBridge 143:86740a56073b 1631 /** \brief ITM Receive Character
AnnaBridge 143:86740a56073b 1632
AnnaBridge 143:86740a56073b 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 143:86740a56073b 1634
AnnaBridge 143:86740a56073b 1635 \return Received character.
AnnaBridge 143:86740a56073b 1636 \return -1 No character pending.
AnnaBridge 143:86740a56073b 1637 */
AnnaBridge 143:86740a56073b 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
AnnaBridge 143:86740a56073b 1639 int32_t ch = -1; /* no character available */
AnnaBridge 143:86740a56073b 1640
AnnaBridge 143:86740a56073b 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
AnnaBridge 143:86740a56073b 1642 ch = ITM_RxBuffer;
AnnaBridge 143:86740a56073b 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 143:86740a56073b 1644 }
AnnaBridge 143:86740a56073b 1645
AnnaBridge 143:86740a56073b 1646 return (ch);
AnnaBridge 143:86740a56073b 1647 }
AnnaBridge 143:86740a56073b 1648
AnnaBridge 143:86740a56073b 1649
AnnaBridge 143:86740a56073b 1650 /** \brief ITM Check Character
AnnaBridge 143:86740a56073b 1651
AnnaBridge 143:86740a56073b 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 143:86740a56073b 1653
AnnaBridge 143:86740a56073b 1654 \return 0 No character available.
AnnaBridge 143:86740a56073b 1655 \return 1 Character available.
AnnaBridge 143:86740a56073b 1656 */
AnnaBridge 143:86740a56073b 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
AnnaBridge 143:86740a56073b 1658
AnnaBridge 143:86740a56073b 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
AnnaBridge 143:86740a56073b 1660 return (0); /* no character available */
AnnaBridge 143:86740a56073b 1661 } else {
AnnaBridge 143:86740a56073b 1662 return (1); /* character available */
AnnaBridge 143:86740a56073b 1663 }
AnnaBridge 143:86740a56073b 1664 }
AnnaBridge 143:86740a56073b 1665
AnnaBridge 143:86740a56073b 1666 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 143:86740a56073b 1667
AnnaBridge 143:86740a56073b 1668
AnnaBridge 143:86740a56073b 1669
AnnaBridge 143:86740a56073b 1670
AnnaBridge 143:86740a56073b 1671 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 1672 }
AnnaBridge 143:86740a56073b 1673 #endif
AnnaBridge 143:86740a56073b 1674
AnnaBridge 143:86740a56073b 1675 #endif /* __CORE_SC300_H_DEPENDANT */
AnnaBridge 143:86740a56073b 1676
AnnaBridge 143:86740a56073b 1677 #endif /* __CMSIS_GENERIC */