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TARGET_DISCO_L072CZ_LRWAN1/core_cm0plus.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Child:
145:64910690c574
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**************************************************************************//**
AnnaBridge 143:86740a56073b 2 * @file core_cm0plus.h
AnnaBridge 143:86740a56073b 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
AnnaBridge 143:86740a56073b 4 * @version V4.10
AnnaBridge 143:86740a56073b 5 * @date 18. March 2015
AnnaBridge 143:86740a56073b 6 *
AnnaBridge 143:86740a56073b 7 * @note
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 ******************************************************************************/
AnnaBridge 143:86740a56073b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 143:86740a56073b 11
AnnaBridge 143:86740a56073b 12 All rights reserved.
AnnaBridge 143:86740a56073b 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 143:86740a56073b 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 15 - Redistributions of source code must retain the above copyright
AnnaBridge 143:86740a56073b 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 143:86740a56073b 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 143:86740a56073b 19 documentation and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 143:86740a56073b 21 to endorse or promote products derived from this software without
AnnaBridge 143:86740a56073b 22 specific prior written permission.
AnnaBridge 143:86740a56073b 23 *
AnnaBridge 143:86740a56073b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 143:86740a56073b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 143:86740a56073b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 143:86740a56073b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 143:86740a56073b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 143:86740a56073b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 143:86740a56073b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 143:86740a56073b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 143:86740a56073b 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 35 ---------------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 36
AnnaBridge 143:86740a56073b 37
AnnaBridge 143:86740a56073b 38 #if defined ( __ICCARM__ )
AnnaBridge 143:86740a56073b 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 143:86740a56073b 40 #endif
AnnaBridge 143:86740a56073b 41
AnnaBridge 143:86740a56073b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
AnnaBridge 143:86740a56073b 43 #define __CORE_CM0PLUS_H_GENERIC
AnnaBridge 143:86740a56073b 44
AnnaBridge 143:86740a56073b 45 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 46 extern "C" {
AnnaBridge 143:86740a56073b 47 #endif
AnnaBridge 143:86740a56073b 48
AnnaBridge 143:86740a56073b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 143:86740a56073b 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 143:86740a56073b 51
AnnaBridge 143:86740a56073b 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 143:86740a56073b 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 143:86740a56073b 54
AnnaBridge 143:86740a56073b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 143:86740a56073b 56 Unions are used for effective representation of core registers.
AnnaBridge 143:86740a56073b 57
AnnaBridge 143:86740a56073b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 143:86740a56073b 59 Function-like macros are used to allow more efficient code.
AnnaBridge 143:86740a56073b 60 */
AnnaBridge 143:86740a56073b 61
AnnaBridge 143:86740a56073b 62
AnnaBridge 143:86740a56073b 63 /*******************************************************************************
AnnaBridge 143:86740a56073b 64 * CMSIS definitions
AnnaBridge 143:86740a56073b 65 ******************************************************************************/
AnnaBridge 143:86740a56073b 66 /** \ingroup Cortex-M0+
AnnaBridge 143:86740a56073b 67 @{
AnnaBridge 143:86740a56073b 68 */
AnnaBridge 143:86740a56073b 69
AnnaBridge 143:86740a56073b 70 /* CMSIS CM0P definitions */
AnnaBridge 143:86740a56073b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 143:86740a56073b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 143:86740a56073b 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 143:86740a56073b 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
AnnaBridge 143:86740a56073b 75
AnnaBridge 143:86740a56073b 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
AnnaBridge 143:86740a56073b 77
AnnaBridge 143:86740a56073b 78
AnnaBridge 143:86740a56073b 79 #if defined ( __CC_ARM )
AnnaBridge 143:86740a56073b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 143:86740a56073b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 143:86740a56073b 82 #define __STATIC_INLINE static __inline
AnnaBridge 143:86740a56073b 83
AnnaBridge 143:86740a56073b 84 #elif defined ( __GNUC__ )
AnnaBridge 143:86740a56073b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 143:86740a56073b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 143:86740a56073b 87 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 88
AnnaBridge 143:86740a56073b 89 #elif defined ( __ICCARM__ )
AnnaBridge 143:86740a56073b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 143:86740a56073b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 143:86740a56073b 92 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 93
AnnaBridge 143:86740a56073b 94 #elif defined ( __TMS470__ )
AnnaBridge 143:86740a56073b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 143:86740a56073b 96 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 97
AnnaBridge 143:86740a56073b 98 #elif defined ( __TASKING__ )
AnnaBridge 143:86740a56073b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 143:86740a56073b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 143:86740a56073b 101 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 102
AnnaBridge 143:86740a56073b 103 #elif defined ( __CSMC__ )
AnnaBridge 143:86740a56073b 104 #define __packed
AnnaBridge 143:86740a56073b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 143:86740a56073b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 143:86740a56073b 107 #define __STATIC_INLINE static inline
AnnaBridge 143:86740a56073b 108
AnnaBridge 143:86740a56073b 109 #endif
AnnaBridge 143:86740a56073b 110
AnnaBridge 143:86740a56073b 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 143:86740a56073b 112 This core does not support an FPU at all
AnnaBridge 143:86740a56073b 113 */
AnnaBridge 143:86740a56073b 114 #define __FPU_USED 0
AnnaBridge 143:86740a56073b 115
AnnaBridge 143:86740a56073b 116 #if defined ( __CC_ARM )
AnnaBridge 143:86740a56073b 117 #if defined __TARGET_FPU_VFP
AnnaBridge 143:86740a56073b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 119 #endif
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 #elif defined ( __GNUC__ )
AnnaBridge 143:86740a56073b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 143:86740a56073b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 124 #endif
AnnaBridge 143:86740a56073b 125
AnnaBridge 143:86740a56073b 126 #elif defined ( __ICCARM__ )
AnnaBridge 143:86740a56073b 127 #if defined __ARMVFP__
AnnaBridge 143:86740a56073b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 129 #endif
AnnaBridge 143:86740a56073b 130
AnnaBridge 143:86740a56073b 131 #elif defined ( __TMS470__ )
AnnaBridge 143:86740a56073b 132 #if defined __TI__VFP_SUPPORT____
AnnaBridge 143:86740a56073b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 134 #endif
AnnaBridge 143:86740a56073b 135
AnnaBridge 143:86740a56073b 136 #elif defined ( __TASKING__ )
AnnaBridge 143:86740a56073b 137 #if defined __FPU_VFP__
AnnaBridge 143:86740a56073b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 139 #endif
AnnaBridge 143:86740a56073b 140
AnnaBridge 143:86740a56073b 141 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 143:86740a56073b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 143:86740a56073b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 143:86740a56073b 144 #endif
AnnaBridge 143:86740a56073b 145 #endif
AnnaBridge 143:86740a56073b 146
AnnaBridge 143:86740a56073b 147 #include <stdint.h> /* standard types definitions */
AnnaBridge 143:86740a56073b 148 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 143:86740a56073b 149 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 143:86740a56073b 150
AnnaBridge 143:86740a56073b 151 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 152 }
AnnaBridge 143:86740a56073b 153 #endif
AnnaBridge 143:86740a56073b 154
AnnaBridge 143:86740a56073b 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
AnnaBridge 143:86740a56073b 156
AnnaBridge 143:86740a56073b 157 #ifndef __CMSIS_GENERIC
AnnaBridge 143:86740a56073b 158
AnnaBridge 143:86740a56073b 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 143:86740a56073b 160 #define __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 143:86740a56073b 161
AnnaBridge 143:86740a56073b 162 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 163 extern "C" {
AnnaBridge 143:86740a56073b 164 #endif
AnnaBridge 143:86740a56073b 165
AnnaBridge 143:86740a56073b 166 /* check device defines and use defaults */
AnnaBridge 143:86740a56073b 167 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 143:86740a56073b 168 #ifndef __CM0PLUS_REV
AnnaBridge 143:86740a56073b 169 #define __CM0PLUS_REV 0x0000
AnnaBridge 143:86740a56073b 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 171 #endif
AnnaBridge 143:86740a56073b 172
AnnaBridge 143:86740a56073b 173 #ifndef __MPU_PRESENT
AnnaBridge 143:86740a56073b 174 #define __MPU_PRESENT 0
AnnaBridge 143:86740a56073b 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 176 #endif
AnnaBridge 143:86740a56073b 177
AnnaBridge 143:86740a56073b 178 #ifndef __VTOR_PRESENT
AnnaBridge 143:86740a56073b 179 #define __VTOR_PRESENT 0
AnnaBridge 143:86740a56073b 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 181 #endif
AnnaBridge 143:86740a56073b 182
AnnaBridge 143:86740a56073b 183 #ifndef __NVIC_PRIO_BITS
AnnaBridge 143:86740a56073b 184 #define __NVIC_PRIO_BITS 2
AnnaBridge 143:86740a56073b 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 186 #endif
AnnaBridge 143:86740a56073b 187
AnnaBridge 143:86740a56073b 188 #ifndef __Vendor_SysTickConfig
AnnaBridge 143:86740a56073b 189 #define __Vendor_SysTickConfig 0
AnnaBridge 143:86740a56073b 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 143:86740a56073b 191 #endif
AnnaBridge 143:86740a56073b 192 #endif
AnnaBridge 143:86740a56073b 193
AnnaBridge 143:86740a56073b 194 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 143:86740a56073b 195 /**
AnnaBridge 143:86740a56073b 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 143:86740a56073b 197
AnnaBridge 143:86740a56073b 198 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 143:86740a56073b 199 \li to specify the access to peripheral variables.
AnnaBridge 143:86740a56073b 200 \li for automatic generation of peripheral register debug information.
AnnaBridge 143:86740a56073b 201 */
AnnaBridge 143:86740a56073b 202 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 203 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 143:86740a56073b 204 #else
AnnaBridge 143:86740a56073b 205 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 143:86740a56073b 206 #endif
AnnaBridge 143:86740a56073b 207 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 143:86740a56073b 208 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 143:86740a56073b 209
AnnaBridge 143:86740a56073b 210 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 211 #define __IM volatile /*!< Defines 'read only' permissions */
AnnaBridge 143:86740a56073b 212 #else
AnnaBridge 143:86740a56073b 213 #define __IM volatile const /*!< Defines 'read only' permissions */
AnnaBridge 143:86740a56073b 214 #endif
AnnaBridge 143:86740a56073b 215 #define __OM volatile /*!< Defines 'write only' permissions */
AnnaBridge 143:86740a56073b 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
AnnaBridge 143:86740a56073b 217
AnnaBridge 143:86740a56073b 218 /*@} end of group Cortex-M0+ */
AnnaBridge 143:86740a56073b 219
AnnaBridge 143:86740a56073b 220
AnnaBridge 143:86740a56073b 221
AnnaBridge 143:86740a56073b 222 /*******************************************************************************
AnnaBridge 143:86740a56073b 223 * Register Abstraction
AnnaBridge 143:86740a56073b 224 Core Register contain:
AnnaBridge 143:86740a56073b 225 - Core Register
AnnaBridge 143:86740a56073b 226 - Core NVIC Register
AnnaBridge 143:86740a56073b 227 - Core SCB Register
AnnaBridge 143:86740a56073b 228 - Core SysTick Register
AnnaBridge 143:86740a56073b 229 - Core MPU Register
AnnaBridge 143:86740a56073b 230 ******************************************************************************/
AnnaBridge 143:86740a56073b 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 143:86740a56073b 232 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 143:86740a56073b 233 */
AnnaBridge 143:86740a56073b 234
AnnaBridge 143:86740a56073b 235 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 236 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 143:86740a56073b 237 \brief Core Register type definitions.
AnnaBridge 143:86740a56073b 238 @{
AnnaBridge 143:86740a56073b 239 */
AnnaBridge 143:86740a56073b 240
AnnaBridge 143:86740a56073b 241 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 143:86740a56073b 242 */
AnnaBridge 143:86740a56073b 243 typedef union
AnnaBridge 143:86740a56073b 244 {
AnnaBridge 143:86740a56073b 245 struct
AnnaBridge 143:86740a56073b 246 {
AnnaBridge 143:86740a56073b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 143:86740a56073b 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 143:86740a56073b 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 143:86740a56073b 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 143:86740a56073b 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 143:86740a56073b 252 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 253 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 254 } APSR_Type;
AnnaBridge 143:86740a56073b 255
AnnaBridge 143:86740a56073b 256 /* APSR Register Definitions */
AnnaBridge 143:86740a56073b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 143:86740a56073b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 143:86740a56073b 259
AnnaBridge 143:86740a56073b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 143:86740a56073b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 143:86740a56073b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 143:86740a56073b 265
AnnaBridge 143:86740a56073b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 143:86740a56073b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 143:86740a56073b 268
AnnaBridge 143:86740a56073b 269
AnnaBridge 143:86740a56073b 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 143:86740a56073b 271 */
AnnaBridge 143:86740a56073b 272 typedef union
AnnaBridge 143:86740a56073b 273 {
AnnaBridge 143:86740a56073b 274 struct
AnnaBridge 143:86740a56073b 275 {
AnnaBridge 143:86740a56073b 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 143:86740a56073b 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 143:86740a56073b 278 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 279 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 280 } IPSR_Type;
AnnaBridge 143:86740a56073b 281
AnnaBridge 143:86740a56073b 282 /* IPSR Register Definitions */
AnnaBridge 143:86740a56073b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 143:86740a56073b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 143:86740a56073b 285
AnnaBridge 143:86740a56073b 286
AnnaBridge 143:86740a56073b 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 143:86740a56073b 288 */
AnnaBridge 143:86740a56073b 289 typedef union
AnnaBridge 143:86740a56073b 290 {
AnnaBridge 143:86740a56073b 291 struct
AnnaBridge 143:86740a56073b 292 {
AnnaBridge 143:86740a56073b 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 143:86740a56073b 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 143:86740a56073b 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 143:86740a56073b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 143:86740a56073b 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 143:86740a56073b 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 143:86740a56073b 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 143:86740a56073b 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 143:86740a56073b 301 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 302 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 303 } xPSR_Type;
AnnaBridge 143:86740a56073b 304
AnnaBridge 143:86740a56073b 305 /* xPSR Register Definitions */
AnnaBridge 143:86740a56073b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 143:86740a56073b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 143:86740a56073b 308
AnnaBridge 143:86740a56073b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 143:86740a56073b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 143:86740a56073b 311
AnnaBridge 143:86740a56073b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 143:86740a56073b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 143:86740a56073b 314
AnnaBridge 143:86740a56073b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 143:86740a56073b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 143:86740a56073b 317
AnnaBridge 143:86740a56073b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 143:86740a56073b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 143:86740a56073b 320
AnnaBridge 143:86740a56073b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 143:86740a56073b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 143:86740a56073b 323
AnnaBridge 143:86740a56073b 324
AnnaBridge 143:86740a56073b 325 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 143:86740a56073b 326 */
AnnaBridge 143:86740a56073b 327 typedef union
AnnaBridge 143:86740a56073b 328 {
AnnaBridge 143:86740a56073b 329 struct
AnnaBridge 143:86740a56073b 330 {
AnnaBridge 143:86740a56073b 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 143:86740a56073b 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 143:86740a56073b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 143:86740a56073b 334 } b; /*!< Structure used for bit access */
AnnaBridge 143:86740a56073b 335 uint32_t w; /*!< Type used for word access */
AnnaBridge 143:86740a56073b 336 } CONTROL_Type;
AnnaBridge 143:86740a56073b 337
AnnaBridge 143:86740a56073b 338 /* CONTROL Register Definitions */
AnnaBridge 143:86740a56073b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 143:86740a56073b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 143:86740a56073b 341
AnnaBridge 143:86740a56073b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
AnnaBridge 143:86740a56073b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 143:86740a56073b 344
AnnaBridge 143:86740a56073b 345 /*@} end of group CMSIS_CORE */
AnnaBridge 143:86740a56073b 346
AnnaBridge 143:86740a56073b 347
AnnaBridge 143:86740a56073b 348 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 143:86740a56073b 350 \brief Type definitions for the NVIC Registers
AnnaBridge 143:86740a56073b 351 @{
AnnaBridge 143:86740a56073b 352 */
AnnaBridge 143:86740a56073b 353
AnnaBridge 143:86740a56073b 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 143:86740a56073b 355 */
AnnaBridge 143:86740a56073b 356 typedef struct
AnnaBridge 143:86740a56073b 357 {
AnnaBridge 143:86740a56073b 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 143:86740a56073b 359 uint32_t RESERVED0[31];
AnnaBridge 143:86740a56073b 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 143:86740a56073b 361 uint32_t RSERVED1[31];
AnnaBridge 143:86740a56073b 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 143:86740a56073b 363 uint32_t RESERVED2[31];
AnnaBridge 143:86740a56073b 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 143:86740a56073b 365 uint32_t RESERVED3[31];
AnnaBridge 143:86740a56073b 366 uint32_t RESERVED4[64];
AnnaBridge 143:86740a56073b 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 143:86740a56073b 368 } NVIC_Type;
AnnaBridge 143:86740a56073b 369
AnnaBridge 143:86740a56073b 370 /*@} end of group CMSIS_NVIC */
AnnaBridge 143:86740a56073b 371
AnnaBridge 143:86740a56073b 372
AnnaBridge 143:86740a56073b 373 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 374 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 143:86740a56073b 375 \brief Type definitions for the System Control Block Registers
AnnaBridge 143:86740a56073b 376 @{
AnnaBridge 143:86740a56073b 377 */
AnnaBridge 143:86740a56073b 378
AnnaBridge 143:86740a56073b 379 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 143:86740a56073b 380 */
AnnaBridge 143:86740a56073b 381 typedef struct
AnnaBridge 143:86740a56073b 382 {
AnnaBridge 143:86740a56073b 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 143:86740a56073b 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 143:86740a56073b 385 #if (__VTOR_PRESENT == 1)
AnnaBridge 143:86740a56073b 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 143:86740a56073b 387 #else
AnnaBridge 143:86740a56073b 388 uint32_t RESERVED0;
AnnaBridge 143:86740a56073b 389 #endif
AnnaBridge 143:86740a56073b 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 143:86740a56073b 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 143:86740a56073b 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 143:86740a56073b 393 uint32_t RESERVED1;
AnnaBridge 143:86740a56073b 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 143:86740a56073b 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 143:86740a56073b 396 } SCB_Type;
AnnaBridge 143:86740a56073b 397
AnnaBridge 143:86740a56073b 398 /* SCB CPUID Register Definitions */
AnnaBridge 143:86740a56073b 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 143:86740a56073b 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 143:86740a56073b 401
AnnaBridge 143:86740a56073b 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 143:86740a56073b 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 143:86740a56073b 404
AnnaBridge 143:86740a56073b 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 143:86740a56073b 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 143:86740a56073b 407
AnnaBridge 143:86740a56073b 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 143:86740a56073b 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 143:86740a56073b 410
AnnaBridge 143:86740a56073b 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 143:86740a56073b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 143:86740a56073b 413
AnnaBridge 143:86740a56073b 414 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 143:86740a56073b 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 143:86740a56073b 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 143:86740a56073b 417
AnnaBridge 143:86740a56073b 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 143:86740a56073b 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 143:86740a56073b 420
AnnaBridge 143:86740a56073b 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 143:86740a56073b 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 143:86740a56073b 423
AnnaBridge 143:86740a56073b 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 143:86740a56073b 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 143:86740a56073b 426
AnnaBridge 143:86740a56073b 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 143:86740a56073b 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 143:86740a56073b 429
AnnaBridge 143:86740a56073b 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 143:86740a56073b 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 143:86740a56073b 432
AnnaBridge 143:86740a56073b 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 143:86740a56073b 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 143:86740a56073b 435
AnnaBridge 143:86740a56073b 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 143:86740a56073b 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 143:86740a56073b 438
AnnaBridge 143:86740a56073b 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 143:86740a56073b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 143:86740a56073b 441
AnnaBridge 143:86740a56073b 442 #if (__VTOR_PRESENT == 1)
AnnaBridge 143:86740a56073b 443 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 143:86740a56073b 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 143:86740a56073b 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 143:86740a56073b 446 #endif
AnnaBridge 143:86740a56073b 447
AnnaBridge 143:86740a56073b 448 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 143:86740a56073b 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 143:86740a56073b 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 143:86740a56073b 451
AnnaBridge 143:86740a56073b 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 143:86740a56073b 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 143:86740a56073b 454
AnnaBridge 143:86740a56073b 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 143:86740a56073b 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 143:86740a56073b 457
AnnaBridge 143:86740a56073b 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 143:86740a56073b 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 143:86740a56073b 460
AnnaBridge 143:86740a56073b 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 143:86740a56073b 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 143:86740a56073b 463
AnnaBridge 143:86740a56073b 464 /* SCB System Control Register Definitions */
AnnaBridge 143:86740a56073b 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 143:86740a56073b 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 143:86740a56073b 467
AnnaBridge 143:86740a56073b 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 143:86740a56073b 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 143:86740a56073b 470
AnnaBridge 143:86740a56073b 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 143:86740a56073b 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 143:86740a56073b 473
AnnaBridge 143:86740a56073b 474 /* SCB Configuration Control Register Definitions */
AnnaBridge 143:86740a56073b 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 143:86740a56073b 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 143:86740a56073b 477
AnnaBridge 143:86740a56073b 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 143:86740a56073b 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 143:86740a56073b 480
AnnaBridge 143:86740a56073b 481 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 143:86740a56073b 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 143:86740a56073b 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 143:86740a56073b 484
AnnaBridge 143:86740a56073b 485 /*@} end of group CMSIS_SCB */
AnnaBridge 143:86740a56073b 486
AnnaBridge 143:86740a56073b 487
AnnaBridge 143:86740a56073b 488 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 143:86740a56073b 490 \brief Type definitions for the System Timer Registers.
AnnaBridge 143:86740a56073b 491 @{
AnnaBridge 143:86740a56073b 492 */
AnnaBridge 143:86740a56073b 493
AnnaBridge 143:86740a56073b 494 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 143:86740a56073b 495 */
AnnaBridge 143:86740a56073b 496 typedef struct
AnnaBridge 143:86740a56073b 497 {
AnnaBridge 143:86740a56073b 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 143:86740a56073b 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 143:86740a56073b 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 143:86740a56073b 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 143:86740a56073b 502 } SysTick_Type;
AnnaBridge 143:86740a56073b 503
AnnaBridge 143:86740a56073b 504 /* SysTick Control / Status Register Definitions */
AnnaBridge 143:86740a56073b 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 143:86740a56073b 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 143:86740a56073b 507
AnnaBridge 143:86740a56073b 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 143:86740a56073b 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 143:86740a56073b 510
AnnaBridge 143:86740a56073b 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 143:86740a56073b 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 143:86740a56073b 513
AnnaBridge 143:86740a56073b 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 143:86740a56073b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 143:86740a56073b 516
AnnaBridge 143:86740a56073b 517 /* SysTick Reload Register Definitions */
AnnaBridge 143:86740a56073b 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 143:86740a56073b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 143:86740a56073b 520
AnnaBridge 143:86740a56073b 521 /* SysTick Current Register Definitions */
AnnaBridge 143:86740a56073b 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 143:86740a56073b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 143:86740a56073b 524
AnnaBridge 143:86740a56073b 525 /* SysTick Calibration Register Definitions */
AnnaBridge 143:86740a56073b 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 143:86740a56073b 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 143:86740a56073b 528
AnnaBridge 143:86740a56073b 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 143:86740a56073b 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 143:86740a56073b 531
AnnaBridge 143:86740a56073b 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 143:86740a56073b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 143:86740a56073b 534
AnnaBridge 143:86740a56073b 535 /*@} end of group CMSIS_SysTick */
AnnaBridge 143:86740a56073b 536
AnnaBridge 143:86740a56073b 537 #if (__MPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 538 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 143:86740a56073b 540 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 143:86740a56073b 541 @{
AnnaBridge 143:86740a56073b 542 */
AnnaBridge 143:86740a56073b 543
AnnaBridge 143:86740a56073b 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 143:86740a56073b 545 */
AnnaBridge 143:86740a56073b 546 typedef struct
AnnaBridge 143:86740a56073b 547 {
AnnaBridge 143:86740a56073b 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 143:86740a56073b 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 143:86740a56073b 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 143:86740a56073b 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 143:86740a56073b 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 553 } MPU_Type;
AnnaBridge 143:86740a56073b 554
AnnaBridge 143:86740a56073b 555 /* MPU Type Register */
AnnaBridge 143:86740a56073b 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
AnnaBridge 143:86740a56073b 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 143:86740a56073b 558
AnnaBridge 143:86740a56073b 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
AnnaBridge 143:86740a56073b 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 143:86740a56073b 561
AnnaBridge 143:86740a56073b 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 143:86740a56073b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 143:86740a56073b 564
AnnaBridge 143:86740a56073b 565 /* MPU Control Register */
AnnaBridge 143:86740a56073b 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 143:86740a56073b 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 143:86740a56073b 568
AnnaBridge 143:86740a56073b 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 143:86740a56073b 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 143:86740a56073b 571
AnnaBridge 143:86740a56073b 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
AnnaBridge 143:86740a56073b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 143:86740a56073b 574
AnnaBridge 143:86740a56073b 575 /* MPU Region Number Register */
AnnaBridge 143:86740a56073b 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
AnnaBridge 143:86740a56073b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 143:86740a56073b 578
AnnaBridge 143:86740a56073b 579 /* MPU Region Base Address Register */
AnnaBridge 143:86740a56073b 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
AnnaBridge 143:86740a56073b 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 143:86740a56073b 582
AnnaBridge 143:86740a56073b 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
AnnaBridge 143:86740a56073b 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 143:86740a56073b 585
AnnaBridge 143:86740a56073b 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
AnnaBridge 143:86740a56073b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 143:86740a56073b 588
AnnaBridge 143:86740a56073b 589 /* MPU Region Attribute and Size Register */
AnnaBridge 143:86740a56073b 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 143:86740a56073b 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 143:86740a56073b 592
AnnaBridge 143:86740a56073b 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 143:86740a56073b 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 143:86740a56073b 595
AnnaBridge 143:86740a56073b 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 143:86740a56073b 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 143:86740a56073b 598
AnnaBridge 143:86740a56073b 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 143:86740a56073b 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 143:86740a56073b 601
AnnaBridge 143:86740a56073b 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 143:86740a56073b 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 143:86740a56073b 604
AnnaBridge 143:86740a56073b 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 143:86740a56073b 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 143:86740a56073b 607
AnnaBridge 143:86740a56073b 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 143:86740a56073b 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 143:86740a56073b 610
AnnaBridge 143:86740a56073b 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 143:86740a56073b 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 143:86740a56073b 613
AnnaBridge 143:86740a56073b 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
AnnaBridge 143:86740a56073b 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 143:86740a56073b 616
AnnaBridge 143:86740a56073b 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
AnnaBridge 143:86740a56073b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 143:86740a56073b 619
AnnaBridge 143:86740a56073b 620 /*@} end of group CMSIS_MPU */
AnnaBridge 143:86740a56073b 621 #endif
AnnaBridge 143:86740a56073b 622
AnnaBridge 143:86740a56073b 623
AnnaBridge 143:86740a56073b 624 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 143:86740a56073b 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
AnnaBridge 143:86740a56073b 627 are only accessible over DAP and not via processor. Therefore
AnnaBridge 143:86740a56073b 628 they are not covered by the Cortex-M0 header file.
AnnaBridge 143:86740a56073b 629 @{
AnnaBridge 143:86740a56073b 630 */
AnnaBridge 143:86740a56073b 631 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 143:86740a56073b 632
AnnaBridge 143:86740a56073b 633
AnnaBridge 143:86740a56073b 634 /** \ingroup CMSIS_core_register
AnnaBridge 143:86740a56073b 635 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 143:86740a56073b 636 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 143:86740a56073b 637 @{
AnnaBridge 143:86740a56073b 638 */
AnnaBridge 143:86740a56073b 639
AnnaBridge 143:86740a56073b 640 /* Memory mapping of Cortex-M0+ Hardware */
AnnaBridge 143:86740a56073b 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 143:86740a56073b 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 143:86740a56073b 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 143:86740a56073b 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 143:86740a56073b 645
AnnaBridge 143:86740a56073b 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 143:86740a56073b 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 143:86740a56073b 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 143:86740a56073b 649
AnnaBridge 143:86740a56073b 650 #if (__MPU_PRESENT == 1)
AnnaBridge 143:86740a56073b 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 143:86740a56073b 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 143:86740a56073b 653 #endif
AnnaBridge 143:86740a56073b 654
AnnaBridge 143:86740a56073b 655 /*@} */
AnnaBridge 143:86740a56073b 656
AnnaBridge 143:86740a56073b 657
AnnaBridge 143:86740a56073b 658
AnnaBridge 143:86740a56073b 659 /*******************************************************************************
AnnaBridge 143:86740a56073b 660 * Hardware Abstraction Layer
AnnaBridge 143:86740a56073b 661 Core Function Interface contains:
AnnaBridge 143:86740a56073b 662 - Core NVIC Functions
AnnaBridge 143:86740a56073b 663 - Core SysTick Functions
AnnaBridge 143:86740a56073b 664 - Core Register Access Functions
AnnaBridge 143:86740a56073b 665 ******************************************************************************/
AnnaBridge 143:86740a56073b 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 143:86740a56073b 667 */
AnnaBridge 143:86740a56073b 668
AnnaBridge 143:86740a56073b 669
AnnaBridge 143:86740a56073b 670
AnnaBridge 143:86740a56073b 671 /* ########################## NVIC functions #################################### */
AnnaBridge 143:86740a56073b 672 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 143:86740a56073b 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 143:86740a56073b 674 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 143:86740a56073b 675 @{
AnnaBridge 143:86740a56073b 676 */
AnnaBridge 143:86740a56073b 677
AnnaBridge 143:86740a56073b 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 143:86740a56073b 679 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 143:86740a56073b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 143:86740a56073b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 143:86740a56073b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 143:86740a56073b 683
AnnaBridge 143:86740a56073b 684
AnnaBridge 143:86740a56073b 685 /** \brief Enable External Interrupt
AnnaBridge 143:86740a56073b 686
AnnaBridge 143:86740a56073b 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 143:86740a56073b 688
AnnaBridge 143:86740a56073b 689 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 690 */
AnnaBridge 143:86740a56073b 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 692 {
AnnaBridge 143:86740a56073b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 694 }
AnnaBridge 143:86740a56073b 695
AnnaBridge 143:86740a56073b 696
AnnaBridge 143:86740a56073b 697 /** \brief Disable External Interrupt
AnnaBridge 143:86740a56073b 698
AnnaBridge 143:86740a56073b 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 143:86740a56073b 700
AnnaBridge 143:86740a56073b 701 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 702 */
AnnaBridge 143:86740a56073b 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 704 {
AnnaBridge 143:86740a56073b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 706 __DSB();
AnnaBridge 143:86740a56073b 707 __ISB();
AnnaBridge 143:86740a56073b 708 }
AnnaBridge 143:86740a56073b 709
AnnaBridge 143:86740a56073b 710
AnnaBridge 143:86740a56073b 711 /** \brief Get Pending Interrupt
AnnaBridge 143:86740a56073b 712
AnnaBridge 143:86740a56073b 713 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 143:86740a56073b 714 for the specified interrupt.
AnnaBridge 143:86740a56073b 715
AnnaBridge 143:86740a56073b 716 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 717
AnnaBridge 143:86740a56073b 718 \return 0 Interrupt status is not pending.
AnnaBridge 143:86740a56073b 719 \return 1 Interrupt status is pending.
AnnaBridge 143:86740a56073b 720 */
AnnaBridge 143:86740a56073b 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 722 {
AnnaBridge 143:86740a56073b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 143:86740a56073b 724 }
AnnaBridge 143:86740a56073b 725
AnnaBridge 143:86740a56073b 726
AnnaBridge 143:86740a56073b 727 /** \brief Set Pending Interrupt
AnnaBridge 143:86740a56073b 728
AnnaBridge 143:86740a56073b 729 The function sets the pending bit of an external interrupt.
AnnaBridge 143:86740a56073b 730
AnnaBridge 143:86740a56073b 731 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 732 */
AnnaBridge 143:86740a56073b 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 734 {
AnnaBridge 143:86740a56073b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 736 }
AnnaBridge 143:86740a56073b 737
AnnaBridge 143:86740a56073b 738
AnnaBridge 143:86740a56073b 739 /** \brief Clear Pending Interrupt
AnnaBridge 143:86740a56073b 740
AnnaBridge 143:86740a56073b 741 The function clears the pending bit of an external interrupt.
AnnaBridge 143:86740a56073b 742
AnnaBridge 143:86740a56073b 743 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 143:86740a56073b 744 */
AnnaBridge 143:86740a56073b 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 746 {
AnnaBridge 143:86740a56073b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 143:86740a56073b 748 }
AnnaBridge 143:86740a56073b 749
AnnaBridge 143:86740a56073b 750
AnnaBridge 143:86740a56073b 751 /** \brief Set Interrupt Priority
AnnaBridge 143:86740a56073b 752
AnnaBridge 143:86740a56073b 753 The function sets the priority of an interrupt.
AnnaBridge 143:86740a56073b 754
AnnaBridge 143:86740a56073b 755 \note The priority cannot be set for every core interrupt.
AnnaBridge 143:86740a56073b 756
AnnaBridge 143:86740a56073b 757 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 758 \param [in] priority Priority to set.
AnnaBridge 143:86740a56073b 759 */
AnnaBridge 143:86740a56073b 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 143:86740a56073b 761 {
AnnaBridge 143:86740a56073b 762 if((int32_t)(IRQn) < 0) {
AnnaBridge 143:86740a56073b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 143:86740a56073b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 143:86740a56073b 765 }
AnnaBridge 143:86740a56073b 766 else {
AnnaBridge 143:86740a56073b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 143:86740a56073b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 143:86740a56073b 769 }
AnnaBridge 143:86740a56073b 770 }
AnnaBridge 143:86740a56073b 771
AnnaBridge 143:86740a56073b 772
AnnaBridge 143:86740a56073b 773 /** \brief Get Interrupt Priority
AnnaBridge 143:86740a56073b 774
AnnaBridge 143:86740a56073b 775 The function reads the priority of an interrupt. The interrupt
AnnaBridge 143:86740a56073b 776 number can be positive to specify an external (device specific)
AnnaBridge 143:86740a56073b 777 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 143:86740a56073b 778
AnnaBridge 143:86740a56073b 779
AnnaBridge 143:86740a56073b 780 \param [in] IRQn Interrupt number.
AnnaBridge 143:86740a56073b 781 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 143:86740a56073b 782 priority bits of the microcontroller.
AnnaBridge 143:86740a56073b 783 */
AnnaBridge 143:86740a56073b 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 143:86740a56073b 785 {
AnnaBridge 143:86740a56073b 786
AnnaBridge 143:86740a56073b 787 if((int32_t)(IRQn) < 0) {
AnnaBridge 143:86740a56073b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 143:86740a56073b 789 }
AnnaBridge 143:86740a56073b 790 else {
AnnaBridge 143:86740a56073b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 143:86740a56073b 792 }
AnnaBridge 143:86740a56073b 793 }
AnnaBridge 143:86740a56073b 794
AnnaBridge 143:86740a56073b 795
AnnaBridge 143:86740a56073b 796 /** \brief System Reset
AnnaBridge 143:86740a56073b 797
AnnaBridge 143:86740a56073b 798 The function initiates a system reset request to reset the MCU.
AnnaBridge 143:86740a56073b 799 */
AnnaBridge 143:86740a56073b 800 __STATIC_INLINE void NVIC_SystemReset(void)
AnnaBridge 143:86740a56073b 801 {
AnnaBridge 143:86740a56073b 802 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 143:86740a56073b 803 buffered write are completed before reset */
AnnaBridge 143:86740a56073b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 143:86740a56073b 805 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 143:86740a56073b 806 __DSB(); /* Ensure completion of memory access */
AnnaBridge 143:86740a56073b 807 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 143:86740a56073b 808 }
AnnaBridge 143:86740a56073b 809
AnnaBridge 143:86740a56073b 810 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 143:86740a56073b 811
AnnaBridge 143:86740a56073b 812
AnnaBridge 143:86740a56073b 813
AnnaBridge 143:86740a56073b 814 /* ################################## SysTick function ############################################ */
AnnaBridge 143:86740a56073b 815 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 143:86740a56073b 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 143:86740a56073b 817 \brief Functions that configure the System.
AnnaBridge 143:86740a56073b 818 @{
AnnaBridge 143:86740a56073b 819 */
AnnaBridge 143:86740a56073b 820
AnnaBridge 143:86740a56073b 821 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 143:86740a56073b 822
AnnaBridge 143:86740a56073b 823 /** \brief System Tick Configuration
AnnaBridge 143:86740a56073b 824
AnnaBridge 143:86740a56073b 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 143:86740a56073b 826 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 143:86740a56073b 827
AnnaBridge 143:86740a56073b 828 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 143:86740a56073b 829
AnnaBridge 143:86740a56073b 830 \return 0 Function succeeded.
AnnaBridge 143:86740a56073b 831 \return 1 Function failed.
AnnaBridge 143:86740a56073b 832
AnnaBridge 143:86740a56073b 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 143:86740a56073b 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 143:86740a56073b 835 must contain a vendor-specific implementation of this function.
AnnaBridge 143:86740a56073b 836
AnnaBridge 143:86740a56073b 837 */
AnnaBridge 143:86740a56073b 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 143:86740a56073b 839 {
AnnaBridge 143:86740a56073b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
AnnaBridge 143:86740a56073b 841
AnnaBridge 143:86740a56073b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 143:86740a56073b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 143:86740a56073b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 143:86740a56073b 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 143:86740a56073b 846 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 143:86740a56073b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 143:86740a56073b 848 return (0UL); /* Function successful */
AnnaBridge 143:86740a56073b 849 }
AnnaBridge 143:86740a56073b 850
AnnaBridge 143:86740a56073b 851 #endif
AnnaBridge 143:86740a56073b 852
AnnaBridge 143:86740a56073b 853 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 143:86740a56073b 854
AnnaBridge 143:86740a56073b 855
AnnaBridge 143:86740a56073b 856
AnnaBridge 143:86740a56073b 857
AnnaBridge 143:86740a56073b 858 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 859 }
AnnaBridge 143:86740a56073b 860 #endif
AnnaBridge 143:86740a56073b 861
AnnaBridge 143:86740a56073b 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
AnnaBridge 143:86740a56073b 863
AnnaBridge 143:86740a56073b 864 #endif /* __CMSIS_GENERIC */