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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_L072CZ_LRWAN1/core_ca_mmu.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 ;/**************************************************************************//**
AnnaBridge 143:86740a56073b 2 ; * @file core_ca_mmu.h
AnnaBridge 143:86740a56073b 3 ; * @brief MMU Startup File for A9_MP Device Series
AnnaBridge 143:86740a56073b 4 ; * @version V1.01
AnnaBridge 143:86740a56073b 5 ; * @date 10 Sept 2014
AnnaBridge 143:86740a56073b 6 ; *
AnnaBridge 143:86740a56073b 7 ; * @note
AnnaBridge 143:86740a56073b 8 ; *
AnnaBridge 143:86740a56073b 9 ; ******************************************************************************/
AnnaBridge 143:86740a56073b 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
AnnaBridge 143:86740a56073b 11 ;
AnnaBridge 143:86740a56073b 12 ; All rights reserved.
AnnaBridge 143:86740a56073b 13 ; Redistribution and use in source and binary forms, with or without
AnnaBridge 143:86740a56073b 14 ; modification, are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 15 ; - Redistributions of source code must retain the above copyright
AnnaBridge 143:86740a56073b 16 ; notice, this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 17 ; - Redistributions in binary form must reproduce the above copyright
AnnaBridge 143:86740a56073b 18 ; notice, this list of conditions and the following disclaimer in the
AnnaBridge 143:86740a56073b 19 ; documentation and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 20 ; - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 143:86740a56073b 21 ; to endorse or promote products derived from this software without
AnnaBridge 143:86740a56073b 22 ; specific prior written permission.
AnnaBridge 143:86740a56073b 23 ; *
AnnaBridge 143:86740a56073b 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 143:86740a56073b 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 143:86740a56073b 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 143:86740a56073b 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 143:86740a56073b 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 143:86740a56073b 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 143:86740a56073b 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 143:86740a56073b 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 143:86740a56073b 34 ; POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 35 ; ---------------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 36
AnnaBridge 143:86740a56073b 37 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 38 extern "C" {
AnnaBridge 143:86740a56073b 39 #endif
AnnaBridge 143:86740a56073b 40
AnnaBridge 143:86740a56073b 41 #ifndef _MMU_FUNC_H
AnnaBridge 143:86740a56073b 42 #define _MMU_FUNC_H
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 #define SECTION_DESCRIPTOR (0x2)
AnnaBridge 143:86740a56073b 45 #define SECTION_MASK (0xFFFFFFFC)
AnnaBridge 143:86740a56073b 46
AnnaBridge 143:86740a56073b 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 143:86740a56073b 48 #define SECTION_B_SHIFT (2)
AnnaBridge 143:86740a56073b 49 #define SECTION_C_SHIFT (3)
AnnaBridge 143:86740a56073b 50 #define SECTION_TEX0_SHIFT (12)
AnnaBridge 143:86740a56073b 51 #define SECTION_TEX1_SHIFT (13)
AnnaBridge 143:86740a56073b 52 #define SECTION_TEX2_SHIFT (14)
AnnaBridge 143:86740a56073b 53
AnnaBridge 143:86740a56073b 54 #define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge 143:86740a56073b 55 #define SECTION_XN_SHIFT (4)
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 143:86740a56073b 58 #define SECTION_DOMAIN_SHIFT (5)
AnnaBridge 143:86740a56073b 59
AnnaBridge 143:86740a56073b 60 #define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge 143:86740a56073b 61 #define SECTION_P_SHIFT (9)
AnnaBridge 143:86740a56073b 62
AnnaBridge 143:86740a56073b 63 #define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge 143:86740a56073b 64 #define SECTION_AP_SHIFT (10)
AnnaBridge 143:86740a56073b 65 #define SECTION_AP2_SHIFT (15)
AnnaBridge 143:86740a56073b 66
AnnaBridge 143:86740a56073b 67 #define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge 143:86740a56073b 68 #define SECTION_S_SHIFT (16)
AnnaBridge 143:86740a56073b 69
AnnaBridge 143:86740a56073b 70 #define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge 143:86740a56073b 71 #define SECTION_NG_SHIFT (17)
AnnaBridge 143:86740a56073b 72
AnnaBridge 143:86740a56073b 73 #define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge 143:86740a56073b 74 #define SECTION_NS_SHIFT (19)
AnnaBridge 143:86740a56073b 75
AnnaBridge 143:86740a56073b 76
AnnaBridge 143:86740a56073b 77 #define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge 143:86740a56073b 78 #define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge 143:86740a56073b 79
AnnaBridge 143:86740a56073b 80 #define PAGE_L2_4K_DESC (0x2)
AnnaBridge 143:86740a56073b 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge 143:86740a56073b 82
AnnaBridge 143:86740a56073b 83 #define PAGE_L2_64K_DESC (0x1)
AnnaBridge 143:86740a56073b 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge 143:86740a56073b 85
AnnaBridge 143:86740a56073b 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge 143:86740a56073b 87 #define PAGE_4K_B_SHIFT (2)
AnnaBridge 143:86740a56073b 88 #define PAGE_4K_C_SHIFT (3)
AnnaBridge 143:86740a56073b 89 #define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge 143:86740a56073b 90 #define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge 143:86740a56073b 91 #define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge 143:86740a56073b 92
AnnaBridge 143:86740a56073b 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 143:86740a56073b 94 #define PAGE_64K_B_SHIFT (2)
AnnaBridge 143:86740a56073b 95 #define PAGE_64K_C_SHIFT (3)
AnnaBridge 143:86740a56073b 96 #define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge 143:86740a56073b 97 #define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge 143:86740a56073b 98 #define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge 143:86740a56073b 99
AnnaBridge 143:86740a56073b 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 143:86740a56073b 101 #define PAGE_B_SHIFT (2)
AnnaBridge 143:86740a56073b 102 #define PAGE_C_SHIFT (3)
AnnaBridge 143:86740a56073b 103 #define PAGE_TEX_SHIFT (12)
AnnaBridge 143:86740a56073b 104
AnnaBridge 143:86740a56073b 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge 143:86740a56073b 106 #define PAGE_XN_4K_SHIFT (0)
AnnaBridge 143:86740a56073b 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge 143:86740a56073b 108 #define PAGE_XN_64K_SHIFT (15)
AnnaBridge 143:86740a56073b 109
AnnaBridge 143:86740a56073b 110
AnnaBridge 143:86740a56073b 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 143:86740a56073b 112 #define PAGE_DOMAIN_SHIFT (5)
AnnaBridge 143:86740a56073b 113
AnnaBridge 143:86740a56073b 114 #define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge 143:86740a56073b 115 #define PAGE_P_SHIFT (9)
AnnaBridge 143:86740a56073b 116
AnnaBridge 143:86740a56073b 117 #define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge 143:86740a56073b 118 #define PAGE_AP_SHIFT (4)
AnnaBridge 143:86740a56073b 119 #define PAGE_AP2_SHIFT (9)
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 #define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge 143:86740a56073b 122 #define PAGE_S_SHIFT (10)
AnnaBridge 143:86740a56073b 123
AnnaBridge 143:86740a56073b 124 #define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge 143:86740a56073b 125 #define PAGE_NG_SHIFT (11)
AnnaBridge 143:86740a56073b 126
AnnaBridge 143:86740a56073b 127 #define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge 143:86740a56073b 128 #define PAGE_NS_SHIFT (3)
AnnaBridge 143:86740a56073b 129
AnnaBridge 143:86740a56073b 130 #define OFFSET_1M (0x00100000)
AnnaBridge 143:86740a56073b 131 #define OFFSET_64K (0x00010000)
AnnaBridge 143:86740a56073b 132 #define OFFSET_4K (0x00001000)
AnnaBridge 143:86740a56073b 133
AnnaBridge 143:86740a56073b 134 #define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge 143:86740a56073b 135
AnnaBridge 143:86740a56073b 136 /* ########################### MMU Function Access ########################### */
AnnaBridge 143:86740a56073b 137 /** \ingroup MMU_FunctionInterface
AnnaBridge 143:86740a56073b 138 \defgroup MMU_Functions MMU Functions Interface
AnnaBridge 143:86740a56073b 139 @{
AnnaBridge 143:86740a56073b 140 */
AnnaBridge 143:86740a56073b 141
AnnaBridge 143:86740a56073b 142 /* Attributes enumerations */
AnnaBridge 143:86740a56073b 143
AnnaBridge 143:86740a56073b 144 /* Region size attributes */
AnnaBridge 143:86740a56073b 145 typedef enum
AnnaBridge 143:86740a56073b 146 {
AnnaBridge 143:86740a56073b 147 SECTION,
AnnaBridge 143:86740a56073b 148 PAGE_4k,
AnnaBridge 143:86740a56073b 149 PAGE_64k,
AnnaBridge 143:86740a56073b 150 } mmu_region_size_Type;
AnnaBridge 143:86740a56073b 151
AnnaBridge 143:86740a56073b 152 /* Region type attributes */
AnnaBridge 143:86740a56073b 153 typedef enum
AnnaBridge 143:86740a56073b 154 {
AnnaBridge 143:86740a56073b 155 NORMAL,
AnnaBridge 143:86740a56073b 156 DEVICE,
AnnaBridge 143:86740a56073b 157 SHARED_DEVICE,
AnnaBridge 143:86740a56073b 158 NON_SHARED_DEVICE,
AnnaBridge 143:86740a56073b 159 STRONGLY_ORDERED
AnnaBridge 143:86740a56073b 160 } mmu_memory_Type;
AnnaBridge 143:86740a56073b 161
AnnaBridge 143:86740a56073b 162 /* Region cacheability attributes */
AnnaBridge 143:86740a56073b 163 typedef enum
AnnaBridge 143:86740a56073b 164 {
AnnaBridge 143:86740a56073b 165 NON_CACHEABLE,
AnnaBridge 143:86740a56073b 166 WB_WA,
AnnaBridge 143:86740a56073b 167 WT,
AnnaBridge 143:86740a56073b 168 WB_NO_WA,
AnnaBridge 143:86740a56073b 169 } mmu_cacheability_Type;
AnnaBridge 143:86740a56073b 170
AnnaBridge 143:86740a56073b 171 /* Region parity check attributes */
AnnaBridge 143:86740a56073b 172 typedef enum
AnnaBridge 143:86740a56073b 173 {
AnnaBridge 143:86740a56073b 174 ECC_DISABLED,
AnnaBridge 143:86740a56073b 175 ECC_ENABLED,
AnnaBridge 143:86740a56073b 176 } mmu_ecc_check_Type;
AnnaBridge 143:86740a56073b 177
AnnaBridge 143:86740a56073b 178 /* Region execution attributes */
AnnaBridge 143:86740a56073b 179 typedef enum
AnnaBridge 143:86740a56073b 180 {
AnnaBridge 143:86740a56073b 181 EXECUTE,
AnnaBridge 143:86740a56073b 182 NON_EXECUTE,
AnnaBridge 143:86740a56073b 183 } mmu_execute_Type;
AnnaBridge 143:86740a56073b 184
AnnaBridge 143:86740a56073b 185 /* Region global attributes */
AnnaBridge 143:86740a56073b 186 typedef enum
AnnaBridge 143:86740a56073b 187 {
AnnaBridge 143:86740a56073b 188 GLOBAL,
AnnaBridge 143:86740a56073b 189 NON_GLOBAL,
AnnaBridge 143:86740a56073b 190 } mmu_global_Type;
AnnaBridge 143:86740a56073b 191
AnnaBridge 143:86740a56073b 192 /* Region shareability attributes */
AnnaBridge 143:86740a56073b 193 typedef enum
AnnaBridge 143:86740a56073b 194 {
AnnaBridge 143:86740a56073b 195 NON_SHARED,
AnnaBridge 143:86740a56073b 196 SHARED,
AnnaBridge 143:86740a56073b 197 } mmu_shared_Type;
AnnaBridge 143:86740a56073b 198
AnnaBridge 143:86740a56073b 199 /* Region security attributes */
AnnaBridge 143:86740a56073b 200 typedef enum
AnnaBridge 143:86740a56073b 201 {
AnnaBridge 143:86740a56073b 202 SECURE,
AnnaBridge 143:86740a56073b 203 NON_SECURE,
AnnaBridge 143:86740a56073b 204 } mmu_secure_Type;
AnnaBridge 143:86740a56073b 205
AnnaBridge 143:86740a56073b 206 /* Region access attributes */
AnnaBridge 143:86740a56073b 207 typedef enum
AnnaBridge 143:86740a56073b 208 {
AnnaBridge 143:86740a56073b 209 NO_ACCESS,
AnnaBridge 143:86740a56073b 210 RW,
AnnaBridge 143:86740a56073b 211 READ,
AnnaBridge 143:86740a56073b 212 } mmu_access_Type;
AnnaBridge 143:86740a56073b 213
AnnaBridge 143:86740a56073b 214 /* Memory Region definition */
AnnaBridge 143:86740a56073b 215 typedef struct RegionStruct {
AnnaBridge 143:86740a56073b 216 mmu_region_size_Type rg_t;
AnnaBridge 143:86740a56073b 217 mmu_memory_Type mem_t;
AnnaBridge 143:86740a56073b 218 uint8_t domain;
AnnaBridge 143:86740a56073b 219 mmu_cacheability_Type inner_norm_t;
AnnaBridge 143:86740a56073b 220 mmu_cacheability_Type outer_norm_t;
AnnaBridge 143:86740a56073b 221 mmu_ecc_check_Type e_t;
AnnaBridge 143:86740a56073b 222 mmu_execute_Type xn_t;
AnnaBridge 143:86740a56073b 223 mmu_global_Type g_t;
AnnaBridge 143:86740a56073b 224 mmu_secure_Type sec_t;
AnnaBridge 143:86740a56073b 225 mmu_access_Type priv_t;
AnnaBridge 143:86740a56073b 226 mmu_access_Type user_t;
AnnaBridge 143:86740a56073b 227 mmu_shared_Type sh_t;
AnnaBridge 143:86740a56073b 228
AnnaBridge 143:86740a56073b 229 } mmu_region_attributes_Type;
AnnaBridge 143:86740a56073b 230
AnnaBridge 143:86740a56073b 231 /** \brief Set section execution-never attribute
AnnaBridge 143:86740a56073b 232
AnnaBridge 143:86740a56073b 233 The function sets section execution-never attribute
AnnaBridge 143:86740a56073b 234
AnnaBridge 143:86740a56073b 235 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 143:86740a56073b 237
AnnaBridge 143:86740a56073b 238 \return 0
AnnaBridge 143:86740a56073b 239 */
AnnaBridge 143:86740a56073b 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge 143:86740a56073b 241 {
AnnaBridge 143:86740a56073b 242 *descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge 143:86740a56073b 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge 143:86740a56073b 244 return 0;
AnnaBridge 143:86740a56073b 245 }
AnnaBridge 143:86740a56073b 246
AnnaBridge 143:86740a56073b 247 /** \brief Set section domain
AnnaBridge 143:86740a56073b 248
AnnaBridge 143:86740a56073b 249 The function sets section domain
AnnaBridge 143:86740a56073b 250
AnnaBridge 143:86740a56073b 251 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 252 \param [in] domain Section domain
AnnaBridge 143:86740a56073b 253
AnnaBridge 143:86740a56073b 254 \return 0
AnnaBridge 143:86740a56073b 255 */
AnnaBridge 143:86740a56073b 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 143:86740a56073b 257 {
AnnaBridge 143:86740a56073b 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge 143:86740a56073b 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge 143:86740a56073b 260 return 0;
AnnaBridge 143:86740a56073b 261 }
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263 /** \brief Set section parity check
AnnaBridge 143:86740a56073b 264
AnnaBridge 143:86740a56073b 265 The function sets section parity check
AnnaBridge 143:86740a56073b 266
AnnaBridge 143:86740a56073b 267 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 143:86740a56073b 269
AnnaBridge 143:86740a56073b 270 \return 0
AnnaBridge 143:86740a56073b 271 */
AnnaBridge 143:86740a56073b 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 143:86740a56073b 273 {
AnnaBridge 143:86740a56073b 274 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 143:86740a56073b 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 143:86740a56073b 276 return 0;
AnnaBridge 143:86740a56073b 277 }
AnnaBridge 143:86740a56073b 278
AnnaBridge 143:86740a56073b 279 /** \brief Set section access privileges
AnnaBridge 143:86740a56073b 280
AnnaBridge 143:86740a56073b 281 The function sets section access privileges
AnnaBridge 143:86740a56073b 282
AnnaBridge 143:86740a56073b 283 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 143:86740a56073b 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 143:86740a56073b 286 \param [in] afe Access flag enable
AnnaBridge 143:86740a56073b 287
AnnaBridge 143:86740a56073b 288 \return 0
AnnaBridge 143:86740a56073b 289 */
AnnaBridge 143:86740a56073b 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 143:86740a56073b 291 {
AnnaBridge 143:86740a56073b 292 uint32_t ap = 0;
AnnaBridge 143:86740a56073b 293
AnnaBridge 143:86740a56073b 294 if (afe == 0) { //full access
AnnaBridge 143:86740a56073b 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 143:86740a56073b 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 143:86740a56073b 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 143:86740a56073b 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 143:86740a56073b 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 143:86740a56073b 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 143:86740a56073b 301 }
AnnaBridge 143:86740a56073b 302
AnnaBridge 143:86740a56073b 303 else { //Simplified access
AnnaBridge 143:86740a56073b 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 143:86740a56073b 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 143:86740a56073b 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 143:86740a56073b 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 143:86740a56073b 308 }
AnnaBridge 143:86740a56073b 309
AnnaBridge 143:86740a56073b 310 *descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge 143:86740a56073b 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge 143:86740a56073b 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge 143:86740a56073b 313
AnnaBridge 143:86740a56073b 314 return 0;
AnnaBridge 143:86740a56073b 315 }
AnnaBridge 143:86740a56073b 316
AnnaBridge 143:86740a56073b 317 /** \brief Set section shareability
AnnaBridge 143:86740a56073b 318
AnnaBridge 143:86740a56073b 319 The function sets section shareability
AnnaBridge 143:86740a56073b 320
AnnaBridge 143:86740a56073b 321 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge 143:86740a56073b 323
AnnaBridge 143:86740a56073b 324 \return 0
AnnaBridge 143:86740a56073b 325 */
AnnaBridge 143:86740a56073b 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge 143:86740a56073b 327 {
AnnaBridge 143:86740a56073b 328 *descriptor_l1 &= SECTION_S_MASK;
AnnaBridge 143:86740a56073b 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge 143:86740a56073b 330 return 0;
AnnaBridge 143:86740a56073b 331 }
AnnaBridge 143:86740a56073b 332
AnnaBridge 143:86740a56073b 333 /** \brief Set section Global attribute
AnnaBridge 143:86740a56073b 334
AnnaBridge 143:86740a56073b 335 The function sets section Global attribute
AnnaBridge 143:86740a56073b 336
AnnaBridge 143:86740a56073b 337 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge 143:86740a56073b 339
AnnaBridge 143:86740a56073b 340 \return 0
AnnaBridge 143:86740a56073b 341 */
AnnaBridge 143:86740a56073b 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge 143:86740a56073b 343 {
AnnaBridge 143:86740a56073b 344 *descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge 143:86740a56073b 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge 143:86740a56073b 346 return 0;
AnnaBridge 143:86740a56073b 347 }
AnnaBridge 143:86740a56073b 348
AnnaBridge 143:86740a56073b 349 /** \brief Set section Security attribute
AnnaBridge 143:86740a56073b 350
AnnaBridge 143:86740a56073b 351 The function sets section Global attribute
AnnaBridge 143:86740a56073b 352
AnnaBridge 143:86740a56073b 353 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge 143:86740a56073b 355
AnnaBridge 143:86740a56073b 356 \return 0
AnnaBridge 143:86740a56073b 357 */
AnnaBridge 143:86740a56073b 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 143:86740a56073b 359 {
AnnaBridge 143:86740a56073b 360 *descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge 143:86740a56073b 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge 143:86740a56073b 362 return 0;
AnnaBridge 143:86740a56073b 363 }
AnnaBridge 143:86740a56073b 364
AnnaBridge 143:86740a56073b 365 /* Page 4k or 64k */
AnnaBridge 143:86740a56073b 366 /** \brief Set 4k/64k page execution-never attribute
AnnaBridge 143:86740a56073b 367
AnnaBridge 143:86740a56073b 368 The function sets 4k/64k page execution-never attribute
AnnaBridge 143:86740a56073b 369
AnnaBridge 143:86740a56073b 370 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 143:86740a56073b 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 143:86740a56073b 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge 143:86740a56073b 373
AnnaBridge 143:86740a56073b 374 \return 0
AnnaBridge 143:86740a56073b 375 */
AnnaBridge 143:86740a56073b 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge 143:86740a56073b 377 {
AnnaBridge 143:86740a56073b 378 if (page == PAGE_4k)
AnnaBridge 143:86740a56073b 379 {
AnnaBridge 143:86740a56073b 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge 143:86740a56073b 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge 143:86740a56073b 382 }
AnnaBridge 143:86740a56073b 383 else
AnnaBridge 143:86740a56073b 384 {
AnnaBridge 143:86740a56073b 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge 143:86740a56073b 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge 143:86740a56073b 387 }
AnnaBridge 143:86740a56073b 388 return 0;
AnnaBridge 143:86740a56073b 389 }
AnnaBridge 143:86740a56073b 390
AnnaBridge 143:86740a56073b 391 /** \brief Set 4k/64k page domain
AnnaBridge 143:86740a56073b 392
AnnaBridge 143:86740a56073b 393 The function sets 4k/64k page domain
AnnaBridge 143:86740a56073b 394
AnnaBridge 143:86740a56073b 395 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 396 \param [in] domain Page domain
AnnaBridge 143:86740a56073b 397
AnnaBridge 143:86740a56073b 398 \return 0
AnnaBridge 143:86740a56073b 399 */
AnnaBridge 143:86740a56073b 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 143:86740a56073b 401 {
AnnaBridge 143:86740a56073b 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge 143:86740a56073b 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge 143:86740a56073b 404 return 0;
AnnaBridge 143:86740a56073b 405 }
AnnaBridge 143:86740a56073b 406
AnnaBridge 143:86740a56073b 407 /** \brief Set 4k/64k page parity check
AnnaBridge 143:86740a56073b 408
AnnaBridge 143:86740a56073b 409 The function sets 4k/64k page parity check
AnnaBridge 143:86740a56073b 410
AnnaBridge 143:86740a56073b 411 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 143:86740a56073b 413
AnnaBridge 143:86740a56073b 414 \return 0
AnnaBridge 143:86740a56073b 415 */
AnnaBridge 143:86740a56073b 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 143:86740a56073b 417 {
AnnaBridge 143:86740a56073b 418 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 143:86740a56073b 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 143:86740a56073b 420 return 0;
AnnaBridge 143:86740a56073b 421 }
AnnaBridge 143:86740a56073b 422
AnnaBridge 143:86740a56073b 423 /** \brief Set 4k/64k page access privileges
AnnaBridge 143:86740a56073b 424
AnnaBridge 143:86740a56073b 425 The function sets 4k/64k page access privileges
AnnaBridge 143:86740a56073b 426
AnnaBridge 143:86740a56073b 427 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 143:86740a56073b 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 143:86740a56073b 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 143:86740a56073b 430 \param [in] afe Access flag enable
AnnaBridge 143:86740a56073b 431
AnnaBridge 143:86740a56073b 432 \return 0
AnnaBridge 143:86740a56073b 433 */
AnnaBridge 143:86740a56073b 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 143:86740a56073b 435 {
AnnaBridge 143:86740a56073b 436 uint32_t ap = 0;
AnnaBridge 143:86740a56073b 437
AnnaBridge 143:86740a56073b 438 if (afe == 0) { //full access
AnnaBridge 143:86740a56073b 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 143:86740a56073b 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 143:86740a56073b 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 143:86740a56073b 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 143:86740a56073b 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 143:86740a56073b 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge 143:86740a56073b 445 }
AnnaBridge 143:86740a56073b 446
AnnaBridge 143:86740a56073b 447 else { //Simplified access
AnnaBridge 143:86740a56073b 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 143:86740a56073b 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 143:86740a56073b 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 143:86740a56073b 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 143:86740a56073b 452 }
AnnaBridge 143:86740a56073b 453
AnnaBridge 143:86740a56073b 454 *descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge 143:86740a56073b 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge 143:86740a56073b 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge 143:86740a56073b 457
AnnaBridge 143:86740a56073b 458 return 0;
AnnaBridge 143:86740a56073b 459 }
AnnaBridge 143:86740a56073b 460
AnnaBridge 143:86740a56073b 461 /** \brief Set 4k/64k page shareability
AnnaBridge 143:86740a56073b 462
AnnaBridge 143:86740a56073b 463 The function sets 4k/64k page shareability
AnnaBridge 143:86740a56073b 464
AnnaBridge 143:86740a56073b 465 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 143:86740a56073b 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge 143:86740a56073b 467
AnnaBridge 143:86740a56073b 468 \return 0
AnnaBridge 143:86740a56073b 469 */
AnnaBridge 143:86740a56073b 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge 143:86740a56073b 471 {
AnnaBridge 143:86740a56073b 472 *descriptor_l2 &= PAGE_S_MASK;
AnnaBridge 143:86740a56073b 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge 143:86740a56073b 474 return 0;
AnnaBridge 143:86740a56073b 475 }
AnnaBridge 143:86740a56073b 476
AnnaBridge 143:86740a56073b 477 /** \brief Set 4k/64k page Global attribute
AnnaBridge 143:86740a56073b 478
AnnaBridge 143:86740a56073b 479 The function sets 4k/64k page Global attribute
AnnaBridge 143:86740a56073b 480
AnnaBridge 143:86740a56073b 481 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 143:86740a56073b 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge 143:86740a56073b 483
AnnaBridge 143:86740a56073b 484 \return 0
AnnaBridge 143:86740a56073b 485 */
AnnaBridge 143:86740a56073b 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge 143:86740a56073b 487 {
AnnaBridge 143:86740a56073b 488 *descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge 143:86740a56073b 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge 143:86740a56073b 490 return 0;
AnnaBridge 143:86740a56073b 491 }
AnnaBridge 143:86740a56073b 492
AnnaBridge 143:86740a56073b 493 /** \brief Set 4k/64k page Security attribute
AnnaBridge 143:86740a56073b 494
AnnaBridge 143:86740a56073b 495 The function sets 4k/64k page Global attribute
AnnaBridge 143:86740a56073b 496
AnnaBridge 143:86740a56073b 497 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge 143:86740a56073b 499
AnnaBridge 143:86740a56073b 500 \return 0
AnnaBridge 143:86740a56073b 501 */
AnnaBridge 143:86740a56073b 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 143:86740a56073b 503 {
AnnaBridge 143:86740a56073b 504 *descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge 143:86740a56073b 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge 143:86740a56073b 506 return 0;
AnnaBridge 143:86740a56073b 507 }
AnnaBridge 143:86740a56073b 508
AnnaBridge 143:86740a56073b 509
AnnaBridge 143:86740a56073b 510 /** \brief Set Section memory attributes
AnnaBridge 143:86740a56073b 511
AnnaBridge 143:86740a56073b 512 The function sets section memory attributes
AnnaBridge 143:86740a56073b 513
AnnaBridge 143:86740a56073b 514 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 143:86740a56073b 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 143:86740a56073b 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 143:86740a56073b 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 143:86740a56073b 518
AnnaBridge 143:86740a56073b 519 \return 0
AnnaBridge 143:86740a56073b 520 */
AnnaBridge 143:86740a56073b 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge 143:86740a56073b 522 {
AnnaBridge 143:86740a56073b 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge 143:86740a56073b 524
AnnaBridge 143:86740a56073b 525 if (STRONGLY_ORDERED == mem)
AnnaBridge 143:86740a56073b 526 {
AnnaBridge 143:86740a56073b 527 return 0;
AnnaBridge 143:86740a56073b 528 }
AnnaBridge 143:86740a56073b 529 else if (SHARED_DEVICE == mem)
AnnaBridge 143:86740a56073b 530 {
AnnaBridge 143:86740a56073b 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 143:86740a56073b 532 }
AnnaBridge 143:86740a56073b 533 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 143:86740a56073b 534 {
AnnaBridge 143:86740a56073b 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
AnnaBridge 143:86740a56073b 536 }
AnnaBridge 143:86740a56073b 537 else if (NORMAL == mem)
AnnaBridge 143:86740a56073b 538 {
AnnaBridge 143:86740a56073b 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
AnnaBridge 143:86740a56073b 540 switch(inner)
AnnaBridge 143:86740a56073b 541 {
AnnaBridge 143:86740a56073b 542 case NON_CACHEABLE:
AnnaBridge 143:86740a56073b 543 break;
AnnaBridge 143:86740a56073b 544 case WB_WA:
AnnaBridge 143:86740a56073b 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 143:86740a56073b 546 break;
AnnaBridge 143:86740a56073b 547 case WT:
AnnaBridge 143:86740a56073b 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
AnnaBridge 143:86740a56073b 549 break;
AnnaBridge 143:86740a56073b 550 case WB_NO_WA:
AnnaBridge 143:86740a56073b 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
AnnaBridge 143:86740a56073b 552 break;
AnnaBridge 143:86740a56073b 553 }
AnnaBridge 143:86740a56073b 554 switch(outer)
AnnaBridge 143:86740a56073b 555 {
AnnaBridge 143:86740a56073b 556 case NON_CACHEABLE:
AnnaBridge 143:86740a56073b 557 break;
AnnaBridge 143:86740a56073b 558 case WB_WA:
AnnaBridge 143:86740a56073b 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
AnnaBridge 143:86740a56073b 560 break;
AnnaBridge 143:86740a56073b 561 case WT:
AnnaBridge 143:86740a56073b 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
AnnaBridge 143:86740a56073b 563 break;
AnnaBridge 143:86740a56073b 564 case WB_NO_WA:
AnnaBridge 143:86740a56073b 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
AnnaBridge 143:86740a56073b 566 break;
AnnaBridge 143:86740a56073b 567 }
AnnaBridge 143:86740a56073b 568 }
AnnaBridge 143:86740a56073b 569
AnnaBridge 143:86740a56073b 570 return 0;
AnnaBridge 143:86740a56073b 571 }
AnnaBridge 143:86740a56073b 572
AnnaBridge 143:86740a56073b 573 /** \brief Set 4k/64k page memory attributes
AnnaBridge 143:86740a56073b 574
AnnaBridge 143:86740a56073b 575 The function sets 4k/64k page memory attributes
AnnaBridge 143:86740a56073b 576
AnnaBridge 143:86740a56073b 577 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 143:86740a56073b 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 143:86740a56073b 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 143:86740a56073b 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 143:86740a56073b 581
AnnaBridge 143:86740a56073b 582 \return 0
AnnaBridge 143:86740a56073b 583 */
AnnaBridge 143:86740a56073b 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge 143:86740a56073b 585 {
AnnaBridge 143:86740a56073b 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge 143:86740a56073b 587
AnnaBridge 143:86740a56073b 588 if (page == PAGE_64k)
AnnaBridge 143:86740a56073b 589 {
AnnaBridge 143:86740a56073b 590 //same as section
AnnaBridge 143:86740a56073b 591 __memory_section(descriptor_l2, mem, outer, inner);
AnnaBridge 143:86740a56073b 592 }
AnnaBridge 143:86740a56073b 593 else
AnnaBridge 143:86740a56073b 594 {
AnnaBridge 143:86740a56073b 595 if (STRONGLY_ORDERED == mem)
AnnaBridge 143:86740a56073b 596 {
AnnaBridge 143:86740a56073b 597 return 0;
AnnaBridge 143:86740a56073b 598 }
AnnaBridge 143:86740a56073b 599 else if (SHARED_DEVICE == mem)
AnnaBridge 143:86740a56073b 600 {
AnnaBridge 143:86740a56073b 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 143:86740a56073b 602 }
AnnaBridge 143:86740a56073b 603 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 143:86740a56073b 604 {
AnnaBridge 143:86740a56073b 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge 143:86740a56073b 606 }
AnnaBridge 143:86740a56073b 607 else if (NORMAL == mem)
AnnaBridge 143:86740a56073b 608 {
AnnaBridge 143:86740a56073b 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge 143:86740a56073b 610 switch(inner)
AnnaBridge 143:86740a56073b 611 {
AnnaBridge 143:86740a56073b 612 case NON_CACHEABLE:
AnnaBridge 143:86740a56073b 613 break;
AnnaBridge 143:86740a56073b 614 case WB_WA:
AnnaBridge 143:86740a56073b 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 143:86740a56073b 616 break;
AnnaBridge 143:86740a56073b 617 case WT:
AnnaBridge 143:86740a56073b 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
AnnaBridge 143:86740a56073b 619 break;
AnnaBridge 143:86740a56073b 620 case WB_NO_WA:
AnnaBridge 143:86740a56073b 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
AnnaBridge 143:86740a56073b 622 break;
AnnaBridge 143:86740a56073b 623 }
AnnaBridge 143:86740a56073b 624 switch(outer)
AnnaBridge 143:86740a56073b 625 {
AnnaBridge 143:86740a56073b 626 case NON_CACHEABLE:
AnnaBridge 143:86740a56073b 627 break;
AnnaBridge 143:86740a56073b 628 case WB_WA:
AnnaBridge 143:86740a56073b 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 143:86740a56073b 630 break;
AnnaBridge 143:86740a56073b 631 case WT:
AnnaBridge 143:86740a56073b 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge 143:86740a56073b 633 break;
AnnaBridge 143:86740a56073b 634 case WB_NO_WA:
AnnaBridge 143:86740a56073b 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 143:86740a56073b 636 break;
AnnaBridge 143:86740a56073b 637 }
AnnaBridge 143:86740a56073b 638 }
AnnaBridge 143:86740a56073b 639 }
AnnaBridge 143:86740a56073b 640
AnnaBridge 143:86740a56073b 641 return 0;
AnnaBridge 143:86740a56073b 642 }
AnnaBridge 143:86740a56073b 643
AnnaBridge 143:86740a56073b 644 /** \brief Create a L1 section descriptor
AnnaBridge 143:86740a56073b 645
AnnaBridge 143:86740a56073b 646 The function creates a section descriptor.
AnnaBridge 143:86740a56073b 647
AnnaBridge 143:86740a56073b 648 Assumptions:
AnnaBridge 143:86740a56073b 649 - 16MB super sections not supported
AnnaBridge 143:86740a56073b 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
AnnaBridge 143:86740a56073b 651 - Functions always return 0
AnnaBridge 143:86740a56073b 652
AnnaBridge 143:86740a56073b 653 \param [out] descriptor L1 descriptor
AnnaBridge 143:86740a56073b 654 \param [out] descriptor2 L2 descriptor
AnnaBridge 143:86740a56073b 655 \param [in] reg Section attributes
AnnaBridge 143:86740a56073b 656
AnnaBridge 143:86740a56073b 657 \return 0
AnnaBridge 143:86740a56073b 658 */
AnnaBridge 143:86740a56073b 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge 143:86740a56073b 660 {
AnnaBridge 143:86740a56073b 661 *descriptor = 0;
AnnaBridge 143:86740a56073b 662
AnnaBridge 143:86740a56073b 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge 143:86740a56073b 664 __xn_section(descriptor,reg.xn_t);
AnnaBridge 143:86740a56073b 665 __domain_section(descriptor, reg.domain);
AnnaBridge 143:86740a56073b 666 __p_section(descriptor, reg.e_t);
AnnaBridge 143:86740a56073b 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge 143:86740a56073b 668 __shared_section(descriptor,reg.sh_t);
AnnaBridge 143:86740a56073b 669 __global_section(descriptor,reg.g_t);
AnnaBridge 143:86740a56073b 670 __secure_section(descriptor,reg.sec_t);
AnnaBridge 143:86740a56073b 671 *descriptor &= SECTION_MASK;
AnnaBridge 143:86740a56073b 672 *descriptor |= SECTION_DESCRIPTOR;
AnnaBridge 143:86740a56073b 673
AnnaBridge 143:86740a56073b 674 return 0;
AnnaBridge 143:86740a56073b 675
AnnaBridge 143:86740a56073b 676 }
AnnaBridge 143:86740a56073b 677
AnnaBridge 143:86740a56073b 678
AnnaBridge 143:86740a56073b 679 /** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge 143:86740a56073b 680
AnnaBridge 143:86740a56073b 681 The function creates a 4k/64k page descriptor.
AnnaBridge 143:86740a56073b 682 Assumptions:
AnnaBridge 143:86740a56073b 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
AnnaBridge 143:86740a56073b 684 - Functions always return 0
AnnaBridge 143:86740a56073b 685
AnnaBridge 143:86740a56073b 686 \param [out] descriptor L1 descriptor
AnnaBridge 143:86740a56073b 687 \param [out] descriptor2 L2 descriptor
AnnaBridge 143:86740a56073b 688 \param [in] reg 4k/64k page attributes
AnnaBridge 143:86740a56073b 689
AnnaBridge 143:86740a56073b 690 \return 0
AnnaBridge 143:86740a56073b 691 */
AnnaBridge 143:86740a56073b 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
AnnaBridge 143:86740a56073b 693 {
AnnaBridge 143:86740a56073b 694 *descriptor = 0;
AnnaBridge 143:86740a56073b 695 *descriptor2 = 0;
AnnaBridge 143:86740a56073b 696
AnnaBridge 143:86740a56073b 697 switch (reg.rg_t)
AnnaBridge 143:86740a56073b 698 {
AnnaBridge 143:86740a56073b 699 case PAGE_4k:
AnnaBridge 143:86740a56073b 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge 143:86740a56073b 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge 143:86740a56073b 702 __domain_page(descriptor, reg.domain);
AnnaBridge 143:86740a56073b 703 __p_page(descriptor, reg.e_t);
AnnaBridge 143:86740a56073b 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 143:86740a56073b 705 __shared_page(descriptor2,reg.sh_t);
AnnaBridge 143:86740a56073b 706 __global_page(descriptor2,reg.g_t);
AnnaBridge 143:86740a56073b 707 __secure_page(descriptor,reg.sec_t);
AnnaBridge 143:86740a56073b 708 *descriptor &= PAGE_L1_MASK;
AnnaBridge 143:86740a56073b 709 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 143:86740a56073b 710 *descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge 143:86740a56073b 711 *descriptor2 |= PAGE_L2_4K_DESC;
AnnaBridge 143:86740a56073b 712 break;
AnnaBridge 143:86740a56073b 713
AnnaBridge 143:86740a56073b 714 case PAGE_64k:
AnnaBridge 143:86740a56073b 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge 143:86740a56073b 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge 143:86740a56073b 717 __domain_page(descriptor, reg.domain);
AnnaBridge 143:86740a56073b 718 __p_page(descriptor, reg.e_t);
AnnaBridge 143:86740a56073b 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 143:86740a56073b 720 __shared_page(descriptor2,reg.sh_t);
AnnaBridge 143:86740a56073b 721 __global_page(descriptor2,reg.g_t);
AnnaBridge 143:86740a56073b 722 __secure_page(descriptor,reg.sec_t);
AnnaBridge 143:86740a56073b 723 *descriptor &= PAGE_L1_MASK;
AnnaBridge 143:86740a56073b 724 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 143:86740a56073b 725 *descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge 143:86740a56073b 726 *descriptor2 |= PAGE_L2_64K_DESC;
AnnaBridge 143:86740a56073b 727 break;
AnnaBridge 143:86740a56073b 728
AnnaBridge 143:86740a56073b 729 case SECTION:
AnnaBridge 143:86740a56073b 730 //error
AnnaBridge 143:86740a56073b 731 break;
AnnaBridge 143:86740a56073b 732
AnnaBridge 143:86740a56073b 733 }
AnnaBridge 143:86740a56073b 734
AnnaBridge 143:86740a56073b 735 return 0;
AnnaBridge 143:86740a56073b 736
AnnaBridge 143:86740a56073b 737 }
AnnaBridge 143:86740a56073b 738
AnnaBridge 143:86740a56073b 739 /** \brief Create a 1MB Section
AnnaBridge 143:86740a56073b 740
AnnaBridge 143:86740a56073b 741 \param [in] ttb Translation table base address
AnnaBridge 143:86740a56073b 742 \param [in] base_address Section base address
AnnaBridge 143:86740a56073b 743 \param [in] count Number of sections to create
AnnaBridge 143:86740a56073b 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 143:86740a56073b 745
AnnaBridge 143:86740a56073b 746 */
AnnaBridge 143:86740a56073b 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge 143:86740a56073b 748 {
AnnaBridge 143:86740a56073b 749 uint32_t offset;
AnnaBridge 143:86740a56073b 750 uint32_t entry;
AnnaBridge 143:86740a56073b 751 uint32_t i;
AnnaBridge 143:86740a56073b 752
AnnaBridge 143:86740a56073b 753 offset = base_address >> 20;
AnnaBridge 143:86740a56073b 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
AnnaBridge 143:86740a56073b 755
AnnaBridge 143:86740a56073b 756 //4 bytes aligned
AnnaBridge 143:86740a56073b 757 ttb = ttb + offset;
AnnaBridge 143:86740a56073b 758
AnnaBridge 143:86740a56073b 759 for (i = 0; i < count; i++ )
AnnaBridge 143:86740a56073b 760 {
AnnaBridge 143:86740a56073b 761 //4 bytes aligned
AnnaBridge 143:86740a56073b 762 *ttb++ = entry;
AnnaBridge 143:86740a56073b 763 entry += OFFSET_1M;
AnnaBridge 143:86740a56073b 764 }
AnnaBridge 143:86740a56073b 765 }
AnnaBridge 143:86740a56073b 766
AnnaBridge 143:86740a56073b 767 /** \brief Create a 4k page entry
AnnaBridge 143:86740a56073b 768
AnnaBridge 143:86740a56073b 769 \param [in] ttb L1 table base address
AnnaBridge 143:86740a56073b 770 \param [in] base_address 4k base address
AnnaBridge 143:86740a56073b 771 \param [in] count Number of 4k pages to create
AnnaBridge 143:86740a56073b 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 143:86740a56073b 773 \param [in] ttb_l2 L2 table base address
AnnaBridge 143:86740a56073b 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 143:86740a56073b 775
AnnaBridge 143:86740a56073b 776 */
AnnaBridge 143:86740a56073b 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 143:86740a56073b 778 {
AnnaBridge 143:86740a56073b 779
AnnaBridge 143:86740a56073b 780 uint32_t offset, offset2;
AnnaBridge 143:86740a56073b 781 uint32_t entry, entry2;
AnnaBridge 143:86740a56073b 782 uint32_t i;
AnnaBridge 143:86740a56073b 783
AnnaBridge 143:86740a56073b 784
AnnaBridge 143:86740a56073b 785 offset = base_address >> 20;
AnnaBridge 143:86740a56073b 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 143:86740a56073b 787
AnnaBridge 143:86740a56073b 788 //4 bytes aligned
AnnaBridge 143:86740a56073b 789 ttb += offset;
AnnaBridge 143:86740a56073b 790 //create l1_entry
AnnaBridge 143:86740a56073b 791 *ttb = entry;
AnnaBridge 143:86740a56073b 792
AnnaBridge 143:86740a56073b 793 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 143:86740a56073b 794 ttb_l2 += offset2;
AnnaBridge 143:86740a56073b 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
AnnaBridge 143:86740a56073b 796 for (i = 0; i < count; i++ )
AnnaBridge 143:86740a56073b 797 {
AnnaBridge 143:86740a56073b 798 //4 bytes aligned
AnnaBridge 143:86740a56073b 799 *ttb_l2++ = entry2;
AnnaBridge 143:86740a56073b 800 entry2 += OFFSET_4K;
AnnaBridge 143:86740a56073b 801 }
AnnaBridge 143:86740a56073b 802 }
AnnaBridge 143:86740a56073b 803
AnnaBridge 143:86740a56073b 804 /** \brief Create a 64k page entry
AnnaBridge 143:86740a56073b 805
AnnaBridge 143:86740a56073b 806 \param [in] ttb L1 table base address
AnnaBridge 143:86740a56073b 807 \param [in] base_address 64k base address
AnnaBridge 143:86740a56073b 808 \param [in] count Number of 64k pages to create
AnnaBridge 143:86740a56073b 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 143:86740a56073b 810 \param [in] ttb_l2 L2 table base address
AnnaBridge 143:86740a56073b 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 143:86740a56073b 812
AnnaBridge 143:86740a56073b 813 */
AnnaBridge 143:86740a56073b 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 143:86740a56073b 815 {
AnnaBridge 143:86740a56073b 816 uint32_t offset, offset2;
AnnaBridge 143:86740a56073b 817 uint32_t entry, entry2;
AnnaBridge 143:86740a56073b 818 uint32_t i,j;
AnnaBridge 143:86740a56073b 819
AnnaBridge 143:86740a56073b 820
AnnaBridge 143:86740a56073b 821 offset = base_address >> 20;
AnnaBridge 143:86740a56073b 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 143:86740a56073b 823
AnnaBridge 143:86740a56073b 824 //4 bytes aligned
AnnaBridge 143:86740a56073b 825 ttb += offset;
AnnaBridge 143:86740a56073b 826 //create l1_entry
AnnaBridge 143:86740a56073b 827 *ttb = entry;
AnnaBridge 143:86740a56073b 828
AnnaBridge 143:86740a56073b 829 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 143:86740a56073b 830 ttb_l2 += offset2;
AnnaBridge 143:86740a56073b 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
AnnaBridge 143:86740a56073b 832 for (i = 0; i < count; i++ )
AnnaBridge 143:86740a56073b 833 {
AnnaBridge 143:86740a56073b 834 //create 16 entries
AnnaBridge 143:86740a56073b 835 for (j = 0; j < 16; j++)
AnnaBridge 143:86740a56073b 836 //4 bytes aligned
AnnaBridge 143:86740a56073b 837 *ttb_l2++ = entry2;
AnnaBridge 143:86740a56073b 838 entry2 += OFFSET_64K;
AnnaBridge 143:86740a56073b 839 }
AnnaBridge 143:86740a56073b 840 }
AnnaBridge 143:86740a56073b 841
AnnaBridge 143:86740a56073b 842 /*@} end of MMU_Functions */
AnnaBridge 143:86740a56073b 843 #endif
AnnaBridge 143:86740a56073b 844
AnnaBridge 143:86740a56073b 845 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 846 }
AnnaBridge 143:86740a56073b 847 #endif