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TARGET_KL27Z/core_cm4.h@120:7c328cabac7e, 2016-05-10 (annotated)

Committer:: Kojto
Date:: Tue May 10 12:23:43 2016 -0500
Revision:: 120:7c328cabac7e
Child:: 122:f9eeca106725

Release 120 of the mbed library



Changes:

- ST - STMF3XX/F4XX - directories removal

     - STMF3 - pwm range fix

     - STMF1 - Cube driver update

- Renesas - RZ_A1H - async i2c, serial and spi addition

- Freescale - KSDK2 update

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	120:7c328cabac7e	1	/************************************************************************//
Kojto	120:7c328cabac7e	2	* @file core_cm4.h
Kojto	120:7c328cabac7e	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Kojto	120:7c328cabac7e	4	* @version V4.10
Kojto	120:7c328cabac7e	5	* @date 18. March 2015
Kojto	120:7c328cabac7e	6	*
Kojto	120:7c328cabac7e	7	* @note
Kojto	120:7c328cabac7e	8	*
Kojto	120:7c328cabac7e	9	******************************************************************************/
Kojto	120:7c328cabac7e	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto	120:7c328cabac7e	11
Kojto	120:7c328cabac7e	12	All rights reserved.
Kojto	120:7c328cabac7e	13	Redistribution and use in source and binary forms, with or without
Kojto	120:7c328cabac7e	14	modification, are permitted provided that the following conditions are met:
Kojto	120:7c328cabac7e	15	- Redistributions of source code must retain the above copyright
Kojto	120:7c328cabac7e	16	notice, this list of conditions and the following disclaimer.
Kojto	120:7c328cabac7e	17	- Redistributions in binary form must reproduce the above copyright
Kojto	120:7c328cabac7e	18	notice, this list of conditions and the following disclaimer in the
Kojto	120:7c328cabac7e	19	documentation and/or other materials provided with the distribution.
Kojto	120:7c328cabac7e	20	- Neither the name of ARM nor the names of its contributors may be used
Kojto	120:7c328cabac7e	21	to endorse or promote products derived from this software without
Kojto	120:7c328cabac7e	22	specific prior written permission.
Kojto	120:7c328cabac7e	23	*
Kojto	120:7c328cabac7e	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	120:7c328cabac7e	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	120:7c328cabac7e	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto	120:7c328cabac7e	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto	120:7c328cabac7e	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto	120:7c328cabac7e	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto	120:7c328cabac7e	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto	120:7c328cabac7e	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto	120:7c328cabac7e	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto	120:7c328cabac7e	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto	120:7c328cabac7e	34	POSSIBILITY OF SUCH DAMAGE.
Kojto	120:7c328cabac7e	35	---------------------------------------------------------------------------*/
Kojto	120:7c328cabac7e	36
Kojto	120:7c328cabac7e	37
Kojto	120:7c328cabac7e	38	#if defined ( __ICCARM__ )
Kojto	120:7c328cabac7e	39	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	120:7c328cabac7e	40	#endif
Kojto	120:7c328cabac7e	41
Kojto	120:7c328cabac7e	42	#ifndef __CORE_CM4_H_GENERIC
Kojto	120:7c328cabac7e	43	#define __CORE_CM4_H_GENERIC
Kojto	120:7c328cabac7e	44
Kojto	120:7c328cabac7e	45	#ifdef __cplusplus
Kojto	120:7c328cabac7e	46	extern "C" {
Kojto	120:7c328cabac7e	47	#endif
Kojto	120:7c328cabac7e	48
Kojto	120:7c328cabac7e	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	120:7c328cabac7e	50	CMSIS violates the following MISRA-C:2004 rules:
Kojto	120:7c328cabac7e	51
Kojto	120:7c328cabac7e	52	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	120:7c328cabac7e	53	Function definitions in header files are used to allow 'inlining'.
Kojto	120:7c328cabac7e	54
Kojto	120:7c328cabac7e	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	120:7c328cabac7e	56	Unions are used for effective representation of core registers.
Kojto	120:7c328cabac7e	57
Kojto	120:7c328cabac7e	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	120:7c328cabac7e	59	Function-like macros are used to allow more efficient code.
Kojto	120:7c328cabac7e	60	*/
Kojto	120:7c328cabac7e	61
Kojto	120:7c328cabac7e	62
Kojto	120:7c328cabac7e	63	/*******************************************************************************
Kojto	120:7c328cabac7e	64	* CMSIS definitions
Kojto	120:7c328cabac7e	65	******************************************************************************/
Kojto	120:7c328cabac7e	66	/** \ingroup Cortex_M4
Kojto	120:7c328cabac7e	67	@{
Kojto	120:7c328cabac7e	68	*/
Kojto	120:7c328cabac7e	69
Kojto	120:7c328cabac7e	70	/* CMSIS CM4 definitions */
Kojto	120:7c328cabac7e	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	120:7c328cabac7e	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Kojto	120:7c328cabac7e	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
Kojto	120:7c328cabac7e	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Kojto	120:7c328cabac7e	75
Kojto	120:7c328cabac7e	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
Kojto	120:7c328cabac7e	77
Kojto	120:7c328cabac7e	78
Kojto	120:7c328cabac7e	79	#if defined ( __CC_ARM )
Kojto	120:7c328cabac7e	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Kojto	120:7c328cabac7e	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Kojto	120:7c328cabac7e	82	#define __STATIC_INLINE static __inline
Kojto	120:7c328cabac7e	83
Kojto	120:7c328cabac7e	84	#elif defined ( __GNUC__ )
Kojto	120:7c328cabac7e	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	120:7c328cabac7e	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	120:7c328cabac7e	87	#define __STATIC_INLINE static inline
Kojto	120:7c328cabac7e	88
Kojto	120:7c328cabac7e	89	#elif defined ( __ICCARM__ )
Kojto	120:7c328cabac7e	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Kojto	120:7c328cabac7e	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Kojto	120:7c328cabac7e	92	#define __STATIC_INLINE static inline
Kojto	120:7c328cabac7e	93
Kojto	120:7c328cabac7e	94	#elif defined ( __TMS470__ )
Kojto	120:7c328cabac7e	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Kojto	120:7c328cabac7e	96	#define __STATIC_INLINE static inline
Kojto	120:7c328cabac7e	97
Kojto	120:7c328cabac7e	98	#elif defined ( __TASKING__ )
Kojto	120:7c328cabac7e	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Kojto	120:7c328cabac7e	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Kojto	120:7c328cabac7e	101	#define __STATIC_INLINE static inline
Kojto	120:7c328cabac7e	102
Kojto	120:7c328cabac7e	103	#elif defined ( __CSMC__ )
Kojto	120:7c328cabac7e	104	#define __packed
Kojto	120:7c328cabac7e	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	120:7c328cabac7e	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	120:7c328cabac7e	107	#define __STATIC_INLINE static inline
Kojto	120:7c328cabac7e	108
Kojto	120:7c328cabac7e	109	#endif
Kojto	120:7c328cabac7e	110
Kojto	120:7c328cabac7e	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	120:7c328cabac7e	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto	120:7c328cabac7e	113	*/
Kojto	120:7c328cabac7e	114	#if defined ( __CC_ARM )
Kojto	120:7c328cabac7e	115	#if defined __TARGET_FPU_VFP
Kojto	120:7c328cabac7e	116	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	117	#define __FPU_USED 1
Kojto	120:7c328cabac7e	118	#else
Kojto	120:7c328cabac7e	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	120:7c328cabac7e	120	#define __FPU_USED 0
Kojto	120:7c328cabac7e	121	#endif
Kojto	120:7c328cabac7e	122	#else
Kojto	120:7c328cabac7e	123	#define __FPU_USED 0
Kojto	120:7c328cabac7e	124	#endif
Kojto	120:7c328cabac7e	125
Kojto	120:7c328cabac7e	126	#elif defined ( __GNUC__ )
Kojto	120:7c328cabac7e	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	120:7c328cabac7e	128	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	129	#define __FPU_USED 1
Kojto	120:7c328cabac7e	130	#else
Kojto	120:7c328cabac7e	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	120:7c328cabac7e	132	#define __FPU_USED 0
Kojto	120:7c328cabac7e	133	#endif
Kojto	120:7c328cabac7e	134	#else
Kojto	120:7c328cabac7e	135	#define __FPU_USED 0
Kojto	120:7c328cabac7e	136	#endif
Kojto	120:7c328cabac7e	137
Kojto	120:7c328cabac7e	138	#elif defined ( __ICCARM__ )
Kojto	120:7c328cabac7e	139	#if defined __ARMVFP__
Kojto	120:7c328cabac7e	140	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	141	#define __FPU_USED 1
Kojto	120:7c328cabac7e	142	#else
Kojto	120:7c328cabac7e	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	120:7c328cabac7e	144	#define __FPU_USED 0
Kojto	120:7c328cabac7e	145	#endif
Kojto	120:7c328cabac7e	146	#else
Kojto	120:7c328cabac7e	147	#define __FPU_USED 0
Kojto	120:7c328cabac7e	148	#endif
Kojto	120:7c328cabac7e	149
Kojto	120:7c328cabac7e	150	#elif defined ( __TMS470__ )
Kojto	120:7c328cabac7e	151	#if defined __TI_VFP_SUPPORT__
Kojto	120:7c328cabac7e	152	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	153	#define __FPU_USED 1
Kojto	120:7c328cabac7e	154	#else
Kojto	120:7c328cabac7e	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	120:7c328cabac7e	156	#define __FPU_USED 0
Kojto	120:7c328cabac7e	157	#endif
Kojto	120:7c328cabac7e	158	#else
Kojto	120:7c328cabac7e	159	#define __FPU_USED 0
Kojto	120:7c328cabac7e	160	#endif
Kojto	120:7c328cabac7e	161
Kojto	120:7c328cabac7e	162	#elif defined ( __TASKING__ )
Kojto	120:7c328cabac7e	163	#if defined __FPU_VFP__
Kojto	120:7c328cabac7e	164	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	165	#define __FPU_USED 1
Kojto	120:7c328cabac7e	166	#else
Kojto	120:7c328cabac7e	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	120:7c328cabac7e	168	#define __FPU_USED 0
Kojto	120:7c328cabac7e	169	#endif
Kojto	120:7c328cabac7e	170	#else
Kojto	120:7c328cabac7e	171	#define __FPU_USED 0
Kojto	120:7c328cabac7e	172	#endif
Kojto	120:7c328cabac7e	173
Kojto	120:7c328cabac7e	174	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	120:7c328cabac7e	175	#if ( __CSMC__ & 0x400) // FPU present for parser
Kojto	120:7c328cabac7e	176	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	177	#define __FPU_USED 1
Kojto	120:7c328cabac7e	178	#else
Kojto	120:7c328cabac7e	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	120:7c328cabac7e	180	#define __FPU_USED 0
Kojto	120:7c328cabac7e	181	#endif
Kojto	120:7c328cabac7e	182	#else
Kojto	120:7c328cabac7e	183	#define __FPU_USED 0
Kojto	120:7c328cabac7e	184	#endif
Kojto	120:7c328cabac7e	185	#endif
Kojto	120:7c328cabac7e	186
Kojto	120:7c328cabac7e	187	#include <stdint.h> /* standard types definitions */
Kojto	120:7c328cabac7e	188	#include <core_cmInstr.h> /* Core Instruction Access */
Kojto	120:7c328cabac7e	189	#include <core_cmFunc.h> /* Core Function Access */
Kojto	120:7c328cabac7e	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto	120:7c328cabac7e	191
Kojto	120:7c328cabac7e	192	#ifdef __cplusplus
Kojto	120:7c328cabac7e	193	}
Kojto	120:7c328cabac7e	194	#endif
Kojto	120:7c328cabac7e	195
Kojto	120:7c328cabac7e	196	#endif /* __CORE_CM4_H_GENERIC */
Kojto	120:7c328cabac7e	197
Kojto	120:7c328cabac7e	198	#ifndef __CMSIS_GENERIC
Kojto	120:7c328cabac7e	199
Kojto	120:7c328cabac7e	200	#ifndef __CORE_CM4_H_DEPENDANT
Kojto	120:7c328cabac7e	201	#define __CORE_CM4_H_DEPENDANT
Kojto	120:7c328cabac7e	202
Kojto	120:7c328cabac7e	203	#ifdef __cplusplus
Kojto	120:7c328cabac7e	204	extern "C" {
Kojto	120:7c328cabac7e	205	#endif
Kojto	120:7c328cabac7e	206
Kojto	120:7c328cabac7e	207	/* check device defines and use defaults */
Kojto	120:7c328cabac7e	208	#if defined __CHECK_DEVICE_DEFINES
Kojto	120:7c328cabac7e	209	#ifndef __CM4_REV
Kojto	120:7c328cabac7e	210	#define __CM4_REV 0x0000
Kojto	120:7c328cabac7e	211	#warning "__CM4_REV not defined in device header file; using default!"
Kojto	120:7c328cabac7e	212	#endif
Kojto	120:7c328cabac7e	213
Kojto	120:7c328cabac7e	214	#ifndef __FPU_PRESENT
Kojto	120:7c328cabac7e	215	#define __FPU_PRESENT 0
Kojto	120:7c328cabac7e	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto	120:7c328cabac7e	217	#endif
Kojto	120:7c328cabac7e	218
Kojto	120:7c328cabac7e	219	#ifndef __MPU_PRESENT
Kojto	120:7c328cabac7e	220	#define __MPU_PRESENT 0
Kojto	120:7c328cabac7e	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	120:7c328cabac7e	222	#endif
Kojto	120:7c328cabac7e	223
Kojto	120:7c328cabac7e	224	#ifndef __NVIC_PRIO_BITS
Kojto	120:7c328cabac7e	225	#define __NVIC_PRIO_BITS 4
Kojto	120:7c328cabac7e	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	120:7c328cabac7e	227	#endif
Kojto	120:7c328cabac7e	228
Kojto	120:7c328cabac7e	229	#ifndef __Vendor_SysTickConfig
Kojto	120:7c328cabac7e	230	#define __Vendor_SysTickConfig 0
Kojto	120:7c328cabac7e	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	120:7c328cabac7e	232	#endif
Kojto	120:7c328cabac7e	233	#endif
Kojto	120:7c328cabac7e	234
Kojto	120:7c328cabac7e	235	/* IO definitions (access restrictions to peripheral registers) */
Kojto	120:7c328cabac7e	236	/**
Kojto	120:7c328cabac7e	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	120:7c328cabac7e	238
Kojto	120:7c328cabac7e	239	<strong>IO Type Qualifiers</strong> are used
Kojto	120:7c328cabac7e	240	\li to specify the access to peripheral variables.
Kojto	120:7c328cabac7e	241	\li for automatic generation of peripheral register debug information.
Kojto	120:7c328cabac7e	242	*/
Kojto	120:7c328cabac7e	243	#ifdef __cplusplus
Kojto	120:7c328cabac7e	244	#define __I volatile /!< Defines 'read only' permissions /
Kojto	120:7c328cabac7e	245	#else
Kojto	120:7c328cabac7e	246	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	120:7c328cabac7e	247	#endif
Kojto	120:7c328cabac7e	248	#define __O volatile /!< Defines 'write only' permissions /
Kojto	120:7c328cabac7e	249	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	120:7c328cabac7e	250
Kojto	120:7c328cabac7e	251	/@} end of group Cortex_M4 /
Kojto	120:7c328cabac7e	252
Kojto	120:7c328cabac7e	253
Kojto	120:7c328cabac7e	254
Kojto	120:7c328cabac7e	255	/*******************************************************************************
Kojto	120:7c328cabac7e	256	* Register Abstraction
Kojto	120:7c328cabac7e	257	Core Register contain:
Kojto	120:7c328cabac7e	258	- Core Register
Kojto	120:7c328cabac7e	259	- Core NVIC Register
Kojto	120:7c328cabac7e	260	- Core SCB Register
Kojto	120:7c328cabac7e	261	- Core SysTick Register
Kojto	120:7c328cabac7e	262	- Core Debug Register
Kojto	120:7c328cabac7e	263	- Core MPU Register
Kojto	120:7c328cabac7e	264	- Core FPU Register
Kojto	120:7c328cabac7e	265	******************************************************************************/
Kojto	120:7c328cabac7e	266	/** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto	120:7c328cabac7e	267	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	120:7c328cabac7e	268	*/
Kojto	120:7c328cabac7e	269
Kojto	120:7c328cabac7e	270	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	271	\defgroup CMSIS_CORE Status and Control Registers
Kojto	120:7c328cabac7e	272	\brief Core Register type definitions.
Kojto	120:7c328cabac7e	273	@{
Kojto	120:7c328cabac7e	274	*/
Kojto	120:7c328cabac7e	275
Kojto	120:7c328cabac7e	276	/** \brief Union type to access the Application Program Status Register (APSR).
Kojto	120:7c328cabac7e	277	*/
Kojto	120:7c328cabac7e	278	typedef union
Kojto	120:7c328cabac7e	279	{
Kojto	120:7c328cabac7e	280	struct
Kojto	120:7c328cabac7e	281	{
Kojto	120:7c328cabac7e	282	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Kojto	120:7c328cabac7e	283	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	120:7c328cabac7e	284	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Kojto	120:7c328cabac7e	285	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	120:7c328cabac7e	286	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	120:7c328cabac7e	287	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	120:7c328cabac7e	288	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	120:7c328cabac7e	289	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	120:7c328cabac7e	290	} b; /!< Structure used for bit access /
Kojto	120:7c328cabac7e	291	uint32_t w; /!< Type used for word access /
Kojto	120:7c328cabac7e	292	} APSR_Type;
Kojto	120:7c328cabac7e	293
Kojto	120:7c328cabac7e	294	/* APSR Register Definitions */
Kojto	120:7c328cabac7e	295	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	120:7c328cabac7e	296	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	120:7c328cabac7e	297
Kojto	120:7c328cabac7e	298	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	120:7c328cabac7e	299	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	120:7c328cabac7e	300
Kojto	120:7c328cabac7e	301	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	120:7c328cabac7e	302	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	120:7c328cabac7e	303
Kojto	120:7c328cabac7e	304	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	120:7c328cabac7e	305	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	120:7c328cabac7e	306
Kojto	120:7c328cabac7e	307	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	120:7c328cabac7e	308	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	120:7c328cabac7e	309
Kojto	120:7c328cabac7e	310	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Kojto	120:7c328cabac7e	311	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Kojto	120:7c328cabac7e	312
Kojto	120:7c328cabac7e	313
Kojto	120:7c328cabac7e	314	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	120:7c328cabac7e	315	*/
Kojto	120:7c328cabac7e	316	typedef union
Kojto	120:7c328cabac7e	317	{
Kojto	120:7c328cabac7e	318	struct
Kojto	120:7c328cabac7e	319	{
Kojto	120:7c328cabac7e	320	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	120:7c328cabac7e	321	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	120:7c328cabac7e	322	} b; /!< Structure used for bit access /
Kojto	120:7c328cabac7e	323	uint32_t w; /!< Type used for word access /
Kojto	120:7c328cabac7e	324	} IPSR_Type;
Kojto	120:7c328cabac7e	325
Kojto	120:7c328cabac7e	326	/* IPSR Register Definitions */
Kojto	120:7c328cabac7e	327	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	120:7c328cabac7e	328	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	120:7c328cabac7e	329
Kojto	120:7c328cabac7e	330
Kojto	120:7c328cabac7e	331	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	120:7c328cabac7e	332	*/
Kojto	120:7c328cabac7e	333	typedef union
Kojto	120:7c328cabac7e	334	{
Kojto	120:7c328cabac7e	335	struct
Kojto	120:7c328cabac7e	336	{
Kojto	120:7c328cabac7e	337	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	120:7c328cabac7e	338	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Kojto	120:7c328cabac7e	339	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	120:7c328cabac7e	340	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Kojto	120:7c328cabac7e	341	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	120:7c328cabac7e	342	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	120:7c328cabac7e	343	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	120:7c328cabac7e	344	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	120:7c328cabac7e	345	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	120:7c328cabac7e	346	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	120:7c328cabac7e	347	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	120:7c328cabac7e	348	} b; /!< Structure used for bit access /
Kojto	120:7c328cabac7e	349	uint32_t w; /!< Type used for word access /
Kojto	120:7c328cabac7e	350	} xPSR_Type;
Kojto	120:7c328cabac7e	351
Kojto	120:7c328cabac7e	352	/* xPSR Register Definitions */
Kojto	120:7c328cabac7e	353	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	120:7c328cabac7e	354	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	120:7c328cabac7e	355
Kojto	120:7c328cabac7e	356	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	120:7c328cabac7e	357	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	120:7c328cabac7e	358
Kojto	120:7c328cabac7e	359	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	120:7c328cabac7e	360	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	120:7c328cabac7e	361
Kojto	120:7c328cabac7e	362	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	120:7c328cabac7e	363	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	120:7c328cabac7e	364
Kojto	120:7c328cabac7e	365	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	120:7c328cabac7e	366	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	120:7c328cabac7e	367
Kojto	120:7c328cabac7e	368	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	120:7c328cabac7e	369	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	120:7c328cabac7e	370
Kojto	120:7c328cabac7e	371	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	120:7c328cabac7e	372	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	120:7c328cabac7e	373
Kojto	120:7c328cabac7e	374	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Kojto	120:7c328cabac7e	375	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Kojto	120:7c328cabac7e	376
Kojto	120:7c328cabac7e	377	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	120:7c328cabac7e	378	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	120:7c328cabac7e	379
Kojto	120:7c328cabac7e	380
Kojto	120:7c328cabac7e	381	/** \brief Union type to access the Control Registers (CONTROL).
Kojto	120:7c328cabac7e	382	*/
Kojto	120:7c328cabac7e	383	typedef union
Kojto	120:7c328cabac7e	384	{
Kojto	120:7c328cabac7e	385	struct
Kojto	120:7c328cabac7e	386	{
Kojto	120:7c328cabac7e	387	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	120:7c328cabac7e	388	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	120:7c328cabac7e	389	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Kojto	120:7c328cabac7e	390	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Kojto	120:7c328cabac7e	391	} b; /!< Structure used for bit access /
Kojto	120:7c328cabac7e	392	uint32_t w; /!< Type used for word access /
Kojto	120:7c328cabac7e	393	} CONTROL_Type;
Kojto	120:7c328cabac7e	394
Kojto	120:7c328cabac7e	395	/* CONTROL Register Definitions */
Kojto	120:7c328cabac7e	396	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Kojto	120:7c328cabac7e	397	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Kojto	120:7c328cabac7e	398
Kojto	120:7c328cabac7e	399	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	120:7c328cabac7e	400	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	120:7c328cabac7e	401
Kojto	120:7c328cabac7e	402	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	120:7c328cabac7e	403	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	120:7c328cabac7e	404
Kojto	120:7c328cabac7e	405	/@} end of group CMSIS_CORE /
Kojto	120:7c328cabac7e	406
Kojto	120:7c328cabac7e	407
Kojto	120:7c328cabac7e	408	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	409	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	120:7c328cabac7e	410	\brief Type definitions for the NVIC Registers
Kojto	120:7c328cabac7e	411	@{
Kojto	120:7c328cabac7e	412	*/
Kojto	120:7c328cabac7e	413
Kojto	120:7c328cabac7e	414	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	120:7c328cabac7e	415	*/
Kojto	120:7c328cabac7e	416	typedef struct
Kojto	120:7c328cabac7e	417	{
Kojto	120:7c328cabac7e	418	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	120:7c328cabac7e	419	uint32_t RESERVED0[24];
Kojto	120:7c328cabac7e	420	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	120:7c328cabac7e	421	uint32_t RSERVED1[24];
Kojto	120:7c328cabac7e	422	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	120:7c328cabac7e	423	uint32_t RESERVED2[24];
Kojto	120:7c328cabac7e	424	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	120:7c328cabac7e	425	uint32_t RESERVED3[24];
Kojto	120:7c328cabac7e	426	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	120:7c328cabac7e	427	uint32_t RESERVED4[56];
Kojto	120:7c328cabac7e	428	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	120:7c328cabac7e	429	uint32_t RESERVED5[644];
Kojto	120:7c328cabac7e	430	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	120:7c328cabac7e	431	} NVIC_Type;
Kojto	120:7c328cabac7e	432
Kojto	120:7c328cabac7e	433	/* Software Triggered Interrupt Register Definitions */
Kojto	120:7c328cabac7e	434	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	120:7c328cabac7e	435	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Kojto	120:7c328cabac7e	436
Kojto	120:7c328cabac7e	437	/@} end of group CMSIS_NVIC /
Kojto	120:7c328cabac7e	438
Kojto	120:7c328cabac7e	439
Kojto	120:7c328cabac7e	440	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	441	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	120:7c328cabac7e	442	\brief Type definitions for the System Control Block Registers
Kojto	120:7c328cabac7e	443	@{
Kojto	120:7c328cabac7e	444	*/
Kojto	120:7c328cabac7e	445
Kojto	120:7c328cabac7e	446	/** \brief Structure type to access the System Control Block (SCB).
Kojto	120:7c328cabac7e	447	*/
Kojto	120:7c328cabac7e	448	typedef struct
Kojto	120:7c328cabac7e	449	{
Kojto	120:7c328cabac7e	450	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	120:7c328cabac7e	451	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	120:7c328cabac7e	452	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	120:7c328cabac7e	453	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	120:7c328cabac7e	454	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	120:7c328cabac7e	455	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	120:7c328cabac7e	456	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	120:7c328cabac7e	457	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	120:7c328cabac7e	458	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	120:7c328cabac7e	459	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	120:7c328cabac7e	460	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	120:7c328cabac7e	461	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	120:7c328cabac7e	462	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	120:7c328cabac7e	463	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	120:7c328cabac7e	464	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	120:7c328cabac7e	465	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	120:7c328cabac7e	466	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	120:7c328cabac7e	467	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	120:7c328cabac7e	468	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	120:7c328cabac7e	469	uint32_t RESERVED0[5];
Kojto	120:7c328cabac7e	470	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	120:7c328cabac7e	471	} SCB_Type;
Kojto	120:7c328cabac7e	472
Kojto	120:7c328cabac7e	473	/* SCB CPUID Register Definitions */
Kojto	120:7c328cabac7e	474	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Kojto	120:7c328cabac7e	475	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	120:7c328cabac7e	476
Kojto	120:7c328cabac7e	477	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Kojto	120:7c328cabac7e	478	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	120:7c328cabac7e	479
Kojto	120:7c328cabac7e	480	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Kojto	120:7c328cabac7e	481	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	120:7c328cabac7e	482
Kojto	120:7c328cabac7e	483	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Kojto	120:7c328cabac7e	484	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	120:7c328cabac7e	485
Kojto	120:7c328cabac7e	486	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	120:7c328cabac7e	487	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Kojto	120:7c328cabac7e	488
Kojto	120:7c328cabac7e	489	/* SCB Interrupt Control State Register Definitions */
Kojto	120:7c328cabac7e	490	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Kojto	120:7c328cabac7e	491	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Kojto	120:7c328cabac7e	492
Kojto	120:7c328cabac7e	493	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Kojto	120:7c328cabac7e	494	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	120:7c328cabac7e	495
Kojto	120:7c328cabac7e	496	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Kojto	120:7c328cabac7e	497	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	120:7c328cabac7e	498
Kojto	120:7c328cabac7e	499	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Kojto	120:7c328cabac7e	500	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	120:7c328cabac7e	501
Kojto	120:7c328cabac7e	502	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Kojto	120:7c328cabac7e	503	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	120:7c328cabac7e	504
Kojto	120:7c328cabac7e	505	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Kojto	120:7c328cabac7e	506	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	120:7c328cabac7e	507
Kojto	120:7c328cabac7e	508	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Kojto	120:7c328cabac7e	509	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	120:7c328cabac7e	510
Kojto	120:7c328cabac7e	511	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Kojto	120:7c328cabac7e	512	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	120:7c328cabac7e	513
Kojto	120:7c328cabac7e	514	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Kojto	120:7c328cabac7e	515	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	120:7c328cabac7e	516
Kojto	120:7c328cabac7e	517	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	120:7c328cabac7e	518	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	120:7c328cabac7e	519
Kojto	120:7c328cabac7e	520	/* SCB Vector Table Offset Register Definitions */
Kojto	120:7c328cabac7e	521	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	120:7c328cabac7e	522	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	120:7c328cabac7e	523
Kojto	120:7c328cabac7e	524	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	120:7c328cabac7e	525	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Kojto	120:7c328cabac7e	526	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	120:7c328cabac7e	527
Kojto	120:7c328cabac7e	528	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	120:7c328cabac7e	529	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	120:7c328cabac7e	530
Kojto	120:7c328cabac7e	531	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Kojto	120:7c328cabac7e	532	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	120:7c328cabac7e	533
Kojto	120:7c328cabac7e	534	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Kojto	120:7c328cabac7e	535	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	120:7c328cabac7e	536
Kojto	120:7c328cabac7e	537	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	120:7c328cabac7e	538	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	120:7c328cabac7e	539
Kojto	120:7c328cabac7e	540	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	120:7c328cabac7e	541	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	120:7c328cabac7e	542
Kojto	120:7c328cabac7e	543	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	120:7c328cabac7e	544	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Kojto	120:7c328cabac7e	545
Kojto	120:7c328cabac7e	546	/* SCB System Control Register Definitions */
Kojto	120:7c328cabac7e	547	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Kojto	120:7c328cabac7e	548	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	120:7c328cabac7e	549
Kojto	120:7c328cabac7e	550	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Kojto	120:7c328cabac7e	551	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	120:7c328cabac7e	552
Kojto	120:7c328cabac7e	553	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Kojto	120:7c328cabac7e	554	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	120:7c328cabac7e	555
Kojto	120:7c328cabac7e	556	/* SCB Configuration Control Register Definitions */
Kojto	120:7c328cabac7e	557	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Kojto	120:7c328cabac7e	558	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Kojto	120:7c328cabac7e	559
Kojto	120:7c328cabac7e	560	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Kojto	120:7c328cabac7e	561	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	120:7c328cabac7e	562
Kojto	120:7c328cabac7e	563	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Kojto	120:7c328cabac7e	564	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	120:7c328cabac7e	565
Kojto	120:7c328cabac7e	566	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Kojto	120:7c328cabac7e	567	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	120:7c328cabac7e	568
Kojto	120:7c328cabac7e	569	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Kojto	120:7c328cabac7e	570	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	120:7c328cabac7e	571
Kojto	120:7c328cabac7e	572	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	120:7c328cabac7e	573	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Kojto	120:7c328cabac7e	574
Kojto	120:7c328cabac7e	575	/* SCB System Handler Control and State Register Definitions */
Kojto	120:7c328cabac7e	576	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Kojto	120:7c328cabac7e	577	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	120:7c328cabac7e	578
Kojto	120:7c328cabac7e	579	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	120:7c328cabac7e	580	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	120:7c328cabac7e	581
Kojto	120:7c328cabac7e	582	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	120:7c328cabac7e	583	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	120:7c328cabac7e	584
Kojto	120:7c328cabac7e	585	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	120:7c328cabac7e	586	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	120:7c328cabac7e	587
Kojto	120:7c328cabac7e	588	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	120:7c328cabac7e	589	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	120:7c328cabac7e	590
Kojto	120:7c328cabac7e	591	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	120:7c328cabac7e	592	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	120:7c328cabac7e	593
Kojto	120:7c328cabac7e	594	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	120:7c328cabac7e	595	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	120:7c328cabac7e	596
Kojto	120:7c328cabac7e	597	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Kojto	120:7c328cabac7e	598	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	120:7c328cabac7e	599
Kojto	120:7c328cabac7e	600	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Kojto	120:7c328cabac7e	601	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	120:7c328cabac7e	602
Kojto	120:7c328cabac7e	603	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Kojto	120:7c328cabac7e	604	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	120:7c328cabac7e	605
Kojto	120:7c328cabac7e	606	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Kojto	120:7c328cabac7e	607	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	120:7c328cabac7e	608
Kojto	120:7c328cabac7e	609	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Kojto	120:7c328cabac7e	610	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	120:7c328cabac7e	611
Kojto	120:7c328cabac7e	612	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	120:7c328cabac7e	613	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	120:7c328cabac7e	614
Kojto	120:7c328cabac7e	615	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	120:7c328cabac7e	616	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	120:7c328cabac7e	617
Kojto	120:7c328cabac7e	618	/* SCB Configurable Fault Status Registers Definitions */
Kojto	120:7c328cabac7e	619	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	120:7c328cabac7e	620	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	120:7c328cabac7e	621
Kojto	120:7c328cabac7e	622	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	120:7c328cabac7e	623	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	120:7c328cabac7e	624
Kojto	120:7c328cabac7e	625	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	120:7c328cabac7e	626	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	120:7c328cabac7e	627
Kojto	120:7c328cabac7e	628	/* SCB Hard Fault Status Registers Definitions */
Kojto	120:7c328cabac7e	629	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Kojto	120:7c328cabac7e	630	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	120:7c328cabac7e	631
Kojto	120:7c328cabac7e	632	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Kojto	120:7c328cabac7e	633	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	120:7c328cabac7e	634
Kojto	120:7c328cabac7e	635	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Kojto	120:7c328cabac7e	636	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	120:7c328cabac7e	637
Kojto	120:7c328cabac7e	638	/* SCB Debug Fault Status Register Definitions */
Kojto	120:7c328cabac7e	639	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Kojto	120:7c328cabac7e	640	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	120:7c328cabac7e	641
Kojto	120:7c328cabac7e	642	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Kojto	120:7c328cabac7e	643	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	120:7c328cabac7e	644
Kojto	120:7c328cabac7e	645	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Kojto	120:7c328cabac7e	646	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	120:7c328cabac7e	647
Kojto	120:7c328cabac7e	648	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Kojto	120:7c328cabac7e	649	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	120:7c328cabac7e	650
Kojto	120:7c328cabac7e	651	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	120:7c328cabac7e	652	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Kojto	120:7c328cabac7e	653
Kojto	120:7c328cabac7e	654	/@} end of group CMSIS_SCB /
Kojto	120:7c328cabac7e	655
Kojto	120:7c328cabac7e	656
Kojto	120:7c328cabac7e	657	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	658	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	120:7c328cabac7e	659	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	120:7c328cabac7e	660	@{
Kojto	120:7c328cabac7e	661	*/
Kojto	120:7c328cabac7e	662
Kojto	120:7c328cabac7e	663	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	120:7c328cabac7e	664	*/
Kojto	120:7c328cabac7e	665	typedef struct
Kojto	120:7c328cabac7e	666	{
Kojto	120:7c328cabac7e	667	uint32_t RESERVED0[1];
Kojto	120:7c328cabac7e	668	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	120:7c328cabac7e	669	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Kojto	120:7c328cabac7e	670	} SCnSCB_Type;
Kojto	120:7c328cabac7e	671
Kojto	120:7c328cabac7e	672	/* Interrupt Controller Type Register Definitions */
Kojto	120:7c328cabac7e	673	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	120:7c328cabac7e	674	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Kojto	120:7c328cabac7e	675
Kojto	120:7c328cabac7e	676	/* Auxiliary Control Register Definitions */
Kojto	120:7c328cabac7e	677	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
Kojto	120:7c328cabac7e	678	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
Kojto	120:7c328cabac7e	679
Kojto	120:7c328cabac7e	680	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
Kojto	120:7c328cabac7e	681	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
Kojto	120:7c328cabac7e	682
Kojto	120:7c328cabac7e	683	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Kojto	120:7c328cabac7e	684	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Kojto	120:7c328cabac7e	685
Kojto	120:7c328cabac7e	686	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Kojto	120:7c328cabac7e	687	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Kojto	120:7c328cabac7e	688
Kojto	120:7c328cabac7e	689	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	120:7c328cabac7e	690	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Kojto	120:7c328cabac7e	691
Kojto	120:7c328cabac7e	692	/@} end of group CMSIS_SCnotSCB /
Kojto	120:7c328cabac7e	693
Kojto	120:7c328cabac7e	694
Kojto	120:7c328cabac7e	695	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	696	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	120:7c328cabac7e	697	\brief Type definitions for the System Timer Registers.
Kojto	120:7c328cabac7e	698	@{
Kojto	120:7c328cabac7e	699	*/
Kojto	120:7c328cabac7e	700
Kojto	120:7c328cabac7e	701	/** \brief Structure type to access the System Timer (SysTick).
Kojto	120:7c328cabac7e	702	*/
Kojto	120:7c328cabac7e	703	typedef struct
Kojto	120:7c328cabac7e	704	{
Kojto	120:7c328cabac7e	705	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	120:7c328cabac7e	706	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	120:7c328cabac7e	707	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	120:7c328cabac7e	708	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	120:7c328cabac7e	709	} SysTick_Type;
Kojto	120:7c328cabac7e	710
Kojto	120:7c328cabac7e	711	/* SysTick Control / Status Register Definitions */
Kojto	120:7c328cabac7e	712	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Kojto	120:7c328cabac7e	713	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	120:7c328cabac7e	714
Kojto	120:7c328cabac7e	715	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Kojto	120:7c328cabac7e	716	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	120:7c328cabac7e	717
Kojto	120:7c328cabac7e	718	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Kojto	120:7c328cabac7e	719	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	120:7c328cabac7e	720
Kojto	120:7c328cabac7e	721	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	120:7c328cabac7e	722	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Kojto	120:7c328cabac7e	723
Kojto	120:7c328cabac7e	724	/* SysTick Reload Register Definitions */
Kojto	120:7c328cabac7e	725	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	120:7c328cabac7e	726	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Kojto	120:7c328cabac7e	727
Kojto	120:7c328cabac7e	728	/* SysTick Current Register Definitions */
Kojto	120:7c328cabac7e	729	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	120:7c328cabac7e	730	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Kojto	120:7c328cabac7e	731
Kojto	120:7c328cabac7e	732	/* SysTick Calibration Register Definitions */
Kojto	120:7c328cabac7e	733	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Kojto	120:7c328cabac7e	734	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	120:7c328cabac7e	735
Kojto	120:7c328cabac7e	736	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Kojto	120:7c328cabac7e	737	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	120:7c328cabac7e	738
Kojto	120:7c328cabac7e	739	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	120:7c328cabac7e	740	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Kojto	120:7c328cabac7e	741
Kojto	120:7c328cabac7e	742	/@} end of group CMSIS_SysTick /
Kojto	120:7c328cabac7e	743
Kojto	120:7c328cabac7e	744
Kojto	120:7c328cabac7e	745	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	746	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	120:7c328cabac7e	747	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	120:7c328cabac7e	748	@{
Kojto	120:7c328cabac7e	749	*/
Kojto	120:7c328cabac7e	750
Kojto	120:7c328cabac7e	751	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	120:7c328cabac7e	752	*/
Kojto	120:7c328cabac7e	753	typedef struct
Kojto	120:7c328cabac7e	754	{
Kojto	120:7c328cabac7e	755	__O union
Kojto	120:7c328cabac7e	756	{
Kojto	120:7c328cabac7e	757	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	120:7c328cabac7e	758	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	120:7c328cabac7e	759	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	120:7c328cabac7e	760	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	120:7c328cabac7e	761	uint32_t RESERVED0[864];
Kojto	120:7c328cabac7e	762	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	120:7c328cabac7e	763	uint32_t RESERVED1[15];
Kojto	120:7c328cabac7e	764	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	120:7c328cabac7e	765	uint32_t RESERVED2[15];
Kojto	120:7c328cabac7e	766	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	120:7c328cabac7e	767	uint32_t RESERVED3[29];
Kojto	120:7c328cabac7e	768	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	120:7c328cabac7e	769	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	120:7c328cabac7e	770	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	120:7c328cabac7e	771	uint32_t RESERVED4[43];
Kojto	120:7c328cabac7e	772	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	120:7c328cabac7e	773	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	120:7c328cabac7e	774	uint32_t RESERVED5[6];
Kojto	120:7c328cabac7e	775	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	120:7c328cabac7e	776	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	120:7c328cabac7e	777	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	120:7c328cabac7e	778	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	120:7c328cabac7e	779	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	120:7c328cabac7e	780	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	120:7c328cabac7e	781	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	120:7c328cabac7e	782	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	120:7c328cabac7e	783	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	120:7c328cabac7e	784	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	120:7c328cabac7e	785	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	120:7c328cabac7e	786	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	120:7c328cabac7e	787	} ITM_Type;
Kojto	120:7c328cabac7e	788
Kojto	120:7c328cabac7e	789	/* ITM Trace Privilege Register Definitions */
Kojto	120:7c328cabac7e	790	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	120:7c328cabac7e	791	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Kojto	120:7c328cabac7e	792
Kojto	120:7c328cabac7e	793	/* ITM Trace Control Register Definitions */
Kojto	120:7c328cabac7e	794	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Kojto	120:7c328cabac7e	795	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	120:7c328cabac7e	796
Kojto	120:7c328cabac7e	797	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Kojto	120:7c328cabac7e	798	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	120:7c328cabac7e	799
Kojto	120:7c328cabac7e	800	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Kojto	120:7c328cabac7e	801	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	120:7c328cabac7e	802
Kojto	120:7c328cabac7e	803	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Kojto	120:7c328cabac7e	804	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Kojto	120:7c328cabac7e	805
Kojto	120:7c328cabac7e	806	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Kojto	120:7c328cabac7e	807	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	120:7c328cabac7e	808
Kojto	120:7c328cabac7e	809	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Kojto	120:7c328cabac7e	810	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	120:7c328cabac7e	811
Kojto	120:7c328cabac7e	812	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Kojto	120:7c328cabac7e	813	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	120:7c328cabac7e	814
Kojto	120:7c328cabac7e	815	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Kojto	120:7c328cabac7e	816	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	120:7c328cabac7e	817
Kojto	120:7c328cabac7e	818	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	120:7c328cabac7e	819	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Kojto	120:7c328cabac7e	820
Kojto	120:7c328cabac7e	821	/* ITM Integration Write Register Definitions */
Kojto	120:7c328cabac7e	822	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	120:7c328cabac7e	823	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Kojto	120:7c328cabac7e	824
Kojto	120:7c328cabac7e	825	/* ITM Integration Read Register Definitions */
Kojto	120:7c328cabac7e	826	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	120:7c328cabac7e	827	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Kojto	120:7c328cabac7e	828
Kojto	120:7c328cabac7e	829	/* ITM Integration Mode Control Register Definitions */
Kojto	120:7c328cabac7e	830	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	120:7c328cabac7e	831	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Kojto	120:7c328cabac7e	832
Kojto	120:7c328cabac7e	833	/* ITM Lock Status Register Definitions */
Kojto	120:7c328cabac7e	834	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Kojto	120:7c328cabac7e	835	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	120:7c328cabac7e	836
Kojto	120:7c328cabac7e	837	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Kojto	120:7c328cabac7e	838	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	120:7c328cabac7e	839
Kojto	120:7c328cabac7e	840	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	120:7c328cabac7e	841	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Kojto	120:7c328cabac7e	842
Kojto	120:7c328cabac7e	843	/@}/ /* end of group CMSIS_ITM */
Kojto	120:7c328cabac7e	844
Kojto	120:7c328cabac7e	845
Kojto	120:7c328cabac7e	846	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	847	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	120:7c328cabac7e	848	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	120:7c328cabac7e	849	@{
Kojto	120:7c328cabac7e	850	*/
Kojto	120:7c328cabac7e	851
Kojto	120:7c328cabac7e	852	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	120:7c328cabac7e	853	*/
Kojto	120:7c328cabac7e	854	typedef struct
Kojto	120:7c328cabac7e	855	{
Kojto	120:7c328cabac7e	856	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	120:7c328cabac7e	857	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	120:7c328cabac7e	858	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	120:7c328cabac7e	859	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	120:7c328cabac7e	860	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	120:7c328cabac7e	861	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	120:7c328cabac7e	862	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	120:7c328cabac7e	863	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	120:7c328cabac7e	864	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	120:7c328cabac7e	865	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Kojto	120:7c328cabac7e	866	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	120:7c328cabac7e	867	uint32_t RESERVED0[1];
Kojto	120:7c328cabac7e	868	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	120:7c328cabac7e	869	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Kojto	120:7c328cabac7e	870	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	120:7c328cabac7e	871	uint32_t RESERVED1[1];
Kojto	120:7c328cabac7e	872	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	120:7c328cabac7e	873	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Kojto	120:7c328cabac7e	874	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	120:7c328cabac7e	875	uint32_t RESERVED2[1];
Kojto	120:7c328cabac7e	876	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	120:7c328cabac7e	877	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Kojto	120:7c328cabac7e	878	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	120:7c328cabac7e	879	} DWT_Type;
Kojto	120:7c328cabac7e	880
Kojto	120:7c328cabac7e	881	/* DWT Control Register Definitions */
Kojto	120:7c328cabac7e	882	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Kojto	120:7c328cabac7e	883	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	120:7c328cabac7e	884
Kojto	120:7c328cabac7e	885	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Kojto	120:7c328cabac7e	886	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	120:7c328cabac7e	887
Kojto	120:7c328cabac7e	888	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Kojto	120:7c328cabac7e	889	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	120:7c328cabac7e	890
Kojto	120:7c328cabac7e	891	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Kojto	120:7c328cabac7e	892	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	120:7c328cabac7e	893
Kojto	120:7c328cabac7e	894	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Kojto	120:7c328cabac7e	895	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	120:7c328cabac7e	896
Kojto	120:7c328cabac7e	897	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Kojto	120:7c328cabac7e	898	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	120:7c328cabac7e	899
Kojto	120:7c328cabac7e	900	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Kojto	120:7c328cabac7e	901	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	120:7c328cabac7e	902
Kojto	120:7c328cabac7e	903	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Kojto	120:7c328cabac7e	904	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	120:7c328cabac7e	905
Kojto	120:7c328cabac7e	906	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	120:7c328cabac7e	907	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	120:7c328cabac7e	908
Kojto	120:7c328cabac7e	909	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Kojto	120:7c328cabac7e	910	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	120:7c328cabac7e	911
Kojto	120:7c328cabac7e	912	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Kojto	120:7c328cabac7e	913	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	120:7c328cabac7e	914
Kojto	120:7c328cabac7e	915	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Kojto	120:7c328cabac7e	916	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	120:7c328cabac7e	917
Kojto	120:7c328cabac7e	918	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Kojto	120:7c328cabac7e	919	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	120:7c328cabac7e	920
Kojto	120:7c328cabac7e	921	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Kojto	120:7c328cabac7e	922	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	120:7c328cabac7e	923
Kojto	120:7c328cabac7e	924	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Kojto	120:7c328cabac7e	925	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	120:7c328cabac7e	926
Kojto	120:7c328cabac7e	927	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Kojto	120:7c328cabac7e	928	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	120:7c328cabac7e	929
Kojto	120:7c328cabac7e	930	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Kojto	120:7c328cabac7e	931	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	120:7c328cabac7e	932
Kojto	120:7c328cabac7e	933	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	120:7c328cabac7e	934	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	120:7c328cabac7e	935
Kojto	120:7c328cabac7e	936	/* DWT CPI Count Register Definitions */
Kojto	120:7c328cabac7e	937	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	120:7c328cabac7e	938	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Kojto	120:7c328cabac7e	939
Kojto	120:7c328cabac7e	940	/* DWT Exception Overhead Count Register Definitions */
Kojto	120:7c328cabac7e	941	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	120:7c328cabac7e	942	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	120:7c328cabac7e	943
Kojto	120:7c328cabac7e	944	/* DWT Sleep Count Register Definitions */
Kojto	120:7c328cabac7e	945	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	120:7c328cabac7e	946	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	120:7c328cabac7e	947
Kojto	120:7c328cabac7e	948	/* DWT LSU Count Register Definitions */
Kojto	120:7c328cabac7e	949	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	120:7c328cabac7e	950	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	120:7c328cabac7e	951
Kojto	120:7c328cabac7e	952	/* DWT Folded-instruction Count Register Definitions */
Kojto	120:7c328cabac7e	953	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	120:7c328cabac7e	954	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	120:7c328cabac7e	955
Kojto	120:7c328cabac7e	956	/* DWT Comparator Mask Register Definitions */
Kojto	120:7c328cabac7e	957	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	120:7c328cabac7e	958	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Kojto	120:7c328cabac7e	959
Kojto	120:7c328cabac7e	960	/* DWT Comparator Function Register Definitions */
Kojto	120:7c328cabac7e	961	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Kojto	120:7c328cabac7e	962	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	120:7c328cabac7e	963
Kojto	120:7c328cabac7e	964	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Kojto	120:7c328cabac7e	965	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Kojto	120:7c328cabac7e	966
Kojto	120:7c328cabac7e	967	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Kojto	120:7c328cabac7e	968	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Kojto	120:7c328cabac7e	969
Kojto	120:7c328cabac7e	970	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	120:7c328cabac7e	971	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	120:7c328cabac7e	972
Kojto	120:7c328cabac7e	973	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Kojto	120:7c328cabac7e	974	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Kojto	120:7c328cabac7e	975
Kojto	120:7c328cabac7e	976	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Kojto	120:7c328cabac7e	977	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Kojto	120:7c328cabac7e	978
Kojto	120:7c328cabac7e	979	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Kojto	120:7c328cabac7e	980	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Kojto	120:7c328cabac7e	981
Kojto	120:7c328cabac7e	982	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Kojto	120:7c328cabac7e	983	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Kojto	120:7c328cabac7e	984
Kojto	120:7c328cabac7e	985	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	120:7c328cabac7e	986	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Kojto	120:7c328cabac7e	987
Kojto	120:7c328cabac7e	988	/@}/ /* end of group CMSIS_DWT */
Kojto	120:7c328cabac7e	989
Kojto	120:7c328cabac7e	990
Kojto	120:7c328cabac7e	991	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	992	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	120:7c328cabac7e	993	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	120:7c328cabac7e	994	@{
Kojto	120:7c328cabac7e	995	*/
Kojto	120:7c328cabac7e	996
Kojto	120:7c328cabac7e	997	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	120:7c328cabac7e	998	*/
Kojto	120:7c328cabac7e	999	typedef struct
Kojto	120:7c328cabac7e	1000	{
Kojto	120:7c328cabac7e	1001	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	120:7c328cabac7e	1002	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	120:7c328cabac7e	1003	uint32_t RESERVED0[2];
Kojto	120:7c328cabac7e	1004	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	120:7c328cabac7e	1005	uint32_t RESERVED1[55];
Kojto	120:7c328cabac7e	1006	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	120:7c328cabac7e	1007	uint32_t RESERVED2[131];
Kojto	120:7c328cabac7e	1008	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	120:7c328cabac7e	1009	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	120:7c328cabac7e	1010	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	120:7c328cabac7e	1011	uint32_t RESERVED3[759];
Kojto	120:7c328cabac7e	1012	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	120:7c328cabac7e	1013	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	120:7c328cabac7e	1014	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	120:7c328cabac7e	1015	uint32_t RESERVED4[1];
Kojto	120:7c328cabac7e	1016	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	120:7c328cabac7e	1017	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	120:7c328cabac7e	1018	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	120:7c328cabac7e	1019	uint32_t RESERVED5[39];
Kojto	120:7c328cabac7e	1020	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	120:7c328cabac7e	1021	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	120:7c328cabac7e	1022	uint32_t RESERVED7[8];
Kojto	120:7c328cabac7e	1023	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	120:7c328cabac7e	1024	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	120:7c328cabac7e	1025	} TPI_Type;
Kojto	120:7c328cabac7e	1026
Kojto	120:7c328cabac7e	1027	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	120:7c328cabac7e	1028	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	120:7c328cabac7e	1029	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Kojto	120:7c328cabac7e	1030
Kojto	120:7c328cabac7e	1031	/* TPI Selected Pin Protocol Register Definitions */
Kojto	120:7c328cabac7e	1032	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	120:7c328cabac7e	1033	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Kojto	120:7c328cabac7e	1034
Kojto	120:7c328cabac7e	1035	/* TPI Formatter and Flush Status Register Definitions */
Kojto	120:7c328cabac7e	1036	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Kojto	120:7c328cabac7e	1037	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	120:7c328cabac7e	1038
Kojto	120:7c328cabac7e	1039	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Kojto	120:7c328cabac7e	1040	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	120:7c328cabac7e	1041
Kojto	120:7c328cabac7e	1042	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Kojto	120:7c328cabac7e	1043	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	120:7c328cabac7e	1044
Kojto	120:7c328cabac7e	1045	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	120:7c328cabac7e	1046	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Kojto	120:7c328cabac7e	1047
Kojto	120:7c328cabac7e	1048	/* TPI Formatter and Flush Control Register Definitions */
Kojto	120:7c328cabac7e	1049	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Kojto	120:7c328cabac7e	1050	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	120:7c328cabac7e	1051
Kojto	120:7c328cabac7e	1052	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Kojto	120:7c328cabac7e	1053	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	120:7c328cabac7e	1054
Kojto	120:7c328cabac7e	1055	/* TPI TRIGGER Register Definitions */
Kojto	120:7c328cabac7e	1056	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	120:7c328cabac7e	1057	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	120:7c328cabac7e	1058
Kojto	120:7c328cabac7e	1059	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	120:7c328cabac7e	1060	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	120:7c328cabac7e	1061	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	120:7c328cabac7e	1062
Kojto	120:7c328cabac7e	1063	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Kojto	120:7c328cabac7e	1064	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	120:7c328cabac7e	1065
Kojto	120:7c328cabac7e	1066	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	120:7c328cabac7e	1067	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	120:7c328cabac7e	1068
Kojto	120:7c328cabac7e	1069	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Kojto	120:7c328cabac7e	1070	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	120:7c328cabac7e	1071
Kojto	120:7c328cabac7e	1072	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Kojto	120:7c328cabac7e	1073	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	120:7c328cabac7e	1074
Kojto	120:7c328cabac7e	1075	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Kojto	120:7c328cabac7e	1076	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	120:7c328cabac7e	1077
Kojto	120:7c328cabac7e	1078	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	120:7c328cabac7e	1079	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Kojto	120:7c328cabac7e	1080
Kojto	120:7c328cabac7e	1081	/* TPI ITATBCTR2 Register Definitions */
Kojto	120:7c328cabac7e	1082	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	120:7c328cabac7e	1083	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	120:7c328cabac7e	1084
Kojto	120:7c328cabac7e	1085	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	120:7c328cabac7e	1086	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	120:7c328cabac7e	1087	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	120:7c328cabac7e	1088
Kojto	120:7c328cabac7e	1089	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Kojto	120:7c328cabac7e	1090	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	120:7c328cabac7e	1091
Kojto	120:7c328cabac7e	1092	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	120:7c328cabac7e	1093	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	120:7c328cabac7e	1094
Kojto	120:7c328cabac7e	1095	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Kojto	120:7c328cabac7e	1096	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	120:7c328cabac7e	1097
Kojto	120:7c328cabac7e	1098	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Kojto	120:7c328cabac7e	1099	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	120:7c328cabac7e	1100
Kojto	120:7c328cabac7e	1101	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Kojto	120:7c328cabac7e	1102	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	120:7c328cabac7e	1103
Kojto	120:7c328cabac7e	1104	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	120:7c328cabac7e	1105	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Kojto	120:7c328cabac7e	1106
Kojto	120:7c328cabac7e	1107	/* TPI ITATBCTR0 Register Definitions */
Kojto	120:7c328cabac7e	1108	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	120:7c328cabac7e	1109	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	120:7c328cabac7e	1110
Kojto	120:7c328cabac7e	1111	/* TPI Integration Mode Control Register Definitions */
Kojto	120:7c328cabac7e	1112	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	120:7c328cabac7e	1113	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Kojto	120:7c328cabac7e	1114
Kojto	120:7c328cabac7e	1115	/* TPI DEVID Register Definitions */
Kojto	120:7c328cabac7e	1116	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Kojto	120:7c328cabac7e	1117	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	120:7c328cabac7e	1118
Kojto	120:7c328cabac7e	1119	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Kojto	120:7c328cabac7e	1120	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	120:7c328cabac7e	1121
Kojto	120:7c328cabac7e	1122	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Kojto	120:7c328cabac7e	1123	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	120:7c328cabac7e	1124
Kojto	120:7c328cabac7e	1125	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Kojto	120:7c328cabac7e	1126	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	120:7c328cabac7e	1127
Kojto	120:7c328cabac7e	1128	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Kojto	120:7c328cabac7e	1129	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	120:7c328cabac7e	1130
Kojto	120:7c328cabac7e	1131	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	120:7c328cabac7e	1132	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Kojto	120:7c328cabac7e	1133
Kojto	120:7c328cabac7e	1134	/* TPI DEVTYPE Register Definitions */
Kojto	120:7c328cabac7e	1135	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Kojto	120:7c328cabac7e	1136	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	120:7c328cabac7e	1137
Kojto	120:7c328cabac7e	1138	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	120:7c328cabac7e	1139	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	120:7c328cabac7e	1140
Kojto	120:7c328cabac7e	1141	/@}/ /* end of group CMSIS_TPI */
Kojto	120:7c328cabac7e	1142
Kojto	120:7c328cabac7e	1143
Kojto	120:7c328cabac7e	1144	#if (__MPU_PRESENT == 1)
Kojto	120:7c328cabac7e	1145	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	1146	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	120:7c328cabac7e	1147	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	120:7c328cabac7e	1148	@{
Kojto	120:7c328cabac7e	1149	*/
Kojto	120:7c328cabac7e	1150
Kojto	120:7c328cabac7e	1151	/** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto	120:7c328cabac7e	1152	*/
Kojto	120:7c328cabac7e	1153	typedef struct
Kojto	120:7c328cabac7e	1154	{
Kojto	120:7c328cabac7e	1155	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	120:7c328cabac7e	1156	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	120:7c328cabac7e	1157	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Kojto	120:7c328cabac7e	1158	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	120:7c328cabac7e	1159	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Kojto	120:7c328cabac7e	1160	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Kojto	120:7c328cabac7e	1161	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Kojto	120:7c328cabac7e	1162	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Kojto	120:7c328cabac7e	1163	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Kojto	120:7c328cabac7e	1164	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Kojto	120:7c328cabac7e	1165	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Kojto	120:7c328cabac7e	1166	} MPU_Type;
Kojto	120:7c328cabac7e	1167
Kojto	120:7c328cabac7e	1168	/* MPU Type Register */
Kojto	120:7c328cabac7e	1169	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Kojto	120:7c328cabac7e	1170	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	120:7c328cabac7e	1171
Kojto	120:7c328cabac7e	1172	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Kojto	120:7c328cabac7e	1173	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	120:7c328cabac7e	1174
Kojto	120:7c328cabac7e	1175	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	120:7c328cabac7e	1176	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Kojto	120:7c328cabac7e	1177
Kojto	120:7c328cabac7e	1178	/* MPU Control Register */
Kojto	120:7c328cabac7e	1179	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Kojto	120:7c328cabac7e	1180	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	120:7c328cabac7e	1181
Kojto	120:7c328cabac7e	1182	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Kojto	120:7c328cabac7e	1183	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	120:7c328cabac7e	1184
Kojto	120:7c328cabac7e	1185	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	120:7c328cabac7e	1186	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Kojto	120:7c328cabac7e	1187
Kojto	120:7c328cabac7e	1188	/* MPU Region Number Register */
Kojto	120:7c328cabac7e	1189	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	120:7c328cabac7e	1190	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Kojto	120:7c328cabac7e	1191
Kojto	120:7c328cabac7e	1192	/* MPU Region Base Address Register */
Kojto	120:7c328cabac7e	1193	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Kojto	120:7c328cabac7e	1194	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	120:7c328cabac7e	1195
Kojto	120:7c328cabac7e	1196	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Kojto	120:7c328cabac7e	1197	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Kojto	120:7c328cabac7e	1198
Kojto	120:7c328cabac7e	1199	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	120:7c328cabac7e	1200	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Kojto	120:7c328cabac7e	1201
Kojto	120:7c328cabac7e	1202	/* MPU Region Attribute and Size Register */
Kojto	120:7c328cabac7e	1203	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Kojto	120:7c328cabac7e	1204	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Kojto	120:7c328cabac7e	1205
Kojto	120:7c328cabac7e	1206	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Kojto	120:7c328cabac7e	1207	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Kojto	120:7c328cabac7e	1208
Kojto	120:7c328cabac7e	1209	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Kojto	120:7c328cabac7e	1210	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Kojto	120:7c328cabac7e	1211
Kojto	120:7c328cabac7e	1212	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Kojto	120:7c328cabac7e	1213	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Kojto	120:7c328cabac7e	1214
Kojto	120:7c328cabac7e	1215	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Kojto	120:7c328cabac7e	1216	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Kojto	120:7c328cabac7e	1217
Kojto	120:7c328cabac7e	1218	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Kojto	120:7c328cabac7e	1219	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Kojto	120:7c328cabac7e	1220
Kojto	120:7c328cabac7e	1221	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Kojto	120:7c328cabac7e	1222	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Kojto	120:7c328cabac7e	1223
Kojto	120:7c328cabac7e	1224	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Kojto	120:7c328cabac7e	1225	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Kojto	120:7c328cabac7e	1226
Kojto	120:7c328cabac7e	1227	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Kojto	120:7c328cabac7e	1228	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Kojto	120:7c328cabac7e	1229
Kojto	120:7c328cabac7e	1230	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	120:7c328cabac7e	1231	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Kojto	120:7c328cabac7e	1232
Kojto	120:7c328cabac7e	1233	/@} end of group CMSIS_MPU /
Kojto	120:7c328cabac7e	1234	#endif
Kojto	120:7c328cabac7e	1235
Kojto	120:7c328cabac7e	1236
Kojto	120:7c328cabac7e	1237	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	1238	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	1239	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto	120:7c328cabac7e	1240	\brief Type definitions for the Floating Point Unit (FPU)
Kojto	120:7c328cabac7e	1241	@{
Kojto	120:7c328cabac7e	1242	*/
Kojto	120:7c328cabac7e	1243
Kojto	120:7c328cabac7e	1244	/** \brief Structure type to access the Floating Point Unit (FPU).
Kojto	120:7c328cabac7e	1245	*/
Kojto	120:7c328cabac7e	1246	typedef struct
Kojto	120:7c328cabac7e	1247	{
Kojto	120:7c328cabac7e	1248	uint32_t RESERVED0[1];
Kojto	120:7c328cabac7e	1249	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Kojto	120:7c328cabac7e	1250	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Kojto	120:7c328cabac7e	1251	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Kojto	120:7c328cabac7e	1252	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Kojto	120:7c328cabac7e	1253	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Kojto	120:7c328cabac7e	1254	} FPU_Type;
Kojto	120:7c328cabac7e	1255
Kojto	120:7c328cabac7e	1256	/* Floating-Point Context Control Register */
Kojto	120:7c328cabac7e	1257	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Kojto	120:7c328cabac7e	1258	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Kojto	120:7c328cabac7e	1259
Kojto	120:7c328cabac7e	1260	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Kojto	120:7c328cabac7e	1261	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Kojto	120:7c328cabac7e	1262
Kojto	120:7c328cabac7e	1263	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Kojto	120:7c328cabac7e	1264	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Kojto	120:7c328cabac7e	1265
Kojto	120:7c328cabac7e	1266	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Kojto	120:7c328cabac7e	1267	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Kojto	120:7c328cabac7e	1268
Kojto	120:7c328cabac7e	1269	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Kojto	120:7c328cabac7e	1270	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Kojto	120:7c328cabac7e	1271
Kojto	120:7c328cabac7e	1272	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Kojto	120:7c328cabac7e	1273	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Kojto	120:7c328cabac7e	1274
Kojto	120:7c328cabac7e	1275	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Kojto	120:7c328cabac7e	1276	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Kojto	120:7c328cabac7e	1277
Kojto	120:7c328cabac7e	1278	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Kojto	120:7c328cabac7e	1279	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Kojto	120:7c328cabac7e	1280
Kojto	120:7c328cabac7e	1281	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Kojto	120:7c328cabac7e	1282	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Kojto	120:7c328cabac7e	1283
Kojto	120:7c328cabac7e	1284	/* Floating-Point Context Address Register */
Kojto	120:7c328cabac7e	1285	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Kojto	120:7c328cabac7e	1286	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Kojto	120:7c328cabac7e	1287
Kojto	120:7c328cabac7e	1288	/* Floating-Point Default Status Control Register */
Kojto	120:7c328cabac7e	1289	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Kojto	120:7c328cabac7e	1290	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Kojto	120:7c328cabac7e	1291
Kojto	120:7c328cabac7e	1292	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Kojto	120:7c328cabac7e	1293	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Kojto	120:7c328cabac7e	1294
Kojto	120:7c328cabac7e	1295	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Kojto	120:7c328cabac7e	1296	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Kojto	120:7c328cabac7e	1297
Kojto	120:7c328cabac7e	1298	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Kojto	120:7c328cabac7e	1299	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Kojto	120:7c328cabac7e	1300
Kojto	120:7c328cabac7e	1301	/* Media and FP Feature Register 0 */
Kojto	120:7c328cabac7e	1302	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Kojto	120:7c328cabac7e	1303	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Kojto	120:7c328cabac7e	1304
Kojto	120:7c328cabac7e	1305	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Kojto	120:7c328cabac7e	1306	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Kojto	120:7c328cabac7e	1307
Kojto	120:7c328cabac7e	1308	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Kojto	120:7c328cabac7e	1309	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Kojto	120:7c328cabac7e	1310
Kojto	120:7c328cabac7e	1311	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Kojto	120:7c328cabac7e	1312	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Kojto	120:7c328cabac7e	1313
Kojto	120:7c328cabac7e	1314	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Kojto	120:7c328cabac7e	1315	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Kojto	120:7c328cabac7e	1316
Kojto	120:7c328cabac7e	1317	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Kojto	120:7c328cabac7e	1318	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Kojto	120:7c328cabac7e	1319
Kojto	120:7c328cabac7e	1320	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Kojto	120:7c328cabac7e	1321	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Kojto	120:7c328cabac7e	1322
Kojto	120:7c328cabac7e	1323	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Kojto	120:7c328cabac7e	1324	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Kojto	120:7c328cabac7e	1325
Kojto	120:7c328cabac7e	1326	/* Media and FP Feature Register 1 */
Kojto	120:7c328cabac7e	1327	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Kojto	120:7c328cabac7e	1328	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Kojto	120:7c328cabac7e	1329
Kojto	120:7c328cabac7e	1330	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Kojto	120:7c328cabac7e	1331	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Kojto	120:7c328cabac7e	1332
Kojto	120:7c328cabac7e	1333	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Kojto	120:7c328cabac7e	1334	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Kojto	120:7c328cabac7e	1335
Kojto	120:7c328cabac7e	1336	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Kojto	120:7c328cabac7e	1337	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Kojto	120:7c328cabac7e	1338
Kojto	120:7c328cabac7e	1339	/@} end of group CMSIS_FPU /
Kojto	120:7c328cabac7e	1340	#endif
Kojto	120:7c328cabac7e	1341
Kojto	120:7c328cabac7e	1342
Kojto	120:7c328cabac7e	1343	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	1344	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	120:7c328cabac7e	1345	\brief Type definitions for the Core Debug Registers
Kojto	120:7c328cabac7e	1346	@{
Kojto	120:7c328cabac7e	1347	*/
Kojto	120:7c328cabac7e	1348
Kojto	120:7c328cabac7e	1349	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	120:7c328cabac7e	1350	*/
Kojto	120:7c328cabac7e	1351	typedef struct
Kojto	120:7c328cabac7e	1352	{
Kojto	120:7c328cabac7e	1353	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	120:7c328cabac7e	1354	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	120:7c328cabac7e	1355	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	120:7c328cabac7e	1356	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	120:7c328cabac7e	1357	} CoreDebug_Type;
Kojto	120:7c328cabac7e	1358
Kojto	120:7c328cabac7e	1359	/* Debug Halting Control and Status Register */
Kojto	120:7c328cabac7e	1360	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	120:7c328cabac7e	1361	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	120:7c328cabac7e	1362
Kojto	120:7c328cabac7e	1363	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	120:7c328cabac7e	1364	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	120:7c328cabac7e	1365
Kojto	120:7c328cabac7e	1366	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	120:7c328cabac7e	1367	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	120:7c328cabac7e	1368
Kojto	120:7c328cabac7e	1369	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	120:7c328cabac7e	1370	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	120:7c328cabac7e	1371
Kojto	120:7c328cabac7e	1372	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	120:7c328cabac7e	1373	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	120:7c328cabac7e	1374
Kojto	120:7c328cabac7e	1375	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Kojto	120:7c328cabac7e	1376	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	120:7c328cabac7e	1377
Kojto	120:7c328cabac7e	1378	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	120:7c328cabac7e	1379	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	120:7c328cabac7e	1380
Kojto	120:7c328cabac7e	1381	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	120:7c328cabac7e	1382	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	120:7c328cabac7e	1383
Kojto	120:7c328cabac7e	1384	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	120:7c328cabac7e	1385	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	120:7c328cabac7e	1386
Kojto	120:7c328cabac7e	1387	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Kojto	120:7c328cabac7e	1388	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	120:7c328cabac7e	1389
Kojto	120:7c328cabac7e	1390	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Kojto	120:7c328cabac7e	1391	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	120:7c328cabac7e	1392
Kojto	120:7c328cabac7e	1393	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	120:7c328cabac7e	1394	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	120:7c328cabac7e	1395
Kojto	120:7c328cabac7e	1396	/* Debug Core Register Selector Register */
Kojto	120:7c328cabac7e	1397	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Kojto	120:7c328cabac7e	1398	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	120:7c328cabac7e	1399
Kojto	120:7c328cabac7e	1400	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	120:7c328cabac7e	1401	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	120:7c328cabac7e	1402
Kojto	120:7c328cabac7e	1403	/* Debug Exception and Monitor Control Register */
Kojto	120:7c328cabac7e	1404	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Kojto	120:7c328cabac7e	1405	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	120:7c328cabac7e	1406
Kojto	120:7c328cabac7e	1407	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	120:7c328cabac7e	1408	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	120:7c328cabac7e	1409
Kojto	120:7c328cabac7e	1410	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	120:7c328cabac7e	1411	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	120:7c328cabac7e	1412
Kojto	120:7c328cabac7e	1413	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	120:7c328cabac7e	1414	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	120:7c328cabac7e	1415
Kojto	120:7c328cabac7e	1416	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Kojto	120:7c328cabac7e	1417	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	120:7c328cabac7e	1418
Kojto	120:7c328cabac7e	1419	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	120:7c328cabac7e	1420	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	120:7c328cabac7e	1421
Kojto	120:7c328cabac7e	1422	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	120:7c328cabac7e	1423	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	120:7c328cabac7e	1424
Kojto	120:7c328cabac7e	1425	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	120:7c328cabac7e	1426	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	120:7c328cabac7e	1427
Kojto	120:7c328cabac7e	1428	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	120:7c328cabac7e	1429	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	120:7c328cabac7e	1430
Kojto	120:7c328cabac7e	1431	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	120:7c328cabac7e	1432	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	120:7c328cabac7e	1433
Kojto	120:7c328cabac7e	1434	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	120:7c328cabac7e	1435	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	120:7c328cabac7e	1436
Kojto	120:7c328cabac7e	1437	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	120:7c328cabac7e	1438	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	120:7c328cabac7e	1439
Kojto	120:7c328cabac7e	1440	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	120:7c328cabac7e	1441	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	120:7c328cabac7e	1442
Kojto	120:7c328cabac7e	1443	/@} end of group CMSIS_CoreDebug /
Kojto	120:7c328cabac7e	1444
Kojto	120:7c328cabac7e	1445
Kojto	120:7c328cabac7e	1446	/** \ingroup CMSIS_core_register
Kojto	120:7c328cabac7e	1447	\defgroup CMSIS_core_base Core Definitions
Kojto	120:7c328cabac7e	1448	\brief Definitions for base addresses, unions, and structures.
Kojto	120:7c328cabac7e	1449	@{
Kojto	120:7c328cabac7e	1450	*/
Kojto	120:7c328cabac7e	1451
Kojto	120:7c328cabac7e	1452	/* Memory mapping of Cortex-M4 Hardware */
Kojto	120:7c328cabac7e	1453	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	120:7c328cabac7e	1454	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	120:7c328cabac7e	1455	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	120:7c328cabac7e	1456	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	120:7c328cabac7e	1457	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	120:7c328cabac7e	1458	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	120:7c328cabac7e	1459	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	120:7c328cabac7e	1460	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	120:7c328cabac7e	1461
Kojto	120:7c328cabac7e	1462	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	120:7c328cabac7e	1463	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	120:7c328cabac7e	1464	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	120:7c328cabac7e	1465	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	120:7c328cabac7e	1466	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	120:7c328cabac7e	1467	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	120:7c328cabac7e	1468	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	120:7c328cabac7e	1469	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Kojto	120:7c328cabac7e	1470
Kojto	120:7c328cabac7e	1471	#if (__MPU_PRESENT == 1)
Kojto	120:7c328cabac7e	1472	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	120:7c328cabac7e	1473	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	120:7c328cabac7e	1474	#endif
Kojto	120:7c328cabac7e	1475
Kojto	120:7c328cabac7e	1476	#if (__FPU_PRESENT == 1)
Kojto	120:7c328cabac7e	1477	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Kojto	120:7c328cabac7e	1478	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Kojto	120:7c328cabac7e	1479	#endif
Kojto	120:7c328cabac7e	1480
Kojto	120:7c328cabac7e	1481	/@} /
Kojto	120:7c328cabac7e	1482
Kojto	120:7c328cabac7e	1483
Kojto	120:7c328cabac7e	1484
Kojto	120:7c328cabac7e	1485	/*******************************************************************************
Kojto	120:7c328cabac7e	1486	* Hardware Abstraction Layer
Kojto	120:7c328cabac7e	1487	Core Function Interface contains:
Kojto	120:7c328cabac7e	1488	- Core NVIC Functions
Kojto	120:7c328cabac7e	1489	- Core SysTick Functions
Kojto	120:7c328cabac7e	1490	- Core Debug Functions
Kojto	120:7c328cabac7e	1491	- Core Register Access Functions
Kojto	120:7c328cabac7e	1492	******************************************************************************/
Kojto	120:7c328cabac7e	1493	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	120:7c328cabac7e	1494	*/
Kojto	120:7c328cabac7e	1495
Kojto	120:7c328cabac7e	1496
Kojto	120:7c328cabac7e	1497
Kojto	120:7c328cabac7e	1498	/* ########################## NVIC functions #################################### */
Kojto	120:7c328cabac7e	1499	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	120:7c328cabac7e	1500	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	120:7c328cabac7e	1501	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	120:7c328cabac7e	1502	@{
Kojto	120:7c328cabac7e	1503	*/
Kojto	120:7c328cabac7e	1504
Kojto	120:7c328cabac7e	1505	/** \brief Set Priority Grouping
Kojto	120:7c328cabac7e	1506
Kojto	120:7c328cabac7e	1507	The function sets the priority grouping field using the required unlock sequence.
Kojto	120:7c328cabac7e	1508	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	120:7c328cabac7e	1509	Only values from 0..7 are used.
Kojto	120:7c328cabac7e	1510	In case of a conflict between priority grouping and available
Kojto	120:7c328cabac7e	1511	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	120:7c328cabac7e	1512
Kojto	120:7c328cabac7e	1513	\param [in] PriorityGroup Priority grouping field.
Kojto	120:7c328cabac7e	1514	*/
Kojto	120:7c328cabac7e	1515	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	120:7c328cabac7e	1516	{
Kojto	120:7c328cabac7e	1517	uint32_t reg_value;
Kojto	120:7c328cabac7e	1518	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	120:7c328cabac7e	1519
Kojto	120:7c328cabac7e	1520	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	120:7c328cabac7e	1521	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	120:7c328cabac7e	1522	reg_value = (reg_value \|
Kojto	120:7c328cabac7e	1523	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	120:7c328cabac7e	1524	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto	120:7c328cabac7e	1525	SCB->AIRCR = reg_value;
Kojto	120:7c328cabac7e	1526	}
Kojto	120:7c328cabac7e	1527
Kojto	120:7c328cabac7e	1528
Kojto	120:7c328cabac7e	1529	/** \brief Get Priority Grouping
Kojto	120:7c328cabac7e	1530
Kojto	120:7c328cabac7e	1531	The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	120:7c328cabac7e	1532
Kojto	120:7c328cabac7e	1533	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	120:7c328cabac7e	1534	*/
Kojto	120:7c328cabac7e	1535	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto	120:7c328cabac7e	1536	{
Kojto	120:7c328cabac7e	1537	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto	120:7c328cabac7e	1538	}
Kojto	120:7c328cabac7e	1539
Kojto	120:7c328cabac7e	1540
Kojto	120:7c328cabac7e	1541	/** \brief Enable External Interrupt
Kojto	120:7c328cabac7e	1542
Kojto	120:7c328cabac7e	1543	The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto	120:7c328cabac7e	1544
Kojto	120:7c328cabac7e	1545	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	120:7c328cabac7e	1546	*/
Kojto	120:7c328cabac7e	1547	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1548	{
Kojto	120:7c328cabac7e	1549	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	120:7c328cabac7e	1550	}
Kojto	120:7c328cabac7e	1551
Kojto	120:7c328cabac7e	1552
Kojto	120:7c328cabac7e	1553	/** \brief Disable External Interrupt
Kojto	120:7c328cabac7e	1554
Kojto	120:7c328cabac7e	1555	The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto	120:7c328cabac7e	1556
Kojto	120:7c328cabac7e	1557	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	120:7c328cabac7e	1558	*/
Kojto	120:7c328cabac7e	1559	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1560	{
Kojto	120:7c328cabac7e	1561	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	120:7c328cabac7e	1562	}
Kojto	120:7c328cabac7e	1563
Kojto	120:7c328cabac7e	1564
Kojto	120:7c328cabac7e	1565	/** \brief Get Pending Interrupt
Kojto	120:7c328cabac7e	1566
Kojto	120:7c328cabac7e	1567	The function reads the pending register in the NVIC and returns the pending bit
Kojto	120:7c328cabac7e	1568	for the specified interrupt.
Kojto	120:7c328cabac7e	1569
Kojto	120:7c328cabac7e	1570	\param [in] IRQn Interrupt number.
Kojto	120:7c328cabac7e	1571
Kojto	120:7c328cabac7e	1572	\return 0 Interrupt status is not pending.
Kojto	120:7c328cabac7e	1573	\return 1 Interrupt status is pending.
Kojto	120:7c328cabac7e	1574	*/
Kojto	120:7c328cabac7e	1575	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1576	{
Kojto	120:7c328cabac7e	1577	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	120:7c328cabac7e	1578	}
Kojto	120:7c328cabac7e	1579
Kojto	120:7c328cabac7e	1580
Kojto	120:7c328cabac7e	1581	/** \brief Set Pending Interrupt
Kojto	120:7c328cabac7e	1582
Kojto	120:7c328cabac7e	1583	The function sets the pending bit of an external interrupt.
Kojto	120:7c328cabac7e	1584
Kojto	120:7c328cabac7e	1585	\param [in] IRQn Interrupt number. Value cannot be negative.
Kojto	120:7c328cabac7e	1586	*/
Kojto	120:7c328cabac7e	1587	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1588	{
Kojto	120:7c328cabac7e	1589	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	120:7c328cabac7e	1590	}
Kojto	120:7c328cabac7e	1591
Kojto	120:7c328cabac7e	1592
Kojto	120:7c328cabac7e	1593	/** \brief Clear Pending Interrupt
Kojto	120:7c328cabac7e	1594
Kojto	120:7c328cabac7e	1595	The function clears the pending bit of an external interrupt.
Kojto	120:7c328cabac7e	1596
Kojto	120:7c328cabac7e	1597	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	120:7c328cabac7e	1598	*/
Kojto	120:7c328cabac7e	1599	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1600	{
Kojto	120:7c328cabac7e	1601	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	120:7c328cabac7e	1602	}
Kojto	120:7c328cabac7e	1603
Kojto	120:7c328cabac7e	1604
Kojto	120:7c328cabac7e	1605	/** \brief Get Active Interrupt
Kojto	120:7c328cabac7e	1606
Kojto	120:7c328cabac7e	1607	The function reads the active register in NVIC and returns the active bit.
Kojto	120:7c328cabac7e	1608
Kojto	120:7c328cabac7e	1609	\param [in] IRQn Interrupt number.
Kojto	120:7c328cabac7e	1610
Kojto	120:7c328cabac7e	1611	\return 0 Interrupt status is not active.
Kojto	120:7c328cabac7e	1612	\return 1 Interrupt status is active.
Kojto	120:7c328cabac7e	1613	*/
Kojto	120:7c328cabac7e	1614	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1615	{
Kojto	120:7c328cabac7e	1616	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	120:7c328cabac7e	1617	}
Kojto	120:7c328cabac7e	1618
Kojto	120:7c328cabac7e	1619
Kojto	120:7c328cabac7e	1620	/** \brief Set Interrupt Priority
Kojto	120:7c328cabac7e	1621
Kojto	120:7c328cabac7e	1622	The function sets the priority of an interrupt.
Kojto	120:7c328cabac7e	1623
Kojto	120:7c328cabac7e	1624	\note The priority cannot be set for every core interrupt.
Kojto	120:7c328cabac7e	1625
Kojto	120:7c328cabac7e	1626	\param [in] IRQn Interrupt number.
Kojto	120:7c328cabac7e	1627	\param [in] priority Priority to set.
Kojto	120:7c328cabac7e	1628	*/
Kojto	120:7c328cabac7e	1629	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	120:7c328cabac7e	1630	{
Kojto	120:7c328cabac7e	1631	if((int32_t)IRQn < 0) {
Kojto	120:7c328cabac7e	1632	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	120:7c328cabac7e	1633	}
Kojto	120:7c328cabac7e	1634	else {
Kojto	120:7c328cabac7e	1635	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	120:7c328cabac7e	1636	}
Kojto	120:7c328cabac7e	1637	}
Kojto	120:7c328cabac7e	1638
Kojto	120:7c328cabac7e	1639
Kojto	120:7c328cabac7e	1640	/** \brief Get Interrupt Priority
Kojto	120:7c328cabac7e	1641
Kojto	120:7c328cabac7e	1642	The function reads the priority of an interrupt. The interrupt
Kojto	120:7c328cabac7e	1643	number can be positive to specify an external (device specific)
Kojto	120:7c328cabac7e	1644	interrupt, or negative to specify an internal (core) interrupt.
Kojto	120:7c328cabac7e	1645
Kojto	120:7c328cabac7e	1646
Kojto	120:7c328cabac7e	1647	\param [in] IRQn Interrupt number.
Kojto	120:7c328cabac7e	1648	\return Interrupt Priority. Value is aligned automatically to the implemented
Kojto	120:7c328cabac7e	1649	priority bits of the microcontroller.
Kojto	120:7c328cabac7e	1650	*/
Kojto	120:7c328cabac7e	1651	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto	120:7c328cabac7e	1652	{
Kojto	120:7c328cabac7e	1653
Kojto	120:7c328cabac7e	1654	if((int32_t)IRQn < 0) {
Kojto	120:7c328cabac7e	1655	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	120:7c328cabac7e	1656	}
Kojto	120:7c328cabac7e	1657	else {
Kojto	120:7c328cabac7e	1658	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	120:7c328cabac7e	1659	}
Kojto	120:7c328cabac7e	1660	}
Kojto	120:7c328cabac7e	1661
Kojto	120:7c328cabac7e	1662
Kojto	120:7c328cabac7e	1663	/** \brief Encode Priority
Kojto	120:7c328cabac7e	1664
Kojto	120:7c328cabac7e	1665	The function encodes the priority for an interrupt with the given priority group,
Kojto	120:7c328cabac7e	1666	preemptive priority value, and subpriority value.
Kojto	120:7c328cabac7e	1667	In case of a conflict between priority grouping and available
Kojto	120:7c328cabac7e	1668	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	120:7c328cabac7e	1669
Kojto	120:7c328cabac7e	1670	\param [in] PriorityGroup Used priority group.
Kojto	120:7c328cabac7e	1671	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	120:7c328cabac7e	1672	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	120:7c328cabac7e	1673	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	120:7c328cabac7e	1674	*/
Kojto	120:7c328cabac7e	1675	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	120:7c328cabac7e	1676	{
Kojto	120:7c328cabac7e	1677	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	120:7c328cabac7e	1678	uint32_t PreemptPriorityBits;
Kojto	120:7c328cabac7e	1679	uint32_t SubPriorityBits;
Kojto	120:7c328cabac7e	1680
Kojto	120:7c328cabac7e	1681	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	120:7c328cabac7e	1682	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	120:7c328cabac7e	1683
Kojto	120:7c328cabac7e	1684	return (
Kojto	120:7c328cabac7e	1685	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	120:7c328cabac7e	1686	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto	120:7c328cabac7e	1687	);
Kojto	120:7c328cabac7e	1688	}
Kojto	120:7c328cabac7e	1689
Kojto	120:7c328cabac7e	1690
Kojto	120:7c328cabac7e	1691	/** \brief Decode Priority
Kojto	120:7c328cabac7e	1692
Kojto	120:7c328cabac7e	1693	The function decodes an interrupt priority value with a given priority group to
Kojto	120:7c328cabac7e	1694	preemptive priority value and subpriority value.
Kojto	120:7c328cabac7e	1695	In case of a conflict between priority grouping and available
Kojto	120:7c328cabac7e	1696	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto	120:7c328cabac7e	1697
Kojto	120:7c328cabac7e	1698	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	120:7c328cabac7e	1699	\param [in] PriorityGroup Used priority group.
Kojto	120:7c328cabac7e	1700	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	120:7c328cabac7e	1701	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	120:7c328cabac7e	1702	*/
Kojto	120:7c328cabac7e	1703	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto	120:7c328cabac7e	1704	{
Kojto	120:7c328cabac7e	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	120:7c328cabac7e	1706	uint32_t PreemptPriorityBits;
Kojto	120:7c328cabac7e	1707	uint32_t SubPriorityBits;
Kojto	120:7c328cabac7e	1708
Kojto	120:7c328cabac7e	1709	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	120:7c328cabac7e	1710	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	120:7c328cabac7e	1711
Kojto	120:7c328cabac7e	1712	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	120:7c328cabac7e	1713	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto	120:7c328cabac7e	1714	}
Kojto	120:7c328cabac7e	1715
Kojto	120:7c328cabac7e	1716
Kojto	120:7c328cabac7e	1717	/** \brief System Reset
Kojto	120:7c328cabac7e	1718
Kojto	120:7c328cabac7e	1719	The function initiates a system reset request to reset the MCU.
Kojto	120:7c328cabac7e	1720	*/
Kojto	120:7c328cabac7e	1721	__STATIC_INLINE void NVIC_SystemReset(void)
Kojto	120:7c328cabac7e	1722	{
Kojto	120:7c328cabac7e	1723	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	120:7c328cabac7e	1724	buffered write are completed before reset */
Kojto	120:7c328cabac7e	1725	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	120:7c328cabac7e	1726	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	120:7c328cabac7e	1727	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	120:7c328cabac7e	1728	__DSB(); /* Ensure completion of memory access */
Kojto	120:7c328cabac7e	1729	while(1) { __NOP(); } /* wait until reset */
Kojto	120:7c328cabac7e	1730	}
Kojto	120:7c328cabac7e	1731
Kojto	120:7c328cabac7e	1732	/@} end of CMSIS_Core_NVICFunctions /
Kojto	120:7c328cabac7e	1733
Kojto	120:7c328cabac7e	1734
Kojto	120:7c328cabac7e	1735
Kojto	120:7c328cabac7e	1736	/* ################################## SysTick function ############################################ */
Kojto	120:7c328cabac7e	1737	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	120:7c328cabac7e	1738	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	120:7c328cabac7e	1739	\brief Functions that configure the System.
Kojto	120:7c328cabac7e	1740	@{
Kojto	120:7c328cabac7e	1741	*/
Kojto	120:7c328cabac7e	1742
Kojto	120:7c328cabac7e	1743	#if (__Vendor_SysTickConfig == 0)
Kojto	120:7c328cabac7e	1744
Kojto	120:7c328cabac7e	1745	/** \brief System Tick Configuration
Kojto	120:7c328cabac7e	1746
Kojto	120:7c328cabac7e	1747	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	120:7c328cabac7e	1748	Counter is in free running mode to generate periodic interrupts.
Kojto	120:7c328cabac7e	1749
Kojto	120:7c328cabac7e	1750	\param [in] ticks Number of ticks between two interrupts.
Kojto	120:7c328cabac7e	1751
Kojto	120:7c328cabac7e	1752	\return 0 Function succeeded.
Kojto	120:7c328cabac7e	1753	\return 1 Function failed.
Kojto	120:7c328cabac7e	1754
Kojto	120:7c328cabac7e	1755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	120:7c328cabac7e	1756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	120:7c328cabac7e	1757	must contain a vendor-specific implementation of this function.
Kojto	120:7c328cabac7e	1758
Kojto	120:7c328cabac7e	1759	*/
Kojto	120:7c328cabac7e	1760	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	120:7c328cabac7e	1761	{
Kojto	120:7c328cabac7e	1762	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto	120:7c328cabac7e	1763
Kojto	120:7c328cabac7e	1764	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	120:7c328cabac7e	1765	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	120:7c328cabac7e	1766	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	120:7c328cabac7e	1767	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	120:7c328cabac7e	1768	SysTick_CTRL_TICKINT_Msk \|
Kojto	120:7c328cabac7e	1769	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	120:7c328cabac7e	1770	return (0UL); /* Function successful */
Kojto	120:7c328cabac7e	1771	}
Kojto	120:7c328cabac7e	1772
Kojto	120:7c328cabac7e	1773	#endif
Kojto	120:7c328cabac7e	1774
Kojto	120:7c328cabac7e	1775	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	120:7c328cabac7e	1776
Kojto	120:7c328cabac7e	1777
Kojto	120:7c328cabac7e	1778
Kojto	120:7c328cabac7e	1779	/* ##################################### Debug In/Output function ########################################### */
Kojto	120:7c328cabac7e	1780	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	120:7c328cabac7e	1781	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	120:7c328cabac7e	1782	\brief Functions that access the ITM debug interface.
Kojto	120:7c328cabac7e	1783	@{
Kojto	120:7c328cabac7e	1784	*/
Kojto	120:7c328cabac7e	1785
Kojto	120:7c328cabac7e	1786	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	120:7c328cabac7e	1787	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	120:7c328cabac7e	1788
Kojto	120:7c328cabac7e	1789
Kojto	120:7c328cabac7e	1790	/** \brief ITM Send Character
Kojto	120:7c328cabac7e	1791
Kojto	120:7c328cabac7e	1792	The function transmits a character via the ITM channel 0, and
Kojto	120:7c328cabac7e	1793	\li Just returns when no debugger is connected that has booked the output.
Kojto	120:7c328cabac7e	1794	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	120:7c328cabac7e	1795
Kojto	120:7c328cabac7e	1796	\param [in] ch Character to transmit.
Kojto	120:7c328cabac7e	1797
Kojto	120:7c328cabac7e	1798	\returns Character to transmit.
Kojto	120:7c328cabac7e	1799	*/
Kojto	120:7c328cabac7e	1800	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	120:7c328cabac7e	1801	{
Kojto	120:7c328cabac7e	1802	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	120:7c328cabac7e	1803	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto	120:7c328cabac7e	1804	{
Kojto	120:7c328cabac7e	1805	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	120:7c328cabac7e	1806	ITM->PORT[0].u8 = (uint8_t)ch;
Kojto	120:7c328cabac7e	1807	}
Kojto	120:7c328cabac7e	1808	return (ch);
Kojto	120:7c328cabac7e	1809	}
Kojto	120:7c328cabac7e	1810
Kojto	120:7c328cabac7e	1811
Kojto	120:7c328cabac7e	1812	/** \brief ITM Receive Character
Kojto	120:7c328cabac7e	1813
Kojto	120:7c328cabac7e	1814	The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	120:7c328cabac7e	1815
Kojto	120:7c328cabac7e	1816	\return Received character.
Kojto	120:7c328cabac7e	1817	\return -1 No character pending.
Kojto	120:7c328cabac7e	1818	*/
Kojto	120:7c328cabac7e	1819	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto	120:7c328cabac7e	1820	int32_t ch = -1; /* no character available */
Kojto	120:7c328cabac7e	1821
Kojto	120:7c328cabac7e	1822	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto	120:7c328cabac7e	1823	ch = ITM_RxBuffer;
Kojto	120:7c328cabac7e	1824	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	120:7c328cabac7e	1825	}
Kojto	120:7c328cabac7e	1826
Kojto	120:7c328cabac7e	1827	return (ch);
Kojto	120:7c328cabac7e	1828	}
Kojto	120:7c328cabac7e	1829
Kojto	120:7c328cabac7e	1830
Kojto	120:7c328cabac7e	1831	/** \brief ITM Check Character
Kojto	120:7c328cabac7e	1832
Kojto	120:7c328cabac7e	1833	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	120:7c328cabac7e	1834
Kojto	120:7c328cabac7e	1835	\return 0 No character available.
Kojto	120:7c328cabac7e	1836	\return 1 Character available.
Kojto	120:7c328cabac7e	1837	*/
Kojto	120:7c328cabac7e	1838	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto	120:7c328cabac7e	1839
Kojto	120:7c328cabac7e	1840	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto	120:7c328cabac7e	1841	return (0); /* no character available */
Kojto	120:7c328cabac7e	1842	} else {
Kojto	120:7c328cabac7e	1843	return (1); /* character available */
Kojto	120:7c328cabac7e	1844	}
Kojto	120:7c328cabac7e	1845	}
Kojto	120:7c328cabac7e	1846
Kojto	120:7c328cabac7e	1847	/@} end of CMSIS_core_DebugFunctions /
Kojto	120:7c328cabac7e	1848
Kojto	120:7c328cabac7e	1849
Kojto	120:7c328cabac7e	1850
Kojto	120:7c328cabac7e	1851
Kojto	120:7c328cabac7e	1852	#ifdef __cplusplus
Kojto	120:7c328cabac7e	1853	}
Kojto	120:7c328cabac7e	1854	#endif
Kojto	120:7c328cabac7e	1855
Kojto	120:7c328cabac7e	1856	#endif /* __CORE_CM4_H_DEPENDANT */
Kojto	120:7c328cabac7e	1857
Kojto	120:7c328cabac7e	1858	#endif /* __CMSIS_GENERIC */