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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC2368/core_caFunc.h@121:6c34061e7c34, 2016-05-25 (annotated)

Committer:
Kojto
Date:
Wed May 25 16:44:06 2016 +0100
Revision:
121:6c34061e7c34
Parent:
115:87f2f5183dfb 
Release 121 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - F7 - analogin conversion fix

     - F1, F4 - serial flushed prior init fix

     - CAN added for F042K6,F072RB,F091RC

     - NUCLE_L053R8/F030R8/F070RB,F103RB - ticker 16bit counter fix

- NXP - LPC812 PWMOut conflict issue fix

      - KSDK - PWMout fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_caFunc.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-A Core Function Access Header File
bogdanm 92:4fc01daae5a5 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #ifndef __CORE_CAFUNC_H__
bogdanm 92:4fc01daae5a5 39 #define __CORE_CAFUNC_H__
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 /* ########################### Core Function Access ########################### */
bogdanm 92:4fc01daae5a5 43 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
bogdanm 92:4fc01daae5a5 45 @{
bogdanm 92:4fc01daae5a5 46 */
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 92:4fc01daae5a5 49 /* ARM armcc specific functions */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 #if (__ARMCC_VERSION < 400677)
bogdanm 92:4fc01daae5a5 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
bogdanm 92:4fc01daae5a5 53 #endif
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #define MODE_USR 0x10
bogdanm 92:4fc01daae5a5 56 #define MODE_FIQ 0x11
bogdanm 92:4fc01daae5a5 57 #define MODE_IRQ 0x12
bogdanm 92:4fc01daae5a5 58 #define MODE_SVC 0x13
bogdanm 92:4fc01daae5a5 59 #define MODE_MON 0x16
bogdanm 92:4fc01daae5a5 60 #define MODE_ABT 0x17
bogdanm 92:4fc01daae5a5 61 #define MODE_HYP 0x1A
bogdanm 92:4fc01daae5a5 62 #define MODE_UND 0x1B
bogdanm 92:4fc01daae5a5 63 #define MODE_SYS 0x1F
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 /** \brief Get APSR Register
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 This function returns the content of the APSR Register.
bogdanm 92:4fc01daae5a5 68
bogdanm 92:4fc01daae5a5 69 \return APSR Register value
bogdanm 92:4fc01daae5a5 70 */
bogdanm 92:4fc01daae5a5 71 __STATIC_INLINE uint32_t __get_APSR(void)
bogdanm 92:4fc01daae5a5 72 {
bogdanm 92:4fc01daae5a5 73 register uint32_t __regAPSR __ASM("apsr");
bogdanm 92:4fc01daae5a5 74 return(__regAPSR);
bogdanm 92:4fc01daae5a5 75 }
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 /** \brief Get CPSR Register
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 This function returns the content of the CPSR Register.
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 \return CPSR Register value
bogdanm 92:4fc01daae5a5 83 */
bogdanm 92:4fc01daae5a5 84 __STATIC_INLINE uint32_t __get_CPSR(void)
bogdanm 92:4fc01daae5a5 85 {
bogdanm 92:4fc01daae5a5 86 register uint32_t __regCPSR __ASM("cpsr");
bogdanm 92:4fc01daae5a5 87 return(__regCPSR);
bogdanm 92:4fc01daae5a5 88 }
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 /** \brief Set Stack Pointer
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 This function assigns the given value to the current stack pointer.
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 \param [in] topOfStack Stack Pointer value to set
bogdanm 92:4fc01daae5a5 95 */
bogdanm 92:4fc01daae5a5 96 register uint32_t __regSP __ASM("sp");
bogdanm 92:4fc01daae5a5 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
bogdanm 92:4fc01daae5a5 98 {
bogdanm 92:4fc01daae5a5 99 __regSP = topOfStack;
bogdanm 92:4fc01daae5a5 100 }
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 /** \brief Get link register
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 This function returns the value of the link register
bogdanm 92:4fc01daae5a5 106
bogdanm 92:4fc01daae5a5 107 \return Value of link register
bogdanm 92:4fc01daae5a5 108 */
bogdanm 92:4fc01daae5a5 109 register uint32_t __reglr __ASM("lr");
bogdanm 92:4fc01daae5a5 110 __STATIC_INLINE uint32_t __get_LR(void)
bogdanm 92:4fc01daae5a5 111 {
bogdanm 92:4fc01daae5a5 112 return(__reglr);
bogdanm 92:4fc01daae5a5 113 }
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 /** \brief Set link register
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 This function sets the value of the link register
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 \param [in] lr LR value to set
bogdanm 92:4fc01daae5a5 120 */
bogdanm 92:4fc01daae5a5 121 __STATIC_INLINE void __set_LR(uint32_t lr)
bogdanm 92:4fc01daae5a5 122 {
bogdanm 92:4fc01daae5a5 123 __reglr = lr;
bogdanm 92:4fc01daae5a5 124 }
bogdanm 92:4fc01daae5a5 125
bogdanm 92:4fc01daae5a5 126 /** \brief Set Process Stack Pointer
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
bogdanm 92:4fc01daae5a5 131 */
bogdanm 92:4fc01daae5a5 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
bogdanm 92:4fc01daae5a5 133 {
bogdanm 92:4fc01daae5a5 134 ARM
bogdanm 92:4fc01daae5a5 135 PRESERVE8
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
bogdanm 92:4fc01daae5a5 138 MRS R1, CPSR
bogdanm 92:4fc01daae5a5 139 CPS #MODE_SYS ;no effect in USR mode
bogdanm 92:4fc01daae5a5 140 MOV SP, R0
bogdanm 92:4fc01daae5a5 141 MSR CPSR_c, R1 ;no effect in USR mode
bogdanm 92:4fc01daae5a5 142 ISB
bogdanm 92:4fc01daae5a5 143 BX LR
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 }
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 /** \brief Set User Mode
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 This function changes the processor state to User Mode
bogdanm 92:4fc01daae5a5 150 */
bogdanm 92:4fc01daae5a5 151 __STATIC_ASM void __set_CPS_USR(void)
bogdanm 92:4fc01daae5a5 152 {
bogdanm 92:4fc01daae5a5 153 ARM
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 CPS #MODE_USR
bogdanm 92:4fc01daae5a5 156 BX LR
bogdanm 92:4fc01daae5a5 157 }
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 /** \brief Enable FIQ
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
bogdanm 92:4fc01daae5a5 163 Can only be executed in Privileged modes.
bogdanm 92:4fc01daae5a5 164 */
bogdanm 92:4fc01daae5a5 165 #define __enable_fault_irq __enable_fiq
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167
bogdanm 92:4fc01daae5a5 168 /** \brief Disable FIQ
bogdanm 92:4fc01daae5a5 169
bogdanm 92:4fc01daae5a5 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
bogdanm 92:4fc01daae5a5 171 Can only be executed in Privileged modes.
bogdanm 92:4fc01daae5a5 172 */
bogdanm 92:4fc01daae5a5 173 #define __disable_fault_irq __disable_fiq
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 /** \brief Get FPSCR
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 This function returns the current value of the Floating Point Status/Control register.
bogdanm 92:4fc01daae5a5 179
bogdanm 92:4fc01daae5a5 180 \return Floating Point Status/Control register value
bogdanm 92:4fc01daae5a5 181 */
bogdanm 92:4fc01daae5a5 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
bogdanm 92:4fc01daae5a5 183 {
bogdanm 92:4fc01daae5a5 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 92:4fc01daae5a5 185 register uint32_t __regfpscr __ASM("fpscr");
bogdanm 92:4fc01daae5a5 186 return(__regfpscr);
bogdanm 92:4fc01daae5a5 187 #else
bogdanm 92:4fc01daae5a5 188 return(0);
bogdanm 92:4fc01daae5a5 189 #endif
bogdanm 92:4fc01daae5a5 190 }
bogdanm 92:4fc01daae5a5 191
bogdanm 92:4fc01daae5a5 192
bogdanm 92:4fc01daae5a5 193 /** \brief Set FPSCR
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 This function assigns the given value to the Floating Point Status/Control register.
bogdanm 92:4fc01daae5a5 196
bogdanm 92:4fc01daae5a5 197 \param [in] fpscr Floating Point Status/Control value to set
bogdanm 92:4fc01daae5a5 198 */
bogdanm 92:4fc01daae5a5 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
bogdanm 92:4fc01daae5a5 200 {
bogdanm 92:4fc01daae5a5 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 92:4fc01daae5a5 202 register uint32_t __regfpscr __ASM("fpscr");
bogdanm 92:4fc01daae5a5 203 __regfpscr = (fpscr);
bogdanm 92:4fc01daae5a5 204 #endif
bogdanm 92:4fc01daae5a5 205 }
bogdanm 92:4fc01daae5a5 206
bogdanm 92:4fc01daae5a5 207 /** \brief Get FPEXC
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 This function returns the current value of the Floating Point Exception Control register.
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 \return Floating Point Exception Control register value
bogdanm 92:4fc01daae5a5 212 */
bogdanm 92:4fc01daae5a5 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
bogdanm 92:4fc01daae5a5 214 {
bogdanm 92:4fc01daae5a5 215 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 216 register uint32_t __regfpexc __ASM("fpexc");
bogdanm 92:4fc01daae5a5 217 return(__regfpexc);
bogdanm 92:4fc01daae5a5 218 #else
bogdanm 92:4fc01daae5a5 219 return(0);
bogdanm 92:4fc01daae5a5 220 #endif
bogdanm 92:4fc01daae5a5 221 }
bogdanm 92:4fc01daae5a5 222
bogdanm 92:4fc01daae5a5 223
bogdanm 92:4fc01daae5a5 224 /** \brief Set FPEXC
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 This function assigns the given value to the Floating Point Exception Control register.
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 \param [in] fpscr Floating Point Exception Control value to set
bogdanm 92:4fc01daae5a5 229 */
bogdanm 92:4fc01daae5a5 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
bogdanm 92:4fc01daae5a5 231 {
bogdanm 92:4fc01daae5a5 232 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 233 register uint32_t __regfpexc __ASM("fpexc");
bogdanm 92:4fc01daae5a5 234 __regfpexc = (fpexc);
bogdanm 92:4fc01daae5a5 235 #endif
bogdanm 92:4fc01daae5a5 236 }
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 /** \brief Get CPACR
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 This function returns the current value of the Coprocessor Access Control register.
bogdanm 92:4fc01daae5a5 241
bogdanm 92:4fc01daae5a5 242 \return Coprocessor Access Control register value
bogdanm 92:4fc01daae5a5 243 */
bogdanm 92:4fc01daae5a5 244 __STATIC_INLINE uint32_t __get_CPACR(void)
bogdanm 92:4fc01daae5a5 245 {
bogdanm 92:4fc01daae5a5 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
bogdanm 92:4fc01daae5a5 247 return __regCPACR;
bogdanm 92:4fc01daae5a5 248 }
bogdanm 92:4fc01daae5a5 249
bogdanm 92:4fc01daae5a5 250 /** \brief Set CPACR
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 This function assigns the given value to the Coprocessor Access Control register.
bogdanm 92:4fc01daae5a5 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
bogdanm 92:4fc01daae5a5 255 */
bogdanm 92:4fc01daae5a5 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
bogdanm 92:4fc01daae5a5 257 {
bogdanm 92:4fc01daae5a5 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
bogdanm 92:4fc01daae5a5 259 __regCPACR = cpacr;
bogdanm 92:4fc01daae5a5 260 __ISB();
bogdanm 92:4fc01daae5a5 261 }
bogdanm 92:4fc01daae5a5 262
bogdanm 92:4fc01daae5a5 263 /** \brief Get CBAR
bogdanm 92:4fc01daae5a5 264
bogdanm 92:4fc01daae5a5 265 This function returns the value of the Configuration Base Address register.
bogdanm 92:4fc01daae5a5 266
bogdanm 92:4fc01daae5a5 267 \return Configuration Base Address register value
bogdanm 92:4fc01daae5a5 268 */
bogdanm 92:4fc01daae5a5 269 __STATIC_INLINE uint32_t __get_CBAR() {
bogdanm 92:4fc01daae5a5 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
bogdanm 92:4fc01daae5a5 271 return(__regCBAR);
bogdanm 92:4fc01daae5a5 272 }
bogdanm 92:4fc01daae5a5 273
bogdanm 92:4fc01daae5a5 274 /** \brief Get TTBR0
bogdanm 92:4fc01daae5a5 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 \return Translation Table Base Register 0 value
bogdanm 92:4fc01daae5a5 279 */
bogdanm 92:4fc01daae5a5 280 __STATIC_INLINE uint32_t __get_TTBR0() {
bogdanm 92:4fc01daae5a5 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
bogdanm 92:4fc01daae5a5 282 return(__regTTBR0);
bogdanm 92:4fc01daae5a5 283 }
bogdanm 92:4fc01daae5a5 284
bogdanm 92:4fc01daae5a5 285 /** \brief Set TTBR0
bogdanm 92:4fc01daae5a5 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
bogdanm 92:4fc01daae5a5 288
bogdanm 92:4fc01daae5a5 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
bogdanm 92:4fc01daae5a5 290 */
bogdanm 92:4fc01daae5a5 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
bogdanm 92:4fc01daae5a5 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
bogdanm 92:4fc01daae5a5 293 __regTTBR0 = ttbr0;
bogdanm 92:4fc01daae5a5 294 __ISB();
bogdanm 92:4fc01daae5a5 295 }
bogdanm 92:4fc01daae5a5 296
bogdanm 92:4fc01daae5a5 297 /** \brief Get DACR
bogdanm 92:4fc01daae5a5 298
bogdanm 92:4fc01daae5a5 299 This function returns the value of the Domain Access Control Register.
bogdanm 92:4fc01daae5a5 300
bogdanm 92:4fc01daae5a5 301 \return Domain Access Control Register value
bogdanm 92:4fc01daae5a5 302 */
bogdanm 92:4fc01daae5a5 303 __STATIC_INLINE uint32_t __get_DACR() {
bogdanm 92:4fc01daae5a5 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
bogdanm 92:4fc01daae5a5 305 return(__regDACR);
bogdanm 92:4fc01daae5a5 306 }
bogdanm 92:4fc01daae5a5 307
bogdanm 92:4fc01daae5a5 308 /** \brief Set DACR
bogdanm 92:4fc01daae5a5 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 \param [in] dacr Domain Access Control Register value to set
bogdanm 92:4fc01daae5a5 313 */
bogdanm 92:4fc01daae5a5 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
bogdanm 92:4fc01daae5a5 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
bogdanm 92:4fc01daae5a5 316 __regDACR = dacr;
bogdanm 92:4fc01daae5a5 317 __ISB();
bogdanm 92:4fc01daae5a5 318 }
bogdanm 92:4fc01daae5a5 319
bogdanm 92:4fc01daae5a5 320 /******************************** Cache and BTAC enable ****************************************************/
bogdanm 92:4fc01daae5a5 321
bogdanm 92:4fc01daae5a5 322 /** \brief Set SCTLR
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 This function assigns the given value to the System Control Register.
bogdanm 92:4fc01daae5a5 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
bogdanm 92:4fc01daae5a5 327 */
bogdanm 92:4fc01daae5a5 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
bogdanm 92:4fc01daae5a5 329 {
bogdanm 92:4fc01daae5a5 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
bogdanm 92:4fc01daae5a5 331 __regSCTLR = sctlr;
bogdanm 92:4fc01daae5a5 332 }
bogdanm 92:4fc01daae5a5 333
bogdanm 92:4fc01daae5a5 334 /** \brief Get SCTLR
bogdanm 92:4fc01daae5a5 335
bogdanm 92:4fc01daae5a5 336 This function returns the value of the System Control Register.
bogdanm 92:4fc01daae5a5 337
bogdanm 92:4fc01daae5a5 338 \return System Control Register value
bogdanm 92:4fc01daae5a5 339 */
bogdanm 92:4fc01daae5a5 340 __STATIC_INLINE uint32_t __get_SCTLR() {
bogdanm 92:4fc01daae5a5 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
bogdanm 92:4fc01daae5a5 342 return(__regSCTLR);
bogdanm 92:4fc01daae5a5 343 }
bogdanm 92:4fc01daae5a5 344
bogdanm 92:4fc01daae5a5 345 /** \brief Enable Caches
bogdanm 92:4fc01daae5a5 346
bogdanm 92:4fc01daae5a5 347 Enable Caches
bogdanm 92:4fc01daae5a5 348 */
bogdanm 92:4fc01daae5a5 349 __STATIC_INLINE void __enable_caches(void) {
bogdanm 92:4fc01daae5a5 350 // Set I bit 12 to enable I Cache
bogdanm 92:4fc01daae5a5 351 // Set C bit 2 to enable D Cache
bogdanm 92:4fc01daae5a5 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
bogdanm 92:4fc01daae5a5 353 }
bogdanm 92:4fc01daae5a5 354
bogdanm 92:4fc01daae5a5 355 /** \brief Disable Caches
bogdanm 92:4fc01daae5a5 356
bogdanm 92:4fc01daae5a5 357 Disable Caches
bogdanm 92:4fc01daae5a5 358 */
bogdanm 92:4fc01daae5a5 359 __STATIC_INLINE void __disable_caches(void) {
bogdanm 92:4fc01daae5a5 360 // Clear I bit 12 to disable I Cache
bogdanm 92:4fc01daae5a5 361 // Clear C bit 2 to disable D Cache
bogdanm 92:4fc01daae5a5 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
bogdanm 92:4fc01daae5a5 363 __ISB();
bogdanm 92:4fc01daae5a5 364 }
bogdanm 92:4fc01daae5a5 365
bogdanm 92:4fc01daae5a5 366 /** \brief Enable BTAC
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 Enable BTAC
bogdanm 92:4fc01daae5a5 369 */
bogdanm 92:4fc01daae5a5 370 __STATIC_INLINE void __enable_btac(void) {
bogdanm 92:4fc01daae5a5 371 // Set Z bit 11 to enable branch prediction
bogdanm 92:4fc01daae5a5 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
bogdanm 92:4fc01daae5a5 373 __ISB();
bogdanm 92:4fc01daae5a5 374 }
bogdanm 92:4fc01daae5a5 375
bogdanm 92:4fc01daae5a5 376 /** \brief Disable BTAC
bogdanm 92:4fc01daae5a5 377
bogdanm 92:4fc01daae5a5 378 Disable BTAC
bogdanm 92:4fc01daae5a5 379 */
bogdanm 92:4fc01daae5a5 380 __STATIC_INLINE void __disable_btac(void) {
bogdanm 92:4fc01daae5a5 381 // Clear Z bit 11 to disable branch prediction
bogdanm 92:4fc01daae5a5 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
bogdanm 92:4fc01daae5a5 383 }
bogdanm 92:4fc01daae5a5 384
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /** \brief Enable MMU
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 Enable MMU
bogdanm 92:4fc01daae5a5 389 */
bogdanm 92:4fc01daae5a5 390 __STATIC_INLINE void __enable_mmu(void) {
bogdanm 92:4fc01daae5a5 391 // Set M bit 0 to enable the MMU
bogdanm 92:4fc01daae5a5 392 // Set AFE bit to enable simplified access permissions model
bogdanm 92:4fc01daae5a5 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
bogdanm 92:4fc01daae5a5 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
bogdanm 92:4fc01daae5a5 395 __ISB();
bogdanm 92:4fc01daae5a5 396 }
bogdanm 92:4fc01daae5a5 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
bogdanm 92:4fc01daae5a5 399
Kojto 108:34e6b704fe68 400 Disable MMU
bogdanm 92:4fc01daae5a5 401 */
bogdanm 92:4fc01daae5a5 402 __STATIC_INLINE void __disable_mmu(void) {
bogdanm 92:4fc01daae5a5 403 // Clear M bit 0 to disable the MMU
bogdanm 92:4fc01daae5a5 404 __set_SCTLR( __get_SCTLR() & ~1);
bogdanm 92:4fc01daae5a5 405 __ISB();
bogdanm 92:4fc01daae5a5 406 }
bogdanm 92:4fc01daae5a5 407
bogdanm 92:4fc01daae5a5 408 /******************************** TLB maintenance operations ************************************************/
bogdanm 92:4fc01daae5a5 409 /** \brief Invalidate the whole tlb
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 TLBIALL. Invalidate the whole tlb
bogdanm 92:4fc01daae5a5 412 */
bogdanm 92:4fc01daae5a5 413
bogdanm 92:4fc01daae5a5 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
bogdanm 92:4fc01daae5a5 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
bogdanm 92:4fc01daae5a5 416 __TLBIALL = 0;
bogdanm 92:4fc01daae5a5 417 __DSB();
bogdanm 92:4fc01daae5a5 418 __ISB();
bogdanm 92:4fc01daae5a5 419 }
bogdanm 92:4fc01daae5a5 420
bogdanm 92:4fc01daae5a5 421 /******************************** BTB maintenance operations ************************************************/
bogdanm 92:4fc01daae5a5 422 /** \brief Invalidate entire branch predictor array
bogdanm 92:4fc01daae5a5 423
bogdanm 92:4fc01daae5a5 424 BPIALL. Branch Predictor Invalidate All.
bogdanm 92:4fc01daae5a5 425 */
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 __STATIC_INLINE void __v7_inv_btac(void) {
bogdanm 92:4fc01daae5a5 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
bogdanm 92:4fc01daae5a5 429 __BPIALL = 0;
bogdanm 92:4fc01daae5a5 430 __DSB(); //ensure completion of the invalidation
bogdanm 92:4fc01daae5a5 431 __ISB(); //ensure instruction fetch path sees new state
bogdanm 92:4fc01daae5a5 432 }
bogdanm 92:4fc01daae5a5 433
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 /******************************** L1 cache operations ******************************************************/
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 /** \brief Invalidate the whole I$
bogdanm 92:4fc01daae5a5 438
bogdanm 92:4fc01daae5a5 439 ICIALLU. Instruction Cache Invalidate All to PoU
bogdanm 92:4fc01daae5a5 440 */
bogdanm 92:4fc01daae5a5 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
bogdanm 92:4fc01daae5a5 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
bogdanm 92:4fc01daae5a5 443 __ICIALLU = 0;
bogdanm 92:4fc01daae5a5 444 __DSB(); //ensure completion of the invalidation
bogdanm 92:4fc01daae5a5 445 __ISB(); //ensure instruction fetch path sees new I cache state
bogdanm 92:4fc01daae5a5 446 }
bogdanm 92:4fc01daae5a5 447
bogdanm 92:4fc01daae5a5 448 /** \brief Clean D$ by MVA
bogdanm 92:4fc01daae5a5 449
bogdanm 92:4fc01daae5a5 450 DCCMVAC. Data cache clean by MVA to PoC
bogdanm 92:4fc01daae5a5 451 */
bogdanm 92:4fc01daae5a5 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
bogdanm 92:4fc01daae5a5 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
bogdanm 92:4fc01daae5a5 454 __DCCMVAC = (uint32_t)va;
bogdanm 92:4fc01daae5a5 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
bogdanm 92:4fc01daae5a5 456 }
bogdanm 92:4fc01daae5a5 457
bogdanm 92:4fc01daae5a5 458 /** \brief Invalidate D$ by MVA
bogdanm 92:4fc01daae5a5 459
bogdanm 92:4fc01daae5a5 460 DCIMVAC. Data cache invalidate by MVA to PoC
bogdanm 92:4fc01daae5a5 461 */
bogdanm 92:4fc01daae5a5 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
bogdanm 92:4fc01daae5a5 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
bogdanm 92:4fc01daae5a5 464 __DCIMVAC = (uint32_t)va;
bogdanm 92:4fc01daae5a5 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
bogdanm 92:4fc01daae5a5 466 }
bogdanm 92:4fc01daae5a5 467
bogdanm 92:4fc01daae5a5 468 /** \brief Clean and Invalidate D$ by MVA
bogdanm 92:4fc01daae5a5 469
bogdanm 92:4fc01daae5a5 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
bogdanm 92:4fc01daae5a5 471 */
bogdanm 92:4fc01daae5a5 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
bogdanm 92:4fc01daae5a5 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
bogdanm 92:4fc01daae5a5 474 __DCCIMVAC = (uint32_t)va;
bogdanm 92:4fc01daae5a5 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
bogdanm 92:4fc01daae5a5 476 }
bogdanm 92:4fc01daae5a5 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
bogdanm 92:4fc01daae5a5 481 */
bogdanm 92:4fc01daae5a5 482 #pragma push
bogdanm 92:4fc01daae5a5 483 #pragma arm
bogdanm 92:4fc01daae5a5 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
bogdanm 92:4fc01daae5a5 485 ARM
bogdanm 92:4fc01daae5a5 486
bogdanm 92:4fc01daae5a5 487 PUSH {R4-R11}
bogdanm 92:4fc01daae5a5 488
bogdanm 92:4fc01daae5a5 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
bogdanm 92:4fc01daae5a5 490 ANDS R3, R6, #0x07000000 // Extract coherency level
bogdanm 92:4fc01daae5a5 491 MOV R3, R3, LSR #23 // Total cache levels << 1
bogdanm 92:4fc01daae5a5 492 BEQ Finished // If 0, no need to clean
bogdanm 92:4fc01daae5a5 493
bogdanm 92:4fc01daae5a5 494 MOV R10, #0 // R10 holds current cache level << 1
bogdanm 92:4fc01daae5a5 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
bogdanm 92:4fc01daae5a5 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
bogdanm 92:4fc01daae5a5 497 AND R1, R1, #7 // Isolate those lower 3 bits
bogdanm 92:4fc01daae5a5 498 CMP R1, #2
bogdanm 92:4fc01daae5a5 499 BLT Skip // No cache or only instruction cache at this level
bogdanm 92:4fc01daae5a5 500
bogdanm 92:4fc01daae5a5 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
bogdanm 92:4fc01daae5a5 502 ISB // ISB to sync the change to the CacheSizeID reg
bogdanm 92:4fc01daae5a5 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
bogdanm 92:4fc01daae5a5 504 AND R2, R1, #7 // Extract the line length field
bogdanm 92:4fc01daae5a5 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
bogdanm 92:4fc01daae5a5 506 LDR R4, =0x3FF
bogdanm 92:4fc01daae5a5 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
bogdanm 92:4fc01daae5a5 508 CLZ R5, R4 // R5 is the bit position of the way size increment
bogdanm 92:4fc01daae5a5 509 LDR R7, =0x7FFF
bogdanm 92:4fc01daae5a5 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
bogdanm 92:4fc01daae5a5 511
bogdanm 92:4fc01daae5a5 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
bogdanm 92:4fc01daae5a5 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
bogdanm 92:4fc01daae5a5 516 CMP R0, #0
bogdanm 92:4fc01daae5a5 517 BNE Dccsw
bogdanm 92:4fc01daae5a5 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 519 B cont
bogdanm 92:4fc01daae5a5 520 Dccsw CMP R0, #1
bogdanm 92:4fc01daae5a5 521 BNE Dccisw
bogdanm 92:4fc01daae5a5 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
bogdanm 92:4fc01daae5a5 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 525 cont SUBS R9, R9, #1 // Decrement the Way number
bogdanm 92:4fc01daae5a5 526 BGE Loop3
bogdanm 92:4fc01daae5a5 527 SUBS R7, R7, #1 // Decrement the Set number
bogdanm 92:4fc01daae5a5 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
bogdanm 92:4fc01daae5a5 530 CMP R3, R10
bogdanm 92:4fc01daae5a5 531 BGT Loop1
bogdanm 92:4fc01daae5a5 532
bogdanm 92:4fc01daae5a5 533 Finished
bogdanm 92:4fc01daae5a5 534 DSB
bogdanm 92:4fc01daae5a5 535 POP {R4-R11}
bogdanm 92:4fc01daae5a5 536 BX lr
bogdanm 92:4fc01daae5a5 537
bogdanm 92:4fc01daae5a5 538 }
bogdanm 92:4fc01daae5a5 539 #pragma pop
bogdanm 92:4fc01daae5a5 540
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 /** \brief Invalidate the whole D$
bogdanm 92:4fc01daae5a5 543
bogdanm 92:4fc01daae5a5 544 DCISW. Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 545 */
bogdanm 92:4fc01daae5a5 546
bogdanm 92:4fc01daae5a5 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
bogdanm 92:4fc01daae5a5 548 __v7_all_cache(0);
bogdanm 92:4fc01daae5a5 549 }
bogdanm 92:4fc01daae5a5 550
bogdanm 92:4fc01daae5a5 551 /** \brief Clean the whole D$
bogdanm 92:4fc01daae5a5 552
bogdanm 92:4fc01daae5a5 553 DCCSW. Clean by Set/Way
bogdanm 92:4fc01daae5a5 554 */
bogdanm 92:4fc01daae5a5 555
bogdanm 92:4fc01daae5a5 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
bogdanm 92:4fc01daae5a5 557 __v7_all_cache(1);
bogdanm 92:4fc01daae5a5 558 }
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 /** \brief Clean and invalidate the whole D$
bogdanm 92:4fc01daae5a5 561
bogdanm 92:4fc01daae5a5 562 DCCISW. Clean and Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 563 */
bogdanm 92:4fc01daae5a5 564
bogdanm 92:4fc01daae5a5 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
bogdanm 92:4fc01daae5a5 566 __v7_all_cache(2);
bogdanm 92:4fc01daae5a5 567 }
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 #include "core_ca_mmu.h"
bogdanm 92:4fc01daae5a5 570
bogdanm 92:4fc01daae5a5 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
bogdanm 92:4fc01daae5a5 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
Kojto 121:6c34061e7c34 814 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 815
Kojto 121:6c34061e7c34 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 817 */
Kojto 121:6c34061e7c34 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 820 __DMB();
Kojto 121:6c34061e7c34 821 }
Kojto 121:6c34061e7c34 822
Kojto 115:87f2f5183dfb 823 #include "core_ca_mmu.h"
bogdanm 92:4fc01daae5a5 824
bogdanm 92:4fc01daae5a5 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 95:7e07b6fb45cf 826 /* GNU gcc specific functions */
Kojto 95:7e07b6fb45cf 827
Kojto 95:7e07b6fb45cf 828 #define MODE_USR 0x10
Kojto 95:7e07b6fb45cf 829 #define MODE_FIQ 0x11
Kojto 95:7e07b6fb45cf 830 #define MODE_IRQ 0x12
Kojto 95:7e07b6fb45cf 831 #define MODE_SVC 0x13
Kojto 95:7e07b6fb45cf 832 #define MODE_MON 0x16
Kojto 95:7e07b6fb45cf 833 #define MODE_ABT 0x17
Kojto 95:7e07b6fb45cf 834 #define MODE_HYP 0x1A
Kojto 95:7e07b6fb45cf 835 #define MODE_UND 0x1B
Kojto 95:7e07b6fb45cf 836 #define MODE_SYS 0x1F
Kojto 95:7e07b6fb45cf 837
Kojto 95:7e07b6fb45cf 838
Kojto 95:7e07b6fb45cf 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 95:7e07b6fb45cf 840 {
Kojto 95:7e07b6fb45cf 841 __ASM volatile ("cpsie i");
Kojto 95:7e07b6fb45cf 842 }
Kojto 95:7e07b6fb45cf 843
Kojto 95:7e07b6fb45cf 844 /** \brief Disable IRQ Interrupts
Kojto 95:7e07b6fb45cf 845
Kojto 95:7e07b6fb45cf 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 95:7e07b6fb45cf 847 Can only be executed in Privileged modes.
Kojto 95:7e07b6fb45cf 848 */
Kojto 95:7e07b6fb45cf 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 95:7e07b6fb45cf 850 {
Kojto 95:7e07b6fb45cf 851 uint32_t result;
Kojto 95:7e07b6fb45cf 852
Kojto 95:7e07b6fb45cf 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 95:7e07b6fb45cf 854 __ASM volatile ("cpsid i");
Kojto 95:7e07b6fb45cf 855 return(result & 0x80);
Kojto 95:7e07b6fb45cf 856 }
Kojto 95:7e07b6fb45cf 857
Kojto 95:7e07b6fb45cf 858
Kojto 95:7e07b6fb45cf 859 /** \brief Get APSR Register
Kojto 95:7e07b6fb45cf 860
Kojto 95:7e07b6fb45cf 861 This function returns the content of the APSR Register.
Kojto 95:7e07b6fb45cf 862
Kojto 95:7e07b6fb45cf 863 \return APSR Register value
Kojto 95:7e07b6fb45cf 864 */
Kojto 95:7e07b6fb45cf 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 95:7e07b6fb45cf 866 {
Kojto 95:7e07b6fb45cf 867 #if 1
Kojto 108:34e6b704fe68 868 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 95:7e07b6fb45cf 870 #else
Kojto 95:7e07b6fb45cf 871 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 872 #endif
Kojto 95:7e07b6fb45cf 873 return(__regAPSR);
Kojto 95:7e07b6fb45cf 874 }
Kojto 95:7e07b6fb45cf 875
Kojto 95:7e07b6fb45cf 876
Kojto 95:7e07b6fb45cf 877 /** \brief Get CPSR Register
Kojto 95:7e07b6fb45cf 878
Kojto 95:7e07b6fb45cf 879 This function returns the content of the CPSR Register.
Kojto 95:7e07b6fb45cf 880
Kojto 95:7e07b6fb45cf 881 \return CPSR Register value
Kojto 95:7e07b6fb45cf 882 */
Kojto 95:7e07b6fb45cf 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 95:7e07b6fb45cf 884 {
Kojto 95:7e07b6fb45cf 885 #if 1
Kojto 95:7e07b6fb45cf 886 register uint32_t __regCPSR;
Kojto 95:7e07b6fb45cf 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 95:7e07b6fb45cf 888 #else
Kojto 95:7e07b6fb45cf 889 register uint32_t __regCPSR __ASM("cpsr");
Kojto 95:7e07b6fb45cf 890 #endif
Kojto 95:7e07b6fb45cf 891 return(__regCPSR);
Kojto 95:7e07b6fb45cf 892 }
Kojto 95:7e07b6fb45cf 893
Kojto 95:7e07b6fb45cf 894 #if 0
Kojto 95:7e07b6fb45cf 895 /** \brief Set Stack Pointer
Kojto 95:7e07b6fb45cf 896
Kojto 95:7e07b6fb45cf 897 This function assigns the given value to the current stack pointer.
Kojto 95:7e07b6fb45cf 898
Kojto 95:7e07b6fb45cf 899 \param [in] topOfStack Stack Pointer value to set
Kojto 95:7e07b6fb45cf 900 */
Kojto 95:7e07b6fb45cf 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 95:7e07b6fb45cf 902 {
Kojto 95:7e07b6fb45cf 903 register uint32_t __regSP __ASM("sp");
Kojto 95:7e07b6fb45cf 904 __regSP = topOfStack;
Kojto 95:7e07b6fb45cf 905 }
Kojto 95:7e07b6fb45cf 906 #endif
Kojto 95:7e07b6fb45cf 907
Kojto 95:7e07b6fb45cf 908 /** \brief Get link register
Kojto 95:7e07b6fb45cf 909
Kojto 95:7e07b6fb45cf 910 This function returns the value of the link register
Kojto 95:7e07b6fb45cf 911
Kojto 95:7e07b6fb45cf 912 \return Value of link register
Kojto 95:7e07b6fb45cf 913 */
Kojto 95:7e07b6fb45cf 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 95:7e07b6fb45cf 915 {
Kojto 95:7e07b6fb45cf 916 register uint32_t __reglr __ASM("lr");
Kojto 95:7e07b6fb45cf 917 return(__reglr);
Kojto 95:7e07b6fb45cf 918 }
Kojto 95:7e07b6fb45cf 919
Kojto 95:7e07b6fb45cf 920 #if 0
Kojto 95:7e07b6fb45cf 921 /** \brief Set link register
Kojto 95:7e07b6fb45cf 922
Kojto 95:7e07b6fb45cf 923 This function sets the value of the link register
Kojto 95:7e07b6fb45cf 924
Kojto 95:7e07b6fb45cf 925 \param [in] lr LR value to set
Kojto 95:7e07b6fb45cf 926 */
Kojto 95:7e07b6fb45cf 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 95:7e07b6fb45cf 928 {
Kojto 95:7e07b6fb45cf 929 register uint32_t __reglr __ASM("lr");
Kojto 95:7e07b6fb45cf 930 __reglr = lr;
Kojto 95:7e07b6fb45cf 931 }
Kojto 95:7e07b6fb45cf 932 #endif
Kojto 95:7e07b6fb45cf 933
Kojto 95:7e07b6fb45cf 934 /** \brief Set Process Stack Pointer
Kojto 95:7e07b6fb45cf 935
Kojto 95:7e07b6fb45cf 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 95:7e07b6fb45cf 937
Kojto 95:7e07b6fb45cf 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 95:7e07b6fb45cf 939 */
Kojto 108:34e6b704fe68 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 941 {
Kojto 108:34e6b704fe68 942 __asm__ volatile (
Kojto 108:34e6b704fe68 943 ".ARM;"
Kojto 108:34e6b704fe68 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 945
Kojto 108:34e6b704fe68 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 947 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 948 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 949 "MOV SP, R0;"
Kojto 108:34e6b704fe68 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 951 "ISB;"
Kojto 108:34e6b704fe68 952 //"BX LR;"
Kojto 108:34e6b704fe68 953 :
Kojto 108:34e6b704fe68 954 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 955 : "r0", "r1");
Kojto 108:34e6b704fe68 956 return;
Kojto 108:34e6b704fe68 957 }
Kojto 95:7e07b6fb45cf 958
Kojto 95:7e07b6fb45cf 959 /** \brief Set User Mode
Kojto 95:7e07b6fb45cf 960
Kojto 95:7e07b6fb45cf 961 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 962 */
Kojto 108:34e6b704fe68 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 964 {
Kojto 108:34e6b704fe68 965 __asm__ volatile (
Kojto 108:34e6b704fe68 966 ".ARM;"
Kojto 95:7e07b6fb45cf 967
Kojto 108:34e6b704fe68 968 "CPS %0;"
Kojto 108:34e6b704fe68 969 //"BX LR;"
Kojto 108:34e6b704fe68 970 :
Kojto 108:34e6b704fe68 971 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 972 : );
Kojto 108:34e6b704fe68 973 return;
Kojto 108:34e6b704fe68 974 }
Kojto 108:34e6b704fe68 975
Kojto 95:7e07b6fb45cf 976
Kojto 95:7e07b6fb45cf 977 /** \brief Enable FIQ
Kojto 95:7e07b6fb45cf 978
Kojto 95:7e07b6fb45cf 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 95:7e07b6fb45cf 980 Can only be executed in Privileged modes.
Kojto 95:7e07b6fb45cf 981 */
Kojto 108:34e6b704fe68 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 95:7e07b6fb45cf 983
Kojto 95:7e07b6fb45cf 984
Kojto 95:7e07b6fb45cf 985 /** \brief Disable FIQ
Kojto 95:7e07b6fb45cf 986
Kojto 95:7e07b6fb45cf 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 95:7e07b6fb45cf 988 Can only be executed in Privileged modes.
Kojto 95:7e07b6fb45cf 989 */
Kojto 108:34e6b704fe68 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 95:7e07b6fb45cf 991
Kojto 95:7e07b6fb45cf 992
Kojto 95:7e07b6fb45cf 993 /** \brief Get FPSCR
Kojto 95:7e07b6fb45cf 994
Kojto 95:7e07b6fb45cf 995 This function returns the current value of the Floating Point Status/Control register.
Kojto 95:7e07b6fb45cf 996
Kojto 95:7e07b6fb45cf 997 \return Floating Point Status/Control register value
Kojto 95:7e07b6fb45cf 998 */
Kojto 95:7e07b6fb45cf 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 95:7e07b6fb45cf 1000 {
Kojto 95:7e07b6fb45cf 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 95:7e07b6fb45cf 1002 #if 1
Kojto 95:7e07b6fb45cf 1003 uint32_t result;
Kojto 95:7e07b6fb45cf 1004
Kojto 95:7e07b6fb45cf 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 95:7e07b6fb45cf 1006 return (result);
Kojto 95:7e07b6fb45cf 1007 #else
Kojto 95:7e07b6fb45cf 1008 register uint32_t __regfpscr __ASM("fpscr");
Kojto 95:7e07b6fb45cf 1009 return(__regfpscr);
Kojto 95:7e07b6fb45cf 1010 #endif
Kojto 95:7e07b6fb45cf 1011 #else
Kojto 95:7e07b6fb45cf 1012 return(0);
Kojto 95:7e07b6fb45cf 1013 #endif
Kojto 95:7e07b6fb45cf 1014 }
Kojto 95:7e07b6fb45cf 1015
Kojto 95:7e07b6fb45cf 1016
Kojto 95:7e07b6fb45cf 1017 /** \brief Set FPSCR
Kojto 95:7e07b6fb45cf 1018
Kojto 95:7e07b6fb45cf 1019 This function assigns the given value to the Floating Point Status/Control register.
Kojto 95:7e07b6fb45cf 1020
Kojto 95:7e07b6fb45cf 1021 \param [in] fpscr Floating Point Status/Control value to set
Kojto 95:7e07b6fb45cf 1022 */
Kojto 95:7e07b6fb45cf 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 95:7e07b6fb45cf 1024 {
Kojto 95:7e07b6fb45cf 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 95:7e07b6fb45cf 1026 #if 1
Kojto 95:7e07b6fb45cf 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 95:7e07b6fb45cf 1028 #else
Kojto 95:7e07b6fb45cf 1029 register uint32_t __regfpscr __ASM("fpscr");
Kojto 95:7e07b6fb45cf 1030 __regfpscr = (fpscr);
Kojto 95:7e07b6fb45cf 1031 #endif
Kojto 95:7e07b6fb45cf 1032 #endif
Kojto 95:7e07b6fb45cf 1033 }
Kojto 95:7e07b6fb45cf 1034
Kojto 95:7e07b6fb45cf 1035 /** \brief Get FPEXC
Kojto 95:7e07b6fb45cf 1036
Kojto 95:7e07b6fb45cf 1037 This function returns the current value of the Floating Point Exception Control register.
Kojto 95:7e07b6fb45cf 1038
Kojto 95:7e07b6fb45cf 1039 \return Floating Point Exception Control register value
Kojto 95:7e07b6fb45cf 1040 */
Kojto 95:7e07b6fb45cf 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 95:7e07b6fb45cf 1042 {
Kojto 95:7e07b6fb45cf 1043 #if (__FPU_PRESENT == 1)
Kojto 95:7e07b6fb45cf 1044 #if 1
Kojto 95:7e07b6fb45cf 1045 uint32_t result;
Kojto 95:7e07b6fb45cf 1046
Kojto 95:7e07b6fb45cf 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 95:7e07b6fb45cf 1048 return (result);
Kojto 95:7e07b6fb45cf 1049 #else
Kojto 95:7e07b6fb45cf 1050 register uint32_t __regfpexc __ASM("fpexc");
Kojto 95:7e07b6fb45cf 1051 return(__regfpexc);
Kojto 95:7e07b6fb45cf 1052 #endif
Kojto 95:7e07b6fb45cf 1053 #else
Kojto 95:7e07b6fb45cf 1054 return(0);
Kojto 95:7e07b6fb45cf 1055 #endif
Kojto 95:7e07b6fb45cf 1056 }
Kojto 95:7e07b6fb45cf 1057
Kojto 95:7e07b6fb45cf 1058
Kojto 95:7e07b6fb45cf 1059 /** \brief Set FPEXC
Kojto 95:7e07b6fb45cf 1060
Kojto 95:7e07b6fb45cf 1061 This function assigns the given value to the Floating Point Exception Control register.
Kojto 95:7e07b6fb45cf 1062
Kojto 95:7e07b6fb45cf 1063 \param [in] fpscr Floating Point Exception Control value to set
Kojto 95:7e07b6fb45cf 1064 */
Kojto 95:7e07b6fb45cf 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 95:7e07b6fb45cf 1066 {
Kojto 95:7e07b6fb45cf 1067 #if (__FPU_PRESENT == 1)
Kojto 95:7e07b6fb45cf 1068 #if 1
Kojto 95:7e07b6fb45cf 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 95:7e07b6fb45cf 1070 #else
Kojto 95:7e07b6fb45cf 1071 register uint32_t __regfpexc __ASM("fpexc");
Kojto 95:7e07b6fb45cf 1072 __regfpexc = (fpexc);
Kojto 95:7e07b6fb45cf 1073 #endif
Kojto 95:7e07b6fb45cf 1074 #endif
Kojto 95:7e07b6fb45cf 1075 }
Kojto 95:7e07b6fb45cf 1076
Kojto 95:7e07b6fb45cf 1077 /** \brief Get CPACR
Kojto 95:7e07b6fb45cf 1078
Kojto 95:7e07b6fb45cf 1079 This function returns the current value of the Coprocessor Access Control register.
Kojto 95:7e07b6fb45cf 1080
Kojto 95:7e07b6fb45cf 1081 \return Coprocessor Access Control register value
Kojto 95:7e07b6fb45cf 1082 */
Kojto 95:7e07b6fb45cf 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 95:7e07b6fb45cf 1084 {
Kojto 95:7e07b6fb45cf 1085 #if 1
Kojto 95:7e07b6fb45cf 1086 register uint32_t __regCPACR;
Kojto 95:7e07b6fb45cf 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 95:7e07b6fb45cf 1088 #else
Kojto 95:7e07b6fb45cf 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 95:7e07b6fb45cf 1090 #endif
Kojto 95:7e07b6fb45cf 1091 return __regCPACR;
Kojto 95:7e07b6fb45cf 1092 }
Kojto 95:7e07b6fb45cf 1093
Kojto 95:7e07b6fb45cf 1094 /** \brief Set CPACR
Kojto 95:7e07b6fb45cf 1095
Kojto 95:7e07b6fb45cf 1096 This function assigns the given value to the Coprocessor Access Control register.
Kojto 95:7e07b6fb45cf 1097
Kojto 108:34e6b704fe68 1098 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 95:7e07b6fb45cf 1099 */
Kojto 95:7e07b6fb45cf 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 95:7e07b6fb45cf 1101 {
Kojto 95:7e07b6fb45cf 1102 #if 1
Kojto 95:7e07b6fb45cf 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 95:7e07b6fb45cf 1104 #else
Kojto 95:7e07b6fb45cf 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 95:7e07b6fb45cf 1106 __regCPACR = cpacr;
Kojto 95:7e07b6fb45cf 1107 #endif
Kojto 95:7e07b6fb45cf 1108 __ISB();
Kojto 95:7e07b6fb45cf 1109 }
Kojto 95:7e07b6fb45cf 1110
Kojto 95:7e07b6fb45cf 1111 /** \brief Get CBAR
Kojto 95:7e07b6fb45cf 1112
Kojto 95:7e07b6fb45cf 1113 This function returns the value of the Configuration Base Address register.
Kojto 95:7e07b6fb45cf 1114
Kojto 95:7e07b6fb45cf 1115 \return Configuration Base Address register value
Kojto 95:7e07b6fb45cf 1116 */
Kojto 95:7e07b6fb45cf 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 95:7e07b6fb45cf 1118 #if 1
Kojto 95:7e07b6fb45cf 1119 register uint32_t __regCBAR;
Kojto 95:7e07b6fb45cf 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 95:7e07b6fb45cf 1121 #else
Kojto 95:7e07b6fb45cf 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 95:7e07b6fb45cf 1123 #endif
Kojto 95:7e07b6fb45cf 1124 return(__regCBAR);
Kojto 95:7e07b6fb45cf 1125 }
Kojto 95:7e07b6fb45cf 1126
Kojto 95:7e07b6fb45cf 1127 /** \brief Get TTBR0
Kojto 95:7e07b6fb45cf 1128
Kojto 108:34e6b704fe68 1129 This function returns the value of the Translation Table Base Register 0.
Kojto 95:7e07b6fb45cf 1130
Kojto 95:7e07b6fb45cf 1131 \return Translation Table Base Register 0 value
Kojto 95:7e07b6fb45cf 1132 */
Kojto 95:7e07b6fb45cf 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 95:7e07b6fb45cf 1134 #if 1
Kojto 95:7e07b6fb45cf 1135 register uint32_t __regTTBR0;
Kojto 95:7e07b6fb45cf 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 95:7e07b6fb45cf 1137 #else
Kojto 95:7e07b6fb45cf 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 95:7e07b6fb45cf 1139 #endif
Kojto 95:7e07b6fb45cf 1140 return(__regTTBR0);
Kojto 95:7e07b6fb45cf 1141 }
Kojto 95:7e07b6fb45cf 1142
Kojto 95:7e07b6fb45cf 1143 /** \brief Set TTBR0
Kojto 95:7e07b6fb45cf 1144
Kojto 108:34e6b704fe68 1145 This function assigns the given value to the Translation Table Base Register 0.
Kojto 95:7e07b6fb45cf 1146
Kojto 95:7e07b6fb45cf 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 95:7e07b6fb45cf 1148 */
Kojto 95:7e07b6fb45cf 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 95:7e07b6fb45cf 1150 #if 1
Kojto 95:7e07b6fb45cf 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 95:7e07b6fb45cf 1152 #else
Kojto 95:7e07b6fb45cf 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 95:7e07b6fb45cf 1154 __regTTBR0 = ttbr0;
Kojto 95:7e07b6fb45cf 1155 #endif
Kojto 95:7e07b6fb45cf 1156 __ISB();
Kojto 95:7e07b6fb45cf 1157 }
Kojto 95:7e07b6fb45cf 1158
Kojto 95:7e07b6fb45cf 1159 /** \brief Get DACR
Kojto 95:7e07b6fb45cf 1160
Kojto 95:7e07b6fb45cf 1161 This function returns the value of the Domain Access Control Register.
Kojto 95:7e07b6fb45cf 1162
Kojto 95:7e07b6fb45cf 1163 \return Domain Access Control Register value
Kojto 95:7e07b6fb45cf 1164 */
Kojto 95:7e07b6fb45cf 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 95:7e07b6fb45cf 1166 #if 1
Kojto 95:7e07b6fb45cf 1167 register uint32_t __regDACR;
Kojto 95:7e07b6fb45cf 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 95:7e07b6fb45cf 1169 #else
Kojto 95:7e07b6fb45cf 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 95:7e07b6fb45cf 1171 #endif
Kojto 95:7e07b6fb45cf 1172 return(__regDACR);
Kojto 95:7e07b6fb45cf 1173 }
Kojto 95:7e07b6fb45cf 1174
Kojto 95:7e07b6fb45cf 1175 /** \brief Set DACR
Kojto 95:7e07b6fb45cf 1176
Kojto 108:34e6b704fe68 1177 This function assigns the given value to the Domain Access Control Register.
Kojto 95:7e07b6fb45cf 1178
Kojto 95:7e07b6fb45cf 1179 \param [in] dacr Domain Access Control Register value to set
Kojto 95:7e07b6fb45cf 1180 */
Kojto 95:7e07b6fb45cf 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 95:7e07b6fb45cf 1182 #if 1
Kojto 95:7e07b6fb45cf 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 95:7e07b6fb45cf 1184 #else
Kojto 95:7e07b6fb45cf 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 95:7e07b6fb45cf 1186 __regDACR = dacr;
Kojto 95:7e07b6fb45cf 1187 #endif
Kojto 95:7e07b6fb45cf 1188 __ISB();
Kojto 95:7e07b6fb45cf 1189 }
Kojto 95:7e07b6fb45cf 1190
Kojto 95:7e07b6fb45cf 1191 /******************************** Cache and BTAC enable ****************************************************/
Kojto 95:7e07b6fb45cf 1192
Kojto 95:7e07b6fb45cf 1193 /** \brief Set SCTLR
Kojto 95:7e07b6fb45cf 1194
Kojto 95:7e07b6fb45cf 1195 This function assigns the given value to the System Control Register.
Kojto 95:7e07b6fb45cf 1196
Kojto 108:34e6b704fe68 1197 \param [in] sctlr System Control Register value to set
Kojto 95:7e07b6fb45cf 1198 */
Kojto 95:7e07b6fb45cf 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 95:7e07b6fb45cf 1200 {
Kojto 95:7e07b6fb45cf 1201 #if 1
Kojto 95:7e07b6fb45cf 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 95:7e07b6fb45cf 1203 #else
Kojto 95:7e07b6fb45cf 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 95:7e07b6fb45cf 1205 __regSCTLR = sctlr;
Kojto 95:7e07b6fb45cf 1206 #endif
Kojto 95:7e07b6fb45cf 1207 }
Kojto 95:7e07b6fb45cf 1208
Kojto 95:7e07b6fb45cf 1209 /** \brief Get SCTLR
Kojto 95:7e07b6fb45cf 1210
Kojto 95:7e07b6fb45cf 1211 This function returns the value of the System Control Register.
Kojto 95:7e07b6fb45cf 1212
Kojto 95:7e07b6fb45cf 1213 \return System Control Register value
Kojto 95:7e07b6fb45cf 1214 */
Kojto 95:7e07b6fb45cf 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 95:7e07b6fb45cf 1216 #if 1
Kojto 95:7e07b6fb45cf 1217 register uint32_t __regSCTLR;
Kojto 95:7e07b6fb45cf 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 95:7e07b6fb45cf 1219 #else
Kojto 95:7e07b6fb45cf 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 95:7e07b6fb45cf 1221 #endif
Kojto 95:7e07b6fb45cf 1222 return(__regSCTLR);
Kojto 95:7e07b6fb45cf 1223 }
Kojto 95:7e07b6fb45cf 1224
Kojto 95:7e07b6fb45cf 1225 /** \brief Enable Caches
Kojto 95:7e07b6fb45cf 1226
Kojto 95:7e07b6fb45cf 1227 Enable Caches
Kojto 95:7e07b6fb45cf 1228 */
Kojto 95:7e07b6fb45cf 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 95:7e07b6fb45cf 1230 // Set I bit 12 to enable I Cache
Kojto 95:7e07b6fb45cf 1231 // Set C bit 2 to enable D Cache
Kojto 95:7e07b6fb45cf 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 95:7e07b6fb45cf 1233 }
Kojto 95:7e07b6fb45cf 1234
Kojto 95:7e07b6fb45cf 1235 /** \brief Disable Caches
Kojto 95:7e07b6fb45cf 1236
Kojto 95:7e07b6fb45cf 1237 Disable Caches
Kojto 95:7e07b6fb45cf 1238 */
Kojto 95:7e07b6fb45cf 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 95:7e07b6fb45cf 1240 // Clear I bit 12 to disable I Cache
Kojto 95:7e07b6fb45cf 1241 // Clear C bit 2 to disable D Cache
Kojto 95:7e07b6fb45cf 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 95:7e07b6fb45cf 1243 __ISB();
Kojto 95:7e07b6fb45cf 1244 }
Kojto 95:7e07b6fb45cf 1245
Kojto 95:7e07b6fb45cf 1246 /** \brief Enable BTAC
Kojto 95:7e07b6fb45cf 1247
Kojto 95:7e07b6fb45cf 1248 Enable BTAC
Kojto 95:7e07b6fb45cf 1249 */
Kojto 95:7e07b6fb45cf 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 95:7e07b6fb45cf 1251 // Set Z bit 11 to enable branch prediction
Kojto 95:7e07b6fb45cf 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 95:7e07b6fb45cf 1253 __ISB();
Kojto 95:7e07b6fb45cf 1254 }
Kojto 95:7e07b6fb45cf 1255
Kojto 95:7e07b6fb45cf 1256 /** \brief Disable BTAC
Kojto 95:7e07b6fb45cf 1257
Kojto 95:7e07b6fb45cf 1258 Disable BTAC
Kojto 95:7e07b6fb45cf 1259 */
Kojto 95:7e07b6fb45cf 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 95:7e07b6fb45cf 1261 // Clear Z bit 11 to disable branch prediction
Kojto 95:7e07b6fb45cf 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 95:7e07b6fb45cf 1263 }
Kojto 95:7e07b6fb45cf 1264
Kojto 95:7e07b6fb45cf 1265
Kojto 95:7e07b6fb45cf 1266 /** \brief Enable MMU
Kojto 95:7e07b6fb45cf 1267
Kojto 95:7e07b6fb45cf 1268 Enable MMU
Kojto 95:7e07b6fb45cf 1269 */
Kojto 95:7e07b6fb45cf 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 95:7e07b6fb45cf 1271 // Set M bit 0 to enable the MMU
Kojto 95:7e07b6fb45cf 1272 // Set AFE bit to enable simplified access permissions model
Kojto 95:7e07b6fb45cf 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 95:7e07b6fb45cf 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 95:7e07b6fb45cf 1275 __ISB();
Kojto 95:7e07b6fb45cf 1276 }
Kojto 95:7e07b6fb45cf 1277
Kojto 108:34e6b704fe68 1278 /** \brief Disable MMU
Kojto 95:7e07b6fb45cf 1279
Kojto 108:34e6b704fe68 1280 Disable MMU
Kojto 95:7e07b6fb45cf 1281 */
Kojto 95:7e07b6fb45cf 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 95:7e07b6fb45cf 1283 // Clear M bit 0 to disable the MMU
Kojto 95:7e07b6fb45cf 1284 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 95:7e07b6fb45cf 1285 __ISB();
Kojto 95:7e07b6fb45cf 1286 }
Kojto 95:7e07b6fb45cf 1287
Kojto 95:7e07b6fb45cf 1288 /******************************** TLB maintenance operations ************************************************/
Kojto 95:7e07b6fb45cf 1289 /** \brief Invalidate the whole tlb
Kojto 95:7e07b6fb45cf 1290
Kojto 95:7e07b6fb45cf 1291 TLBIALL. Invalidate the whole tlb
Kojto 95:7e07b6fb45cf 1292 */
Kojto 95:7e07b6fb45cf 1293
Kojto 95:7e07b6fb45cf 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 95:7e07b6fb45cf 1295 #if 1
Kojto 95:7e07b6fb45cf 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 95:7e07b6fb45cf 1297 #else
Kojto 95:7e07b6fb45cf 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 95:7e07b6fb45cf 1299 __TLBIALL = 0;
Kojto 95:7e07b6fb45cf 1300 #endif
Kojto 95:7e07b6fb45cf 1301 __DSB();
Kojto 95:7e07b6fb45cf 1302 __ISB();
Kojto 95:7e07b6fb45cf 1303 }
Kojto 95:7e07b6fb45cf 1304
Kojto 95:7e07b6fb45cf 1305 /******************************** BTB maintenance operations ************************************************/
Kojto 95:7e07b6fb45cf 1306 /** \brief Invalidate entire branch predictor array
Kojto 95:7e07b6fb45cf 1307
Kojto 95:7e07b6fb45cf 1308 BPIALL. Branch Predictor Invalidate All.
Kojto 95:7e07b6fb45cf 1309 */
Kojto 95:7e07b6fb45cf 1310
Kojto 95:7e07b6fb45cf 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 95:7e07b6fb45cf 1312 #if 1
Kojto 95:7e07b6fb45cf 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 95:7e07b6fb45cf 1314 #else
Kojto 95:7e07b6fb45cf 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 95:7e07b6fb45cf 1316 __BPIALL = 0;
Kojto 95:7e07b6fb45cf 1317 #endif
Kojto 95:7e07b6fb45cf 1318 __DSB(); //ensure completion of the invalidation
Kojto 95:7e07b6fb45cf 1319 __ISB(); //ensure instruction fetch path sees new state
Kojto 95:7e07b6fb45cf 1320 }
Kojto 95:7e07b6fb45cf 1321
Kojto 95:7e07b6fb45cf 1322
Kojto 95:7e07b6fb45cf 1323 /******************************** L1 cache operations ******************************************************/
Kojto 95:7e07b6fb45cf 1324
Kojto 95:7e07b6fb45cf 1325 /** \brief Invalidate the whole I$
Kojto 95:7e07b6fb45cf 1326
Kojto 95:7e07b6fb45cf 1327 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 95:7e07b6fb45cf 1328 */
Kojto 95:7e07b6fb45cf 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 95:7e07b6fb45cf 1330 #if 1
Kojto 95:7e07b6fb45cf 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 95:7e07b6fb45cf 1332 #else
Kojto 95:7e07b6fb45cf 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 95:7e07b6fb45cf 1334 __ICIALLU = 0;
Kojto 95:7e07b6fb45cf 1335 #endif
Kojto 95:7e07b6fb45cf 1336 __DSB(); //ensure completion of the invalidation
Kojto 95:7e07b6fb45cf 1337 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 95:7e07b6fb45cf 1338 }
Kojto 95:7e07b6fb45cf 1339
Kojto 95:7e07b6fb45cf 1340 /** \brief Clean D$ by MVA
Kojto 95:7e07b6fb45cf 1341
Kojto 95:7e07b6fb45cf 1342 DCCMVAC. Data cache clean by MVA to PoC
Kojto 95:7e07b6fb45cf 1343 */
Kojto 95:7e07b6fb45cf 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 95:7e07b6fb45cf 1345 #if 1
Kojto 95:7e07b6fb45cf 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 95:7e07b6fb45cf 1347 #else
Kojto 95:7e07b6fb45cf 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 95:7e07b6fb45cf 1349 __DCCMVAC = (uint32_t)va;
Kojto 95:7e07b6fb45cf 1350 #endif
Kojto 95:7e07b6fb45cf 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 95:7e07b6fb45cf 1352 }
Kojto 95:7e07b6fb45cf 1353
Kojto 95:7e07b6fb45cf 1354 /** \brief Invalidate D$ by MVA
Kojto 95:7e07b6fb45cf 1355
Kojto 95:7e07b6fb45cf 1356 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 95:7e07b6fb45cf 1357 */
Kojto 95:7e07b6fb45cf 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 95:7e07b6fb45cf 1359 #if 1
Kojto 95:7e07b6fb45cf 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 95:7e07b6fb45cf 1361 #else
Kojto 95:7e07b6fb45cf 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 95:7e07b6fb45cf 1363 __DCIMVAC = (uint32_t)va;
Kojto 95:7e07b6fb45cf 1364 #endif
Kojto 95:7e07b6fb45cf 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 95:7e07b6fb45cf 1366 }
Kojto 95:7e07b6fb45cf 1367
Kojto 95:7e07b6fb45cf 1368 /** \brief Clean and Invalidate D$ by MVA
Kojto 95:7e07b6fb45cf 1369
Kojto 95:7e07b6fb45cf 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 95:7e07b6fb45cf 1371 */
Kojto 95:7e07b6fb45cf 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 95:7e07b6fb45cf 1373 #if 1
Kojto 95:7e07b6fb45cf 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 95:7e07b6fb45cf 1375 #else
Kojto 95:7e07b6fb45cf 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 95:7e07b6fb45cf 1377 __DCCIMVAC = (uint32_t)va;
Kojto 95:7e07b6fb45cf 1378 #endif
Kojto 95:7e07b6fb45cf 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 95:7e07b6fb45cf 1380 }
Kojto 95:7e07b6fb45cf 1381
Kojto 108:34e6b704fe68 1382 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 95:7e07b6fb45cf 1383
Kojto 108:34e6b704fe68 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 95:7e07b6fb45cf 1385 */
Kojto 95:7e07b6fb45cf 1386 extern void __v7_all_cache(uint32_t op);
Kojto 95:7e07b6fb45cf 1387
Kojto 95:7e07b6fb45cf 1388
Kojto 95:7e07b6fb45cf 1389 /** \brief Invalidate the whole D$
Kojto 95:7e07b6fb45cf 1390
Kojto 95:7e07b6fb45cf 1391 DCISW. Invalidate by Set/Way
Kojto 95:7e07b6fb45cf 1392 */
Kojto 95:7e07b6fb45cf 1393
Kojto 95:7e07b6fb45cf 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 95:7e07b6fb45cf 1395 __v7_all_cache(0);
Kojto 95:7e07b6fb45cf 1396 }
Kojto 95:7e07b6fb45cf 1397
Kojto 95:7e07b6fb45cf 1398 /** \brief Clean the whole D$
Kojto 95:7e07b6fb45cf 1399
Kojto 95:7e07b6fb45cf 1400 DCCSW. Clean by Set/Way
Kojto 95:7e07b6fb45cf 1401 */
Kojto 95:7e07b6fb45cf 1402
Kojto 95:7e07b6fb45cf 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 95:7e07b6fb45cf 1404 __v7_all_cache(1);
Kojto 95:7e07b6fb45cf 1405 }
Kojto 95:7e07b6fb45cf 1406
Kojto 95:7e07b6fb45cf 1407 /** \brief Clean and invalidate the whole D$
Kojto 95:7e07b6fb45cf 1408
Kojto 95:7e07b6fb45cf 1409 DCCISW. Clean and Invalidate by Set/Way
Kojto 95:7e07b6fb45cf 1410 */
Kojto 95:7e07b6fb45cf 1411
Kojto 95:7e07b6fb45cf 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 95:7e07b6fb45cf 1413 __v7_all_cache(2);
Kojto 95:7e07b6fb45cf 1414 }
Kojto 95:7e07b6fb45cf 1415
Kojto 95:7e07b6fb45cf 1416 #include "core_ca_mmu.h"
bogdanm 92:4fc01daae5a5 1417
bogdanm 92:4fc01daae5a5 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
bogdanm 92:4fc01daae5a5 1419
bogdanm 92:4fc01daae5a5 1420 #error TASKING Compiler support not implemented for Cortex-A
bogdanm 92:4fc01daae5a5 1421
bogdanm 92:4fc01daae5a5 1422 #endif
bogdanm 92:4fc01daae5a5 1423
bogdanm 92:4fc01daae5a5 1424 /*@} end of CMSIS_Core_RegAccFunctions */
bogdanm 92:4fc01daae5a5 1425
bogdanm 92:4fc01daae5a5 1426
bogdanm 92:4fc01daae5a5 1427 #endif /* __CORE_CAFUNC_H__ */