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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_F334C8/core_caFunc.h@121:6c34061e7c34, 2016-05-25 (annotated)

Committer:
Kojto
Date:
Wed May 25 16:44:06 2016 +0100
Revision:
121:6c34061e7c34
Parent:
115:87f2f5183dfb
Child:
130:d75b3fe1f5cb
Release 121 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - F7 - analogin conversion fix

     - F1, F4 - serial flushed prior init fix

     - CAN added for F042K6,F072RB,F091RC

     - NUCLE_L053R8/F030R8/F070RB,F103RB - ticker 16bit counter fix

- NXP - LPC812 PWMOut conflict issue fix

      - KSDK - PWMout fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 100:cbbeb26dbd92 1 /**************************************************************************//**
Kojto 100:cbbeb26dbd92 2 * @file core_caFunc.h
Kojto 100:cbbeb26dbd92 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 100:cbbeb26dbd92 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 100:cbbeb26dbd92 6 *
Kojto 100:cbbeb26dbd92 7 * @note
Kojto 100:cbbeb26dbd92 8 *
Kojto 100:cbbeb26dbd92 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 100:cbbeb26dbd92 11
Kojto 100:cbbeb26dbd92 12 All rights reserved.
Kojto 100:cbbeb26dbd92 13 Redistribution and use in source and binary forms, with or without
Kojto 100:cbbeb26dbd92 14 modification, are permitted provided that the following conditions are met:
Kojto 100:cbbeb26dbd92 15 - Redistributions of source code must retain the above copyright
Kojto 100:cbbeb26dbd92 16 notice, this list of conditions and the following disclaimer.
Kojto 100:cbbeb26dbd92 17 - Redistributions in binary form must reproduce the above copyright
Kojto 100:cbbeb26dbd92 18 notice, this list of conditions and the following disclaimer in the
Kojto 100:cbbeb26dbd92 19 documentation and/or other materials provided with the distribution.
Kojto 100:cbbeb26dbd92 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 100:cbbeb26dbd92 21 to endorse or promote products derived from this software without
Kojto 100:cbbeb26dbd92 22 specific prior written permission.
Kojto 100:cbbeb26dbd92 23 *
Kojto 100:cbbeb26dbd92 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 100:cbbeb26dbd92 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 100:cbbeb26dbd92 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 100:cbbeb26dbd92 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 100:cbbeb26dbd92 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 100:cbbeb26dbd92 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 100:cbbeb26dbd92 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 100:cbbeb26dbd92 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 100:cbbeb26dbd92 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 100:cbbeb26dbd92 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 100:cbbeb26dbd92 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 100:cbbeb26dbd92 35 ---------------------------------------------------------------------------*/
Kojto 100:cbbeb26dbd92 36
Kojto 100:cbbeb26dbd92 37
Kojto 100:cbbeb26dbd92 38 #ifndef __CORE_CAFUNC_H__
Kojto 100:cbbeb26dbd92 39 #define __CORE_CAFUNC_H__
Kojto 100:cbbeb26dbd92 40
Kojto 100:cbbeb26dbd92 41
Kojto 100:cbbeb26dbd92 42 /* ########################### Core Function Access ########################### */
Kojto 100:cbbeb26dbd92 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 100:cbbeb26dbd92 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 100:cbbeb26dbd92 45 @{
Kojto 100:cbbeb26dbd92 46 */
Kojto 100:cbbeb26dbd92 47
Kojto 100:cbbeb26dbd92 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 100:cbbeb26dbd92 49 /* ARM armcc specific functions */
Kojto 100:cbbeb26dbd92 50
Kojto 100:cbbeb26dbd92 51 #if (__ARMCC_VERSION < 400677)
Kojto 100:cbbeb26dbd92 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 100:cbbeb26dbd92 53 #endif
Kojto 100:cbbeb26dbd92 54
Kojto 100:cbbeb26dbd92 55 #define MODE_USR 0x10
Kojto 100:cbbeb26dbd92 56 #define MODE_FIQ 0x11
Kojto 100:cbbeb26dbd92 57 #define MODE_IRQ 0x12
Kojto 100:cbbeb26dbd92 58 #define MODE_SVC 0x13
Kojto 100:cbbeb26dbd92 59 #define MODE_MON 0x16
Kojto 100:cbbeb26dbd92 60 #define MODE_ABT 0x17
Kojto 100:cbbeb26dbd92 61 #define MODE_HYP 0x1A
Kojto 100:cbbeb26dbd92 62 #define MODE_UND 0x1B
Kojto 100:cbbeb26dbd92 63 #define MODE_SYS 0x1F
Kojto 100:cbbeb26dbd92 64
Kojto 100:cbbeb26dbd92 65 /** \brief Get APSR Register
Kojto 100:cbbeb26dbd92 66
Kojto 100:cbbeb26dbd92 67 This function returns the content of the APSR Register.
Kojto 100:cbbeb26dbd92 68
Kojto 100:cbbeb26dbd92 69 \return APSR Register value
Kojto 100:cbbeb26dbd92 70 */
Kojto 100:cbbeb26dbd92 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 100:cbbeb26dbd92 72 {
Kojto 100:cbbeb26dbd92 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 100:cbbeb26dbd92 74 return(__regAPSR);
Kojto 100:cbbeb26dbd92 75 }
Kojto 100:cbbeb26dbd92 76
Kojto 100:cbbeb26dbd92 77
Kojto 100:cbbeb26dbd92 78 /** \brief Get CPSR Register
Kojto 100:cbbeb26dbd92 79
Kojto 100:cbbeb26dbd92 80 This function returns the content of the CPSR Register.
Kojto 100:cbbeb26dbd92 81
Kojto 100:cbbeb26dbd92 82 \return CPSR Register value
Kojto 100:cbbeb26dbd92 83 */
Kojto 100:cbbeb26dbd92 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 100:cbbeb26dbd92 85 {
Kojto 100:cbbeb26dbd92 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 100:cbbeb26dbd92 87 return(__regCPSR);
Kojto 100:cbbeb26dbd92 88 }
Kojto 100:cbbeb26dbd92 89
Kojto 100:cbbeb26dbd92 90 /** \brief Set Stack Pointer
Kojto 100:cbbeb26dbd92 91
Kojto 100:cbbeb26dbd92 92 This function assigns the given value to the current stack pointer.
Kojto 100:cbbeb26dbd92 93
Kojto 100:cbbeb26dbd92 94 \param [in] topOfStack Stack Pointer value to set
Kojto 100:cbbeb26dbd92 95 */
Kojto 100:cbbeb26dbd92 96 register uint32_t __regSP __ASM("sp");
Kojto 100:cbbeb26dbd92 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 100:cbbeb26dbd92 98 {
Kojto 100:cbbeb26dbd92 99 __regSP = topOfStack;
Kojto 100:cbbeb26dbd92 100 }
Kojto 100:cbbeb26dbd92 101
Kojto 100:cbbeb26dbd92 102
Kojto 100:cbbeb26dbd92 103 /** \brief Get link register
Kojto 100:cbbeb26dbd92 104
Kojto 100:cbbeb26dbd92 105 This function returns the value of the link register
Kojto 100:cbbeb26dbd92 106
Kojto 100:cbbeb26dbd92 107 \return Value of link register
Kojto 100:cbbeb26dbd92 108 */
Kojto 100:cbbeb26dbd92 109 register uint32_t __reglr __ASM("lr");
Kojto 100:cbbeb26dbd92 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 100:cbbeb26dbd92 111 {
Kojto 100:cbbeb26dbd92 112 return(__reglr);
Kojto 100:cbbeb26dbd92 113 }
Kojto 100:cbbeb26dbd92 114
Kojto 100:cbbeb26dbd92 115 /** \brief Set link register
Kojto 100:cbbeb26dbd92 116
Kojto 100:cbbeb26dbd92 117 This function sets the value of the link register
Kojto 100:cbbeb26dbd92 118
Kojto 100:cbbeb26dbd92 119 \param [in] lr LR value to set
Kojto 100:cbbeb26dbd92 120 */
Kojto 100:cbbeb26dbd92 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 100:cbbeb26dbd92 122 {
Kojto 100:cbbeb26dbd92 123 __reglr = lr;
Kojto 100:cbbeb26dbd92 124 }
Kojto 100:cbbeb26dbd92 125
Kojto 100:cbbeb26dbd92 126 /** \brief Set Process Stack Pointer
Kojto 100:cbbeb26dbd92 127
Kojto 100:cbbeb26dbd92 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 100:cbbeb26dbd92 129
Kojto 100:cbbeb26dbd92 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 100:cbbeb26dbd92 131 */
Kojto 100:cbbeb26dbd92 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 100:cbbeb26dbd92 133 {
Kojto 100:cbbeb26dbd92 134 ARM
Kojto 100:cbbeb26dbd92 135 PRESERVE8
Kojto 100:cbbeb26dbd92 136
Kojto 100:cbbeb26dbd92 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 100:cbbeb26dbd92 138 MRS R1, CPSR
Kojto 100:cbbeb26dbd92 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 100:cbbeb26dbd92 140 MOV SP, R0
Kojto 100:cbbeb26dbd92 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 100:cbbeb26dbd92 142 ISB
Kojto 100:cbbeb26dbd92 143 BX LR
Kojto 100:cbbeb26dbd92 144
Kojto 100:cbbeb26dbd92 145 }
Kojto 100:cbbeb26dbd92 146
Kojto 100:cbbeb26dbd92 147 /** \brief Set User Mode
Kojto 100:cbbeb26dbd92 148
Kojto 100:cbbeb26dbd92 149 This function changes the processor state to User Mode
Kojto 100:cbbeb26dbd92 150 */
Kojto 100:cbbeb26dbd92 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 100:cbbeb26dbd92 152 {
Kojto 100:cbbeb26dbd92 153 ARM
Kojto 100:cbbeb26dbd92 154
Kojto 100:cbbeb26dbd92 155 CPS #MODE_USR
Kojto 100:cbbeb26dbd92 156 BX LR
Kojto 100:cbbeb26dbd92 157 }
Kojto 100:cbbeb26dbd92 158
Kojto 100:cbbeb26dbd92 159
Kojto 100:cbbeb26dbd92 160 /** \brief Enable FIQ
Kojto 100:cbbeb26dbd92 161
Kojto 100:cbbeb26dbd92 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 163 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 164 */
Kojto 100:cbbeb26dbd92 165 #define __enable_fault_irq __enable_fiq
Kojto 100:cbbeb26dbd92 166
Kojto 100:cbbeb26dbd92 167
Kojto 100:cbbeb26dbd92 168 /** \brief Disable FIQ
Kojto 100:cbbeb26dbd92 169
Kojto 100:cbbeb26dbd92 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 171 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 172 */
Kojto 100:cbbeb26dbd92 173 #define __disable_fault_irq __disable_fiq
Kojto 100:cbbeb26dbd92 174
Kojto 100:cbbeb26dbd92 175
Kojto 100:cbbeb26dbd92 176 /** \brief Get FPSCR
Kojto 100:cbbeb26dbd92 177
Kojto 100:cbbeb26dbd92 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 179
Kojto 100:cbbeb26dbd92 180 \return Floating Point Status/Control register value
Kojto 100:cbbeb26dbd92 181 */
Kojto 100:cbbeb26dbd92 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 100:cbbeb26dbd92 183 {
Kojto 100:cbbeb26dbd92 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 186 return(__regfpscr);
Kojto 100:cbbeb26dbd92 187 #else
Kojto 100:cbbeb26dbd92 188 return(0);
Kojto 100:cbbeb26dbd92 189 #endif
Kojto 100:cbbeb26dbd92 190 }
Kojto 100:cbbeb26dbd92 191
Kojto 100:cbbeb26dbd92 192
Kojto 100:cbbeb26dbd92 193 /** \brief Set FPSCR
Kojto 100:cbbeb26dbd92 194
Kojto 100:cbbeb26dbd92 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 196
Kojto 100:cbbeb26dbd92 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 100:cbbeb26dbd92 198 */
Kojto 100:cbbeb26dbd92 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 100:cbbeb26dbd92 200 {
Kojto 100:cbbeb26dbd92 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 203 __regfpscr = (fpscr);
Kojto 100:cbbeb26dbd92 204 #endif
Kojto 100:cbbeb26dbd92 205 }
Kojto 100:cbbeb26dbd92 206
Kojto 100:cbbeb26dbd92 207 /** \brief Get FPEXC
Kojto 100:cbbeb26dbd92 208
Kojto 100:cbbeb26dbd92 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 210
Kojto 100:cbbeb26dbd92 211 \return Floating Point Exception Control register value
Kojto 100:cbbeb26dbd92 212 */
Kojto 100:cbbeb26dbd92 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 100:cbbeb26dbd92 214 {
Kojto 100:cbbeb26dbd92 215 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 217 return(__regfpexc);
Kojto 100:cbbeb26dbd92 218 #else
Kojto 100:cbbeb26dbd92 219 return(0);
Kojto 100:cbbeb26dbd92 220 #endif
Kojto 100:cbbeb26dbd92 221 }
Kojto 100:cbbeb26dbd92 222
Kojto 100:cbbeb26dbd92 223
Kojto 100:cbbeb26dbd92 224 /** \brief Set FPEXC
Kojto 100:cbbeb26dbd92 225
Kojto 100:cbbeb26dbd92 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 227
Kojto 100:cbbeb26dbd92 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 100:cbbeb26dbd92 229 */
Kojto 100:cbbeb26dbd92 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 100:cbbeb26dbd92 231 {
Kojto 100:cbbeb26dbd92 232 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 234 __regfpexc = (fpexc);
Kojto 100:cbbeb26dbd92 235 #endif
Kojto 100:cbbeb26dbd92 236 }
Kojto 100:cbbeb26dbd92 237
Kojto 100:cbbeb26dbd92 238 /** \brief Get CPACR
Kojto 100:cbbeb26dbd92 239
Kojto 100:cbbeb26dbd92 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 241
Kojto 100:cbbeb26dbd92 242 \return Coprocessor Access Control register value
Kojto 100:cbbeb26dbd92 243 */
Kojto 100:cbbeb26dbd92 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 100:cbbeb26dbd92 245 {
Kojto 100:cbbeb26dbd92 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 247 return __regCPACR;
Kojto 100:cbbeb26dbd92 248 }
Kojto 100:cbbeb26dbd92 249
Kojto 100:cbbeb26dbd92 250 /** \brief Set CPACR
Kojto 100:cbbeb26dbd92 251
Kojto 100:cbbeb26dbd92 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 100:cbbeb26dbd92 255 */
Kojto 100:cbbeb26dbd92 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 100:cbbeb26dbd92 257 {
Kojto 100:cbbeb26dbd92 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 259 __regCPACR = cpacr;
Kojto 100:cbbeb26dbd92 260 __ISB();
Kojto 100:cbbeb26dbd92 261 }
Kojto 100:cbbeb26dbd92 262
Kojto 100:cbbeb26dbd92 263 /** \brief Get CBAR
Kojto 100:cbbeb26dbd92 264
Kojto 100:cbbeb26dbd92 265 This function returns the value of the Configuration Base Address register.
Kojto 100:cbbeb26dbd92 266
Kojto 100:cbbeb26dbd92 267 \return Configuration Base Address register value
Kojto 100:cbbeb26dbd92 268 */
Kojto 100:cbbeb26dbd92 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 100:cbbeb26dbd92 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 100:cbbeb26dbd92 271 return(__regCBAR);
Kojto 100:cbbeb26dbd92 272 }
Kojto 100:cbbeb26dbd92 273
Kojto 100:cbbeb26dbd92 274 /** \brief Get TTBR0
Kojto 100:cbbeb26dbd92 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 277
Kojto 100:cbbeb26dbd92 278 \return Translation Table Base Register 0 value
Kojto 100:cbbeb26dbd92 279 */
Kojto 100:cbbeb26dbd92 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 100:cbbeb26dbd92 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 282 return(__regTTBR0);
Kojto 100:cbbeb26dbd92 283 }
Kojto 100:cbbeb26dbd92 284
Kojto 100:cbbeb26dbd92 285 /** \brief Set TTBR0
Kojto 100:cbbeb26dbd92 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 288
Kojto 100:cbbeb26dbd92 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 100:cbbeb26dbd92 290 */
Kojto 100:cbbeb26dbd92 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 100:cbbeb26dbd92 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 293 __regTTBR0 = ttbr0;
Kojto 100:cbbeb26dbd92 294 __ISB();
Kojto 100:cbbeb26dbd92 295 }
Kojto 100:cbbeb26dbd92 296
Kojto 100:cbbeb26dbd92 297 /** \brief Get DACR
Kojto 100:cbbeb26dbd92 298
Kojto 100:cbbeb26dbd92 299 This function returns the value of the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 300
Kojto 100:cbbeb26dbd92 301 \return Domain Access Control Register value
Kojto 100:cbbeb26dbd92 302 */
Kojto 100:cbbeb26dbd92 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 100:cbbeb26dbd92 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 305 return(__regDACR);
Kojto 100:cbbeb26dbd92 306 }
Kojto 100:cbbeb26dbd92 307
Kojto 100:cbbeb26dbd92 308 /** \brief Set DACR
Kojto 100:cbbeb26dbd92 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 311
Kojto 100:cbbeb26dbd92 312 \param [in] dacr Domain Access Control Register value to set
Kojto 100:cbbeb26dbd92 313 */
Kojto 100:cbbeb26dbd92 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 100:cbbeb26dbd92 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 316 __regDACR = dacr;
Kojto 100:cbbeb26dbd92 317 __ISB();
Kojto 100:cbbeb26dbd92 318 }
Kojto 100:cbbeb26dbd92 319
Kojto 100:cbbeb26dbd92 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 100:cbbeb26dbd92 321
Kojto 100:cbbeb26dbd92 322 /** \brief Set SCTLR
Kojto 100:cbbeb26dbd92 323
Kojto 100:cbbeb26dbd92 324 This function assigns the given value to the System Control Register.
Kojto 100:cbbeb26dbd92 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 100:cbbeb26dbd92 327 */
Kojto 100:cbbeb26dbd92 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 100:cbbeb26dbd92 329 {
Kojto 100:cbbeb26dbd92 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 331 __regSCTLR = sctlr;
Kojto 100:cbbeb26dbd92 332 }
Kojto 100:cbbeb26dbd92 333
Kojto 100:cbbeb26dbd92 334 /** \brief Get SCTLR
Kojto 100:cbbeb26dbd92 335
Kojto 100:cbbeb26dbd92 336 This function returns the value of the System Control Register.
Kojto 100:cbbeb26dbd92 337
Kojto 100:cbbeb26dbd92 338 \return System Control Register value
Kojto 100:cbbeb26dbd92 339 */
Kojto 100:cbbeb26dbd92 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 100:cbbeb26dbd92 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 342 return(__regSCTLR);
Kojto 100:cbbeb26dbd92 343 }
Kojto 100:cbbeb26dbd92 344
Kojto 100:cbbeb26dbd92 345 /** \brief Enable Caches
Kojto 100:cbbeb26dbd92 346
Kojto 100:cbbeb26dbd92 347 Enable Caches
Kojto 100:cbbeb26dbd92 348 */
Kojto 100:cbbeb26dbd92 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 100:cbbeb26dbd92 350 // Set I bit 12 to enable I Cache
Kojto 100:cbbeb26dbd92 351 // Set C bit 2 to enable D Cache
Kojto 100:cbbeb26dbd92 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 100:cbbeb26dbd92 353 }
Kojto 100:cbbeb26dbd92 354
Kojto 100:cbbeb26dbd92 355 /** \brief Disable Caches
Kojto 100:cbbeb26dbd92 356
Kojto 100:cbbeb26dbd92 357 Disable Caches
Kojto 100:cbbeb26dbd92 358 */
Kojto 100:cbbeb26dbd92 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 100:cbbeb26dbd92 360 // Clear I bit 12 to disable I Cache
Kojto 100:cbbeb26dbd92 361 // Clear C bit 2 to disable D Cache
Kojto 100:cbbeb26dbd92 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 100:cbbeb26dbd92 363 __ISB();
Kojto 100:cbbeb26dbd92 364 }
Kojto 100:cbbeb26dbd92 365
Kojto 100:cbbeb26dbd92 366 /** \brief Enable BTAC
Kojto 100:cbbeb26dbd92 367
Kojto 100:cbbeb26dbd92 368 Enable BTAC
Kojto 100:cbbeb26dbd92 369 */
Kojto 100:cbbeb26dbd92 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 100:cbbeb26dbd92 371 // Set Z bit 11 to enable branch prediction
Kojto 100:cbbeb26dbd92 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 100:cbbeb26dbd92 373 __ISB();
Kojto 100:cbbeb26dbd92 374 }
Kojto 100:cbbeb26dbd92 375
Kojto 100:cbbeb26dbd92 376 /** \brief Disable BTAC
Kojto 100:cbbeb26dbd92 377
Kojto 100:cbbeb26dbd92 378 Disable BTAC
Kojto 100:cbbeb26dbd92 379 */
Kojto 100:cbbeb26dbd92 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 100:cbbeb26dbd92 381 // Clear Z bit 11 to disable branch prediction
Kojto 100:cbbeb26dbd92 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 100:cbbeb26dbd92 383 }
Kojto 100:cbbeb26dbd92 384
Kojto 100:cbbeb26dbd92 385
Kojto 100:cbbeb26dbd92 386 /** \brief Enable MMU
Kojto 100:cbbeb26dbd92 387
Kojto 100:cbbeb26dbd92 388 Enable MMU
Kojto 100:cbbeb26dbd92 389 */
Kojto 100:cbbeb26dbd92 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 100:cbbeb26dbd92 391 // Set M bit 0 to enable the MMU
Kojto 100:cbbeb26dbd92 392 // Set AFE bit to enable simplified access permissions model
Kojto 100:cbbeb26dbd92 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 100:cbbeb26dbd92 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 100:cbbeb26dbd92 395 __ISB();
Kojto 100:cbbeb26dbd92 396 }
Kojto 100:cbbeb26dbd92 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 100:cbbeb26dbd92 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 100:cbbeb26dbd92 401 */
Kojto 100:cbbeb26dbd92 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 100:cbbeb26dbd92 403 // Clear M bit 0 to disable the MMU
Kojto 100:cbbeb26dbd92 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 100:cbbeb26dbd92 405 __ISB();
Kojto 100:cbbeb26dbd92 406 }
Kojto 100:cbbeb26dbd92 407
Kojto 100:cbbeb26dbd92 408 /******************************** TLB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 409 /** \brief Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 410
Kojto 100:cbbeb26dbd92 411 TLBIALL. Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 412 */
Kojto 100:cbbeb26dbd92 413
Kojto 100:cbbeb26dbd92 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 100:cbbeb26dbd92 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 100:cbbeb26dbd92 416 __TLBIALL = 0;
Kojto 100:cbbeb26dbd92 417 __DSB();
Kojto 100:cbbeb26dbd92 418 __ISB();
Kojto 100:cbbeb26dbd92 419 }
Kojto 100:cbbeb26dbd92 420
Kojto 100:cbbeb26dbd92 421 /******************************** BTB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 422 /** \brief Invalidate entire branch predictor array
Kojto 100:cbbeb26dbd92 423
Kojto 100:cbbeb26dbd92 424 BPIALL. Branch Predictor Invalidate All.
Kojto 100:cbbeb26dbd92 425 */
Kojto 100:cbbeb26dbd92 426
Kojto 100:cbbeb26dbd92 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 100:cbbeb26dbd92 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 100:cbbeb26dbd92 429 __BPIALL = 0;
Kojto 100:cbbeb26dbd92 430 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 100:cbbeb26dbd92 432 }
Kojto 100:cbbeb26dbd92 433
Kojto 100:cbbeb26dbd92 434
Kojto 100:cbbeb26dbd92 435 /******************************** L1 cache operations ******************************************************/
Kojto 100:cbbeb26dbd92 436
Kojto 100:cbbeb26dbd92 437 /** \brief Invalidate the whole I$
Kojto 100:cbbeb26dbd92 438
Kojto 100:cbbeb26dbd92 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 100:cbbeb26dbd92 440 */
Kojto 100:cbbeb26dbd92 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 100:cbbeb26dbd92 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 100:cbbeb26dbd92 443 __ICIALLU = 0;
Kojto 100:cbbeb26dbd92 444 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 100:cbbeb26dbd92 446 }
Kojto 100:cbbeb26dbd92 447
Kojto 100:cbbeb26dbd92 448 /** \brief Clean D$ by MVA
Kojto 100:cbbeb26dbd92 449
Kojto 100:cbbeb26dbd92 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 100:cbbeb26dbd92 451 */
Kojto 100:cbbeb26dbd92 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 100:cbbeb26dbd92 454 __DCCMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 456 }
Kojto 100:cbbeb26dbd92 457
Kojto 100:cbbeb26dbd92 458 /** \brief Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 459
Kojto 100:cbbeb26dbd92 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 461 */
Kojto 100:cbbeb26dbd92 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 100:cbbeb26dbd92 464 __DCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 466 }
Kojto 100:cbbeb26dbd92 467
Kojto 100:cbbeb26dbd92 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 469
Kojto 100:cbbeb26dbd92 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 471 */
Kojto 100:cbbeb26dbd92 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 100:cbbeb26dbd92 474 __DCCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 476 }
Kojto 100:cbbeb26dbd92 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 100:cbbeb26dbd92 481 */
Kojto 100:cbbeb26dbd92 482 #pragma push
Kojto 100:cbbeb26dbd92 483 #pragma arm
Kojto 100:cbbeb26dbd92 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 100:cbbeb26dbd92 485 ARM
Kojto 100:cbbeb26dbd92 486
Kojto 100:cbbeb26dbd92 487 PUSH {R4-R11}
Kojto 100:cbbeb26dbd92 488
Kojto 100:cbbeb26dbd92 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 100:cbbeb26dbd92 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 100:cbbeb26dbd92 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 100:cbbeb26dbd92 492 BEQ Finished // If 0, no need to clean
Kojto 100:cbbeb26dbd92 493
Kojto 100:cbbeb26dbd92 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 100:cbbeb26dbd92 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 100:cbbeb26dbd92 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 100:cbbeb26dbd92 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 100:cbbeb26dbd92 498 CMP R1, #2
Kojto 100:cbbeb26dbd92 499 BLT Skip // No cache or only instruction cache at this level
Kojto 100:cbbeb26dbd92 500
Kojto 100:cbbeb26dbd92 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 100:cbbeb26dbd92 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 100:cbbeb26dbd92 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 100:cbbeb26dbd92 504 AND R2, R1, #7 // Extract the line length field
Kojto 100:cbbeb26dbd92 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 100:cbbeb26dbd92 506 LDR R4, =0x3FF
Kojto 100:cbbeb26dbd92 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 100:cbbeb26dbd92 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 100:cbbeb26dbd92 509 LDR R7, =0x7FFF
Kojto 100:cbbeb26dbd92 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 100:cbbeb26dbd92 511
Kojto 100:cbbeb26dbd92 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 100:cbbeb26dbd92 513
Kojto 100:cbbeb26dbd92 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 100:cbbeb26dbd92 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 100:cbbeb26dbd92 516 CMP R0, #0
Kojto 100:cbbeb26dbd92 517 BNE Dccsw
Kojto 100:cbbeb26dbd92 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 519 B cont
Kojto 100:cbbeb26dbd92 520 Dccsw CMP R0, #1
Kojto 100:cbbeb26dbd92 521 BNE Dccisw
Kojto 100:cbbeb26dbd92 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 100:cbbeb26dbd92 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 100:cbbeb26dbd92 526 BGE Loop3
Kojto 100:cbbeb26dbd92 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 100:cbbeb26dbd92 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 100:cbbeb26dbd92 530 CMP R3, R10
Kojto 100:cbbeb26dbd92 531 BGT Loop1
Kojto 100:cbbeb26dbd92 532
Kojto 100:cbbeb26dbd92 533 Finished
Kojto 100:cbbeb26dbd92 534 DSB
Kojto 100:cbbeb26dbd92 535 POP {R4-R11}
Kojto 100:cbbeb26dbd92 536 BX lr
Kojto 100:cbbeb26dbd92 537
Kojto 100:cbbeb26dbd92 538 }
Kojto 100:cbbeb26dbd92 539 #pragma pop
Kojto 100:cbbeb26dbd92 540
Kojto 100:cbbeb26dbd92 541
Kojto 100:cbbeb26dbd92 542 /** \brief Invalidate the whole D$
Kojto 100:cbbeb26dbd92 543
Kojto 100:cbbeb26dbd92 544 DCISW. Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 545 */
Kojto 100:cbbeb26dbd92 546
Kojto 100:cbbeb26dbd92 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 548 __v7_all_cache(0);
Kojto 100:cbbeb26dbd92 549 }
Kojto 100:cbbeb26dbd92 550
Kojto 100:cbbeb26dbd92 551 /** \brief Clean the whole D$
Kojto 100:cbbeb26dbd92 552
Kojto 100:cbbeb26dbd92 553 DCCSW. Clean by Set/Way
Kojto 100:cbbeb26dbd92 554 */
Kojto 100:cbbeb26dbd92 555
Kojto 100:cbbeb26dbd92 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 100:cbbeb26dbd92 557 __v7_all_cache(1);
Kojto 100:cbbeb26dbd92 558 }
Kojto 100:cbbeb26dbd92 559
Kojto 100:cbbeb26dbd92 560 /** \brief Clean and invalidate the whole D$
Kojto 100:cbbeb26dbd92 561
Kojto 100:cbbeb26dbd92 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 563 */
Kojto 100:cbbeb26dbd92 564
Kojto 100:cbbeb26dbd92 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 566 __v7_all_cache(2);
Kojto 100:cbbeb26dbd92 567 }
Kojto 100:cbbeb26dbd92 568
Kojto 100:cbbeb26dbd92 569 #include "core_ca_mmu.h"
Kojto 100:cbbeb26dbd92 570
Kojto 100:cbbeb26dbd92 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 100:cbbeb26dbd92 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
Kojto 121:6c34061e7c34 814 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 815
Kojto 121:6c34061e7c34 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 817 */
Kojto 121:6c34061e7c34 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 820 __DMB();
Kojto 121:6c34061e7c34 821 }
Kojto 121:6c34061e7c34 822
Kojto 115:87f2f5183dfb 823 #include "core_ca_mmu.h"
Kojto 100:cbbeb26dbd92 824
Kojto 100:cbbeb26dbd92 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 100:cbbeb26dbd92 826 /* GNU gcc specific functions */
Kojto 100:cbbeb26dbd92 827
Kojto 100:cbbeb26dbd92 828 #define MODE_USR 0x10
Kojto 100:cbbeb26dbd92 829 #define MODE_FIQ 0x11
Kojto 100:cbbeb26dbd92 830 #define MODE_IRQ 0x12
Kojto 100:cbbeb26dbd92 831 #define MODE_SVC 0x13
Kojto 100:cbbeb26dbd92 832 #define MODE_MON 0x16
Kojto 100:cbbeb26dbd92 833 #define MODE_ABT 0x17
Kojto 100:cbbeb26dbd92 834 #define MODE_HYP 0x1A
Kojto 100:cbbeb26dbd92 835 #define MODE_UND 0x1B
Kojto 100:cbbeb26dbd92 836 #define MODE_SYS 0x1F
Kojto 100:cbbeb26dbd92 837
Kojto 100:cbbeb26dbd92 838
Kojto 100:cbbeb26dbd92 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 100:cbbeb26dbd92 840 {
Kojto 100:cbbeb26dbd92 841 __ASM volatile ("cpsie i");
Kojto 100:cbbeb26dbd92 842 }
Kojto 100:cbbeb26dbd92 843
Kojto 100:cbbeb26dbd92 844 /** \brief Disable IRQ Interrupts
Kojto 100:cbbeb26dbd92 845
Kojto 100:cbbeb26dbd92 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 100:cbbeb26dbd92 847 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 848 */
Kojto 100:cbbeb26dbd92 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 100:cbbeb26dbd92 850 {
Kojto 100:cbbeb26dbd92 851 uint32_t result;
Kojto 100:cbbeb26dbd92 852
Kojto 100:cbbeb26dbd92 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 100:cbbeb26dbd92 854 __ASM volatile ("cpsid i");
Kojto 100:cbbeb26dbd92 855 return(result & 0x80);
Kojto 100:cbbeb26dbd92 856 }
Kojto 100:cbbeb26dbd92 857
Kojto 100:cbbeb26dbd92 858
Kojto 100:cbbeb26dbd92 859 /** \brief Get APSR Register
Kojto 100:cbbeb26dbd92 860
Kojto 100:cbbeb26dbd92 861 This function returns the content of the APSR Register.
Kojto 100:cbbeb26dbd92 862
Kojto 100:cbbeb26dbd92 863 \return APSR Register value
Kojto 100:cbbeb26dbd92 864 */
Kojto 100:cbbeb26dbd92 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 100:cbbeb26dbd92 866 {
Kojto 100:cbbeb26dbd92 867 #if 1
Kojto 108:34e6b704fe68 868 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 100:cbbeb26dbd92 870 #else
Kojto 100:cbbeb26dbd92 871 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 872 #endif
Kojto 100:cbbeb26dbd92 873 return(__regAPSR);
Kojto 100:cbbeb26dbd92 874 }
Kojto 100:cbbeb26dbd92 875
Kojto 100:cbbeb26dbd92 876
Kojto 100:cbbeb26dbd92 877 /** \brief Get CPSR Register
Kojto 100:cbbeb26dbd92 878
Kojto 100:cbbeb26dbd92 879 This function returns the content of the CPSR Register.
Kojto 100:cbbeb26dbd92 880
Kojto 100:cbbeb26dbd92 881 \return CPSR Register value
Kojto 100:cbbeb26dbd92 882 */
Kojto 100:cbbeb26dbd92 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 100:cbbeb26dbd92 884 {
Kojto 100:cbbeb26dbd92 885 #if 1
Kojto 100:cbbeb26dbd92 886 register uint32_t __regCPSR;
Kojto 100:cbbeb26dbd92 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 100:cbbeb26dbd92 888 #else
Kojto 100:cbbeb26dbd92 889 register uint32_t __regCPSR __ASM("cpsr");
Kojto 100:cbbeb26dbd92 890 #endif
Kojto 100:cbbeb26dbd92 891 return(__regCPSR);
Kojto 100:cbbeb26dbd92 892 }
Kojto 100:cbbeb26dbd92 893
Kojto 100:cbbeb26dbd92 894 #if 0
Kojto 100:cbbeb26dbd92 895 /** \brief Set Stack Pointer
Kojto 100:cbbeb26dbd92 896
Kojto 100:cbbeb26dbd92 897 This function assigns the given value to the current stack pointer.
Kojto 100:cbbeb26dbd92 898
Kojto 100:cbbeb26dbd92 899 \param [in] topOfStack Stack Pointer value to set
Kojto 100:cbbeb26dbd92 900 */
Kojto 100:cbbeb26dbd92 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 100:cbbeb26dbd92 902 {
Kojto 100:cbbeb26dbd92 903 register uint32_t __regSP __ASM("sp");
Kojto 100:cbbeb26dbd92 904 __regSP = topOfStack;
Kojto 100:cbbeb26dbd92 905 }
Kojto 100:cbbeb26dbd92 906 #endif
Kojto 100:cbbeb26dbd92 907
Kojto 100:cbbeb26dbd92 908 /** \brief Get link register
Kojto 100:cbbeb26dbd92 909
Kojto 100:cbbeb26dbd92 910 This function returns the value of the link register
Kojto 100:cbbeb26dbd92 911
Kojto 100:cbbeb26dbd92 912 \return Value of link register
Kojto 100:cbbeb26dbd92 913 */
Kojto 100:cbbeb26dbd92 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 100:cbbeb26dbd92 915 {
Kojto 100:cbbeb26dbd92 916 register uint32_t __reglr __ASM("lr");
Kojto 100:cbbeb26dbd92 917 return(__reglr);
Kojto 100:cbbeb26dbd92 918 }
Kojto 100:cbbeb26dbd92 919
Kojto 100:cbbeb26dbd92 920 #if 0
Kojto 100:cbbeb26dbd92 921 /** \brief Set link register
Kojto 100:cbbeb26dbd92 922
Kojto 100:cbbeb26dbd92 923 This function sets the value of the link register
Kojto 100:cbbeb26dbd92 924
Kojto 100:cbbeb26dbd92 925 \param [in] lr LR value to set
Kojto 100:cbbeb26dbd92 926 */
Kojto 100:cbbeb26dbd92 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 100:cbbeb26dbd92 928 {
Kojto 100:cbbeb26dbd92 929 register uint32_t __reglr __ASM("lr");
Kojto 100:cbbeb26dbd92 930 __reglr = lr;
Kojto 100:cbbeb26dbd92 931 }
Kojto 100:cbbeb26dbd92 932 #endif
Kojto 100:cbbeb26dbd92 933
Kojto 100:cbbeb26dbd92 934 /** \brief Set Process Stack Pointer
Kojto 100:cbbeb26dbd92 935
Kojto 100:cbbeb26dbd92 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 100:cbbeb26dbd92 937
Kojto 100:cbbeb26dbd92 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 100:cbbeb26dbd92 939 */
Kojto 108:34e6b704fe68 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 941 {
Kojto 108:34e6b704fe68 942 __asm__ volatile (
Kojto 108:34e6b704fe68 943 ".ARM;"
Kojto 108:34e6b704fe68 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 945
Kojto 108:34e6b704fe68 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 947 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 948 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 949 "MOV SP, R0;"
Kojto 108:34e6b704fe68 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 951 "ISB;"
Kojto 108:34e6b704fe68 952 //"BX LR;"
Kojto 108:34e6b704fe68 953 :
Kojto 108:34e6b704fe68 954 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 955 : "r0", "r1");
Kojto 108:34e6b704fe68 956 return;
Kojto 108:34e6b704fe68 957 }
Kojto 100:cbbeb26dbd92 958
Kojto 100:cbbeb26dbd92 959 /** \brief Set User Mode
Kojto 100:cbbeb26dbd92 960
Kojto 100:cbbeb26dbd92 961 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 962 */
Kojto 108:34e6b704fe68 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 964 {
Kojto 108:34e6b704fe68 965 __asm__ volatile (
Kojto 108:34e6b704fe68 966 ".ARM;"
Kojto 100:cbbeb26dbd92 967
Kojto 108:34e6b704fe68 968 "CPS %0;"
Kojto 108:34e6b704fe68 969 //"BX LR;"
Kojto 108:34e6b704fe68 970 :
Kojto 108:34e6b704fe68 971 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 972 : );
Kojto 108:34e6b704fe68 973 return;
Kojto 108:34e6b704fe68 974 }
Kojto 108:34e6b704fe68 975
Kojto 100:cbbeb26dbd92 976
Kojto 100:cbbeb26dbd92 977 /** \brief Enable FIQ
Kojto 100:cbbeb26dbd92 978
Kojto 100:cbbeb26dbd92 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 980 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 981 */
Kojto 108:34e6b704fe68 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 100:cbbeb26dbd92 983
Kojto 100:cbbeb26dbd92 984
Kojto 100:cbbeb26dbd92 985 /** \brief Disable FIQ
Kojto 100:cbbeb26dbd92 986
Kojto 100:cbbeb26dbd92 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 988 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 989 */
Kojto 108:34e6b704fe68 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 100:cbbeb26dbd92 991
Kojto 100:cbbeb26dbd92 992
Kojto 100:cbbeb26dbd92 993 /** \brief Get FPSCR
Kojto 100:cbbeb26dbd92 994
Kojto 100:cbbeb26dbd92 995 This function returns the current value of the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 996
Kojto 100:cbbeb26dbd92 997 \return Floating Point Status/Control register value
Kojto 100:cbbeb26dbd92 998 */
Kojto 100:cbbeb26dbd92 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 100:cbbeb26dbd92 1000 {
Kojto 100:cbbeb26dbd92 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 1002 #if 1
Kojto 100:cbbeb26dbd92 1003 uint32_t result;
Kojto 100:cbbeb26dbd92 1004
Kojto 100:cbbeb26dbd92 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 100:cbbeb26dbd92 1006 return (result);
Kojto 100:cbbeb26dbd92 1007 #else
Kojto 100:cbbeb26dbd92 1008 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 1009 return(__regfpscr);
Kojto 100:cbbeb26dbd92 1010 #endif
Kojto 100:cbbeb26dbd92 1011 #else
Kojto 100:cbbeb26dbd92 1012 return(0);
Kojto 100:cbbeb26dbd92 1013 #endif
Kojto 100:cbbeb26dbd92 1014 }
Kojto 100:cbbeb26dbd92 1015
Kojto 100:cbbeb26dbd92 1016
Kojto 100:cbbeb26dbd92 1017 /** \brief Set FPSCR
Kojto 100:cbbeb26dbd92 1018
Kojto 100:cbbeb26dbd92 1019 This function assigns the given value to the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 1020
Kojto 100:cbbeb26dbd92 1021 \param [in] fpscr Floating Point Status/Control value to set
Kojto 100:cbbeb26dbd92 1022 */
Kojto 100:cbbeb26dbd92 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 100:cbbeb26dbd92 1024 {
Kojto 100:cbbeb26dbd92 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 1026 #if 1
Kojto 100:cbbeb26dbd92 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 100:cbbeb26dbd92 1028 #else
Kojto 100:cbbeb26dbd92 1029 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 1030 __regfpscr = (fpscr);
Kojto 100:cbbeb26dbd92 1031 #endif
Kojto 100:cbbeb26dbd92 1032 #endif
Kojto 100:cbbeb26dbd92 1033 }
Kojto 100:cbbeb26dbd92 1034
Kojto 100:cbbeb26dbd92 1035 /** \brief Get FPEXC
Kojto 100:cbbeb26dbd92 1036
Kojto 100:cbbeb26dbd92 1037 This function returns the current value of the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 1038
Kojto 100:cbbeb26dbd92 1039 \return Floating Point Exception Control register value
Kojto 100:cbbeb26dbd92 1040 */
Kojto 100:cbbeb26dbd92 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 100:cbbeb26dbd92 1042 {
Kojto 100:cbbeb26dbd92 1043 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 1044 #if 1
Kojto 100:cbbeb26dbd92 1045 uint32_t result;
Kojto 100:cbbeb26dbd92 1046
Kojto 100:cbbeb26dbd92 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 100:cbbeb26dbd92 1048 return (result);
Kojto 100:cbbeb26dbd92 1049 #else
Kojto 100:cbbeb26dbd92 1050 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 1051 return(__regfpexc);
Kojto 100:cbbeb26dbd92 1052 #endif
Kojto 100:cbbeb26dbd92 1053 #else
Kojto 100:cbbeb26dbd92 1054 return(0);
Kojto 100:cbbeb26dbd92 1055 #endif
Kojto 100:cbbeb26dbd92 1056 }
Kojto 100:cbbeb26dbd92 1057
Kojto 100:cbbeb26dbd92 1058
Kojto 100:cbbeb26dbd92 1059 /** \brief Set FPEXC
Kojto 100:cbbeb26dbd92 1060
Kojto 100:cbbeb26dbd92 1061 This function assigns the given value to the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 1062
Kojto 100:cbbeb26dbd92 1063 \param [in] fpscr Floating Point Exception Control value to set
Kojto 100:cbbeb26dbd92 1064 */
Kojto 100:cbbeb26dbd92 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 100:cbbeb26dbd92 1066 {
Kojto 100:cbbeb26dbd92 1067 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 1068 #if 1
Kojto 100:cbbeb26dbd92 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 100:cbbeb26dbd92 1070 #else
Kojto 100:cbbeb26dbd92 1071 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 1072 __regfpexc = (fpexc);
Kojto 100:cbbeb26dbd92 1073 #endif
Kojto 100:cbbeb26dbd92 1074 #endif
Kojto 100:cbbeb26dbd92 1075 }
Kojto 100:cbbeb26dbd92 1076
Kojto 100:cbbeb26dbd92 1077 /** \brief Get CPACR
Kojto 100:cbbeb26dbd92 1078
Kojto 100:cbbeb26dbd92 1079 This function returns the current value of the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 1080
Kojto 100:cbbeb26dbd92 1081 \return Coprocessor Access Control register value
Kojto 100:cbbeb26dbd92 1082 */
Kojto 100:cbbeb26dbd92 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 100:cbbeb26dbd92 1084 {
Kojto 100:cbbeb26dbd92 1085 #if 1
Kojto 100:cbbeb26dbd92 1086 register uint32_t __regCPACR;
Kojto 100:cbbeb26dbd92 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 100:cbbeb26dbd92 1088 #else
Kojto 100:cbbeb26dbd92 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 1090 #endif
Kojto 100:cbbeb26dbd92 1091 return __regCPACR;
Kojto 100:cbbeb26dbd92 1092 }
Kojto 100:cbbeb26dbd92 1093
Kojto 100:cbbeb26dbd92 1094 /** \brief Set CPACR
Kojto 100:cbbeb26dbd92 1095
Kojto 100:cbbeb26dbd92 1096 This function assigns the given value to the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 1097
Kojto 108:34e6b704fe68 1098 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 100:cbbeb26dbd92 1099 */
Kojto 100:cbbeb26dbd92 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 100:cbbeb26dbd92 1101 {
Kojto 100:cbbeb26dbd92 1102 #if 1
Kojto 100:cbbeb26dbd92 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 100:cbbeb26dbd92 1104 #else
Kojto 100:cbbeb26dbd92 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 1106 __regCPACR = cpacr;
Kojto 100:cbbeb26dbd92 1107 #endif
Kojto 100:cbbeb26dbd92 1108 __ISB();
Kojto 100:cbbeb26dbd92 1109 }
Kojto 100:cbbeb26dbd92 1110
Kojto 100:cbbeb26dbd92 1111 /** \brief Get CBAR
Kojto 100:cbbeb26dbd92 1112
Kojto 100:cbbeb26dbd92 1113 This function returns the value of the Configuration Base Address register.
Kojto 100:cbbeb26dbd92 1114
Kojto 100:cbbeb26dbd92 1115 \return Configuration Base Address register value
Kojto 100:cbbeb26dbd92 1116 */
Kojto 100:cbbeb26dbd92 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 100:cbbeb26dbd92 1118 #if 1
Kojto 100:cbbeb26dbd92 1119 register uint32_t __regCBAR;
Kojto 100:cbbeb26dbd92 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 100:cbbeb26dbd92 1121 #else
Kojto 100:cbbeb26dbd92 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 100:cbbeb26dbd92 1123 #endif
Kojto 100:cbbeb26dbd92 1124 return(__regCBAR);
Kojto 100:cbbeb26dbd92 1125 }
Kojto 100:cbbeb26dbd92 1126
Kojto 100:cbbeb26dbd92 1127 /** \brief Get TTBR0
Kojto 100:cbbeb26dbd92 1128
Kojto 108:34e6b704fe68 1129 This function returns the value of the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 1130
Kojto 100:cbbeb26dbd92 1131 \return Translation Table Base Register 0 value
Kojto 100:cbbeb26dbd92 1132 */
Kojto 100:cbbeb26dbd92 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 100:cbbeb26dbd92 1134 #if 1
Kojto 100:cbbeb26dbd92 1135 register uint32_t __regTTBR0;
Kojto 100:cbbeb26dbd92 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 100:cbbeb26dbd92 1137 #else
Kojto 100:cbbeb26dbd92 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 1139 #endif
Kojto 100:cbbeb26dbd92 1140 return(__regTTBR0);
Kojto 100:cbbeb26dbd92 1141 }
Kojto 100:cbbeb26dbd92 1142
Kojto 100:cbbeb26dbd92 1143 /** \brief Set TTBR0
Kojto 100:cbbeb26dbd92 1144
Kojto 108:34e6b704fe68 1145 This function assigns the given value to the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 1146
Kojto 100:cbbeb26dbd92 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 100:cbbeb26dbd92 1148 */
Kojto 100:cbbeb26dbd92 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 100:cbbeb26dbd92 1150 #if 1
Kojto 100:cbbeb26dbd92 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 100:cbbeb26dbd92 1152 #else
Kojto 100:cbbeb26dbd92 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 1154 __regTTBR0 = ttbr0;
Kojto 100:cbbeb26dbd92 1155 #endif
Kojto 100:cbbeb26dbd92 1156 __ISB();
Kojto 100:cbbeb26dbd92 1157 }
Kojto 100:cbbeb26dbd92 1158
Kojto 100:cbbeb26dbd92 1159 /** \brief Get DACR
Kojto 100:cbbeb26dbd92 1160
Kojto 100:cbbeb26dbd92 1161 This function returns the value of the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 1162
Kojto 100:cbbeb26dbd92 1163 \return Domain Access Control Register value
Kojto 100:cbbeb26dbd92 1164 */
Kojto 100:cbbeb26dbd92 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 100:cbbeb26dbd92 1166 #if 1
Kojto 100:cbbeb26dbd92 1167 register uint32_t __regDACR;
Kojto 100:cbbeb26dbd92 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 100:cbbeb26dbd92 1169 #else
Kojto 100:cbbeb26dbd92 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 1171 #endif
Kojto 100:cbbeb26dbd92 1172 return(__regDACR);
Kojto 100:cbbeb26dbd92 1173 }
Kojto 100:cbbeb26dbd92 1174
Kojto 100:cbbeb26dbd92 1175 /** \brief Set DACR
Kojto 100:cbbeb26dbd92 1176
Kojto 108:34e6b704fe68 1177 This function assigns the given value to the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 1178
Kojto 100:cbbeb26dbd92 1179 \param [in] dacr Domain Access Control Register value to set
Kojto 100:cbbeb26dbd92 1180 */
Kojto 100:cbbeb26dbd92 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 100:cbbeb26dbd92 1182 #if 1
Kojto 100:cbbeb26dbd92 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 100:cbbeb26dbd92 1184 #else
Kojto 100:cbbeb26dbd92 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 1186 __regDACR = dacr;
Kojto 100:cbbeb26dbd92 1187 #endif
Kojto 100:cbbeb26dbd92 1188 __ISB();
Kojto 100:cbbeb26dbd92 1189 }
Kojto 100:cbbeb26dbd92 1190
Kojto 100:cbbeb26dbd92 1191 /******************************** Cache and BTAC enable ****************************************************/
Kojto 100:cbbeb26dbd92 1192
Kojto 100:cbbeb26dbd92 1193 /** \brief Set SCTLR
Kojto 100:cbbeb26dbd92 1194
Kojto 100:cbbeb26dbd92 1195 This function assigns the given value to the System Control Register.
Kojto 100:cbbeb26dbd92 1196
Kojto 108:34e6b704fe68 1197 \param [in] sctlr System Control Register value to set
Kojto 100:cbbeb26dbd92 1198 */
Kojto 100:cbbeb26dbd92 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 100:cbbeb26dbd92 1200 {
Kojto 100:cbbeb26dbd92 1201 #if 1
Kojto 100:cbbeb26dbd92 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 100:cbbeb26dbd92 1203 #else
Kojto 100:cbbeb26dbd92 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 1205 __regSCTLR = sctlr;
Kojto 100:cbbeb26dbd92 1206 #endif
Kojto 100:cbbeb26dbd92 1207 }
Kojto 100:cbbeb26dbd92 1208
Kojto 100:cbbeb26dbd92 1209 /** \brief Get SCTLR
Kojto 100:cbbeb26dbd92 1210
Kojto 100:cbbeb26dbd92 1211 This function returns the value of the System Control Register.
Kojto 100:cbbeb26dbd92 1212
Kojto 100:cbbeb26dbd92 1213 \return System Control Register value
Kojto 100:cbbeb26dbd92 1214 */
Kojto 100:cbbeb26dbd92 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 100:cbbeb26dbd92 1216 #if 1
Kojto 100:cbbeb26dbd92 1217 register uint32_t __regSCTLR;
Kojto 100:cbbeb26dbd92 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 100:cbbeb26dbd92 1219 #else
Kojto 100:cbbeb26dbd92 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 1221 #endif
Kojto 100:cbbeb26dbd92 1222 return(__regSCTLR);
Kojto 100:cbbeb26dbd92 1223 }
Kojto 100:cbbeb26dbd92 1224
Kojto 100:cbbeb26dbd92 1225 /** \brief Enable Caches
Kojto 100:cbbeb26dbd92 1226
Kojto 100:cbbeb26dbd92 1227 Enable Caches
Kojto 100:cbbeb26dbd92 1228 */
Kojto 100:cbbeb26dbd92 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 100:cbbeb26dbd92 1230 // Set I bit 12 to enable I Cache
Kojto 100:cbbeb26dbd92 1231 // Set C bit 2 to enable D Cache
Kojto 100:cbbeb26dbd92 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 100:cbbeb26dbd92 1233 }
Kojto 100:cbbeb26dbd92 1234
Kojto 100:cbbeb26dbd92 1235 /** \brief Disable Caches
Kojto 100:cbbeb26dbd92 1236
Kojto 100:cbbeb26dbd92 1237 Disable Caches
Kojto 100:cbbeb26dbd92 1238 */
Kojto 100:cbbeb26dbd92 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 100:cbbeb26dbd92 1240 // Clear I bit 12 to disable I Cache
Kojto 100:cbbeb26dbd92 1241 // Clear C bit 2 to disable D Cache
Kojto 100:cbbeb26dbd92 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 100:cbbeb26dbd92 1243 __ISB();
Kojto 100:cbbeb26dbd92 1244 }
Kojto 100:cbbeb26dbd92 1245
Kojto 100:cbbeb26dbd92 1246 /** \brief Enable BTAC
Kojto 100:cbbeb26dbd92 1247
Kojto 100:cbbeb26dbd92 1248 Enable BTAC
Kojto 100:cbbeb26dbd92 1249 */
Kojto 100:cbbeb26dbd92 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 100:cbbeb26dbd92 1251 // Set Z bit 11 to enable branch prediction
Kojto 100:cbbeb26dbd92 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 100:cbbeb26dbd92 1253 __ISB();
Kojto 100:cbbeb26dbd92 1254 }
Kojto 100:cbbeb26dbd92 1255
Kojto 100:cbbeb26dbd92 1256 /** \brief Disable BTAC
Kojto 100:cbbeb26dbd92 1257
Kojto 100:cbbeb26dbd92 1258 Disable BTAC
Kojto 100:cbbeb26dbd92 1259 */
Kojto 100:cbbeb26dbd92 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 100:cbbeb26dbd92 1261 // Clear Z bit 11 to disable branch prediction
Kojto 100:cbbeb26dbd92 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 100:cbbeb26dbd92 1263 }
Kojto 100:cbbeb26dbd92 1264
Kojto 100:cbbeb26dbd92 1265
Kojto 100:cbbeb26dbd92 1266 /** \brief Enable MMU
Kojto 100:cbbeb26dbd92 1267
Kojto 100:cbbeb26dbd92 1268 Enable MMU
Kojto 100:cbbeb26dbd92 1269 */
Kojto 100:cbbeb26dbd92 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 100:cbbeb26dbd92 1271 // Set M bit 0 to enable the MMU
Kojto 100:cbbeb26dbd92 1272 // Set AFE bit to enable simplified access permissions model
Kojto 100:cbbeb26dbd92 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 100:cbbeb26dbd92 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 100:cbbeb26dbd92 1275 __ISB();
Kojto 100:cbbeb26dbd92 1276 }
Kojto 100:cbbeb26dbd92 1277
Kojto 108:34e6b704fe68 1278 /** \brief Disable MMU
Kojto 100:cbbeb26dbd92 1279
Kojto 108:34e6b704fe68 1280 Disable MMU
Kojto 100:cbbeb26dbd92 1281 */
Kojto 100:cbbeb26dbd92 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 100:cbbeb26dbd92 1283 // Clear M bit 0 to disable the MMU
Kojto 100:cbbeb26dbd92 1284 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 100:cbbeb26dbd92 1285 __ISB();
Kojto 100:cbbeb26dbd92 1286 }
Kojto 100:cbbeb26dbd92 1287
Kojto 100:cbbeb26dbd92 1288 /******************************** TLB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 1289 /** \brief Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 1290
Kojto 100:cbbeb26dbd92 1291 TLBIALL. Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 1292 */
Kojto 100:cbbeb26dbd92 1293
Kojto 100:cbbeb26dbd92 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 100:cbbeb26dbd92 1295 #if 1
Kojto 100:cbbeb26dbd92 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 100:cbbeb26dbd92 1297 #else
Kojto 100:cbbeb26dbd92 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 100:cbbeb26dbd92 1299 __TLBIALL = 0;
Kojto 100:cbbeb26dbd92 1300 #endif
Kojto 100:cbbeb26dbd92 1301 __DSB();
Kojto 100:cbbeb26dbd92 1302 __ISB();
Kojto 100:cbbeb26dbd92 1303 }
Kojto 100:cbbeb26dbd92 1304
Kojto 100:cbbeb26dbd92 1305 /******************************** BTB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 1306 /** \brief Invalidate entire branch predictor array
Kojto 100:cbbeb26dbd92 1307
Kojto 100:cbbeb26dbd92 1308 BPIALL. Branch Predictor Invalidate All.
Kojto 100:cbbeb26dbd92 1309 */
Kojto 100:cbbeb26dbd92 1310
Kojto 100:cbbeb26dbd92 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 100:cbbeb26dbd92 1312 #if 1
Kojto 100:cbbeb26dbd92 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 100:cbbeb26dbd92 1314 #else
Kojto 100:cbbeb26dbd92 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 100:cbbeb26dbd92 1316 __BPIALL = 0;
Kojto 100:cbbeb26dbd92 1317 #endif
Kojto 100:cbbeb26dbd92 1318 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 1319 __ISB(); //ensure instruction fetch path sees new state
Kojto 100:cbbeb26dbd92 1320 }
Kojto 100:cbbeb26dbd92 1321
Kojto 100:cbbeb26dbd92 1322
Kojto 100:cbbeb26dbd92 1323 /******************************** L1 cache operations ******************************************************/
Kojto 100:cbbeb26dbd92 1324
Kojto 100:cbbeb26dbd92 1325 /** \brief Invalidate the whole I$
Kojto 100:cbbeb26dbd92 1326
Kojto 100:cbbeb26dbd92 1327 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 100:cbbeb26dbd92 1328 */
Kojto 100:cbbeb26dbd92 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 100:cbbeb26dbd92 1330 #if 1
Kojto 100:cbbeb26dbd92 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 100:cbbeb26dbd92 1332 #else
Kojto 100:cbbeb26dbd92 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 100:cbbeb26dbd92 1334 __ICIALLU = 0;
Kojto 100:cbbeb26dbd92 1335 #endif
Kojto 100:cbbeb26dbd92 1336 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 1337 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 100:cbbeb26dbd92 1338 }
Kojto 100:cbbeb26dbd92 1339
Kojto 100:cbbeb26dbd92 1340 /** \brief Clean D$ by MVA
Kojto 100:cbbeb26dbd92 1341
Kojto 100:cbbeb26dbd92 1342 DCCMVAC. Data cache clean by MVA to PoC
Kojto 100:cbbeb26dbd92 1343 */
Kojto 100:cbbeb26dbd92 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 1345 #if 1
Kojto 100:cbbeb26dbd92 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 100:cbbeb26dbd92 1347 #else
Kojto 100:cbbeb26dbd92 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 100:cbbeb26dbd92 1349 __DCCMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 1350 #endif
Kojto 100:cbbeb26dbd92 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 1352 }
Kojto 100:cbbeb26dbd92 1353
Kojto 100:cbbeb26dbd92 1354 /** \brief Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 1355
Kojto 100:cbbeb26dbd92 1356 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 1357 */
Kojto 100:cbbeb26dbd92 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 1359 #if 1
Kojto 100:cbbeb26dbd92 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 100:cbbeb26dbd92 1361 #else
Kojto 100:cbbeb26dbd92 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 100:cbbeb26dbd92 1363 __DCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 1364 #endif
Kojto 100:cbbeb26dbd92 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 1366 }
Kojto 100:cbbeb26dbd92 1367
Kojto 100:cbbeb26dbd92 1368 /** \brief Clean and Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 1369
Kojto 100:cbbeb26dbd92 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 1371 */
Kojto 100:cbbeb26dbd92 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 1373 #if 1
Kojto 100:cbbeb26dbd92 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 100:cbbeb26dbd92 1375 #else
Kojto 100:cbbeb26dbd92 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 100:cbbeb26dbd92 1377 __DCCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 1378 #endif
Kojto 100:cbbeb26dbd92 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 1380 }
Kojto 100:cbbeb26dbd92 1381
Kojto 108:34e6b704fe68 1382 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 100:cbbeb26dbd92 1383
Kojto 108:34e6b704fe68 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 100:cbbeb26dbd92 1385 */
Kojto 100:cbbeb26dbd92 1386 extern void __v7_all_cache(uint32_t op);
Kojto 100:cbbeb26dbd92 1387
Kojto 100:cbbeb26dbd92 1388
Kojto 100:cbbeb26dbd92 1389 /** \brief Invalidate the whole D$
Kojto 100:cbbeb26dbd92 1390
Kojto 100:cbbeb26dbd92 1391 DCISW. Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 1392 */
Kojto 100:cbbeb26dbd92 1393
Kojto 100:cbbeb26dbd92 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 1395 __v7_all_cache(0);
Kojto 100:cbbeb26dbd92 1396 }
Kojto 100:cbbeb26dbd92 1397
Kojto 100:cbbeb26dbd92 1398 /** \brief Clean the whole D$
Kojto 100:cbbeb26dbd92 1399
Kojto 100:cbbeb26dbd92 1400 DCCSW. Clean by Set/Way
Kojto 100:cbbeb26dbd92 1401 */
Kojto 100:cbbeb26dbd92 1402
Kojto 100:cbbeb26dbd92 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 100:cbbeb26dbd92 1404 __v7_all_cache(1);
Kojto 100:cbbeb26dbd92 1405 }
Kojto 100:cbbeb26dbd92 1406
Kojto 100:cbbeb26dbd92 1407 /** \brief Clean and invalidate the whole D$
Kojto 100:cbbeb26dbd92 1408
Kojto 100:cbbeb26dbd92 1409 DCCISW. Clean and Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 1410 */
Kojto 100:cbbeb26dbd92 1411
Kojto 100:cbbeb26dbd92 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 1413 __v7_all_cache(2);
Kojto 100:cbbeb26dbd92 1414 }
Kojto 100:cbbeb26dbd92 1415
Kojto 100:cbbeb26dbd92 1416 #include "core_ca_mmu.h"
Kojto 100:cbbeb26dbd92 1417
Kojto 100:cbbeb26dbd92 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 100:cbbeb26dbd92 1419
Kojto 100:cbbeb26dbd92 1420 #error TASKING Compiler support not implemented for Cortex-A
Kojto 100:cbbeb26dbd92 1421
Kojto 100:cbbeb26dbd92 1422 #endif
Kojto 100:cbbeb26dbd92 1423
Kojto 100:cbbeb26dbd92 1424 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 100:cbbeb26dbd92 1425
Kojto 100:cbbeb26dbd92 1426
Kojto 100:cbbeb26dbd92 1427 #endif /* __CORE_CAFUNC_H__ */