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TARGET_UBRIDGE/TOOLCHAIN_GCC_ARM/fsl_lmem_cache.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /*
AnnaBridge 145:64910690c574 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 145:64910690c574 3 * All rights reserved.
AnnaBridge 145:64910690c574 4 *
AnnaBridge 145:64910690c574 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 145:64910690c574 6 * are permitted provided that the following conditions are met:
AnnaBridge 145:64910690c574 7 *
AnnaBridge 145:64910690c574 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 145:64910690c574 9 * of conditions and the following disclaimer.
AnnaBridge 145:64910690c574 10 *
AnnaBridge 145:64910690c574 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 145:64910690c574 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 145:64910690c574 13 * other materials provided with the distribution.
AnnaBridge 145:64910690c574 14 *
AnnaBridge 145:64910690c574 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 145:64910690c574 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 145:64910690c574 17 * software without specific prior written permission.
AnnaBridge 145:64910690c574 18 *
AnnaBridge 145:64910690c574 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 145:64910690c574 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 145:64910690c574 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 145:64910690c574 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 145:64910690c574 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 145:64910690c574 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 145:64910690c574 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 145:64910690c574 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 145:64910690c574 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 145:64910690c574 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 145:64910690c574 29 */
AnnaBridge 145:64910690c574 30 #ifndef _FSL_LMEM_CACHE_H_
AnnaBridge 145:64910690c574 31 #define _FSL_LMEM_CACHE_H_
AnnaBridge 145:64910690c574 32
AnnaBridge 145:64910690c574 33 #include "fsl_common.h"
AnnaBridge 145:64910690c574 34
AnnaBridge 145:64910690c574 35 /*!
AnnaBridge 145:64910690c574 36 * @addtogroup lmem_cache
AnnaBridge 145:64910690c574 37 * @{
AnnaBridge 145:64910690c574 38 */
AnnaBridge 145:64910690c574 39
AnnaBridge 145:64910690c574 40
AnnaBridge 145:64910690c574 41 /*******************************************************************************
AnnaBridge 145:64910690c574 42 * Definitions
AnnaBridge 145:64910690c574 43 ******************************************************************************/
AnnaBridge 145:64910690c574 44
AnnaBridge 145:64910690c574 45 /*! @name Driver version */
AnnaBridge 145:64910690c574 46 /*@{*/
AnnaBridge 145:64910690c574 47 /*! @brief LMEM controller driver version 2.1.0. */
AnnaBridge 145:64910690c574 48 #define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
AnnaBridge 145:64910690c574 49 /*@}*/
AnnaBridge 145:64910690c574 50
AnnaBridge 145:64910690c574 51 #define LMEM_CACHE_LINE_SIZE (0x10U) /*!< Cache line is 16-bytes. */
AnnaBridge 145:64910690c574 52 #define LMEM_CACHE_SIZE_ONEWAY (4096U) /*!< Cache size is 4K-bytes one way. */
AnnaBridge 145:64910690c574 53
AnnaBridge 145:64910690c574 54 /*! @brief LMEM cache mode options. */
AnnaBridge 145:64910690c574 55 typedef enum _lmem_cache_mode
AnnaBridge 145:64910690c574 56 {
AnnaBridge 145:64910690c574 57 kLMEM_NonCacheable = 0x0U, /*!< Cache mode: non-cacheable. */
AnnaBridge 145:64910690c574 58 kLMEM_CacheWriteThrough = 0x2U, /*!< Cache mode: write-through. */
AnnaBridge 145:64910690c574 59 kLMEM_CacheWriteBack = 0x3U /*!< Cache mode: write-back. */
AnnaBridge 145:64910690c574 60 } lmem_cache_mode_t;
AnnaBridge 145:64910690c574 61
AnnaBridge 145:64910690c574 62 /*! @brief LMEM cache regions. */
AnnaBridge 145:64910690c574 63 typedef enum _lmem_cache_region
AnnaBridge 145:64910690c574 64 {
AnnaBridge 145:64910690c574 65 kLMEM_CacheRegion15 = 0U, /*!< Cache Region 15. */
AnnaBridge 145:64910690c574 66 kLMEM_CacheRegion14, /*!< Cache Region 14. */
AnnaBridge 145:64910690c574 67 kLMEM_CacheRegion13, /*!< Cache Region 13. */
AnnaBridge 145:64910690c574 68 kLMEM_CacheRegion12, /*!< Cache Region 12. */
AnnaBridge 145:64910690c574 69 kLMEM_CacheRegion11, /*!< Cache Region 11. */
AnnaBridge 145:64910690c574 70 kLMEM_CacheRegion10, /*!< Cache Region 10. */
AnnaBridge 145:64910690c574 71 kLMEM_CacheRegion9, /*!< Cache Region 9. */
AnnaBridge 145:64910690c574 72 kLMEM_CacheRegion8, /*!< Cache Region 8. */
AnnaBridge 145:64910690c574 73 kLMEM_CacheRegion7, /*!< Cache Region 7. */
AnnaBridge 145:64910690c574 74 kLMEM_CacheRegion6, /*!< Cache Region 6. */
AnnaBridge 145:64910690c574 75 kLMEM_CacheRegion5, /*!< Cache Region 5. */
AnnaBridge 145:64910690c574 76 kLMEM_CacheRegion4, /*!< Cache Region 4. */
AnnaBridge 145:64910690c574 77 kLMEM_CacheRegion3, /*!< Cache Region 3. */
AnnaBridge 145:64910690c574 78 kLMEM_CacheRegion2, /*!< Cache Region 2. */
AnnaBridge 145:64910690c574 79 kLMEM_CacheRegion1, /*!< Cache Region 1. */
AnnaBridge 145:64910690c574 80 kLMEM_CacheRegion0 /*!< Cache Region 0. */
AnnaBridge 145:64910690c574 81 } lmem_cache_region_t;
AnnaBridge 145:64910690c574 82
AnnaBridge 145:64910690c574 83 /*! @brief LMEM cache line command. */
AnnaBridge 145:64910690c574 84 typedef enum _lmem_cache_line_command
AnnaBridge 145:64910690c574 85 {
AnnaBridge 145:64910690c574 86 kLMEM_CacheLineSearchReadOrWrite = 0U, /*!< Cache line search and read or write. */
AnnaBridge 145:64910690c574 87 kLMEM_CacheLineInvalidate, /*!< Cache line invalidate. */
AnnaBridge 145:64910690c574 88 kLMEM_CacheLinePush, /*!< Cache line push. */
AnnaBridge 145:64910690c574 89 kLMEM_CacheLineClear, /*!< Cache line clear. */
AnnaBridge 145:64910690c574 90 } lmem_cache_line_command_t;
AnnaBridge 145:64910690c574 91
AnnaBridge 145:64910690c574 92 /*******************************************************************************
AnnaBridge 145:64910690c574 93 * API
AnnaBridge 145:64910690c574 94 ******************************************************************************/
AnnaBridge 145:64910690c574 95
AnnaBridge 145:64910690c574 96 #if defined(__cplusplus)
AnnaBridge 145:64910690c574 97 extern "C" {
AnnaBridge 145:64910690c574 98 #endif
AnnaBridge 145:64910690c574 99
AnnaBridge 145:64910690c574 100 /*!
AnnaBridge 145:64910690c574 101 * @name Local Memory Processor Code Bus Cache Control
AnnaBridge 145:64910690c574 102 *@{
AnnaBridge 145:64910690c574 103 */
AnnaBridge 145:64910690c574 104
AnnaBridge 145:64910690c574 105 /*!
AnnaBridge 145:64910690c574 106 * @brief Enables/disables the processor code bus cache.
AnnaBridge 145:64910690c574 107 * This function enables/disables the cache. The function first invalidates the entire cache
AnnaBridge 145:64910690c574 108 * and then enables/disables both the cache and write buffers.
AnnaBridge 145:64910690c574 109 *
AnnaBridge 145:64910690c574 110 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 111 * @param enable The enable or disable flag.
AnnaBridge 145:64910690c574 112 * true - enable the code cache.
AnnaBridge 145:64910690c574 113 * false - disable the code cache.
AnnaBridge 145:64910690c574 114 */
AnnaBridge 145:64910690c574 115 void LMEM_EnableCodeCache(LMEM_Type *base, bool enable);
AnnaBridge 145:64910690c574 116
AnnaBridge 145:64910690c574 117 /*!
AnnaBridge 145:64910690c574 118 * @brief Enables/disables the processor code bus write buffer.
AnnaBridge 145:64910690c574 119 *
AnnaBridge 145:64910690c574 120 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 121 * @param enable The enable or disable flag.
AnnaBridge 145:64910690c574 122 * true - enable the code bus write buffer.
AnnaBridge 145:64910690c574 123 * false - disable the code bus write buffer.
AnnaBridge 145:64910690c574 124 */
AnnaBridge 145:64910690c574 125 static inline void LMEM_EnableCodeWriteBuffer(LMEM_Type *base, bool enable)
AnnaBridge 145:64910690c574 126 {
AnnaBridge 145:64910690c574 127 if (enable)
AnnaBridge 145:64910690c574 128 {
AnnaBridge 145:64910690c574 129 base->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
AnnaBridge 145:64910690c574 130 }
AnnaBridge 145:64910690c574 131 else
AnnaBridge 145:64910690c574 132 {
AnnaBridge 145:64910690c574 133 base->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
AnnaBridge 145:64910690c574 134 }
AnnaBridge 145:64910690c574 135 }
AnnaBridge 145:64910690c574 136
AnnaBridge 145:64910690c574 137 /*!
AnnaBridge 145:64910690c574 138 * @brief Invalidates the processor code bus cache.
AnnaBridge 145:64910690c574 139 * This function invalidates the cache both ways, which means that
AnnaBridge 145:64910690c574 140 * it unconditionally clears valid bits and modifies bits of a cache entry.
AnnaBridge 145:64910690c574 141 *
AnnaBridge 145:64910690c574 142 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 143 */
AnnaBridge 145:64910690c574 144 void LMEM_CodeCacheInvalidateAll(LMEM_Type *base);
AnnaBridge 145:64910690c574 145
AnnaBridge 145:64910690c574 146 /*!
AnnaBridge 145:64910690c574 147 * @brief Pushes all modified lines in the processor code bus cache.
AnnaBridge 145:64910690c574 148 * This function pushes all modified lines in both ways in the entire cache.
AnnaBridge 145:64910690c574 149 * It pushes a cache entry if it is valid and modified and clears the modified bit. If
AnnaBridge 145:64910690c574 150 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 145:64910690c574 151 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 145:64910690c574 152 *
AnnaBridge 145:64910690c574 153 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 154 */
AnnaBridge 145:64910690c574 155 void LMEM_CodeCachePushAll(LMEM_Type *base);
AnnaBridge 145:64910690c574 156
AnnaBridge 145:64910690c574 157 /*!
AnnaBridge 145:64910690c574 158 * @brief Clears the processor code bus cache.
AnnaBridge 145:64910690c574 159 * This function clears the entire cache and pushes (flushes) and
AnnaBridge 145:64910690c574 160 * invalidates the operation.
AnnaBridge 145:64910690c574 161 * Clear - Pushes a cache entry if it is valid and modified, then clears the valid and
AnnaBridge 145:64910690c574 162 * modified bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 145:64910690c574 163 *
AnnaBridge 145:64910690c574 164 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 165 */
AnnaBridge 145:64910690c574 166 void LMEM_CodeCacheClearAll(LMEM_Type *base);
AnnaBridge 145:64910690c574 167
AnnaBridge 145:64910690c574 168 /*!
AnnaBridge 145:64910690c574 169 * @brief Invalidates a specific line in the processor code bus cache.
AnnaBridge 145:64910690c574 170 * This function invalidates a specific line in the cache
AnnaBridge 145:64910690c574 171 * based on the physical address passed in by the user.
AnnaBridge 145:64910690c574 172 * Invalidate - Unconditionally clears valid and modified bits of a cache entry.
AnnaBridge 145:64910690c574 173 *
AnnaBridge 145:64910690c574 174 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 175 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 176 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 177 */
AnnaBridge 145:64910690c574 178 void LMEM_CodeCacheInvalidateLine(LMEM_Type *base, uint32_t address);
AnnaBridge 145:64910690c574 179
AnnaBridge 145:64910690c574 180 /*!
AnnaBridge 145:64910690c574 181 * @brief Invalidates multiple lines in the processor code bus cache.
AnnaBridge 145:64910690c574 182 * This function invalidates multiple lines in the cache
AnnaBridge 145:64910690c574 183 * based on the physical address and length in bytes passed in by the
AnnaBridge 145:64910690c574 184 * user. If the function detects that the length meets or exceeds half the
AnnaBridge 145:64910690c574 185 * cache, the function performs an entire cache invalidate function, which is
AnnaBridge 145:64910690c574 186 * more efficient than invalidating the cache line-by-line.
AnnaBridge 145:64910690c574 187 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 145:64910690c574 188 * check half the total amount of cache.
AnnaBridge 145:64910690c574 189 * Invalidate - Unconditionally clear valid and modified bits of a cache entry.
AnnaBridge 145:64910690c574 190 *
AnnaBridge 145:64910690c574 191 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 192 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 193 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 194 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 145:64910690c574 195 */
AnnaBridge 145:64910690c574 196 void LMEM_CodeCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 145:64910690c574 197
AnnaBridge 145:64910690c574 198 /*!
AnnaBridge 145:64910690c574 199 * @brief Pushes a specific modified line in the processor code bus cache.
AnnaBridge 145:64910690c574 200 * This function pushes a specific modified line based on the physical address passed in
AnnaBridge 145:64910690c574 201 * by the user.
AnnaBridge 145:64910690c574 202 * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If the
AnnaBridge 145:64910690c574 203 * entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 145:64910690c574 204 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 145:64910690c574 205 *
AnnaBridge 145:64910690c574 206 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 207 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 208 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 209 */
AnnaBridge 145:64910690c574 210 void LMEM_CodeCachePushLine(LMEM_Type *base, uint32_t address);
AnnaBridge 145:64910690c574 211
AnnaBridge 145:64910690c574 212 /*!
AnnaBridge 145:64910690c574 213 * @brief Pushes multiple modified lines in the processor code bus cache.
AnnaBridge 145:64910690c574 214 * This function pushes multiple modified lines in the cache
AnnaBridge 145:64910690c574 215 * based on the physical address and length in bytes passed in by the
AnnaBridge 145:64910690c574 216 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 145:64910690c574 217 * cache, the function performs an cache push function, which is
AnnaBridge 145:64910690c574 218 * more efficient than pushing the modified lines in the cache line-by-line.
AnnaBridge 145:64910690c574 219 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 145:64910690c574 220 * check half the total amount of cache.
AnnaBridge 145:64910690c574 221 * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If
AnnaBridge 145:64910690c574 222 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 145:64910690c574 223 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 145:64910690c574 224 *
AnnaBridge 145:64910690c574 225 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 226 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 227 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 228 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 145:64910690c574 229 */
AnnaBridge 145:64910690c574 230 void LMEM_CodeCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 145:64910690c574 231
AnnaBridge 145:64910690c574 232 /*!
AnnaBridge 145:64910690c574 233 * @brief Clears a specific line in the processor code bus cache.
AnnaBridge 145:64910690c574 234 * This function clears a specific line based on the physical address passed in
AnnaBridge 145:64910690c574 235 * by the user.
AnnaBridge 145:64910690c574 236 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 145:64910690c574 237 * modify bits. If entry not valid or not modified, clear the valid bit.
AnnaBridge 145:64910690c574 238 *
AnnaBridge 145:64910690c574 239 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 240 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 241 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 242 */
AnnaBridge 145:64910690c574 243 void LMEM_CodeCacheClearLine(LMEM_Type *base, uint32_t address);
AnnaBridge 145:64910690c574 244
AnnaBridge 145:64910690c574 245 /*!
AnnaBridge 145:64910690c574 246 * @brief Clears multiple lines in the processor code bus cache.
AnnaBridge 145:64910690c574 247 * This function clears multiple lines in the cache
AnnaBridge 145:64910690c574 248 * based on the physical address and length in bytes passed in by the
AnnaBridge 145:64910690c574 249 * user. If the function detects that the length meets or exceeds half the total amount of
AnnaBridge 145:64910690c574 250 * cache, the function performs a cache clear function which is
AnnaBridge 145:64910690c574 251 * more efficient than clearing the lines in the cache line-by-line.
AnnaBridge 145:64910690c574 252 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 145:64910690c574 253 * check half the total amount of cache.
AnnaBridge 145:64910690c574 254 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 145:64910690c574 255 * modify bits. If entry not valid or not modified, clear the valid bit.
AnnaBridge 145:64910690c574 256 *
AnnaBridge 145:64910690c574 257 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 258 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 259 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 260 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 145:64910690c574 261 */
AnnaBridge 145:64910690c574 262 void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 145:64910690c574 263
AnnaBridge 145:64910690c574 264 #if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE
AnnaBridge 145:64910690c574 265 /*!
AnnaBridge 145:64910690c574 266 * @brief Demotes the cache mode of a region in processor code bus cache.
AnnaBridge 145:64910690c574 267 * This function allows the user to demote the cache mode of a region within the device's
AnnaBridge 145:64910690c574 268 * memory map. Demoting the cache mode reduces the cache function applied to a memory
AnnaBridge 145:64910690c574 269 * region from write-back to write-through to non-cacheable. The function checks to see
AnnaBridge 145:64910690c574 270 * if the requested cache mode is higher than or equal to the current cache mode, and if
AnnaBridge 145:64910690c574 271 * so, returns an error. After a region is demoted, its cache mode can only be raised
AnnaBridge 145:64910690c574 272 * by a reset, which returns it to its default state which is the highest cache configure for
AnnaBridge 145:64910690c574 273 * each region.
AnnaBridge 145:64910690c574 274 * To maintain cache coherency, changes to the cache mode should be completed while the
AnnaBridge 145:64910690c574 275 * address space being changed is not being accessed or the cache is disabled. Before a
AnnaBridge 145:64910690c574 276 * cache mode change, this function completes a cache clear all command to push and invalidate any
AnnaBridge 145:64910690c574 277 * cache entries that may have changed.
AnnaBridge 145:64910690c574 278 *
AnnaBridge 145:64910690c574 279 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 280 * @param region The desired region to demote of type lmem_cache_region_t.
AnnaBridge 145:64910690c574 281 * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t.
AnnaBridge 145:64910690c574 282 * @return The execution result.
AnnaBridge 145:64910690c574 283 * kStatus_Success The cache demote operation is successful.
AnnaBridge 145:64910690c574 284 * kStatus_Fail The cache demote operation is failure.
AnnaBridge 145:64910690c574 285 */
AnnaBridge 145:64910690c574 286 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
AnnaBridge 145:64910690c574 287 #endif /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */
AnnaBridge 145:64910690c574 288
AnnaBridge 145:64910690c574 289 /*@}*/
AnnaBridge 145:64910690c574 290
AnnaBridge 145:64910690c574 291 #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
AnnaBridge 145:64910690c574 292 /*!
AnnaBridge 145:64910690c574 293 * @name Local Memory Processor System Bus Cache Control
AnnaBridge 145:64910690c574 294 *@{
AnnaBridge 145:64910690c574 295 */
AnnaBridge 145:64910690c574 296
AnnaBridge 145:64910690c574 297 /*!
AnnaBridge 145:64910690c574 298 * @brief Enables/disables the processor system bus cache.
AnnaBridge 145:64910690c574 299 * This function enables/disables the cache. It first invalidates the entire cache,
AnnaBridge 145:64910690c574 300 * then enables /disable both the cache and write buffer.
AnnaBridge 145:64910690c574 301 *
AnnaBridge 145:64910690c574 302 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 303 * @param The enable or disable flag.
AnnaBridge 145:64910690c574 304 * true - enable the system cache.
AnnaBridge 145:64910690c574 305 * false - disable the system cache.
AnnaBridge 145:64910690c574 306 */
AnnaBridge 145:64910690c574 307 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable);
AnnaBridge 145:64910690c574 308
AnnaBridge 145:64910690c574 309 /*!
AnnaBridge 145:64910690c574 310 * @brief Enables/disables the processor system bus write buffer.
AnnaBridge 145:64910690c574 311 *
AnnaBridge 145:64910690c574 312 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 313 * @param enable The enable or disable flag.
AnnaBridge 145:64910690c574 314 * true - enable the system bus write buffer.
AnnaBridge 145:64910690c574 315 * false - disable the system bus write buffer.
AnnaBridge 145:64910690c574 316 */
AnnaBridge 145:64910690c574 317 static inline void LMEM_EnableSystemWriteBuffer(LMEM_Type *base, bool enable)
AnnaBridge 145:64910690c574 318 {
AnnaBridge 145:64910690c574 319 if (enable)
AnnaBridge 145:64910690c574 320 {
AnnaBridge 145:64910690c574 321 base->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
AnnaBridge 145:64910690c574 322 }
AnnaBridge 145:64910690c574 323 else
AnnaBridge 145:64910690c574 324 {
AnnaBridge 145:64910690c574 325 base->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
AnnaBridge 145:64910690c574 326 }
AnnaBridge 145:64910690c574 327 }
AnnaBridge 145:64910690c574 328
AnnaBridge 145:64910690c574 329 /*!
AnnaBridge 145:64910690c574 330 * @brief Invalidates the processor system bus cache.
AnnaBridge 145:64910690c574 331 * This function invalidates the entire cache both ways.
AnnaBridge 145:64910690c574 332 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
AnnaBridge 145:64910690c574 333 *
AnnaBridge 145:64910690c574 334 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 335 */
AnnaBridge 145:64910690c574 336 void LMEM_SystemCacheInvalidateAll(LMEM_Type *base);
AnnaBridge 145:64910690c574 337
AnnaBridge 145:64910690c574 338 /*!
AnnaBridge 145:64910690c574 339 * @brief Pushes all modified lines in the processor system bus cache.
AnnaBridge 145:64910690c574 340 * This function pushes all modified lines in both ways (the entire cache).
AnnaBridge 145:64910690c574 341 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
AnnaBridge 145:64910690c574 342 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 145:64910690c574 343 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 145:64910690c574 344 *
AnnaBridge 145:64910690c574 345 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 346 */
AnnaBridge 145:64910690c574 347 void LMEM_SystemCachePushAll(LMEM_Type *base);
AnnaBridge 145:64910690c574 348
AnnaBridge 145:64910690c574 349 /*!
AnnaBridge 145:64910690c574 350 * @brief Clears the entire processor system bus cache.
AnnaBridge 145:64910690c574 351 * This function clears the entire cache, which is a push (flush) and
AnnaBridge 145:64910690c574 352 * invalidate operation.
AnnaBridge 145:64910690c574 353 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 145:64910690c574 354 * modify bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 145:64910690c574 355 *
AnnaBridge 145:64910690c574 356 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 357 */
AnnaBridge 145:64910690c574 358 void LMEM_SystemCacheClearAll(LMEM_Type *base);
AnnaBridge 145:64910690c574 359
AnnaBridge 145:64910690c574 360 /*!
AnnaBridge 145:64910690c574 361 * @brief Invalidates a specific line in the processor system bus cache.
AnnaBridge 145:64910690c574 362 * This function invalidates a specific line in the cache
AnnaBridge 145:64910690c574 363 * based on the physical address passed in by the user.
AnnaBridge 145:64910690c574 364 * Invalidate - Unconditionally clears valid and modify bits of a cache entry.
AnnaBridge 145:64910690c574 365 *
AnnaBridge 145:64910690c574 366 * @param base LMEM peripheral base address. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 367 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 368 * @param address The physical address of the cache line.
AnnaBridge 145:64910690c574 369 */
AnnaBridge 145:64910690c574 370 void LMEM_SystemCacheInvalidateLine(LMEM_Type *base, uint32_t address);
AnnaBridge 145:64910690c574 371
AnnaBridge 145:64910690c574 372 /*!
AnnaBridge 145:64910690c574 373 * @brief Invalidates multiple lines in the processor system bus cache.
AnnaBridge 145:64910690c574 374 * This function invalidates multiple lines in the cache
AnnaBridge 145:64910690c574 375 * based on the physical address and length in bytes passed in by the
AnnaBridge 145:64910690c574 376 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 145:64910690c574 377 * cache, the function performs an entire cache invalidate function (which is
AnnaBridge 145:64910690c574 378 * more efficient than invalidating the cache line-by-line).
AnnaBridge 145:64910690c574 379 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 145:64910690c574 380 * check half the total amount of cache.
AnnaBridge 145:64910690c574 381 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
AnnaBridge 145:64910690c574 382 *
AnnaBridge 145:64910690c574 383 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 384 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 385 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 386 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 145:64910690c574 387 */
AnnaBridge 145:64910690c574 388 void LMEM_SystemCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 145:64910690c574 389
AnnaBridge 145:64910690c574 390 /*!
AnnaBridge 145:64910690c574 391 * @brief Pushes a specific modified line in the processor system bus cache.
AnnaBridge 145:64910690c574 392 * This function pushes a specific modified line based on the physical address passed in
AnnaBridge 145:64910690c574 393 * by the user.
AnnaBridge 145:64910690c574 394 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
AnnaBridge 145:64910690c574 395 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 145:64910690c574 396 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 145:64910690c574 397 *
AnnaBridge 145:64910690c574 398 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 399 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 400 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 401 */
AnnaBridge 145:64910690c574 402 void LMEM_SystemCachePushLine(LMEM_Type *base, uint32_t address);
AnnaBridge 145:64910690c574 403
AnnaBridge 145:64910690c574 404 /*!
AnnaBridge 145:64910690c574 405 * @brief Pushes multiple modified lines in the processor system bus cache.
AnnaBridge 145:64910690c574 406 * This function pushes multiple modified lines in the cache
AnnaBridge 145:64910690c574 407 * based on the physical address and length in bytes passed in by the
AnnaBridge 145:64910690c574 408 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 145:64910690c574 409 * cache, the function performs an entire cache push function (which is
AnnaBridge 145:64910690c574 410 * more efficient than pushing the modified lines in the cache line-by-line).
AnnaBridge 145:64910690c574 411 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 145:64910690c574 412 * check half the total amount of cache.
AnnaBridge 145:64910690c574 413 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
AnnaBridge 145:64910690c574 414 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 145:64910690c574 415 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 145:64910690c574 416 *
AnnaBridge 145:64910690c574 417 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 418 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 419 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 420 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 145:64910690c574 421 */
AnnaBridge 145:64910690c574 422 void LMEM_SystemCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 145:64910690c574 423
AnnaBridge 145:64910690c574 424 /*!
AnnaBridge 145:64910690c574 425 * @brief Clears a specific line in the processor system bus cache.
AnnaBridge 145:64910690c574 426 * This function clears a specific line based on the physical address passed in
AnnaBridge 145:64910690c574 427 * by the user.
AnnaBridge 145:64910690c574 428 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 145:64910690c574 429 * modify bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 145:64910690c574 430 *
AnnaBridge 145:64910690c574 431 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 432 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 433 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 434 */
AnnaBridge 145:64910690c574 435 void LMEM_SystemCacheClearLine(LMEM_Type *base, uint32_t address);
AnnaBridge 145:64910690c574 436
AnnaBridge 145:64910690c574 437 /*!
AnnaBridge 145:64910690c574 438 * @brief Clears multiple lines in the processor system bus cache.
AnnaBridge 145:64910690c574 439 * This function clears multiple lines in the cache
AnnaBridge 145:64910690c574 440 * based on the physical address and length in bytes passed in by the
AnnaBridge 145:64910690c574 441 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 145:64910690c574 442 * cache, the function performs an entire cache clear function (which is
AnnaBridge 145:64910690c574 443 * more efficient than clearing the lines in the cache line-by-line).
AnnaBridge 145:64910690c574 444 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 145:64910690c574 445 * check half the total amount of cache.
AnnaBridge 145:64910690c574 446 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 145:64910690c574 447 * modify bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 145:64910690c574 448 *
AnnaBridge 145:64910690c574 449 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 450 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 145:64910690c574 451 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 145:64910690c574 452 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 145:64910690c574 453 */
AnnaBridge 145:64910690c574 454 void LMEM_SystemCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 145:64910690c574 455
AnnaBridge 145:64910690c574 456 /*!
AnnaBridge 145:64910690c574 457 * @brief Demotes the cache mode of a region in the processor system bus cache.
AnnaBridge 145:64910690c574 458 * This function allows the user to demote the cache mode of a region within the device's
AnnaBridge 145:64910690c574 459 * memory map. Demoting the cache mode reduces the cache function applied to a memory
AnnaBridge 145:64910690c574 460 * region from write-back to write-through to non-cacheable. The function checks to see
AnnaBridge 145:64910690c574 461 * if the requested cache mode is higher than or equal to the current cache mode, and if
AnnaBridge 145:64910690c574 462 * so, returns an error. After a region is demoted, its cache mode can only be raised
AnnaBridge 145:64910690c574 463 * by a reset, which returns it to its default state which is the highest cache configure
AnnaBridge 145:64910690c574 464 * for each region.
AnnaBridge 145:64910690c574 465 * To maintain cache coherency, changes to the cache mode should be completed while the
AnnaBridge 145:64910690c574 466 * address space being changed is not being accessed or the cache is disabled. Before a
AnnaBridge 145:64910690c574 467 * cache mode change, this function completes a cache clear all command to push and invalidate any
AnnaBridge 145:64910690c574 468 * cache entries that may have changed.
AnnaBridge 145:64910690c574 469 *
AnnaBridge 145:64910690c574 470 * @param base LMEM peripheral base address.
AnnaBridge 145:64910690c574 471 * @param region The desired region to demote of type lmem_cache_region_t.
AnnaBridge 145:64910690c574 472 * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t.
AnnaBridge 145:64910690c574 473 * @return The execution result.
AnnaBridge 145:64910690c574 474 * kStatus_Success The cache demote operation is successful.
AnnaBridge 145:64910690c574 475 * kStatus_Fail The cache demote operation is failure.
AnnaBridge 145:64910690c574 476 */
AnnaBridge 145:64910690c574 477 status_t LMEM_SystemCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
AnnaBridge 145:64910690c574 478
AnnaBridge 145:64910690c574 479 /*@}*/
AnnaBridge 145:64910690c574 480 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
AnnaBridge 145:64910690c574 481
AnnaBridge 145:64910690c574 482 #if defined(__cplusplus)
AnnaBridge 145:64910690c574 483 }
AnnaBridge 145:64910690c574 484 #endif
AnnaBridge 145:64910690c574 485
AnnaBridge 145:64910690c574 486 /*! @}*/
AnnaBridge 145:64910690c574 487
AnnaBridge 145:64910690c574 488 #endif /* _FSL_LMEM_CACHE_H_*/