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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_SDT51822B/TOOLCHAIN_GCC_ARM/nrf_drv_config.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 146:22da6e220af6 1 /*
AnnaBridge 146:22da6e220af6 2 * Copyright (c) 2015 Nordic Semiconductor ASA
AnnaBridge 146:22da6e220af6 3 * All rights reserved.
AnnaBridge 146:22da6e220af6 4 *
AnnaBridge 146:22da6e220af6 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 146:22da6e220af6 6 * are permitted provided that the following conditions are met:
AnnaBridge 146:22da6e220af6 7 *
AnnaBridge 146:22da6e220af6 8 * 1. Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 146:22da6e220af6 9 * of conditions and the following disclaimer.
AnnaBridge 146:22da6e220af6 10 *
AnnaBridge 146:22da6e220af6 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
AnnaBridge 146:22da6e220af6 12 * integrated circuit in a product or a software update for such product, must reproduce
AnnaBridge 146:22da6e220af6 13 * the above copyright notice, this list of conditions and the following disclaimer in
AnnaBridge 146:22da6e220af6 14 * the documentation and/or other materials provided with the distribution.
AnnaBridge 146:22da6e220af6 15 *
AnnaBridge 146:22da6e220af6 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
AnnaBridge 146:22da6e220af6 17 * used to endorse or promote products derived from this software without specific prior
AnnaBridge 146:22da6e220af6 18 * written permission.
AnnaBridge 146:22da6e220af6 19 *
AnnaBridge 146:22da6e220af6 20 * 4. This software, with or without modification, must only be used with a
AnnaBridge 146:22da6e220af6 21 * Nordic Semiconductor ASA integrated circuit.
AnnaBridge 146:22da6e220af6 22 *
AnnaBridge 146:22da6e220af6 23 * 5. Any software provided in binary or object form under this license must not be reverse
AnnaBridge 146:22da6e220af6 24 * engineered, decompiled, modified and/or disassembled.
AnnaBridge 146:22da6e220af6 25 *
AnnaBridge 146:22da6e220af6 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 146:22da6e220af6 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 146:22da6e220af6 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 146:22da6e220af6 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 146:22da6e220af6 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 146:22da6e220af6 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 146:22da6e220af6 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 146:22da6e220af6 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 146:22da6e220af6 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 146:22da6e220af6 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 146:22da6e220af6 36 *
AnnaBridge 146:22da6e220af6 37 */
AnnaBridge 146:22da6e220af6 38
AnnaBridge 146:22da6e220af6 39
AnnaBridge 146:22da6e220af6 40 #ifndef NRF_DRV_CONFIG_H
AnnaBridge 146:22da6e220af6 41 #define NRF_DRV_CONFIG_H
AnnaBridge 146:22da6e220af6 42
AnnaBridge 146:22da6e220af6 43 /**
AnnaBridge 146:22da6e220af6 44 * Provide a non-zero value here in applications that need to use several
AnnaBridge 146:22da6e220af6 45 * peripherals with the same ID that are sharing certain resources
AnnaBridge 146:22da6e220af6 46 * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
AnnaBridge 146:22da6e220af6 47 * simultaneously. Therefore, this definition allows to initialize the driver
AnnaBridge 146:22da6e220af6 48 * for another peripheral from a given group only after the previously used one
AnnaBridge 146:22da6e220af6 49 * is uninitialized. Normally, this is not possible, because interrupt handlers
AnnaBridge 146:22da6e220af6 50 * are implemented in individual drivers.
AnnaBridge 146:22da6e220af6 51 * This functionality requires a more complicated interrupt handling and driver
AnnaBridge 146:22da6e220af6 52 * initialization, hence it is not always desirable to use it.
AnnaBridge 146:22da6e220af6 53 */
AnnaBridge 146:22da6e220af6 54 #define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
AnnaBridge 146:22da6e220af6 55
AnnaBridge 146:22da6e220af6 56 /* CLOCK */
AnnaBridge 146:22da6e220af6 57 #define CLOCK_ENABLED 1
AnnaBridge 146:22da6e220af6 58
AnnaBridge 146:22da6e220af6 59 #if (CLOCK_ENABLED == 1)
AnnaBridge 146:22da6e220af6 60 #define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
AnnaBridge 146:22da6e220af6 61 #define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
AnnaBridge 146:22da6e220af6 62 #define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 63 #endif
AnnaBridge 146:22da6e220af6 64
AnnaBridge 146:22da6e220af6 65 /* GPIOTE */
AnnaBridge 146:22da6e220af6 66 #define GPIOTE_ENABLED 1
AnnaBridge 146:22da6e220af6 67
AnnaBridge 146:22da6e220af6 68 #if (GPIOTE_ENABLED == 1)
AnnaBridge 146:22da6e220af6 69 #define GPIOTE_CONFIG_USE_SWI_EGU false
AnnaBridge 146:22da6e220af6 70 #define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 71 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8
AnnaBridge 146:22da6e220af6 72 #endif
AnnaBridge 146:22da6e220af6 73
AnnaBridge 146:22da6e220af6 74 /* TIMER */
AnnaBridge 146:22da6e220af6 75 #ifdef SOFTDEVICE_PRESENT
AnnaBridge 146:22da6e220af6 76 #define TIMER0_ENABLED 0
AnnaBridge 146:22da6e220af6 77 #else
AnnaBridge 146:22da6e220af6 78 #define TIMER0_ENABLED 1
AnnaBridge 146:22da6e220af6 79 #endif
AnnaBridge 146:22da6e220af6 80
AnnaBridge 146:22da6e220af6 81 #if (TIMER0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 82 #define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
AnnaBridge 146:22da6e220af6 83 #define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
AnnaBridge 146:22da6e220af6 84 #define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
AnnaBridge 146:22da6e220af6 85 #define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 86
AnnaBridge 146:22da6e220af6 87 #define TIMER0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 88 #endif
AnnaBridge 146:22da6e220af6 89
AnnaBridge 146:22da6e220af6 90 #define TIMER1_ENABLED 1
AnnaBridge 146:22da6e220af6 91
AnnaBridge 146:22da6e220af6 92 #if (TIMER1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 93 #define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
AnnaBridge 146:22da6e220af6 94 #define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
AnnaBridge 146:22da6e220af6 95 #define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
AnnaBridge 146:22da6e220af6 96 #define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 97
AnnaBridge 146:22da6e220af6 98 #define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
AnnaBridge 146:22da6e220af6 99 #endif
AnnaBridge 146:22da6e220af6 100
AnnaBridge 146:22da6e220af6 101 #define TIMER2_ENABLED 1
AnnaBridge 146:22da6e220af6 102
AnnaBridge 146:22da6e220af6 103 #if (TIMER2_ENABLED == 1)
AnnaBridge 146:22da6e220af6 104 #define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
AnnaBridge 146:22da6e220af6 105 #define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
AnnaBridge 146:22da6e220af6 106 #define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
AnnaBridge 146:22da6e220af6 107 #define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 108
AnnaBridge 146:22da6e220af6 109 #define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
AnnaBridge 146:22da6e220af6 110 #endif
AnnaBridge 146:22da6e220af6 111
AnnaBridge 146:22da6e220af6 112 #define TIMER3_ENABLED 0
AnnaBridge 146:22da6e220af6 113
AnnaBridge 146:22da6e220af6 114 #if (TIMER3_ENABLED == 1)
AnnaBridge 146:22da6e220af6 115 #define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
AnnaBridge 146:22da6e220af6 116 #define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
AnnaBridge 146:22da6e220af6 117 #define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
AnnaBridge 146:22da6e220af6 118 #define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 119
AnnaBridge 146:22da6e220af6 120 #define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
AnnaBridge 146:22da6e220af6 121 #endif
AnnaBridge 146:22da6e220af6 122
AnnaBridge 146:22da6e220af6 123 #define TIMER4_ENABLED 0
AnnaBridge 146:22da6e220af6 124
AnnaBridge 146:22da6e220af6 125 #if (TIMER4_ENABLED == 1)
AnnaBridge 146:22da6e220af6 126 #define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
AnnaBridge 146:22da6e220af6 127 #define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
AnnaBridge 146:22da6e220af6 128 #define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
AnnaBridge 146:22da6e220af6 129 #define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 130
AnnaBridge 146:22da6e220af6 131 #define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
AnnaBridge 146:22da6e220af6 132 #endif
AnnaBridge 146:22da6e220af6 133
AnnaBridge 146:22da6e220af6 134
AnnaBridge 146:22da6e220af6 135 #define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
AnnaBridge 146:22da6e220af6 136
AnnaBridge 146:22da6e220af6 137 /* RTC */
AnnaBridge 146:22da6e220af6 138 #define RTC0_ENABLED 0
AnnaBridge 146:22da6e220af6 139
AnnaBridge 146:22da6e220af6 140 #if (RTC0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 141 #define RTC0_CONFIG_FREQUENCY 32678
AnnaBridge 146:22da6e220af6 142 #define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 143 #define RTC0_CONFIG_RELIABLE false
AnnaBridge 146:22da6e220af6 144
AnnaBridge 146:22da6e220af6 145 #define RTC0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 146 #endif
AnnaBridge 146:22da6e220af6 147
AnnaBridge 146:22da6e220af6 148 #define RTC1_ENABLED 0
AnnaBridge 146:22da6e220af6 149
AnnaBridge 146:22da6e220af6 150 #if (RTC1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 151 #define RTC1_CONFIG_FREQUENCY 32768
AnnaBridge 146:22da6e220af6 152 #define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 153 #define RTC1_CONFIG_RELIABLE false
AnnaBridge 146:22da6e220af6 154
AnnaBridge 146:22da6e220af6 155 #define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
AnnaBridge 146:22da6e220af6 156 #endif
AnnaBridge 146:22da6e220af6 157
AnnaBridge 146:22da6e220af6 158 #define RTC2_ENABLED 0
AnnaBridge 146:22da6e220af6 159
AnnaBridge 146:22da6e220af6 160 #if (RTC2_ENABLED == 1)
AnnaBridge 146:22da6e220af6 161 #define RTC2_CONFIG_FREQUENCY 32768
AnnaBridge 146:22da6e220af6 162 #define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 163 #define RTC2_CONFIG_RELIABLE false
AnnaBridge 146:22da6e220af6 164
AnnaBridge 146:22da6e220af6 165 #define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
AnnaBridge 146:22da6e220af6 166 #endif
AnnaBridge 146:22da6e220af6 167
AnnaBridge 146:22da6e220af6 168
AnnaBridge 146:22da6e220af6 169 #define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
AnnaBridge 146:22da6e220af6 170
AnnaBridge 146:22da6e220af6 171 #define NRF_MAXIMUM_LATENCY_US 2000
AnnaBridge 146:22da6e220af6 172
AnnaBridge 146:22da6e220af6 173 /* RNG */
AnnaBridge 146:22da6e220af6 174 #define RNG_ENABLED 0
AnnaBridge 146:22da6e220af6 175
AnnaBridge 146:22da6e220af6 176 #if (RNG_ENABLED == 1)
AnnaBridge 146:22da6e220af6 177 #define RNG_CONFIG_ERROR_CORRECTION true
AnnaBridge 146:22da6e220af6 178 #define RNG_CONFIG_POOL_SIZE 8
AnnaBridge 146:22da6e220af6 179 #define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 180 #endif
AnnaBridge 146:22da6e220af6 181
AnnaBridge 146:22da6e220af6 182 /* PWM */
AnnaBridge 146:22da6e220af6 183
AnnaBridge 146:22da6e220af6 184 #define PWM0_ENABLED 0
AnnaBridge 146:22da6e220af6 185
AnnaBridge 146:22da6e220af6 186 #if (PWM0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 187 #define PWM0_CONFIG_OUT0_PIN 2
AnnaBridge 146:22da6e220af6 188 #define PWM0_CONFIG_OUT1_PIN 3
AnnaBridge 146:22da6e220af6 189 #define PWM0_CONFIG_OUT2_PIN 4
AnnaBridge 146:22da6e220af6 190 #define PWM0_CONFIG_OUT3_PIN 5
AnnaBridge 146:22da6e220af6 191 #define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 192 #define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
AnnaBridge 146:22da6e220af6 193 #define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
AnnaBridge 146:22da6e220af6 194 #define PWM0_CONFIG_TOP_VALUE 1000
AnnaBridge 146:22da6e220af6 195 #define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
AnnaBridge 146:22da6e220af6 196 #define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
AnnaBridge 146:22da6e220af6 197
AnnaBridge 146:22da6e220af6 198 #define PWM0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 199 #endif
AnnaBridge 146:22da6e220af6 200
AnnaBridge 146:22da6e220af6 201 #define PWM1_ENABLED 0
AnnaBridge 146:22da6e220af6 202
AnnaBridge 146:22da6e220af6 203 #if (PWM1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 204 #define PWM1_CONFIG_OUT0_PIN 2
AnnaBridge 146:22da6e220af6 205 #define PWM1_CONFIG_OUT1_PIN 3
AnnaBridge 146:22da6e220af6 206 #define PWM1_CONFIG_OUT2_PIN 4
AnnaBridge 146:22da6e220af6 207 #define PWM1_CONFIG_OUT3_PIN 5
AnnaBridge 146:22da6e220af6 208 #define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 209 #define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
AnnaBridge 146:22da6e220af6 210 #define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
AnnaBridge 146:22da6e220af6 211 #define PWM1_CONFIG_TOP_VALUE 1000
AnnaBridge 146:22da6e220af6 212 #define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
AnnaBridge 146:22da6e220af6 213 #define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
AnnaBridge 146:22da6e220af6 214
AnnaBridge 146:22da6e220af6 215 #define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
AnnaBridge 146:22da6e220af6 216 #endif
AnnaBridge 146:22da6e220af6 217
AnnaBridge 146:22da6e220af6 218 #define PWM2_ENABLED 0
AnnaBridge 146:22da6e220af6 219
AnnaBridge 146:22da6e220af6 220 #if (PWM2_ENABLED == 1)
AnnaBridge 146:22da6e220af6 221 #define PWM2_CONFIG_OUT0_PIN 2
AnnaBridge 146:22da6e220af6 222 #define PWM2_CONFIG_OUT1_PIN 3
AnnaBridge 146:22da6e220af6 223 #define PWM2_CONFIG_OUT2_PIN 4
AnnaBridge 146:22da6e220af6 224 #define PWM2_CONFIG_OUT3_PIN 5
AnnaBridge 146:22da6e220af6 225 #define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 226 #define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
AnnaBridge 146:22da6e220af6 227 #define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
AnnaBridge 146:22da6e220af6 228 #define PWM2_CONFIG_TOP_VALUE 1000
AnnaBridge 146:22da6e220af6 229 #define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
AnnaBridge 146:22da6e220af6 230 #define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
AnnaBridge 146:22da6e220af6 231
AnnaBridge 146:22da6e220af6 232 #define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
AnnaBridge 146:22da6e220af6 233 #endif
AnnaBridge 146:22da6e220af6 234
AnnaBridge 146:22da6e220af6 235 #define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
AnnaBridge 146:22da6e220af6 236
AnnaBridge 146:22da6e220af6 237 /* SPI */
AnnaBridge 146:22da6e220af6 238 #define SPI0_ENABLED 0
AnnaBridge 146:22da6e220af6 239
AnnaBridge 146:22da6e220af6 240 #if (SPI0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 241 #define SPI0_USE_EASY_DMA 0
AnnaBridge 146:22da6e220af6 242
AnnaBridge 146:22da6e220af6 243 #define SPI0_CONFIG_SCK_PIN 2
AnnaBridge 146:22da6e220af6 244 #define SPI0_CONFIG_MOSI_PIN 3
AnnaBridge 146:22da6e220af6 245 #define SPI0_CONFIG_MISO_PIN 4
AnnaBridge 146:22da6e220af6 246 #define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 247
AnnaBridge 146:22da6e220af6 248 #define SPI0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 249 #endif
AnnaBridge 146:22da6e220af6 250
AnnaBridge 146:22da6e220af6 251 #define SPI1_ENABLED 1
AnnaBridge 146:22da6e220af6 252
AnnaBridge 146:22da6e220af6 253 #if (SPI1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 254 #define SPI1_USE_EASY_DMA 0
AnnaBridge 146:22da6e220af6 255
AnnaBridge 146:22da6e220af6 256 #define SPI1_CONFIG_SCK_PIN 2
AnnaBridge 146:22da6e220af6 257 #define SPI1_CONFIG_MOSI_PIN 3
AnnaBridge 146:22da6e220af6 258 #define SPI1_CONFIG_MISO_PIN 4
AnnaBridge 146:22da6e220af6 259 #define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 260
AnnaBridge 146:22da6e220af6 261 #define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
AnnaBridge 146:22da6e220af6 262 #endif
AnnaBridge 146:22da6e220af6 263
AnnaBridge 146:22da6e220af6 264 #define SPI2_ENABLED 0
AnnaBridge 146:22da6e220af6 265
AnnaBridge 146:22da6e220af6 266 #if (SPI2_ENABLED == 1)
AnnaBridge 146:22da6e220af6 267 #define SPI2_USE_EASY_DMA 0
AnnaBridge 146:22da6e220af6 268
AnnaBridge 146:22da6e220af6 269 #define SPI2_CONFIG_SCK_PIN 2
AnnaBridge 146:22da6e220af6 270 #define SPI2_CONFIG_MOSI_PIN 3
AnnaBridge 146:22da6e220af6 271 #define SPI2_CONFIG_MISO_PIN 4
AnnaBridge 146:22da6e220af6 272 #define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 273
AnnaBridge 146:22da6e220af6 274 #define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
AnnaBridge 146:22da6e220af6 275 #endif
AnnaBridge 146:22da6e220af6 276
AnnaBridge 146:22da6e220af6 277 #define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
AnnaBridge 146:22da6e220af6 278
AnnaBridge 146:22da6e220af6 279 /* SPIS */
AnnaBridge 146:22da6e220af6 280 #define SPIS0_ENABLED 0
AnnaBridge 146:22da6e220af6 281
AnnaBridge 146:22da6e220af6 282 #if (SPIS0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 283 #define SPIS0_CONFIG_SCK_PIN 2
AnnaBridge 146:22da6e220af6 284 #define SPIS0_CONFIG_MOSI_PIN 3
AnnaBridge 146:22da6e220af6 285 #define SPIS0_CONFIG_MISO_PIN 4
AnnaBridge 146:22da6e220af6 286 #define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 287
AnnaBridge 146:22da6e220af6 288 #define SPIS0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 289 #endif
AnnaBridge 146:22da6e220af6 290
AnnaBridge 146:22da6e220af6 291 #define SPIS1_ENABLED 1
AnnaBridge 146:22da6e220af6 292
AnnaBridge 146:22da6e220af6 293 #if (SPIS1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 294 #define SPIS1_CONFIG_SCK_PIN 2
AnnaBridge 146:22da6e220af6 295 #define SPIS1_CONFIG_MOSI_PIN 3
AnnaBridge 146:22da6e220af6 296 #define SPIS1_CONFIG_MISO_PIN 4
AnnaBridge 146:22da6e220af6 297 #define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 298
AnnaBridge 146:22da6e220af6 299 #define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
AnnaBridge 146:22da6e220af6 300 #endif
AnnaBridge 146:22da6e220af6 301
AnnaBridge 146:22da6e220af6 302 #define SPIS2_ENABLED 0
AnnaBridge 146:22da6e220af6 303
AnnaBridge 146:22da6e220af6 304 #if (SPIS2_ENABLED == 1)
AnnaBridge 146:22da6e220af6 305 #define SPIS2_CONFIG_SCK_PIN 2
AnnaBridge 146:22da6e220af6 306 #define SPIS2_CONFIG_MOSI_PIN 3
AnnaBridge 146:22da6e220af6 307 #define SPIS2_CONFIG_MISO_PIN 4
AnnaBridge 146:22da6e220af6 308 #define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 309
AnnaBridge 146:22da6e220af6 310 #define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
AnnaBridge 146:22da6e220af6 311 #endif
AnnaBridge 146:22da6e220af6 312
AnnaBridge 146:22da6e220af6 313 #define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
AnnaBridge 146:22da6e220af6 314
AnnaBridge 146:22da6e220af6 315 /* UART */
AnnaBridge 146:22da6e220af6 316 #define UART0_ENABLED 1
AnnaBridge 146:22da6e220af6 317
AnnaBridge 146:22da6e220af6 318 #if (UART0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 319 #define UART0_CONFIG_HWFC NRF_UART_HWFC_ENABLED
AnnaBridge 146:22da6e220af6 320 #define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
AnnaBridge 146:22da6e220af6 321 #define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_9600
AnnaBridge 146:22da6e220af6 322 #define UART0_CONFIG_PSEL_TXD 9
AnnaBridge 146:22da6e220af6 323 #define UART0_CONFIG_PSEL_RXD 11
AnnaBridge 146:22da6e220af6 324 #define UART0_CONFIG_PSEL_CTS 10
AnnaBridge 146:22da6e220af6 325 #define UART0_CONFIG_PSEL_RTS 8
AnnaBridge 146:22da6e220af6 326 #define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
AnnaBridge 146:22da6e220af6 327 #ifdef NRF52
AnnaBridge 146:22da6e220af6 328 #define UART0_CONFIG_USE_EASY_DMA false
AnnaBridge 146:22da6e220af6 329 //Compile time flag
AnnaBridge 146:22da6e220af6 330 #define UART_EASY_DMA_SUPPORT 1
AnnaBridge 146:22da6e220af6 331 #define UART_LEGACY_SUPPORT 1
AnnaBridge 146:22da6e220af6 332 #endif //NRF52
AnnaBridge 146:22da6e220af6 333 #endif
AnnaBridge 146:22da6e220af6 334
AnnaBridge 146:22da6e220af6 335 #define TWI0_ENABLED 1
AnnaBridge 146:22da6e220af6 336
AnnaBridge 146:22da6e220af6 337 #if (TWI0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 338 #define TWI0_USE_EASY_DMA 0
AnnaBridge 146:22da6e220af6 339
AnnaBridge 146:22da6e220af6 340 #define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
AnnaBridge 146:22da6e220af6 341 #define TWI0_CONFIG_SCL 0
AnnaBridge 146:22da6e220af6 342 #define TWI0_CONFIG_SDA 1
AnnaBridge 146:22da6e220af6 343 #define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 344
AnnaBridge 146:22da6e220af6 345 #define TWI0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 346 #endif
AnnaBridge 146:22da6e220af6 347
AnnaBridge 146:22da6e220af6 348 #define TWI1_ENABLED 1
AnnaBridge 146:22da6e220af6 349
AnnaBridge 146:22da6e220af6 350 #if (TWI1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 351 #define TWI1_USE_EASY_DMA 0
AnnaBridge 146:22da6e220af6 352
AnnaBridge 146:22da6e220af6 353 #define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
AnnaBridge 146:22da6e220af6 354 #define TWI1_CONFIG_SCL 0
AnnaBridge 146:22da6e220af6 355 #define TWI1_CONFIG_SDA 1
AnnaBridge 146:22da6e220af6 356 #define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 357
AnnaBridge 146:22da6e220af6 358 #define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
AnnaBridge 146:22da6e220af6 359 #endif
AnnaBridge 146:22da6e220af6 360
AnnaBridge 146:22da6e220af6 361 #define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
AnnaBridge 146:22da6e220af6 362
AnnaBridge 146:22da6e220af6 363 /* TWIS */
AnnaBridge 146:22da6e220af6 364 #define TWIS0_ENABLED 0
AnnaBridge 146:22da6e220af6 365
AnnaBridge 146:22da6e220af6 366 #if (TWIS0_ENABLED == 1)
AnnaBridge 146:22da6e220af6 367 #define TWIS0_CONFIG_ADDR0 0
AnnaBridge 146:22da6e220af6 368 #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
AnnaBridge 146:22da6e220af6 369 #define TWIS0_CONFIG_SCL 0
AnnaBridge 146:22da6e220af6 370 #define TWIS0_CONFIG_SDA 1
AnnaBridge 146:22da6e220af6 371 #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 372
AnnaBridge 146:22da6e220af6 373 #define TWIS0_INSTANCE_INDEX 0
AnnaBridge 146:22da6e220af6 374 #endif
AnnaBridge 146:22da6e220af6 375
AnnaBridge 146:22da6e220af6 376 #define TWIS1_ENABLED 0
AnnaBridge 146:22da6e220af6 377
AnnaBridge 146:22da6e220af6 378 #if (TWIS1_ENABLED == 1)
AnnaBridge 146:22da6e220af6 379 #define TWIS1_CONFIG_ADDR0 0
AnnaBridge 146:22da6e220af6 380 #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
AnnaBridge 146:22da6e220af6 381 #define TWIS1_CONFIG_SCL 0
AnnaBridge 146:22da6e220af6 382 #define TWIS1_CONFIG_SDA 1
AnnaBridge 146:22da6e220af6 383 #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 384
AnnaBridge 146:22da6e220af6 385 #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
AnnaBridge 146:22da6e220af6 386 #endif
AnnaBridge 146:22da6e220af6 387
AnnaBridge 146:22da6e220af6 388 #define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
AnnaBridge 146:22da6e220af6 389 /* For more documentation see nrf_drv_twis.h file */
AnnaBridge 146:22da6e220af6 390 #define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
AnnaBridge 146:22da6e220af6 391 /* For more documentation see nrf_drv_twis.h file */
AnnaBridge 146:22da6e220af6 392 #define TWIS_NO_SYNC_MODE 0
AnnaBridge 146:22da6e220af6 393
AnnaBridge 146:22da6e220af6 394 /* QDEC */
AnnaBridge 146:22da6e220af6 395 #define QDEC_ENABLED 0
AnnaBridge 146:22da6e220af6 396
AnnaBridge 146:22da6e220af6 397 #if (QDEC_ENABLED == 1)
AnnaBridge 146:22da6e220af6 398 #define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
AnnaBridge 146:22da6e220af6 399 #define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
AnnaBridge 146:22da6e220af6 400 #define QDEC_CONFIG_PIO_A 1
AnnaBridge 146:22da6e220af6 401 #define QDEC_CONFIG_PIO_B 2
AnnaBridge 146:22da6e220af6 402 #define QDEC_CONFIG_PIO_LED 3
AnnaBridge 146:22da6e220af6 403 #define QDEC_CONFIG_LEDPRE 511
AnnaBridge 146:22da6e220af6 404 #define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
AnnaBridge 146:22da6e220af6 405 #define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 406 #define QDEC_CONFIG_DBFEN false
AnnaBridge 146:22da6e220af6 407 #define QDEC_CONFIG_SAMPLE_INTEN false
AnnaBridge 146:22da6e220af6 408 #endif
AnnaBridge 146:22da6e220af6 409
AnnaBridge 146:22da6e220af6 410 /* ADC */
AnnaBridge 146:22da6e220af6 411 #define ADC_ENABLED 1
AnnaBridge 146:22da6e220af6 412
AnnaBridge 146:22da6e220af6 413 #if (ADC_ENABLED == 1)
AnnaBridge 146:22da6e220af6 414 #define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 415 #endif
AnnaBridge 146:22da6e220af6 416
AnnaBridge 146:22da6e220af6 417
AnnaBridge 146:22da6e220af6 418 /* SAADC */
AnnaBridge 146:22da6e220af6 419 #define SAADC_ENABLED 0
AnnaBridge 146:22da6e220af6 420
AnnaBridge 146:22da6e220af6 421 #if (SAADC_ENABLED == 1)
AnnaBridge 146:22da6e220af6 422 #define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
AnnaBridge 146:22da6e220af6 423 #define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
AnnaBridge 146:22da6e220af6 424 #define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 425 #endif
AnnaBridge 146:22da6e220af6 426
AnnaBridge 146:22da6e220af6 427 /* PDM */
AnnaBridge 146:22da6e220af6 428 #define PDM_ENABLED 0
AnnaBridge 146:22da6e220af6 429
AnnaBridge 146:22da6e220af6 430 #if (PDM_ENABLED == 1)
AnnaBridge 146:22da6e220af6 431 #define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
AnnaBridge 146:22da6e220af6 432 #define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
AnnaBridge 146:22da6e220af6 433 #define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
AnnaBridge 146:22da6e220af6 434 #define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 435 #endif
AnnaBridge 146:22da6e220af6 436
AnnaBridge 146:22da6e220af6 437 /* COMP */
AnnaBridge 146:22da6e220af6 438 #define COMP_ENABLED 0
AnnaBridge 146:22da6e220af6 439
AnnaBridge 146:22da6e220af6 440 #if (COMP_ENABLED == 1)
AnnaBridge 146:22da6e220af6 441 #define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
AnnaBridge 146:22da6e220af6 442 #define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
AnnaBridge 146:22da6e220af6 443 #define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
AnnaBridge 146:22da6e220af6 444 #define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
AnnaBridge 146:22da6e220af6 445 #define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
AnnaBridge 146:22da6e220af6 446 #define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 447 #define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
AnnaBridge 146:22da6e220af6 448 #endif
AnnaBridge 146:22da6e220af6 449
AnnaBridge 146:22da6e220af6 450 /* LPCOMP */
AnnaBridge 146:22da6e220af6 451 #define LPCOMP_ENABLED 0
AnnaBridge 146:22da6e220af6 452
AnnaBridge 146:22da6e220af6 453 #if (LPCOMP_ENABLED == 1)
AnnaBridge 146:22da6e220af6 454 #define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
AnnaBridge 146:22da6e220af6 455 #define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
AnnaBridge 146:22da6e220af6 456 #define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
AnnaBridge 146:22da6e220af6 457 #define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
AnnaBridge 146:22da6e220af6 458 #endif
AnnaBridge 146:22da6e220af6 459
AnnaBridge 146:22da6e220af6 460 /* WDT */
AnnaBridge 146:22da6e220af6 461 #define WDT_ENABLED 0
AnnaBridge 146:22da6e220af6 462
AnnaBridge 146:22da6e220af6 463 #if (WDT_ENABLED == 1)
AnnaBridge 146:22da6e220af6 464 #define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
AnnaBridge 146:22da6e220af6 465 #define WDT_CONFIG_RELOAD_VALUE 2000
AnnaBridge 146:22da6e220af6 466 #define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
AnnaBridge 146:22da6e220af6 467 #endif
AnnaBridge 146:22da6e220af6 468
AnnaBridge 146:22da6e220af6 469 /* SWI EGU */
AnnaBridge 146:22da6e220af6 470 #ifdef NRF52
AnnaBridge 146:22da6e220af6 471 #define EGU_ENABLED 0
AnnaBridge 146:22da6e220af6 472 #endif
AnnaBridge 146:22da6e220af6 473
AnnaBridge 146:22da6e220af6 474 /* I2S */
AnnaBridge 146:22da6e220af6 475 #define I2S_ENABLED 0
AnnaBridge 146:22da6e220af6 476
AnnaBridge 146:22da6e220af6 477 #if (I2S_ENABLED == 1)
AnnaBridge 146:22da6e220af6 478 #define I2S_CONFIG_SCK_PIN 22
AnnaBridge 146:22da6e220af6 479 #define I2S_CONFIG_LRCK_PIN 23
AnnaBridge 146:22da6e220af6 480 #define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
AnnaBridge 146:22da6e220af6 481 #define I2S_CONFIG_SDOUT_PIN 24
AnnaBridge 146:22da6e220af6 482 #define I2S_CONFIG_SDIN_PIN 25
AnnaBridge 146:22da6e220af6 483 #define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
AnnaBridge 146:22da6e220af6 484 #define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
AnnaBridge 146:22da6e220af6 485 #define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
AnnaBridge 146:22da6e220af6 486 #define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
AnnaBridge 146:22da6e220af6 487 #define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
AnnaBridge 146:22da6e220af6 488 #define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
AnnaBridge 146:22da6e220af6 489 #define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
AnnaBridge 146:22da6e220af6 490 #define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
AnnaBridge 146:22da6e220af6 491 #endif
AnnaBridge 146:22da6e220af6 492
AnnaBridge 146:22da6e220af6 493 #include "nrf_drv_config_validation.h"
AnnaBridge 146:22da6e220af6 494
AnnaBridge 146:22da6e220af6 495 #endif // NRF_DRV_CONFIG_H