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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_ll_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_ll_spi.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of SPI LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_LL_SPI_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_LL_SPI_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx.h"
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	172:65be27845400	48	* @{
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	/** @defgroup SPI_LL SPI
AnnaBridge	172:65be27845400	54	* @{
AnnaBridge	172:65be27845400	55	*/
AnnaBridge	172:65be27845400	56
AnnaBridge	172:65be27845400	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	60
AnnaBridge	172:65be27845400	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	62	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	172:65be27845400	64	* @{
AnnaBridge	172:65be27845400	65	*/
AnnaBridge	172:65be27845400	66
AnnaBridge	172:65be27845400	67	/**
AnnaBridge	172:65be27845400	68	* @brief SPI Init structures definition
AnnaBridge	172:65be27845400	69	*/
AnnaBridge	172:65be27845400	70	typedef struct
AnnaBridge	172:65be27845400	71	{
AnnaBridge	172:65be27845400	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	172:65be27845400	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	172:65be27845400	74
AnnaBridge	172:65be27845400	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	172:65be27845400	76
AnnaBridge	172:65be27845400	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	172:65be27845400	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	172:65be27845400	81
AnnaBridge	172:65be27845400	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	172:65be27845400	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	172:65be27845400	84
AnnaBridge	172:65be27845400	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	172:65be27845400	86
AnnaBridge	172:65be27845400	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	172:65be27845400	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	172:65be27845400	89
AnnaBridge	172:65be27845400	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	172:65be27845400	91
AnnaBridge	172:65be27845400	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	172:65be27845400	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	172:65be27845400	94
AnnaBridge	172:65be27845400	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	172:65be27845400	96
AnnaBridge	172:65be27845400	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	172:65be27845400	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	172:65be27845400	99
AnnaBridge	172:65be27845400	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	172:65be27845400	101
AnnaBridge	172:65be27845400	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	172:65be27845400	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	172:65be27845400	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	172:65be27845400	105
AnnaBridge	172:65be27845400	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	172:65be27845400	107
AnnaBridge	172:65be27845400	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	172:65be27845400	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	172:65be27845400	110
AnnaBridge	172:65be27845400	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	172:65be27845400	112
AnnaBridge	172:65be27845400	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	172:65be27845400	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	172:65be27845400	117
AnnaBridge	172:65be27845400	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	172:65be27845400	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	172:65be27845400	120
AnnaBridge	172:65be27845400	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	} LL_SPI_InitTypeDef;
AnnaBridge	172:65be27845400	124
AnnaBridge	172:65be27845400	125	/**
AnnaBridge	172:65be27845400	126	* @}
AnnaBridge	172:65be27845400	127	*/
AnnaBridge	172:65be27845400	128	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	129
AnnaBridge	172:65be27845400	130	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	172:65be27845400	132	* @{
AnnaBridge	172:65be27845400	133	*/
AnnaBridge	172:65be27845400	134
AnnaBridge	172:65be27845400	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	172:65be27845400	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	172:65be27845400	137	* @{
AnnaBridge	172:65be27845400	138	*/
AnnaBridge	172:65be27845400	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	172:65be27845400	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	172:65be27845400	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	172:65be27845400	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	172:65be27845400	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	172:65be27845400	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	172:65be27845400	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	172:65be27845400	146	/**
AnnaBridge	172:65be27845400	147	* @}
AnnaBridge	172:65be27845400	148	*/
AnnaBridge	172:65be27845400	149
AnnaBridge	172:65be27845400	150	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	172:65be27845400	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	172:65be27845400	152	* @{
AnnaBridge	172:65be27845400	153	*/
AnnaBridge	172:65be27845400	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	172:65be27845400	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	172:65be27845400	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	172:65be27845400	157	/**
AnnaBridge	172:65be27845400	158	* @}
AnnaBridge	172:65be27845400	159	*/
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	172:65be27845400	162	* @{
AnnaBridge	172:65be27845400	163	*/
AnnaBridge	172:65be27845400	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	172:65be27845400	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	172:65be27845400	166	/**
AnnaBridge	172:65be27845400	167	* @}
AnnaBridge	172:65be27845400	168	*/
AnnaBridge	172:65be27845400	169
AnnaBridge	172:65be27845400	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	172:65be27845400	171	* @{
AnnaBridge	172:65be27845400	172	*/
AnnaBridge	172:65be27845400	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	172:65be27845400	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	172:65be27845400	175	/**
AnnaBridge	172:65be27845400	176	* @}
AnnaBridge	172:65be27845400	177	*/
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	172:65be27845400	180	* @{
AnnaBridge	172:65be27845400	181	*/
AnnaBridge	172:65be27845400	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	172:65be27845400	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	172:65be27845400	184	/**
AnnaBridge	172:65be27845400	185	* @}
AnnaBridge	172:65be27845400	186	*/
AnnaBridge	172:65be27845400	187
AnnaBridge	172:65be27845400	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	172:65be27845400	189	* @{
AnnaBridge	172:65be27845400	190	*/
AnnaBridge	172:65be27845400	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	172:65be27845400	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	172:65be27845400	193	/**
AnnaBridge	172:65be27845400	194	* @}
AnnaBridge	172:65be27845400	195	*/
AnnaBridge	172:65be27845400	196
AnnaBridge	172:65be27845400	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	172:65be27845400	198	* @{
AnnaBridge	172:65be27845400	199	*/
AnnaBridge	172:65be27845400	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	172:65be27845400	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	172:65be27845400	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	172:65be27845400	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	172:65be27845400	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	172:65be27845400	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	172:65be27845400	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	172:65be27845400	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	172:65be27845400	208	/**
AnnaBridge	172:65be27845400	209	* @}
AnnaBridge	172:65be27845400	210	*/
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	172:65be27845400	213	* @{
AnnaBridge	172:65be27845400	214	*/
AnnaBridge	172:65be27845400	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	172:65be27845400	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	172:65be27845400	217	/**
AnnaBridge	172:65be27845400	218	* @}
AnnaBridge	172:65be27845400	219	*/
AnnaBridge	172:65be27845400	220
AnnaBridge	172:65be27845400	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	172:65be27845400	222	* @{
AnnaBridge	172:65be27845400	223	*/
AnnaBridge	172:65be27845400	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	172:65be27845400	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	172:65be27845400	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	172:65be27845400	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	172:65be27845400	228	/**
AnnaBridge	172:65be27845400	229	* @}
AnnaBridge	172:65be27845400	230	*/
AnnaBridge	172:65be27845400	231
AnnaBridge	172:65be27845400	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	172:65be27845400	233	* @{
AnnaBridge	172:65be27845400	234	*/
AnnaBridge	172:65be27845400	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	172:65be27845400	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	172:65be27845400	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	172:65be27845400	238	/**
AnnaBridge	172:65be27845400	239	* @}
AnnaBridge	172:65be27845400	240	*/
AnnaBridge	172:65be27845400	241
AnnaBridge	172:65be27845400	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	172:65be27845400	243	* @{
AnnaBridge	172:65be27845400	244	*/
AnnaBridge	172:65be27845400	245	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
AnnaBridge	172:65be27845400	246	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
AnnaBridge	172:65be27845400	247	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
AnnaBridge	172:65be27845400	248	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
AnnaBridge	172:65be27845400	249	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
AnnaBridge	172:65be27845400	250	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
AnnaBridge	172:65be27845400	251	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
AnnaBridge	172:65be27845400	252	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
AnnaBridge	172:65be27845400	253	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
AnnaBridge	172:65be27845400	254	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
AnnaBridge	172:65be27845400	255	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
AnnaBridge	172:65be27845400	256	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
AnnaBridge	172:65be27845400	257	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	172:65be27845400	258	/**
AnnaBridge	172:65be27845400	259	* @}
AnnaBridge	172:65be27845400	260	*/
AnnaBridge	172:65be27845400	261	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	262
AnnaBridge	172:65be27845400	263	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	172:65be27845400	264	* @{
AnnaBridge	172:65be27845400	265	*/
AnnaBridge	172:65be27845400	266	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	172:65be27845400	267	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	172:65be27845400	268	/**
AnnaBridge	172:65be27845400	269	* @}
AnnaBridge	172:65be27845400	270	*/
AnnaBridge	172:65be27845400	271	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	272
AnnaBridge	172:65be27845400	273	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
AnnaBridge	172:65be27845400	274	* @{
AnnaBridge	172:65be27845400	275	*/
AnnaBridge	172:65be27845400	276	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
AnnaBridge	172:65be27845400	277	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
AnnaBridge	172:65be27845400	278	/**
AnnaBridge	172:65be27845400	279	* @}
AnnaBridge	172:65be27845400	280	*/
AnnaBridge	172:65be27845400	281
AnnaBridge	172:65be27845400	282	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
AnnaBridge	172:65be27845400	283	* @{
AnnaBridge	172:65be27845400	284	*/
AnnaBridge	172:65be27845400	285	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
AnnaBridge	172:65be27845400	286	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
AnnaBridge	172:65be27845400	287	/**
AnnaBridge	172:65be27845400	288	* @}
AnnaBridge	172:65be27845400	289	*/
AnnaBridge	172:65be27845400	290
AnnaBridge	172:65be27845400	291	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
AnnaBridge	172:65be27845400	292	* @{
AnnaBridge	172:65be27845400	293	*/
AnnaBridge	172:65be27845400	294	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
AnnaBridge	172:65be27845400	295	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
AnnaBridge	172:65be27845400	296	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
AnnaBridge	172:65be27845400	297	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
AnnaBridge	172:65be27845400	298	/**
AnnaBridge	172:65be27845400	299	* @}
AnnaBridge	172:65be27845400	300	*/
AnnaBridge	172:65be27845400	301
AnnaBridge	172:65be27845400	302	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
AnnaBridge	172:65be27845400	303	* @{
AnnaBridge	172:65be27845400	304	*/
AnnaBridge	172:65be27845400	305	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
AnnaBridge	172:65be27845400	306	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
AnnaBridge	172:65be27845400	307	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
AnnaBridge	172:65be27845400	308	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
AnnaBridge	172:65be27845400	309	/**
AnnaBridge	172:65be27845400	310	* @}
AnnaBridge	172:65be27845400	311	*/
AnnaBridge	172:65be27845400	312
AnnaBridge	172:65be27845400	313	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
AnnaBridge	172:65be27845400	314	* @{
AnnaBridge	172:65be27845400	315	*/
AnnaBridge	172:65be27845400	316	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
AnnaBridge	172:65be27845400	317	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
AnnaBridge	172:65be27845400	318
AnnaBridge	172:65be27845400	319	/**
AnnaBridge	172:65be27845400	320	* @}
AnnaBridge	172:65be27845400	321	*/
AnnaBridge	172:65be27845400	322
AnnaBridge	172:65be27845400	323	/**
AnnaBridge	172:65be27845400	324	* @}
AnnaBridge	172:65be27845400	325	*/
AnnaBridge	172:65be27845400	326
AnnaBridge	172:65be27845400	327	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	328	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	172:65be27845400	329	* @{
AnnaBridge	172:65be27845400	330	*/
AnnaBridge	172:65be27845400	331
AnnaBridge	172:65be27845400	332	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	172:65be27845400	333	* @{
AnnaBridge	172:65be27845400	334	*/
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	/**
AnnaBridge	172:65be27845400	337	* @brief Write a value in SPI register
AnnaBridge	172:65be27845400	338	* @param __INSTANCE__ SPI Instance
AnnaBridge	172:65be27845400	339	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	340	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	341	* @retval None
AnnaBridge	172:65be27845400	342	*/
AnnaBridge	172:65be27845400	343	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	344
AnnaBridge	172:65be27845400	345	/**
AnnaBridge	172:65be27845400	346	* @brief Read a value in SPI register
AnnaBridge	172:65be27845400	347	* @param __INSTANCE__ SPI Instance
AnnaBridge	172:65be27845400	348	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	349	* @retval Register value
AnnaBridge	172:65be27845400	350	*/
AnnaBridge	172:65be27845400	351	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	352	/**
AnnaBridge	172:65be27845400	353	* @}
AnnaBridge	172:65be27845400	354	*/
AnnaBridge	172:65be27845400	355
AnnaBridge	172:65be27845400	356	/**
AnnaBridge	172:65be27845400	357	* @}
AnnaBridge	172:65be27845400	358	*/
AnnaBridge	172:65be27845400	359
AnnaBridge	172:65be27845400	360	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	361	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	172:65be27845400	362	* @{
AnnaBridge	172:65be27845400	363	*/
AnnaBridge	172:65be27845400	364
AnnaBridge	172:65be27845400	365	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	172:65be27845400	366	* @{
AnnaBridge	172:65be27845400	367	*/
AnnaBridge	172:65be27845400	368
AnnaBridge	172:65be27845400	369	/**
AnnaBridge	172:65be27845400	370	* @brief Enable SPI peripheral
AnnaBridge	172:65be27845400	371	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	172:65be27845400	372	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	373	* @retval None
AnnaBridge	172:65be27845400	374	*/
AnnaBridge	172:65be27845400	375	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	376	{
AnnaBridge	172:65be27845400	377	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	378	}
AnnaBridge	172:65be27845400	379
AnnaBridge	172:65be27845400	380	/**
AnnaBridge	172:65be27845400	381	* @brief Disable SPI peripheral
AnnaBridge	172:65be27845400	382	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	172:65be27845400	383	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	172:65be27845400	384	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	385	* @retval None
AnnaBridge	172:65be27845400	386	*/
AnnaBridge	172:65be27845400	387	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	388	{
AnnaBridge	172:65be27845400	389	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	390	}
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	/**
AnnaBridge	172:65be27845400	393	* @brief Check if SPI peripheral is enabled
AnnaBridge	172:65be27845400	394	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	172:65be27845400	395	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	396	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	397	*/
AnnaBridge	172:65be27845400	398	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	399	{
AnnaBridge	172:65be27845400	400	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	172:65be27845400	401	}
AnnaBridge	172:65be27845400	402
AnnaBridge	172:65be27845400	403	/**
AnnaBridge	172:65be27845400	404	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	172:65be27845400	405	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	172:65be27845400	406	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	172:65be27845400	407	* CR1 SSI LL_SPI_SetMode
AnnaBridge	172:65be27845400	408	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	409	* @param Mode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	410	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	172:65be27845400	411	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	172:65be27845400	412	* @retval None
AnnaBridge	172:65be27845400	413	*/
AnnaBridge	172:65be27845400	414	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	172:65be27845400	415	{
AnnaBridge	172:65be27845400	416	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	172:65be27845400	417	}
AnnaBridge	172:65be27845400	418
AnnaBridge	172:65be27845400	419	/**
AnnaBridge	172:65be27845400	420	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	172:65be27845400	421	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	172:65be27845400	422	* CR1 SSI LL_SPI_GetMode
AnnaBridge	172:65be27845400	423	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	424	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	425	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	172:65be27845400	426	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	172:65be27845400	427	*/
AnnaBridge	172:65be27845400	428	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	429	{
AnnaBridge	172:65be27845400	430	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	172:65be27845400	431	}
AnnaBridge	172:65be27845400	432
AnnaBridge	172:65be27845400	433	/**
AnnaBridge	172:65be27845400	434	* @brief Set serial protocol used
AnnaBridge	172:65be27845400	435	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	172:65be27845400	436	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	172:65be27845400	437	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	438	* @param Standard This parameter can be one of the following values:
AnnaBridge	172:65be27845400	439	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	172:65be27845400	440	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	172:65be27845400	441	* @retval None
AnnaBridge	172:65be27845400	442	*/
AnnaBridge	172:65be27845400	443	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	172:65be27845400	444	{
AnnaBridge	172:65be27845400	445	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	172:65be27845400	446	}
AnnaBridge	172:65be27845400	447
AnnaBridge	172:65be27845400	448	/**
AnnaBridge	172:65be27845400	449	* @brief Get serial protocol used
AnnaBridge	172:65be27845400	450	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	172:65be27845400	451	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	452	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	453	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	172:65be27845400	454	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	172:65be27845400	455	*/
AnnaBridge	172:65be27845400	456	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	457	{
AnnaBridge	172:65be27845400	458	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	172:65be27845400	459	}
AnnaBridge	172:65be27845400	460
AnnaBridge	172:65be27845400	461	/**
AnnaBridge	172:65be27845400	462	* @brief Set clock phase
AnnaBridge	172:65be27845400	463	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	172:65be27845400	464	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	465	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	172:65be27845400	466	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	467	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	172:65be27845400	468	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	172:65be27845400	469	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	172:65be27845400	470	* @retval None
AnnaBridge	172:65be27845400	471	*/
AnnaBridge	172:65be27845400	472	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	172:65be27845400	473	{
AnnaBridge	172:65be27845400	474	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	172:65be27845400	475	}
AnnaBridge	172:65be27845400	476
AnnaBridge	172:65be27845400	477	/**
AnnaBridge	172:65be27845400	478	* @brief Get clock phase
AnnaBridge	172:65be27845400	479	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	172:65be27845400	480	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	481	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	482	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	172:65be27845400	483	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	172:65be27845400	484	*/
AnnaBridge	172:65be27845400	485	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	486	{
AnnaBridge	172:65be27845400	487	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	172:65be27845400	488	}
AnnaBridge	172:65be27845400	489
AnnaBridge	172:65be27845400	490	/**
AnnaBridge	172:65be27845400	491	* @brief Set clock polarity
AnnaBridge	172:65be27845400	492	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	172:65be27845400	493	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	494	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	172:65be27845400	495	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	496	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	497	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	172:65be27845400	498	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	172:65be27845400	499	* @retval None
AnnaBridge	172:65be27845400	500	*/
AnnaBridge	172:65be27845400	501	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	172:65be27845400	502	{
AnnaBridge	172:65be27845400	503	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	172:65be27845400	504	}
AnnaBridge	172:65be27845400	505
AnnaBridge	172:65be27845400	506	/**
AnnaBridge	172:65be27845400	507	* @brief Get clock polarity
AnnaBridge	172:65be27845400	508	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	172:65be27845400	509	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	510	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	511	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	172:65be27845400	512	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	172:65be27845400	513	*/
AnnaBridge	172:65be27845400	514	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	515	{
AnnaBridge	172:65be27845400	516	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	172:65be27845400	517	}
AnnaBridge	172:65be27845400	518
AnnaBridge	172:65be27845400	519	/**
AnnaBridge	172:65be27845400	520	* @brief Set baud rate prescaler
AnnaBridge	172:65be27845400	521	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	172:65be27845400	522	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	172:65be27845400	523	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	524	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	172:65be27845400	525	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	172:65be27845400	526	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	172:65be27845400	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	172:65be27845400	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	172:65be27845400	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	172:65be27845400	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	172:65be27845400	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	172:65be27845400	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	172:65be27845400	533	* @retval None
AnnaBridge	172:65be27845400	534	*/
AnnaBridge	172:65be27845400	535	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	172:65be27845400	536	{
AnnaBridge	172:65be27845400	537	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	172:65be27845400	538	}
AnnaBridge	172:65be27845400	539
AnnaBridge	172:65be27845400	540	/**
AnnaBridge	172:65be27845400	541	* @brief Get baud rate prescaler
AnnaBridge	172:65be27845400	542	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	172:65be27845400	543	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	544	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	545	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	172:65be27845400	546	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	172:65be27845400	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	172:65be27845400	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	172:65be27845400	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	172:65be27845400	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	172:65be27845400	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	172:65be27845400	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	172:65be27845400	553	*/
AnnaBridge	172:65be27845400	554	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	555	{
AnnaBridge	172:65be27845400	556	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	172:65be27845400	557	}
AnnaBridge	172:65be27845400	558
AnnaBridge	172:65be27845400	559	/**
AnnaBridge	172:65be27845400	560	* @brief Set transfer bit order
AnnaBridge	172:65be27845400	561	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	562	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	172:65be27845400	563	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	564	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	172:65be27845400	565	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	172:65be27845400	566	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	172:65be27845400	567	* @retval None
AnnaBridge	172:65be27845400	568	*/
AnnaBridge	172:65be27845400	569	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	172:65be27845400	570	{
AnnaBridge	172:65be27845400	571	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	172:65be27845400	572	}
AnnaBridge	172:65be27845400	573
AnnaBridge	172:65be27845400	574	/**
AnnaBridge	172:65be27845400	575	* @brief Get transfer bit order
AnnaBridge	172:65be27845400	576	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	172:65be27845400	577	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	578	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	579	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	172:65be27845400	580	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	172:65be27845400	581	*/
AnnaBridge	172:65be27845400	582	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	583	{
AnnaBridge	172:65be27845400	584	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	172:65be27845400	585	}
AnnaBridge	172:65be27845400	586
AnnaBridge	172:65be27845400	587	/**
AnnaBridge	172:65be27845400	588	* @brief Set transfer direction mode
AnnaBridge	172:65be27845400	589	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	172:65be27845400	590	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	172:65be27845400	591	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	172:65be27845400	592	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	172:65be27845400	593	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	172:65be27845400	594	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	595	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	596	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	172:65be27845400	597	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	172:65be27845400	598	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	172:65be27845400	599	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	172:65be27845400	600	* @retval None
AnnaBridge	172:65be27845400	601	*/
AnnaBridge	172:65be27845400	602	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	172:65be27845400	603	{
AnnaBridge	172:65be27845400	604	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	172:65be27845400	605	}
AnnaBridge	172:65be27845400	606
AnnaBridge	172:65be27845400	607	/**
AnnaBridge	172:65be27845400	608	* @brief Get transfer direction mode
AnnaBridge	172:65be27845400	609	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	172:65be27845400	610	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	172:65be27845400	611	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	172:65be27845400	612	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	613	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	614	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	172:65be27845400	615	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	172:65be27845400	616	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	172:65be27845400	617	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	172:65be27845400	618	*/
AnnaBridge	172:65be27845400	619	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	620	{
AnnaBridge	172:65be27845400	621	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	172:65be27845400	622	}
AnnaBridge	172:65be27845400	623
AnnaBridge	172:65be27845400	624	/**
AnnaBridge	172:65be27845400	625	* @brief Set frame data width
AnnaBridge	172:65be27845400	626	* @rmtoll CR2 DS LL_SPI_SetDataWidth
AnnaBridge	172:65be27845400	627	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	628	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	172:65be27845400	629	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	172:65be27845400	630	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	172:65be27845400	631	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	172:65be27845400	632	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	172:65be27845400	633	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	172:65be27845400	634	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	172:65be27845400	635	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	172:65be27845400	636	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	172:65be27845400	637	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	172:65be27845400	638	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	172:65be27845400	639	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	172:65be27845400	640	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	172:65be27845400	641	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	172:65be27845400	642	* @retval None
AnnaBridge	172:65be27845400	643	*/
AnnaBridge	172:65be27845400	644	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	172:65be27845400	645	{
AnnaBridge	172:65be27845400	646	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
AnnaBridge	172:65be27845400	647	}
AnnaBridge	172:65be27845400	648
AnnaBridge	172:65be27845400	649	/**
AnnaBridge	172:65be27845400	650	* @brief Get frame data width
AnnaBridge	172:65be27845400	651	* @rmtoll CR2 DS LL_SPI_GetDataWidth
AnnaBridge	172:65be27845400	652	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	653	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	654	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	172:65be27845400	655	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	172:65be27845400	656	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	172:65be27845400	657	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	172:65be27845400	658	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	172:65be27845400	659	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	172:65be27845400	660	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	172:65be27845400	661	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	172:65be27845400	662	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	172:65be27845400	663	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	172:65be27845400	664	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	172:65be27845400	665	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	172:65be27845400	666	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	172:65be27845400	667	*/
AnnaBridge	172:65be27845400	668	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	669	{
AnnaBridge	172:65be27845400	670	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
AnnaBridge	172:65be27845400	671	}
AnnaBridge	172:65be27845400	672
AnnaBridge	172:65be27845400	673	/**
AnnaBridge	172:65be27845400	674	* @brief Set threshold of RXFIFO that triggers an RXNE event
AnnaBridge	172:65be27845400	675	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
AnnaBridge	172:65be27845400	676	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	677	* @param Threshold This parameter can be one of the following values:
AnnaBridge	172:65be27845400	678	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	172:65be27845400	679	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	172:65be27845400	680	* @retval None
AnnaBridge	172:65be27845400	681	*/
AnnaBridge	172:65be27845400	682	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge	172:65be27845400	683	{
AnnaBridge	172:65be27845400	684	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
AnnaBridge	172:65be27845400	685	}
AnnaBridge	172:65be27845400	686
AnnaBridge	172:65be27845400	687	/**
AnnaBridge	172:65be27845400	688	* @brief Get threshold of RXFIFO that triggers an RXNE event
AnnaBridge	172:65be27845400	689	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
AnnaBridge	172:65be27845400	690	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	691	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	692	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	172:65be27845400	693	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	172:65be27845400	694	*/
AnnaBridge	172:65be27845400	695	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	696	{
AnnaBridge	172:65be27845400	697	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
AnnaBridge	172:65be27845400	698	}
AnnaBridge	172:65be27845400	699
AnnaBridge	172:65be27845400	700	/**
AnnaBridge	172:65be27845400	701	* @}
AnnaBridge	172:65be27845400	702	*/
AnnaBridge	172:65be27845400	703
AnnaBridge	172:65be27845400	704	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	172:65be27845400	705	* @{
AnnaBridge	172:65be27845400	706	*/
AnnaBridge	172:65be27845400	707
AnnaBridge	172:65be27845400	708	/**
AnnaBridge	172:65be27845400	709	* @brief Enable CRC
AnnaBridge	172:65be27845400	710	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	172:65be27845400	711	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	172:65be27845400	712	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	713	* @retval None
AnnaBridge	172:65be27845400	714	*/
AnnaBridge	172:65be27845400	715	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	716	{
AnnaBridge	172:65be27845400	717	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	172:65be27845400	718	}
AnnaBridge	172:65be27845400	719
AnnaBridge	172:65be27845400	720	/**
AnnaBridge	172:65be27845400	721	* @brief Disable CRC
AnnaBridge	172:65be27845400	722	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	172:65be27845400	723	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	172:65be27845400	724	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	725	* @retval None
AnnaBridge	172:65be27845400	726	*/
AnnaBridge	172:65be27845400	727	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	728	{
AnnaBridge	172:65be27845400	729	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	172:65be27845400	730	}
AnnaBridge	172:65be27845400	731
AnnaBridge	172:65be27845400	732	/**
AnnaBridge	172:65be27845400	733	* @brief Check if CRC is enabled
AnnaBridge	172:65be27845400	734	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	172:65be27845400	735	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	172:65be27845400	736	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	737	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	738	*/
AnnaBridge	172:65be27845400	739	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	740	{
AnnaBridge	172:65be27845400	741	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	172:65be27845400	742	}
AnnaBridge	172:65be27845400	743
AnnaBridge	172:65be27845400	744	/**
AnnaBridge	172:65be27845400	745	* @brief Set CRC Length
AnnaBridge	172:65be27845400	746	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	172:65be27845400	747	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
AnnaBridge	172:65be27845400	748	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	749	* @param CRCLength This parameter can be one of the following values:
AnnaBridge	172:65be27845400	750	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	172:65be27845400	751	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	172:65be27845400	752	* @retval None
AnnaBridge	172:65be27845400	753	*/
AnnaBridge	172:65be27845400	754	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
AnnaBridge	172:65be27845400	755	{
AnnaBridge	172:65be27845400	756	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
AnnaBridge	172:65be27845400	757	}
AnnaBridge	172:65be27845400	758
AnnaBridge	172:65be27845400	759	/**
AnnaBridge	172:65be27845400	760	* @brief Get CRC Length
AnnaBridge	172:65be27845400	761	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
AnnaBridge	172:65be27845400	762	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	763	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	764	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	172:65be27845400	765	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	172:65be27845400	766	*/
AnnaBridge	172:65be27845400	767	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	768	{
AnnaBridge	172:65be27845400	769	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
AnnaBridge	172:65be27845400	770	}
AnnaBridge	172:65be27845400	771
AnnaBridge	172:65be27845400	772	/**
AnnaBridge	172:65be27845400	773	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	172:65be27845400	774	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	172:65be27845400	775	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	172:65be27845400	776	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	777	* @retval None
AnnaBridge	172:65be27845400	778	*/
AnnaBridge	172:65be27845400	779	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	780	{
AnnaBridge	172:65be27845400	781	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	172:65be27845400	782	}
AnnaBridge	172:65be27845400	783
AnnaBridge	172:65be27845400	784	/**
AnnaBridge	172:65be27845400	785	* @brief Set polynomial for CRC calculation
AnnaBridge	172:65be27845400	786	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	172:65be27845400	787	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	788	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	172:65be27845400	789	* @retval None
AnnaBridge	172:65be27845400	790	*/
AnnaBridge	172:65be27845400	791	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	172:65be27845400	792	{
AnnaBridge	172:65be27845400	793	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	172:65be27845400	794	}
AnnaBridge	172:65be27845400	795
AnnaBridge	172:65be27845400	796	/**
AnnaBridge	172:65be27845400	797	* @brief Get polynomial for CRC calculation
AnnaBridge	172:65be27845400	798	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	172:65be27845400	799	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	800	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	172:65be27845400	801	*/
AnnaBridge	172:65be27845400	802	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	803	{
AnnaBridge	172:65be27845400	804	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	172:65be27845400	805	}
AnnaBridge	172:65be27845400	806
AnnaBridge	172:65be27845400	807	/**
AnnaBridge	172:65be27845400	808	* @brief Get Rx CRC
AnnaBridge	172:65be27845400	809	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	172:65be27845400	810	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	811	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	172:65be27845400	812	*/
AnnaBridge	172:65be27845400	813	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	814	{
AnnaBridge	172:65be27845400	815	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	172:65be27845400	816	}
AnnaBridge	172:65be27845400	817
AnnaBridge	172:65be27845400	818	/**
AnnaBridge	172:65be27845400	819	* @brief Get Tx CRC
AnnaBridge	172:65be27845400	820	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	172:65be27845400	821	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	822	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	172:65be27845400	823	*/
AnnaBridge	172:65be27845400	824	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	825	{
AnnaBridge	172:65be27845400	826	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	172:65be27845400	827	}
AnnaBridge	172:65be27845400	828
AnnaBridge	172:65be27845400	829	/**
AnnaBridge	172:65be27845400	830	* @}
AnnaBridge	172:65be27845400	831	*/
AnnaBridge	172:65be27845400	832
AnnaBridge	172:65be27845400	833	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	172:65be27845400	834	* @{
AnnaBridge	172:65be27845400	835	*/
AnnaBridge	172:65be27845400	836
AnnaBridge	172:65be27845400	837	/**
AnnaBridge	172:65be27845400	838	* @brief Set NSS mode
AnnaBridge	172:65be27845400	839	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	172:65be27845400	840	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	172:65be27845400	841	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	172:65be27845400	842	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	843	* @param NSS This parameter can be one of the following values:
AnnaBridge	172:65be27845400	844	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	172:65be27845400	845	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	172:65be27845400	846	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	172:65be27845400	847	* @retval None
AnnaBridge	172:65be27845400	848	*/
AnnaBridge	172:65be27845400	849	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	172:65be27845400	850	{
AnnaBridge	172:65be27845400	851	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	172:65be27845400	852	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	172:65be27845400	853	}
AnnaBridge	172:65be27845400	854
AnnaBridge	172:65be27845400	855	/**
AnnaBridge	172:65be27845400	856	* @brief Get NSS mode
AnnaBridge	172:65be27845400	857	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	172:65be27845400	858	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	172:65be27845400	859	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	860	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	861	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	172:65be27845400	862	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	172:65be27845400	863	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	172:65be27845400	864	*/
AnnaBridge	172:65be27845400	865	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	866	{
AnnaBridge	172:65be27845400	867	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	172:65be27845400	868	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	172:65be27845400	869	return (Ssm \| Ssoe);
AnnaBridge	172:65be27845400	870	}
AnnaBridge	172:65be27845400	871
AnnaBridge	172:65be27845400	872	/**
AnnaBridge	172:65be27845400	873	* @brief Enable NSS pulse management
AnnaBridge	172:65be27845400	874	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	875	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
AnnaBridge	172:65be27845400	876	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	877	* @retval None
AnnaBridge	172:65be27845400	878	*/
AnnaBridge	172:65be27845400	879	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	880	{
AnnaBridge	172:65be27845400	881	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	172:65be27845400	882	}
AnnaBridge	172:65be27845400	883
AnnaBridge	172:65be27845400	884	/**
AnnaBridge	172:65be27845400	885	* @brief Disable NSS pulse management
AnnaBridge	172:65be27845400	886	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	887	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
AnnaBridge	172:65be27845400	888	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	889	* @retval None
AnnaBridge	172:65be27845400	890	*/
AnnaBridge	172:65be27845400	891	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	892	{
AnnaBridge	172:65be27845400	893	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	172:65be27845400	894	}
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	/**
AnnaBridge	172:65be27845400	897	* @brief Check if NSS pulse is enabled
AnnaBridge	172:65be27845400	898	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	899	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
AnnaBridge	172:65be27845400	900	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	901	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	902	*/
AnnaBridge	172:65be27845400	903	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	904	{
AnnaBridge	172:65be27845400	905	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
AnnaBridge	172:65be27845400	906	}
AnnaBridge	172:65be27845400	907
AnnaBridge	172:65be27845400	908	/**
AnnaBridge	172:65be27845400	909	* @}
AnnaBridge	172:65be27845400	910	*/
AnnaBridge	172:65be27845400	911
AnnaBridge	172:65be27845400	912	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	172:65be27845400	913	* @{
AnnaBridge	172:65be27845400	914	*/
AnnaBridge	172:65be27845400	915
AnnaBridge	172:65be27845400	916	/**
AnnaBridge	172:65be27845400	917	* @brief Check if Rx buffer is not empty
AnnaBridge	172:65be27845400	918	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	172:65be27845400	919	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	920	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	921	*/
AnnaBridge	172:65be27845400	922	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	923	{
AnnaBridge	172:65be27845400	924	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	172:65be27845400	925	}
AnnaBridge	172:65be27845400	926
AnnaBridge	172:65be27845400	927	/**
AnnaBridge	172:65be27845400	928	* @brief Check if Tx buffer is empty
AnnaBridge	172:65be27845400	929	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	172:65be27845400	930	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	931	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	932	*/
AnnaBridge	172:65be27845400	933	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	934	{
AnnaBridge	172:65be27845400	935	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	172:65be27845400	936	}
AnnaBridge	172:65be27845400	937
AnnaBridge	172:65be27845400	938	/**
AnnaBridge	172:65be27845400	939	* @brief Get CRC error flag
AnnaBridge	172:65be27845400	940	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	172:65be27845400	941	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	942	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	943	*/
AnnaBridge	172:65be27845400	944	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	945	{
AnnaBridge	172:65be27845400	946	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	172:65be27845400	947	}
AnnaBridge	172:65be27845400	948
AnnaBridge	172:65be27845400	949	/**
AnnaBridge	172:65be27845400	950	* @brief Get mode fault error flag
AnnaBridge	172:65be27845400	951	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	172:65be27845400	952	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	953	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	954	*/
AnnaBridge	172:65be27845400	955	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	956	{
AnnaBridge	172:65be27845400	957	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	172:65be27845400	958	}
AnnaBridge	172:65be27845400	959
AnnaBridge	172:65be27845400	960	/**
AnnaBridge	172:65be27845400	961	* @brief Get overrun error flag
AnnaBridge	172:65be27845400	962	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	172:65be27845400	963	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	964	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	965	*/
AnnaBridge	172:65be27845400	966	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	967	{
AnnaBridge	172:65be27845400	968	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	172:65be27845400	969	}
AnnaBridge	172:65be27845400	970
AnnaBridge	172:65be27845400	971	/**
AnnaBridge	172:65be27845400	972	* @brief Get busy flag
AnnaBridge	172:65be27845400	973	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	172:65be27845400	974	* -When the SPI is correctly disabled
AnnaBridge	172:65be27845400	975	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	172:65be27845400	976	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	172:65be27845400	977	* sent
AnnaBridge	172:65be27845400	978	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	172:65be27845400	979	* each data transfer.
AnnaBridge	172:65be27845400	980	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	172:65be27845400	981	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	982	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	983	*/
AnnaBridge	172:65be27845400	984	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	985	{
AnnaBridge	172:65be27845400	986	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	172:65be27845400	987	}
AnnaBridge	172:65be27845400	988
AnnaBridge	172:65be27845400	989	/**
AnnaBridge	172:65be27845400	990	* @brief Get frame format error flag
AnnaBridge	172:65be27845400	991	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	172:65be27845400	992	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	993	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	994	*/
AnnaBridge	172:65be27845400	995	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	996	{
AnnaBridge	172:65be27845400	997	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	172:65be27845400	998	}
AnnaBridge	172:65be27845400	999
AnnaBridge	172:65be27845400	1000	/**
AnnaBridge	172:65be27845400	1001	* @brief Get FIFO reception Level
AnnaBridge	172:65be27845400	1002	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
AnnaBridge	172:65be27845400	1003	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1004	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1005	* @arg @ref LL_SPI_RX_FIFO_EMPTY
AnnaBridge	172:65be27845400	1006	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
AnnaBridge	172:65be27845400	1007	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
AnnaBridge	172:65be27845400	1008	* @arg @ref LL_SPI_RX_FIFO_FULL
AnnaBridge	172:65be27845400	1009	*/
AnnaBridge	172:65be27845400	1010	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1011	{
AnnaBridge	172:65be27845400	1012	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
AnnaBridge	172:65be27845400	1013	}
AnnaBridge	172:65be27845400	1014
AnnaBridge	172:65be27845400	1015	/**
AnnaBridge	172:65be27845400	1016	* @brief Get FIFO Transmission Level
AnnaBridge	172:65be27845400	1017	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
AnnaBridge	172:65be27845400	1018	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1019	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1020	* @arg @ref LL_SPI_TX_FIFO_EMPTY
AnnaBridge	172:65be27845400	1021	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
AnnaBridge	172:65be27845400	1022	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
AnnaBridge	172:65be27845400	1023	* @arg @ref LL_SPI_TX_FIFO_FULL
AnnaBridge	172:65be27845400	1024	*/
AnnaBridge	172:65be27845400	1025	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1026	{
AnnaBridge	172:65be27845400	1027	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
AnnaBridge	172:65be27845400	1028	}
AnnaBridge	172:65be27845400	1029
AnnaBridge	172:65be27845400	1030	/**
AnnaBridge	172:65be27845400	1031	* @brief Clear CRC error flag
AnnaBridge	172:65be27845400	1032	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	172:65be27845400	1033	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1034	* @retval None
AnnaBridge	172:65be27845400	1035	*/
AnnaBridge	172:65be27845400	1036	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1037	{
AnnaBridge	172:65be27845400	1038	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	172:65be27845400	1039	}
AnnaBridge	172:65be27845400	1040
AnnaBridge	172:65be27845400	1041	/**
AnnaBridge	172:65be27845400	1042	* @brief Clear mode fault error flag
AnnaBridge	172:65be27845400	1043	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	172:65be27845400	1044	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	172:65be27845400	1045	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	172:65be27845400	1046	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1047	* @retval None
AnnaBridge	172:65be27845400	1048	*/
AnnaBridge	172:65be27845400	1049	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1050	{
AnnaBridge	172:65be27845400	1051	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1052	tmpreg = SPIx->SR;
AnnaBridge	172:65be27845400	1053	(void) tmpreg;
AnnaBridge	172:65be27845400	1054	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	1055	(void) tmpreg;
AnnaBridge	172:65be27845400	1056	}
AnnaBridge	172:65be27845400	1057
AnnaBridge	172:65be27845400	1058	/**
AnnaBridge	172:65be27845400	1059	* @brief Clear overrun error flag
AnnaBridge	172:65be27845400	1060	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	172:65be27845400	1061	* register followed by a read access to the SPIx_SR register
AnnaBridge	172:65be27845400	1062	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	172:65be27845400	1063	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1064	* @retval None
AnnaBridge	172:65be27845400	1065	*/
AnnaBridge	172:65be27845400	1066	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1067	{
AnnaBridge	172:65be27845400	1068	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1069	tmpreg = SPIx->DR;
AnnaBridge	172:65be27845400	1070	(void) tmpreg;
AnnaBridge	172:65be27845400	1071	tmpreg = SPIx->SR;
AnnaBridge	172:65be27845400	1072	(void) tmpreg;
AnnaBridge	172:65be27845400	1073	}
AnnaBridge	172:65be27845400	1074
AnnaBridge	172:65be27845400	1075	/**
AnnaBridge	172:65be27845400	1076	* @brief Clear frame format error flag
AnnaBridge	172:65be27845400	1077	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	172:65be27845400	1078	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	172:65be27845400	1079	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1080	* @retval None
AnnaBridge	172:65be27845400	1081	*/
AnnaBridge	172:65be27845400	1082	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1083	{
AnnaBridge	172:65be27845400	1084	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1085	tmpreg = SPIx->SR;
AnnaBridge	172:65be27845400	1086	(void) tmpreg;
AnnaBridge	172:65be27845400	1087	}
AnnaBridge	172:65be27845400	1088
AnnaBridge	172:65be27845400	1089	/**
AnnaBridge	172:65be27845400	1090	* @}
AnnaBridge	172:65be27845400	1091	*/
AnnaBridge	172:65be27845400	1092
AnnaBridge	172:65be27845400	1093	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	172:65be27845400	1094	* @{
AnnaBridge	172:65be27845400	1095	*/
AnnaBridge	172:65be27845400	1096
AnnaBridge	172:65be27845400	1097	/**
AnnaBridge	172:65be27845400	1098	* @brief Enable error interrupt
AnnaBridge	172:65be27845400	1099	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	172:65be27845400	1100	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	172:65be27845400	1101	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1102	* @retval None
AnnaBridge	172:65be27845400	1103	*/
AnnaBridge	172:65be27845400	1104	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1105	{
AnnaBridge	172:65be27845400	1106	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	172:65be27845400	1107	}
AnnaBridge	172:65be27845400	1108
AnnaBridge	172:65be27845400	1109	/**
AnnaBridge	172:65be27845400	1110	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	172:65be27845400	1111	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	172:65be27845400	1112	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1113	* @retval None
AnnaBridge	172:65be27845400	1114	*/
AnnaBridge	172:65be27845400	1115	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1116	{
AnnaBridge	172:65be27845400	1117	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	172:65be27845400	1118	}
AnnaBridge	172:65be27845400	1119
AnnaBridge	172:65be27845400	1120	/**
AnnaBridge	172:65be27845400	1121	* @brief Enable Tx buffer empty interrupt
AnnaBridge	172:65be27845400	1122	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	172:65be27845400	1123	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1124	* @retval None
AnnaBridge	172:65be27845400	1125	*/
AnnaBridge	172:65be27845400	1126	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1127	{
AnnaBridge	172:65be27845400	1128	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	172:65be27845400	1129	}
AnnaBridge	172:65be27845400	1130
AnnaBridge	172:65be27845400	1131	/**
AnnaBridge	172:65be27845400	1132	* @brief Disable error interrupt
AnnaBridge	172:65be27845400	1133	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	172:65be27845400	1134	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	172:65be27845400	1135	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1136	* @retval None
AnnaBridge	172:65be27845400	1137	*/
AnnaBridge	172:65be27845400	1138	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1139	{
AnnaBridge	172:65be27845400	1140	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	172:65be27845400	1141	}
AnnaBridge	172:65be27845400	1142
AnnaBridge	172:65be27845400	1143	/**
AnnaBridge	172:65be27845400	1144	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	172:65be27845400	1145	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	172:65be27845400	1146	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1147	* @retval None
AnnaBridge	172:65be27845400	1148	*/
AnnaBridge	172:65be27845400	1149	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1150	{
AnnaBridge	172:65be27845400	1151	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	172:65be27845400	1152	}
AnnaBridge	172:65be27845400	1153
AnnaBridge	172:65be27845400	1154	/**
AnnaBridge	172:65be27845400	1155	* @brief Disable Tx buffer empty interrupt
AnnaBridge	172:65be27845400	1156	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	172:65be27845400	1157	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1158	* @retval None
AnnaBridge	172:65be27845400	1159	*/
AnnaBridge	172:65be27845400	1160	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1161	{
AnnaBridge	172:65be27845400	1162	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	172:65be27845400	1163	}
AnnaBridge	172:65be27845400	1164
AnnaBridge	172:65be27845400	1165	/**
AnnaBridge	172:65be27845400	1166	* @brief Check if error interrupt is enabled
AnnaBridge	172:65be27845400	1167	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	172:65be27845400	1168	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1169	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1170	*/
AnnaBridge	172:65be27845400	1171	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1172	{
AnnaBridge	172:65be27845400	1173	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	172:65be27845400	1174	}
AnnaBridge	172:65be27845400	1175
AnnaBridge	172:65be27845400	1176	/**
AnnaBridge	172:65be27845400	1177	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	172:65be27845400	1178	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	172:65be27845400	1179	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1180	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1181	*/
AnnaBridge	172:65be27845400	1182	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1183	{
AnnaBridge	172:65be27845400	1184	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	172:65be27845400	1185	}
AnnaBridge	172:65be27845400	1186
AnnaBridge	172:65be27845400	1187	/**
AnnaBridge	172:65be27845400	1188	* @brief Check if Tx buffer empty interrupt
AnnaBridge	172:65be27845400	1189	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	172:65be27845400	1190	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1191	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1192	*/
AnnaBridge	172:65be27845400	1193	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1194	{
AnnaBridge	172:65be27845400	1195	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	172:65be27845400	1196	}
AnnaBridge	172:65be27845400	1197
AnnaBridge	172:65be27845400	1198	/**
AnnaBridge	172:65be27845400	1199	* @}
AnnaBridge	172:65be27845400	1200	*/
AnnaBridge	172:65be27845400	1201
AnnaBridge	172:65be27845400	1202	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	172:65be27845400	1203	* @{
AnnaBridge	172:65be27845400	1204	*/
AnnaBridge	172:65be27845400	1205
AnnaBridge	172:65be27845400	1206	/**
AnnaBridge	172:65be27845400	1207	* @brief Enable DMA Rx
AnnaBridge	172:65be27845400	1208	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	172:65be27845400	1209	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1210	* @retval None
AnnaBridge	172:65be27845400	1211	*/
AnnaBridge	172:65be27845400	1212	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1213	{
AnnaBridge	172:65be27845400	1214	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	172:65be27845400	1215	}
AnnaBridge	172:65be27845400	1216
AnnaBridge	172:65be27845400	1217	/**
AnnaBridge	172:65be27845400	1218	* @brief Disable DMA Rx
AnnaBridge	172:65be27845400	1219	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	172:65be27845400	1220	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1221	* @retval None
AnnaBridge	172:65be27845400	1222	*/
AnnaBridge	172:65be27845400	1223	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1224	{
AnnaBridge	172:65be27845400	1225	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	172:65be27845400	1226	}
AnnaBridge	172:65be27845400	1227
AnnaBridge	172:65be27845400	1228	/**
AnnaBridge	172:65be27845400	1229	* @brief Check if DMA Rx is enabled
AnnaBridge	172:65be27845400	1230	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	172:65be27845400	1231	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1232	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1233	*/
AnnaBridge	172:65be27845400	1234	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1235	{
AnnaBridge	172:65be27845400	1236	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	172:65be27845400	1237	}
AnnaBridge	172:65be27845400	1238
AnnaBridge	172:65be27845400	1239	/**
AnnaBridge	172:65be27845400	1240	* @brief Enable DMA Tx
AnnaBridge	172:65be27845400	1241	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	172:65be27845400	1242	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1243	* @retval None
AnnaBridge	172:65be27845400	1244	*/
AnnaBridge	172:65be27845400	1245	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1246	{
AnnaBridge	172:65be27845400	1247	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	172:65be27845400	1248	}
AnnaBridge	172:65be27845400	1249
AnnaBridge	172:65be27845400	1250	/**
AnnaBridge	172:65be27845400	1251	* @brief Disable DMA Tx
AnnaBridge	172:65be27845400	1252	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	172:65be27845400	1253	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1254	* @retval None
AnnaBridge	172:65be27845400	1255	*/
AnnaBridge	172:65be27845400	1256	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1257	{
AnnaBridge	172:65be27845400	1258	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	172:65be27845400	1259	}
AnnaBridge	172:65be27845400	1260
AnnaBridge	172:65be27845400	1261	/**
AnnaBridge	172:65be27845400	1262	* @brief Check if DMA Tx is enabled
AnnaBridge	172:65be27845400	1263	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	172:65be27845400	1264	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1265	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1266	*/
AnnaBridge	172:65be27845400	1267	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1268	{
AnnaBridge	172:65be27845400	1269	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	172:65be27845400	1270	}
AnnaBridge	172:65be27845400	1271
AnnaBridge	172:65be27845400	1272	/**
AnnaBridge	172:65be27845400	1273	* @brief Set parity of Last DMA reception
AnnaBridge	172:65be27845400	1274	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
AnnaBridge	172:65be27845400	1275	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1276	* @param Parity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1277	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	172:65be27845400	1278	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	172:65be27845400	1279	* @retval None
AnnaBridge	172:65be27845400	1280	*/
AnnaBridge	172:65be27845400	1281	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	172:65be27845400	1282	{
AnnaBridge	172:65be27845400	1283	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
AnnaBridge	172:65be27845400	1284	}
AnnaBridge	172:65be27845400	1285
AnnaBridge	172:65be27845400	1286	/**
AnnaBridge	172:65be27845400	1287	* @brief Get parity configuration for Last DMA reception
AnnaBridge	172:65be27845400	1288	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
AnnaBridge	172:65be27845400	1289	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1290	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1291	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	172:65be27845400	1292	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	172:65be27845400	1293	*/
AnnaBridge	172:65be27845400	1294	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1295	{
AnnaBridge	172:65be27845400	1296	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
AnnaBridge	172:65be27845400	1297	}
AnnaBridge	172:65be27845400	1298
AnnaBridge	172:65be27845400	1299	/**
AnnaBridge	172:65be27845400	1300	* @brief Set parity of Last DMA transmission
AnnaBridge	172:65be27845400	1301	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
AnnaBridge	172:65be27845400	1302	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1303	* @param Parity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1304	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	172:65be27845400	1305	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	172:65be27845400	1306	* @retval None
AnnaBridge	172:65be27845400	1307	*/
AnnaBridge	172:65be27845400	1308	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	172:65be27845400	1309	{
AnnaBridge	172:65be27845400	1310	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
AnnaBridge	172:65be27845400	1311	}
AnnaBridge	172:65be27845400	1312
AnnaBridge	172:65be27845400	1313	/**
AnnaBridge	172:65be27845400	1314	* @brief Get parity configuration for Last DMA transmission
AnnaBridge	172:65be27845400	1315	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
AnnaBridge	172:65be27845400	1316	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1317	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1318	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	172:65be27845400	1319	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	172:65be27845400	1320	*/
AnnaBridge	172:65be27845400	1321	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1322	{
AnnaBridge	172:65be27845400	1323	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
AnnaBridge	172:65be27845400	1324	}
AnnaBridge	172:65be27845400	1325
AnnaBridge	172:65be27845400	1326	/**
AnnaBridge	172:65be27845400	1327	* @brief Get the data register address used for DMA transfer
AnnaBridge	172:65be27845400	1328	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	172:65be27845400	1329	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1330	* @retval Address of data register
AnnaBridge	172:65be27845400	1331	*/
AnnaBridge	172:65be27845400	1332	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1333	{
AnnaBridge	172:65be27845400	1334	return (uint32_t) & (SPIx->DR);
AnnaBridge	172:65be27845400	1335	}
AnnaBridge	172:65be27845400	1336
AnnaBridge	172:65be27845400	1337	/**
AnnaBridge	172:65be27845400	1338	* @}
AnnaBridge	172:65be27845400	1339	*/
AnnaBridge	172:65be27845400	1340
AnnaBridge	172:65be27845400	1341	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	172:65be27845400	1342	* @{
AnnaBridge	172:65be27845400	1343	*/
AnnaBridge	172:65be27845400	1344
AnnaBridge	172:65be27845400	1345	/**
AnnaBridge	172:65be27845400	1346	* @brief Read 8-Bits in the data register
AnnaBridge	172:65be27845400	1347	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	172:65be27845400	1348	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1349	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1350	*/
AnnaBridge	172:65be27845400	1351	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1352	{
AnnaBridge	172:65be27845400	1353	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	172:65be27845400	1354	}
AnnaBridge	172:65be27845400	1355
AnnaBridge	172:65be27845400	1356	/**
AnnaBridge	172:65be27845400	1357	* @brief Read 16-Bits in the data register
AnnaBridge	172:65be27845400	1358	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	172:65be27845400	1359	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1360	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	172:65be27845400	1361	*/
AnnaBridge	172:65be27845400	1362	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1363	{
AnnaBridge	172:65be27845400	1364	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	172:65be27845400	1365	}
AnnaBridge	172:65be27845400	1366
AnnaBridge	172:65be27845400	1367	/**
AnnaBridge	172:65be27845400	1368	* @brief Write 8-Bits in the data register
AnnaBridge	172:65be27845400	1369	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	172:65be27845400	1370	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1372	* @retval None
AnnaBridge	172:65be27845400	1373	*/
AnnaBridge	172:65be27845400	1374	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	172:65be27845400	1375	{
AnnaBridge	172:65be27845400	1376	((__IO uint8_t )&SPIx->DR) = TxData;
AnnaBridge	172:65be27845400	1377	}
AnnaBridge	172:65be27845400	1378
AnnaBridge	172:65be27845400	1379	#if __GNUC__
AnnaBridge	172:65be27845400	1380	# define MAY_ALIAS __attribute__ ((__may_alias__))
AnnaBridge	172:65be27845400	1381	#else
AnnaBridge	172:65be27845400	1382	# define MAY_ALIAS
AnnaBridge	172:65be27845400	1383	#endif
AnnaBridge	172:65be27845400	1384
AnnaBridge	172:65be27845400	1385	typedef __IO uint16_t MAY_ALIAS uint16_io_t;
AnnaBridge	172:65be27845400	1386
AnnaBridge	172:65be27845400	1387	/**
AnnaBridge	172:65be27845400	1388	* @brief Write 16-Bits in the data register
AnnaBridge	172:65be27845400	1389	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	172:65be27845400	1390	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1391	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	172:65be27845400	1392	* @retval None
AnnaBridge	172:65be27845400	1393	*/
AnnaBridge	172:65be27845400	1394	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	172:65be27845400	1395	{
AnnaBridge	172:65be27845400	1396	((uint16_io_t)&SPIx->DR) = TxData;
AnnaBridge	172:65be27845400	1397	}
AnnaBridge	172:65be27845400	1398
AnnaBridge	172:65be27845400	1399	/**
AnnaBridge	172:65be27845400	1400	* @}
AnnaBridge	172:65be27845400	1401	*/
AnnaBridge	172:65be27845400	1402	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	1403	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	172:65be27845400	1404	* @{
AnnaBridge	172:65be27845400	1405	*/
AnnaBridge	172:65be27845400	1406
AnnaBridge	172:65be27845400	1407	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	172:65be27845400	1408	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	172:65be27845400	1409	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	172:65be27845400	1410
AnnaBridge	172:65be27845400	1411	/**
AnnaBridge	172:65be27845400	1412	* @}
AnnaBridge	172:65be27845400	1413	*/
AnnaBridge	172:65be27845400	1414	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	1415	/**
AnnaBridge	172:65be27845400	1416	* @}
AnnaBridge	172:65be27845400	1417	*/
AnnaBridge	172:65be27845400	1418
AnnaBridge	172:65be27845400	1419	/**
AnnaBridge	172:65be27845400	1420	* @}
AnnaBridge	172:65be27845400	1421	*/
AnnaBridge	172:65be27845400	1422
AnnaBridge	172:65be27845400	1423	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
AnnaBridge	172:65be27845400	1424
AnnaBridge	172:65be27845400	1425	/**
AnnaBridge	172:65be27845400	1426	* @}
AnnaBridge	172:65be27845400	1427	*/
AnnaBridge	172:65be27845400	1428
AnnaBridge	172:65be27845400	1429	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1430	}
AnnaBridge	172:65be27845400	1431	#endif
AnnaBridge	172:65be27845400	1432
AnnaBridge	172:65be27845400	1433	#endif /* __STM32L4xx_LL_SPI_H */
AnnaBridge	172:65be27845400	1434
AnnaBridge	172:65be27845400	1435	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/