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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_hal_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_hal_rcc.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of RCC HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_HAL_RCC_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_HAL_RCC_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	172:65be27845400	48	* @{
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	/** @addtogroup RCC
AnnaBridge	172:65be27845400	52	* @{
AnnaBridge	172:65be27845400	53	*/
AnnaBridge	172:65be27845400	54
AnnaBridge	172:65be27845400	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	56	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	172:65be27845400	57	* @{
AnnaBridge	172:65be27845400	58	*/
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/**
AnnaBridge	172:65be27845400	61	* @brief RCC PLL configuration structure definition
AnnaBridge	172:65be27845400	62	*/
AnnaBridge	172:65be27845400	63	typedef struct
AnnaBridge	172:65be27845400	64	{
AnnaBridge	172:65be27845400	65	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	172:65be27845400	66	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	172:65be27845400	67
AnnaBridge	172:65be27845400	68	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	172:65be27845400	69	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	172:65be27845400	70
AnnaBridge	172:65be27845400	71	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge	172:65be27845400	72	This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
AnnaBridge	172:65be27845400	73	This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */
AnnaBridge	172:65be27845400	74
AnnaBridge	172:65be27845400	75	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge	172:65be27845400	76	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
AnnaBridge	172:65be27845400	77
AnnaBridge	172:65be27845400	78	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
AnnaBridge	172:65be27845400	79	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	172:65be27845400	80
AnnaBridge	172:65be27845400	81	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
AnnaBridge	172:65be27845400	82	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
AnnaBridge	172:65be27845400	83
AnnaBridge	172:65be27845400	84	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
AnnaBridge	172:65be27845400	85	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
AnnaBridge	172:65be27845400	86	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge	172:65be27845400	87
AnnaBridge	172:65be27845400	88	}RCC_PLLInitTypeDef;
AnnaBridge	172:65be27845400	89
AnnaBridge	172:65be27845400	90	/**
AnnaBridge	172:65be27845400	91	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
AnnaBridge	172:65be27845400	92	*/
AnnaBridge	172:65be27845400	93	typedef struct
AnnaBridge	172:65be27845400	94	{
AnnaBridge	172:65be27845400	95	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	172:65be27845400	96	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	172:65be27845400	99	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	172:65be27845400	100
AnnaBridge	172:65be27845400	101	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	172:65be27845400	102	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	172:65be27845400	103
AnnaBridge	172:65be27845400	104	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	172:65be27845400	105	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	172:65be27845400	106
AnnaBridge	172:65be27845400	107	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	172:65be27845400	108	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
AnnaBridge	172:65be27845400	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
AnnaBridge	172:65be27845400	110
AnnaBridge	172:65be27845400	111	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	172:65be27845400	112	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	172:65be27845400	113
AnnaBridge	172:65be27845400	114	uint32_t MSIState; /*!< The new state of the MSI.
AnnaBridge	172:65be27845400	115	This parameter can be a value of @ref RCC_MSI_Config */
AnnaBridge	172:65be27845400	116
AnnaBridge	172:65be27845400	117	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	172:65be27845400	118	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge	172:65be27845400	119
AnnaBridge	172:65be27845400	120	uint32_t MSIClockRange; /*!< The MSI frequency range.
AnnaBridge	172:65be27845400	121	This parameter can be a value of @ref RCC_MSI_Clock_Range */
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).
AnnaBridge	172:65be27845400	124	This parameter can be a value of @ref RCC_HSI48_Config */
AnnaBridge	172:65be27845400	125
AnnaBridge	172:65be27845400	126	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	}RCC_OscInitTypeDef;
AnnaBridge	172:65be27845400	129
AnnaBridge	172:65be27845400	130	/**
AnnaBridge	172:65be27845400	131	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	172:65be27845400	132	*/
AnnaBridge	172:65be27845400	133	typedef struct
AnnaBridge	172:65be27845400	134	{
AnnaBridge	172:65be27845400	135	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	172:65be27845400	136	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	172:65be27845400	137
AnnaBridge	172:65be27845400	138	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
AnnaBridge	172:65be27845400	139	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	172:65be27845400	140
AnnaBridge	172:65be27845400	141	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	172:65be27845400	142	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	172:65be27845400	143
AnnaBridge	172:65be27845400	144	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	172:65be27845400	145	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	172:65be27845400	148	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	172:65be27845400	149
AnnaBridge	172:65be27845400	150	}RCC_ClkInitTypeDef;
AnnaBridge	172:65be27845400	151
AnnaBridge	172:65be27845400	152	/**
AnnaBridge	172:65be27845400	153	* @}
AnnaBridge	172:65be27845400	154	*/
AnnaBridge	172:65be27845400	155
AnnaBridge	172:65be27845400	156	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	157	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	172:65be27845400	158	* @{
AnnaBridge	172:65be27845400	159	*/
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	/** @defgroup RCC_Timeout_Value Timeout Values
AnnaBridge	172:65be27845400	162	* @{
AnnaBridge	172:65be27845400	163	*/
AnnaBridge	172:65be27845400	164	#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge	172:65be27845400	165	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	172:65be27845400	166	/**
AnnaBridge	172:65be27845400	167	* @}
AnnaBridge	172:65be27845400	168	*/
AnnaBridge	172:65be27845400	169
AnnaBridge	172:65be27845400	170	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	172:65be27845400	171	* @{
AnnaBridge	172:65be27845400	172	*/
AnnaBridge	172:65be27845400	173	#define RCC_OSCILLATORTYPE_NONE 0x00000000U /!< Oscillator configuration unchanged /
AnnaBridge	172:65be27845400	174	#define RCC_OSCILLATORTYPE_HSE 0x00000001U /!< HSE to configure /
AnnaBridge	172:65be27845400	175	#define RCC_OSCILLATORTYPE_HSI 0x00000002U /!< HSI to configure /
AnnaBridge	172:65be27845400	176	#define RCC_OSCILLATORTYPE_LSE 0x00000004U /!< LSE to configure /
AnnaBridge	172:65be27845400	177	#define RCC_OSCILLATORTYPE_LSI 0x00000008U /!< LSI to configure /
AnnaBridge	172:65be27845400	178	#define RCC_OSCILLATORTYPE_MSI 0x00000010U /!< MSI to configure /
AnnaBridge	172:65be27845400	179	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	180	#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /!< HSI48 to configure /
AnnaBridge	172:65be27845400	181	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	182	/**
AnnaBridge	172:65be27845400	183	* @}
AnnaBridge	172:65be27845400	184	*/
AnnaBridge	172:65be27845400	185
AnnaBridge	172:65be27845400	186	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	172:65be27845400	187	* @{
AnnaBridge	172:65be27845400	188	*/
AnnaBridge	172:65be27845400	189	#define RCC_HSE_OFF 0x00000000U /!< HSE clock deactivation /
AnnaBridge	172:65be27845400	190	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
AnnaBridge	172:65be27845400	191	#define RCC_HSE_BYPASS (RCC_CR_HSEBYP \| RCC_CR_HSEON) /!< External clock source for HSE clock /
AnnaBridge	172:65be27845400	192	/**
AnnaBridge	172:65be27845400	193	* @}
AnnaBridge	172:65be27845400	194	*/
AnnaBridge	172:65be27845400	195
AnnaBridge	172:65be27845400	196	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	172:65be27845400	197	* @{
AnnaBridge	172:65be27845400	198	*/
AnnaBridge	172:65be27845400	199	#define RCC_LSE_OFF 0x00000000U /!< LSE clock deactivation /
AnnaBridge	172:65be27845400	200	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
AnnaBridge	172:65be27845400	201	#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON) /!< External clock source for LSE clock /
AnnaBridge	172:65be27845400	202	/**
AnnaBridge	172:65be27845400	203	* @}
AnnaBridge	172:65be27845400	204	*/
AnnaBridge	172:65be27845400	205
AnnaBridge	172:65be27845400	206	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	172:65be27845400	207	* @{
AnnaBridge	172:65be27845400	208	*/
AnnaBridge	172:65be27845400	209	#define RCC_HSI_OFF 0x00000000U /!< HSI clock deactivation /
AnnaBridge	172:65be27845400	210	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| defined(STM32L443xx) \|\| \
AnnaBridge	172:65be27845400	213	defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
AnnaBridge	172:65be27845400	214	#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
AnnaBridge	172:65be27845400	215	#else
AnnaBridge	172:65be27845400	216	#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
AnnaBridge	172:65be27845400	217	#endif /* STM32L431xx \|\| STM32L432xx \|\| STM32L433xx \|\| STM32L442xx \|\| STM32L443xx \|\| */
AnnaBridge	172:65be27845400	218	/* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
AnnaBridge	172:65be27845400	219	/**
AnnaBridge	172:65be27845400	220	* @}
AnnaBridge	172:65be27845400	221	*/
AnnaBridge	172:65be27845400	222
AnnaBridge	172:65be27845400	223	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	172:65be27845400	224	* @{
AnnaBridge	172:65be27845400	225	*/
AnnaBridge	172:65be27845400	226	#define RCC_LSI_OFF 0x00000000U /!< LSI clock deactivation /
AnnaBridge	172:65be27845400	227	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
AnnaBridge	172:65be27845400	228	/**
AnnaBridge	172:65be27845400	229	* @}
AnnaBridge	172:65be27845400	230	*/
AnnaBridge	172:65be27845400	231
AnnaBridge	172:65be27845400	232	/** @defgroup RCC_MSI_Config MSI Config
AnnaBridge	172:65be27845400	233	* @{
AnnaBridge	172:65be27845400	234	*/
AnnaBridge	172:65be27845400	235	#define RCC_MSI_OFF 0x00000000U /!< MSI clock deactivation /
AnnaBridge	172:65be27845400	236	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
AnnaBridge	172:65be27845400	237
AnnaBridge	172:65be27845400	238	#define RCC_MSICALIBRATION_DEFAULT 0U /!< Default MSI calibration trimming value /
AnnaBridge	172:65be27845400	239	/**
AnnaBridge	172:65be27845400	240	* @}
AnnaBridge	172:65be27845400	241	*/
AnnaBridge	172:65be27845400	242
AnnaBridge	172:65be27845400	243	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	244	/** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge	172:65be27845400	245	* @{
AnnaBridge	172:65be27845400	246	*/
AnnaBridge	172:65be27845400	247	#define RCC_HSI48_OFF 0x00000000U /!< HSI48 clock deactivation /
AnnaBridge	172:65be27845400	248	#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /!< HSI48 clock activation /
AnnaBridge	172:65be27845400	249	/**
AnnaBridge	172:65be27845400	250	* @}
AnnaBridge	172:65be27845400	251	*/
AnnaBridge	172:65be27845400	252	#else
AnnaBridge	172:65be27845400	253	/** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge	172:65be27845400	254	* @{
AnnaBridge	172:65be27845400	255	*/
AnnaBridge	172:65be27845400	256	#define RCC_HSI48_OFF 0x00000000U /!< HSI48 clock deactivation /
AnnaBridge	172:65be27845400	257	/**
AnnaBridge	172:65be27845400	258	* @}
AnnaBridge	172:65be27845400	259	*/
AnnaBridge	172:65be27845400	260	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	261
AnnaBridge	172:65be27845400	262	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	172:65be27845400	263	* @{
AnnaBridge	172:65be27845400	264	*/
AnnaBridge	172:65be27845400	265	#define RCC_PLL_NONE 0x00000000U /!< PLL configuration unchanged /
AnnaBridge	172:65be27845400	266	#define RCC_PLL_OFF 0x00000001U /!< PLL deactivation /
AnnaBridge	172:65be27845400	267	#define RCC_PLL_ON 0x00000002U /!< PLL activation /
AnnaBridge	172:65be27845400	268	/**
AnnaBridge	172:65be27845400	269	* @}
AnnaBridge	172:65be27845400	270	*/
AnnaBridge	172:65be27845400	271
AnnaBridge	172:65be27845400	272	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
AnnaBridge	172:65be27845400	273	* @{
AnnaBridge	172:65be27845400	274	*/
AnnaBridge	172:65be27845400	275	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	276	#define RCC_PLLP_DIV2 0x00000002U /!< PLLP division factor = 2 /
AnnaBridge	172:65be27845400	277	#define RCC_PLLP_DIV3 0x00000003U /!< PLLP division factor = 3 /
AnnaBridge	172:65be27845400	278	#define RCC_PLLP_DIV4 0x00000004U /!< PLLP division factor = 4 /
AnnaBridge	172:65be27845400	279	#define RCC_PLLP_DIV5 0x00000005U /!< PLLP division factor = 5 /
AnnaBridge	172:65be27845400	280	#define RCC_PLLP_DIV6 0x00000006U /!< PLLP division factor = 6 /
AnnaBridge	172:65be27845400	281	#define RCC_PLLP_DIV7 0x00000007U /!< PLLP division factor = 7 /
AnnaBridge	172:65be27845400	282	#define RCC_PLLP_DIV8 0x00000008U /!< PLLP division factor = 8 /
AnnaBridge	172:65be27845400	283	#define RCC_PLLP_DIV9 0x00000009U /!< PLLP division factor = 9 /
AnnaBridge	172:65be27845400	284	#define RCC_PLLP_DIV10 0x0000000AU /!< PLLP division factor = 10 /
AnnaBridge	172:65be27845400	285	#define RCC_PLLP_DIV11 0x0000000BU /!< PLLP division factor = 11 /
AnnaBridge	172:65be27845400	286	#define RCC_PLLP_DIV12 0x0000000CU /!< PLLP division factor = 12 /
AnnaBridge	172:65be27845400	287	#define RCC_PLLP_DIV13 0x0000000DU /!< PLLP division factor = 13 /
AnnaBridge	172:65be27845400	288	#define RCC_PLLP_DIV14 0x0000000EU /!< PLLP division factor = 14 /
AnnaBridge	172:65be27845400	289	#define RCC_PLLP_DIV15 0x0000000FU /!< PLLP division factor = 15 /
AnnaBridge	172:65be27845400	290	#define RCC_PLLP_DIV16 0x00000010U /!< PLLP division factor = 16 /
AnnaBridge	172:65be27845400	291	#define RCC_PLLP_DIV17 0x00000011U /!< PLLP division factor = 17 /
AnnaBridge	172:65be27845400	292	#define RCC_PLLP_DIV18 0x00000012U /!< PLLP division factor = 18 /
AnnaBridge	172:65be27845400	293	#define RCC_PLLP_DIV19 0x00000013U /!< PLLP division factor = 19 /
AnnaBridge	172:65be27845400	294	#define RCC_PLLP_DIV20 0x00000014U /!< PLLP division factor = 20 /
AnnaBridge	172:65be27845400	295	#define RCC_PLLP_DIV21 0x00000015U /!< PLLP division factor = 21 /
AnnaBridge	172:65be27845400	296	#define RCC_PLLP_DIV22 0x00000016U /!< PLLP division factor = 22 /
AnnaBridge	172:65be27845400	297	#define RCC_PLLP_DIV23 0x00000017U /!< PLLP division factor = 23 /
AnnaBridge	172:65be27845400	298	#define RCC_PLLP_DIV24 0x00000018U /!< PLLP division factor = 24 /
AnnaBridge	172:65be27845400	299	#define RCC_PLLP_DIV25 0x00000019U /!< PLLP division factor = 25 /
AnnaBridge	172:65be27845400	300	#define RCC_PLLP_DIV26 0x0000001AU /!< PLLP division factor = 26 /
AnnaBridge	172:65be27845400	301	#define RCC_PLLP_DIV27 0x0000001BU /!< PLLP division factor = 27 /
AnnaBridge	172:65be27845400	302	#define RCC_PLLP_DIV28 0x0000001CU /!< PLLP division factor = 28 /
AnnaBridge	172:65be27845400	303	#define RCC_PLLP_DIV29 0x0000001DU /!< PLLP division factor = 29 /
AnnaBridge	172:65be27845400	304	#define RCC_PLLP_DIV30 0x0000001EU /!< PLLP division factor = 30 /
AnnaBridge	172:65be27845400	305	#define RCC_PLLP_DIV31 0x0000001FU /!< PLLP division factor = 31 /
AnnaBridge	172:65be27845400	306	#else
AnnaBridge	172:65be27845400	307	#define RCC_PLLP_DIV7 0x00000007U /!< PLLP division factor = 7 /
AnnaBridge	172:65be27845400	308	#define RCC_PLLP_DIV17 0x00000011U /!< PLLP division factor = 17 /
AnnaBridge	172:65be27845400	309	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	310	/**
AnnaBridge	172:65be27845400	311	* @}
AnnaBridge	172:65be27845400	312	*/
AnnaBridge	172:65be27845400	313
AnnaBridge	172:65be27845400	314	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
AnnaBridge	172:65be27845400	315	* @{
AnnaBridge	172:65be27845400	316	*/
AnnaBridge	172:65be27845400	317	#define RCC_PLLQ_DIV2 0x00000002U /!< PLLQ division factor = 2 /
AnnaBridge	172:65be27845400	318	#define RCC_PLLQ_DIV4 0x00000004U /!< PLLQ division factor = 4 /
AnnaBridge	172:65be27845400	319	#define RCC_PLLQ_DIV6 0x00000006U /!< PLLQ division factor = 6 /
AnnaBridge	172:65be27845400	320	#define RCC_PLLQ_DIV8 0x00000008U /!< PLLQ division factor = 8 /
AnnaBridge	172:65be27845400	321	/**
AnnaBridge	172:65be27845400	322	* @}
AnnaBridge	172:65be27845400	323	*/
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
AnnaBridge	172:65be27845400	326	* @{
AnnaBridge	172:65be27845400	327	*/
AnnaBridge	172:65be27845400	328	#define RCC_PLLR_DIV2 0x00000002U /!< PLLR division factor = 2 /
AnnaBridge	172:65be27845400	329	#define RCC_PLLR_DIV4 0x00000004U /!< PLLR division factor = 4 /
AnnaBridge	172:65be27845400	330	#define RCC_PLLR_DIV6 0x00000006U /!< PLLR division factor = 6 /
AnnaBridge	172:65be27845400	331	#define RCC_PLLR_DIV8 0x00000008U /!< PLLR division factor = 8 /
AnnaBridge	172:65be27845400	332	/**
AnnaBridge	172:65be27845400	333	* @}
AnnaBridge	172:65be27845400	334	*/
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	172:65be27845400	337	* @{
AnnaBridge	172:65be27845400	338	*/
AnnaBridge	172:65be27845400	339	#define RCC_PLLSOURCE_NONE 0x00000000U /!< No clock selected as PLL entry clock source /
AnnaBridge	172:65be27845400	340	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
AnnaBridge	172:65be27845400	341	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
AnnaBridge	172:65be27845400	342	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	172:65be27845400	343	/**
AnnaBridge	172:65be27845400	344	* @}
AnnaBridge	172:65be27845400	345	*/
AnnaBridge	172:65be27845400	346
AnnaBridge	172:65be27845400	347	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
AnnaBridge	172:65be27845400	348	* @{
AnnaBridge	172:65be27845400	349	*/
AnnaBridge	172:65be27845400	350	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	351	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) /
AnnaBridge	172:65be27845400	352	#else
AnnaBridge	172:65be27845400	353	#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) /
AnnaBridge	172:65be27845400	354	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	355	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
AnnaBridge	172:65be27845400	356	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
AnnaBridge	172:65be27845400	357	/**
AnnaBridge	172:65be27845400	358	* @}
AnnaBridge	172:65be27845400	359	*/
AnnaBridge	172:65be27845400	360
AnnaBridge	172:65be27845400	361	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
AnnaBridge	172:65be27845400	362	* @{
AnnaBridge	172:65be27845400	363	*/
AnnaBridge	172:65be27845400	364	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
AnnaBridge	172:65be27845400	365	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
AnnaBridge	172:65be27845400	366	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
AnnaBridge	172:65be27845400	367	/**
AnnaBridge	172:65be27845400	368	* @}
AnnaBridge	172:65be27845400	369	*/
AnnaBridge	172:65be27845400	370
AnnaBridge	172:65be27845400	371	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	372
AnnaBridge	172:65be27845400	373	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
AnnaBridge	172:65be27845400	374	* @{
AnnaBridge	172:65be27845400	375	*/
AnnaBridge	172:65be27845400	376	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
AnnaBridge	172:65be27845400	377	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	172:65be27845400	378	#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /!< PLLDSICLK selection from PLLSAI2 /
AnnaBridge	172:65be27845400	379	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	172:65be27845400	380	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	172:65be27845400	381	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
AnnaBridge	172:65be27845400	382	#else
AnnaBridge	172:65be27845400	383	#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLLTDCCLK selection from PLLSAI2 /
AnnaBridge	172:65be27845400	384	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	385	/**
AnnaBridge	172:65be27845400	386	* @}
AnnaBridge	172:65be27845400	387	*/
AnnaBridge	172:65be27845400	388
AnnaBridge	172:65be27845400	389	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	390
AnnaBridge	172:65be27845400	391	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
AnnaBridge	172:65be27845400	392	* @{
AnnaBridge	172:65be27845400	393	*/
AnnaBridge	172:65be27845400	394	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
AnnaBridge	172:65be27845400	395	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
AnnaBridge	172:65be27845400	396	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
AnnaBridge	172:65be27845400	397	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
AnnaBridge	172:65be27845400	398	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
AnnaBridge	172:65be27845400	399	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
AnnaBridge	172:65be27845400	400	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
AnnaBridge	172:65be27845400	401	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
AnnaBridge	172:65be27845400	402	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
AnnaBridge	172:65be27845400	403	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
AnnaBridge	172:65be27845400	404	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
AnnaBridge	172:65be27845400	405	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
AnnaBridge	172:65be27845400	406	/**
AnnaBridge	172:65be27845400	407	* @}
AnnaBridge	172:65be27845400	408	*/
AnnaBridge	172:65be27845400	409
AnnaBridge	172:65be27845400	410	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	172:65be27845400	411	* @{
AnnaBridge	172:65be27845400	412	*/
AnnaBridge	172:65be27845400	413	#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /!< SYSCLK to configure /
AnnaBridge	172:65be27845400	414	#define RCC_CLOCKTYPE_HCLK 0x00000002U /!< HCLK to configure /
AnnaBridge	172:65be27845400	415	#define RCC_CLOCKTYPE_PCLK1 0x00000004U /!< PCLK1 to configure /
AnnaBridge	172:65be27845400	416	#define RCC_CLOCKTYPE_PCLK2 0x00000008U /!< PCLK2 to configure /
AnnaBridge	172:65be27845400	417	/**
AnnaBridge	172:65be27845400	418	* @}
AnnaBridge	172:65be27845400	419	*/
AnnaBridge	172:65be27845400	420
AnnaBridge	172:65be27845400	421	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	172:65be27845400	422	* @{
AnnaBridge	172:65be27845400	423	*/
AnnaBridge	172:65be27845400	424	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	172:65be27845400	425	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	172:65be27845400	426	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	172:65be27845400	427	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	172:65be27845400	428	/**
AnnaBridge	172:65be27845400	429	* @}
AnnaBridge	172:65be27845400	430	*/
AnnaBridge	172:65be27845400	431
AnnaBridge	172:65be27845400	432	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	172:65be27845400	433	* @{
AnnaBridge	172:65be27845400	434	*/
AnnaBridge	172:65be27845400	435	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	172:65be27845400	436	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	172:65be27845400	437	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	172:65be27845400	438	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	172:65be27845400	439	/**
AnnaBridge	172:65be27845400	440	* @}
AnnaBridge	172:65be27845400	441	*/
AnnaBridge	172:65be27845400	442
AnnaBridge	172:65be27845400	443	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	172:65be27845400	444	* @{
AnnaBridge	172:65be27845400	445	*/
AnnaBridge	172:65be27845400	446	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	172:65be27845400	447	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	172:65be27845400	448	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	172:65be27845400	449	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	172:65be27845400	450	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	172:65be27845400	451	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	172:65be27845400	452	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	172:65be27845400	453	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	172:65be27845400	454	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	172:65be27845400	455	/**
AnnaBridge	172:65be27845400	456	* @}
AnnaBridge	172:65be27845400	457	*/
AnnaBridge	172:65be27845400	458
AnnaBridge	172:65be27845400	459	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge	172:65be27845400	460	* @{
AnnaBridge	172:65be27845400	461	*/
AnnaBridge	172:65be27845400	462	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	172:65be27845400	463	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	172:65be27845400	464	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	172:65be27845400	465	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	172:65be27845400	466	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	172:65be27845400	467	/**
AnnaBridge	172:65be27845400	468	* @}
AnnaBridge	172:65be27845400	469	*/
AnnaBridge	172:65be27845400	470
AnnaBridge	172:65be27845400	471	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge	172:65be27845400	472	* @{
AnnaBridge	172:65be27845400	473	*/
AnnaBridge	172:65be27845400	474	#define RCC_RTCCLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	172:65be27845400	475	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	172:65be27845400	476	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	172:65be27845400	477	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
AnnaBridge	172:65be27845400	478	/**
AnnaBridge	172:65be27845400	479	* @}
AnnaBridge	172:65be27845400	480	*/
AnnaBridge	172:65be27845400	481
AnnaBridge	172:65be27845400	482	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	172:65be27845400	483	* @{
AnnaBridge	172:65be27845400	484	*/
AnnaBridge	172:65be27845400	485	#define RCC_MCO1 0x00000000U
AnnaBridge	172:65be27845400	486	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
AnnaBridge	172:65be27845400	487	/**
AnnaBridge	172:65be27845400	488	* @}
AnnaBridge	172:65be27845400	489	*/
AnnaBridge	172:65be27845400	490
AnnaBridge	172:65be27845400	491	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge	172:65be27845400	492	* @{
AnnaBridge	172:65be27845400	493	*/
AnnaBridge	172:65be27845400	494	#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /!< MCO1 output disabled, no clock on MCO1 /
AnnaBridge	172:65be27845400	495	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
AnnaBridge	172:65be27845400	496	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
AnnaBridge	172:65be27845400	497	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
AnnaBridge	172:65be27845400	498	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
AnnaBridge	172:65be27845400	499	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
AnnaBridge	172:65be27845400	500	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
AnnaBridge	172:65be27845400	501	#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
AnnaBridge	172:65be27845400	502	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	503	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) /
AnnaBridge	172:65be27845400	504	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	505	/**
AnnaBridge	172:65be27845400	506	* @}
AnnaBridge	172:65be27845400	507	*/
AnnaBridge	172:65be27845400	508
AnnaBridge	172:65be27845400	509	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
AnnaBridge	172:65be27845400	510	* @{
AnnaBridge	172:65be27845400	511	*/
AnnaBridge	172:65be27845400	512	#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
AnnaBridge	172:65be27845400	513	#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
AnnaBridge	172:65be27845400	514	#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
AnnaBridge	172:65be27845400	515	#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
AnnaBridge	172:65be27845400	516	#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
AnnaBridge	172:65be27845400	517	/**
AnnaBridge	172:65be27845400	518	* @}
AnnaBridge	172:65be27845400	519	*/
AnnaBridge	172:65be27845400	520
AnnaBridge	172:65be27845400	521	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	172:65be27845400	522	* @{
AnnaBridge	172:65be27845400	523	*/
AnnaBridge	172:65be27845400	524	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	172:65be27845400	525	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	172:65be27845400	526	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	172:65be27845400	527	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /!< HSI16 Ready Interrupt flag /
AnnaBridge	172:65be27845400	528	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	172:65be27845400	529	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	172:65be27845400	530	#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
AnnaBridge	172:65be27845400	531	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	532	#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
AnnaBridge	172:65be27845400	533	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	534	#define RCC_IT_CSS RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	172:65be27845400	535	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	172:65be27845400	536	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	537	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	172:65be27845400	538	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	539	/**
AnnaBridge	172:65be27845400	540	* @}
AnnaBridge	172:65be27845400	541	*/
AnnaBridge	172:65be27845400	542
AnnaBridge	172:65be27845400	543	/** @defgroup RCC_Flag Flags
AnnaBridge	172:65be27845400	544	* Elements values convention: XXXYYYYYb
AnnaBridge	172:65be27845400	545	* - YYYYY : Flag position in the register
AnnaBridge	172:65be27845400	546	* - XXX : Register index
AnnaBridge	172:65be27845400	547	* - 001: CR register
AnnaBridge	172:65be27845400	548	* - 010: BDCR register
AnnaBridge	172:65be27845400	549	* - 011: CSR register
AnnaBridge	172:65be27845400	550	* - 100: CRRCR register
AnnaBridge	172:65be27845400	551	* @{
AnnaBridge	172:65be27845400	552	*/
AnnaBridge	172:65be27845400	553	/* Flags in the CR register */
AnnaBridge	172:65be27845400	554	#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) \| RCC_CR_MSIRDY_Pos) /!< MSI Ready flag /
AnnaBridge	172:65be27845400	555	#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) \| RCC_CR_HSIRDY_Pos) /!< HSI Ready flag /
AnnaBridge	172:65be27845400	556	#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) \| RCC_CR_HSERDY_Pos) /!< HSE Ready flag /
AnnaBridge	172:65be27845400	557	#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) \| RCC_CR_PLLRDY_Pos) /!< PLL Ready flag /
AnnaBridge	172:65be27845400	558	#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) \| RCC_CR_PLLSAI1RDY_Pos) /!< PLLSAI1 Ready flag /
AnnaBridge	172:65be27845400	559	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	560	#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) \| RCC_CR_PLLSAI2RDY_Pos) /!< PLLSAI2 Ready flag /
AnnaBridge	172:65be27845400	561	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	/* Flags in the BDCR register */
AnnaBridge	172:65be27845400	564	#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) \| RCC_BDCR_LSERDY_Pos) /!< LSE Ready flag /
AnnaBridge	172:65be27845400	565	#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) \| RCC_BDCR_LSECSSD_Pos) /!< LSE Clock Security System Interrupt flag /
AnnaBridge	172:65be27845400	566
AnnaBridge	172:65be27845400	567	/* Flags in the CSR register */
AnnaBridge	172:65be27845400	568	#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) \| RCC_CSR_LSIRDY_Pos) /!< LSI Ready flag /
AnnaBridge	172:65be27845400	569	#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) \| RCC_CSR_RMVF_Pos) /!< Remove reset flag /
AnnaBridge	172:65be27845400	570	#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_FWRSTF_Pos) /!< Firewall reset flag /
AnnaBridge	172:65be27845400	571	#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_OBLRSTF_Pos) /!< Option Byte Loader reset flag /
AnnaBridge	172:65be27845400	572	#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_PINRSTF_Pos) /!< PIN reset flag /
AnnaBridge	172:65be27845400	573	#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_BORRSTF_Pos) /!< BOR reset flag /
AnnaBridge	172:65be27845400	574	#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_SFTRSTF_Pos) /!< Software Reset flag /
AnnaBridge	172:65be27845400	575	#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_IWDGRSTF_Pos) /!< Independent Watchdog reset flag /
AnnaBridge	172:65be27845400	576	#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_WWDGRSTF_Pos) /!< Window watchdog reset flag /
AnnaBridge	172:65be27845400	577	#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) \| RCC_CSR_LPWRRSTF_Pos) /!< Low-Power reset flag /
AnnaBridge	172:65be27845400	578
AnnaBridge	172:65be27845400	579	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	580	/* Flags in the CRRCR register */
AnnaBridge	172:65be27845400	581	#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) \| RCC_CRRCR_HSI48RDY_Pos) /!< HSI48 Ready flag /
AnnaBridge	172:65be27845400	582	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	583	/**
AnnaBridge	172:65be27845400	584	* @}
AnnaBridge	172:65be27845400	585	*/
AnnaBridge	172:65be27845400	586
AnnaBridge	172:65be27845400	587	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
AnnaBridge	172:65be27845400	588	* @{
AnnaBridge	172:65be27845400	589	*/
AnnaBridge	172:65be27845400	590	#define RCC_LSEDRIVE_LOW 0x00000000U /!< LSE low drive capability /
AnnaBridge	172:65be27845400	591	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< LSE medium low drive capability /
AnnaBridge	172:65be27845400	592	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< LSE medium high drive capability /
AnnaBridge	172:65be27845400	593	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
AnnaBridge	172:65be27845400	594	/**
AnnaBridge	172:65be27845400	595	* @}
AnnaBridge	172:65be27845400	596	*/
AnnaBridge	172:65be27845400	597
AnnaBridge	172:65be27845400	598	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
AnnaBridge	172:65be27845400	599	* @{
AnnaBridge	172:65be27845400	600	*/
AnnaBridge	172:65be27845400	601	#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /!< MSI selection after wake-up from STOP /
AnnaBridge	172:65be27845400	602	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
AnnaBridge	172:65be27845400	603	/**
AnnaBridge	172:65be27845400	604	* @}
AnnaBridge	172:65be27845400	605	*/
AnnaBridge	172:65be27845400	606
AnnaBridge	172:65be27845400	607	/**
AnnaBridge	172:65be27845400	608	* @}
AnnaBridge	172:65be27845400	609	*/
AnnaBridge	172:65be27845400	610
AnnaBridge	172:65be27845400	611	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	172:65be27845400	612
AnnaBridge	172:65be27845400	613	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	172:65be27845400	614	* @{
AnnaBridge	172:65be27845400	615	*/
AnnaBridge	172:65be27845400	616
AnnaBridge	172:65be27845400	617	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	172:65be27845400	618	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	172:65be27845400	619	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	620	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	621	* using it.
AnnaBridge	172:65be27845400	622	* @{
AnnaBridge	172:65be27845400	623	*/
AnnaBridge	172:65be27845400	624
AnnaBridge	172:65be27845400	625	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	626	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	627	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
AnnaBridge	172:65be27845400	628	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	629	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
AnnaBridge	172:65be27845400	630	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	631	} while(0)
AnnaBridge	172:65be27845400	632
AnnaBridge	172:65be27845400	633	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	634	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	635	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
AnnaBridge	172:65be27845400	636	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	637	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
AnnaBridge	172:65be27845400	638	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	639	} while(0)
AnnaBridge	172:65be27845400	640
AnnaBridge	172:65be27845400	641	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	642	#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	643	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	644	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
AnnaBridge	172:65be27845400	645	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	646	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
AnnaBridge	172:65be27845400	647	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	648	} while(0)
AnnaBridge	172:65be27845400	649	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	650
AnnaBridge	172:65be27845400	651	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	652	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	653	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
AnnaBridge	172:65be27845400	654	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	655	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
AnnaBridge	172:65be27845400	656	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	657	} while(0)
AnnaBridge	172:65be27845400	658
AnnaBridge	172:65be27845400	659	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	660	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	661	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
AnnaBridge	172:65be27845400	662	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	663	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
AnnaBridge	172:65be27845400	664	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	665	} while(0)
AnnaBridge	172:65be27845400	666
AnnaBridge	172:65be27845400	667	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	668	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	669	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
AnnaBridge	172:65be27845400	670	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	671	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
AnnaBridge	172:65be27845400	672	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	673	} while(0)
AnnaBridge	172:65be27845400	674
AnnaBridge	172:65be27845400	675	#if defined(DMA2D)
AnnaBridge	172:65be27845400	676	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	677	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	678	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge	172:65be27845400	679	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	680	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge	172:65be27845400	681	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	682	} while(0)
AnnaBridge	172:65be27845400	683	#endif /* DMA2D */
AnnaBridge	172:65be27845400	684
AnnaBridge	172:65be27845400	685	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	686	#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	687	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	688	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
AnnaBridge	172:65be27845400	689	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	690	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
AnnaBridge	172:65be27845400	691	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	692	} while(0)
AnnaBridge	172:65be27845400	693	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	694
AnnaBridge	172:65be27845400	695
AnnaBridge	172:65be27845400	696	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
AnnaBridge	172:65be27845400	697
AnnaBridge	172:65be27845400	698	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
AnnaBridge	172:65be27845400	699
AnnaBridge	172:65be27845400	700	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	701	#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
AnnaBridge	172:65be27845400	702	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	703
AnnaBridge	172:65be27845400	704	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
AnnaBridge	172:65be27845400	705
AnnaBridge	172:65be27845400	706	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
AnnaBridge	172:65be27845400	707
AnnaBridge	172:65be27845400	708	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
AnnaBridge	172:65be27845400	709
AnnaBridge	172:65be27845400	710	#if defined(DMA2D)
AnnaBridge	172:65be27845400	711	#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
AnnaBridge	172:65be27845400	712	#endif /* DMA2D */
AnnaBridge	172:65be27845400	713
AnnaBridge	172:65be27845400	714	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	715	#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)
AnnaBridge	172:65be27845400	716	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	717
AnnaBridge	172:65be27845400	718	/**
AnnaBridge	172:65be27845400	719	* @}
AnnaBridge	172:65be27845400	720	*/
AnnaBridge	172:65be27845400	721
AnnaBridge	172:65be27845400	722	/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	172:65be27845400	723	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	172:65be27845400	724	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	725	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	726	* using it.
AnnaBridge	172:65be27845400	727	* @{
AnnaBridge	172:65be27845400	728	*/
AnnaBridge	172:65be27845400	729
AnnaBridge	172:65be27845400	730	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	731	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	732	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
AnnaBridge	172:65be27845400	733	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	734	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
AnnaBridge	172:65be27845400	735	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	736	} while(0)
AnnaBridge	172:65be27845400	737
AnnaBridge	172:65be27845400	738	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	739	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	740	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
AnnaBridge	172:65be27845400	741	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	742	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
AnnaBridge	172:65be27845400	743	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	744	} while(0)
AnnaBridge	172:65be27845400	745
AnnaBridge	172:65be27845400	746	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	747	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	748	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
AnnaBridge	172:65be27845400	749	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	750	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
AnnaBridge	172:65be27845400	751	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	752	} while(0)
AnnaBridge	172:65be27845400	753
AnnaBridge	172:65be27845400	754	#if defined(GPIOD)
AnnaBridge	172:65be27845400	755	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	756	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	757	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
AnnaBridge	172:65be27845400	758	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	759	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
AnnaBridge	172:65be27845400	760	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	761	} while(0)
AnnaBridge	172:65be27845400	762	#endif /* GPIOD */
AnnaBridge	172:65be27845400	763
AnnaBridge	172:65be27845400	764	#if defined(GPIOE)
AnnaBridge	172:65be27845400	765	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	766	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	767	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
AnnaBridge	172:65be27845400	768	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	769	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
AnnaBridge	172:65be27845400	770	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	771	} while(0)
AnnaBridge	172:65be27845400	772	#endif /* GPIOE */
AnnaBridge	172:65be27845400	773
AnnaBridge	172:65be27845400	774	#if defined(GPIOF)
AnnaBridge	172:65be27845400	775	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	776	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	777	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
AnnaBridge	172:65be27845400	778	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	779	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
AnnaBridge	172:65be27845400	780	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	781	} while(0)
AnnaBridge	172:65be27845400	782	#endif /* GPIOF */
AnnaBridge	172:65be27845400	783
AnnaBridge	172:65be27845400	784	#if defined(GPIOG)
AnnaBridge	172:65be27845400	785	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	786	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	787	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
AnnaBridge	172:65be27845400	788	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	789	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
AnnaBridge	172:65be27845400	790	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	791	} while(0)
AnnaBridge	172:65be27845400	792	#endif /* GPIOG */
AnnaBridge	172:65be27845400	793
AnnaBridge	172:65be27845400	794	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	795	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	796	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
AnnaBridge	172:65be27845400	797	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	798	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
AnnaBridge	172:65be27845400	799	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	800	} while(0)
AnnaBridge	172:65be27845400	801
AnnaBridge	172:65be27845400	802	#if defined(GPIOI)
AnnaBridge	172:65be27845400	803	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	804	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	805	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge	172:65be27845400	806	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	807	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge	172:65be27845400	808	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	809	} while(0)
AnnaBridge	172:65be27845400	810	#endif /* GPIOI */
AnnaBridge	172:65be27845400	811
AnnaBridge	172:65be27845400	812	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	813	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	814	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	815	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
AnnaBridge	172:65be27845400	816	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	817	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
AnnaBridge	172:65be27845400	818	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	819	} while(0)
AnnaBridge	172:65be27845400	820	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	821
AnnaBridge	172:65be27845400	822	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	823	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	824	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
AnnaBridge	172:65be27845400	825	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	826	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
AnnaBridge	172:65be27845400	827	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	828	} while(0)
AnnaBridge	172:65be27845400	829
AnnaBridge	172:65be27845400	830	#if defined(DCMI)
AnnaBridge	172:65be27845400	831	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	832	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	833	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge	172:65be27845400	834	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	835	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge	172:65be27845400	836	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	837	} while(0)
AnnaBridge	172:65be27845400	838	#endif /* DCMI */
AnnaBridge	172:65be27845400	839
AnnaBridge	172:65be27845400	840	#if defined(AES)
AnnaBridge	172:65be27845400	841	#define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	842	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	843	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
AnnaBridge	172:65be27845400	844	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	845	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
AnnaBridge	172:65be27845400	846	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	847	} while(0)
AnnaBridge	172:65be27845400	848	#endif /* AES */
AnnaBridge	172:65be27845400	849
AnnaBridge	172:65be27845400	850	#if defined(HASH)
AnnaBridge	172:65be27845400	851	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	852	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	853	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge	172:65be27845400	854	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	855	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge	172:65be27845400	856	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	857	} while(0)
AnnaBridge	172:65be27845400	858	#endif /* HASH */
AnnaBridge	172:65be27845400	859
AnnaBridge	172:65be27845400	860	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	861	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	862	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
AnnaBridge	172:65be27845400	863	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	864	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
AnnaBridge	172:65be27845400	865	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	866	} while(0)
AnnaBridge	172:65be27845400	867
AnnaBridge	172:65be27845400	868	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	869	#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	870	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	871	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
AnnaBridge	172:65be27845400	872	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	873	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
AnnaBridge	172:65be27845400	874	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	875	} while(0)
AnnaBridge	172:65be27845400	876	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	877
AnnaBridge	172:65be27845400	878	#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	879	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	880	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	881	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
AnnaBridge	172:65be27845400	882	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	883	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
AnnaBridge	172:65be27845400	884	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	885	} while(0)
AnnaBridge	172:65be27845400	886	#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
AnnaBridge	172:65be27845400	887
AnnaBridge	172:65be27845400	888
AnnaBridge	172:65be27845400	889	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
AnnaBridge	172:65be27845400	890
AnnaBridge	172:65be27845400	891	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
AnnaBridge	172:65be27845400	892
AnnaBridge	172:65be27845400	893	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
AnnaBridge	172:65be27845400	894
AnnaBridge	172:65be27845400	895	#if defined(GPIOD)
AnnaBridge	172:65be27845400	896	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
AnnaBridge	172:65be27845400	897	#endif /* GPIOD */
AnnaBridge	172:65be27845400	898
AnnaBridge	172:65be27845400	899	#if defined(GPIOE)
AnnaBridge	172:65be27845400	900	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
AnnaBridge	172:65be27845400	901	#endif /* GPIOE */
AnnaBridge	172:65be27845400	902
AnnaBridge	172:65be27845400	903	#if defined(GPIOF)
AnnaBridge	172:65be27845400	904	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
AnnaBridge	172:65be27845400	905	#endif /* GPIOF */
AnnaBridge	172:65be27845400	906
AnnaBridge	172:65be27845400	907	#if defined(GPIOG)
AnnaBridge	172:65be27845400	908	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
AnnaBridge	172:65be27845400	909	#endif /* GPIOG */
AnnaBridge	172:65be27845400	910
AnnaBridge	172:65be27845400	911	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
AnnaBridge	172:65be27845400	912
AnnaBridge	172:65be27845400	913	#if defined(GPIOI)
AnnaBridge	172:65be27845400	914	#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
AnnaBridge	172:65be27845400	915	#endif /* GPIOI */
AnnaBridge	172:65be27845400	916
AnnaBridge	172:65be27845400	917	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	918	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
AnnaBridge	172:65be27845400	919	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	920
AnnaBridge	172:65be27845400	921	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
AnnaBridge	172:65be27845400	922
AnnaBridge	172:65be27845400	923	#if defined(DCMI)
AnnaBridge	172:65be27845400	924	#define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
AnnaBridge	172:65be27845400	925	#endif /* DCMI */
AnnaBridge	172:65be27845400	926
AnnaBridge	172:65be27845400	927	#if defined(AES)
AnnaBridge	172:65be27845400	928	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
AnnaBridge	172:65be27845400	929	#endif /* AES */
AnnaBridge	172:65be27845400	930
AnnaBridge	172:65be27845400	931	#if defined(HASH)
AnnaBridge	172:65be27845400	932	#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
AnnaBridge	172:65be27845400	933	#endif /* HASH */
AnnaBridge	172:65be27845400	934
AnnaBridge	172:65be27845400	935	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
AnnaBridge	172:65be27845400	936
AnnaBridge	172:65be27845400	937	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	938	#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)
AnnaBridge	172:65be27845400	939	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	940
AnnaBridge	172:65be27845400	941	#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	942	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	943	#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
AnnaBridge	172:65be27845400	944
AnnaBridge	172:65be27845400	945	/**
AnnaBridge	172:65be27845400	946	* @}
AnnaBridge	172:65be27845400	947	*/
AnnaBridge	172:65be27845400	948
AnnaBridge	172:65be27845400	949	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	172:65be27845400	950	* @brief Enable or disable the AHB3 peripheral clock.
AnnaBridge	172:65be27845400	951	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	952	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	953	* using it.
AnnaBridge	172:65be27845400	954	* @{
AnnaBridge	172:65be27845400	955	*/
AnnaBridge	172:65be27845400	956
AnnaBridge	172:65be27845400	957	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	958	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	959	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	960	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
AnnaBridge	172:65be27845400	961	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	962	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
AnnaBridge	172:65be27845400	963	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	964	} while(0)
AnnaBridge	172:65be27845400	965	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	966
AnnaBridge	172:65be27845400	967	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	968	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	969	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	970	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
AnnaBridge	172:65be27845400	971	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	972	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
AnnaBridge	172:65be27845400	973	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	974	} while(0)
AnnaBridge	172:65be27845400	975	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	976
AnnaBridge	172:65be27845400	977	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	978	#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	979	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	980	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
AnnaBridge	172:65be27845400	981	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	982	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
AnnaBridge	172:65be27845400	983	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	984	} while(0)
AnnaBridge	172:65be27845400	985	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	986
AnnaBridge	172:65be27845400	987	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	988	#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	989	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	990	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
AnnaBridge	172:65be27845400	991	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	992	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
AnnaBridge	172:65be27845400	993	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	994	} while(0)
AnnaBridge	172:65be27845400	995	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	996
AnnaBridge	172:65be27845400	997	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	998	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
AnnaBridge	172:65be27845400	999	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	1000
AnnaBridge	172:65be27845400	1001	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	1002	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
AnnaBridge	172:65be27845400	1003	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	1004
AnnaBridge	172:65be27845400	1005	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	1006	#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)
AnnaBridge	172:65be27845400	1007	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	1008
AnnaBridge	172:65be27845400	1009	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	1010	#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)
AnnaBridge	172:65be27845400	1011	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	1012
AnnaBridge	172:65be27845400	1013	/**
AnnaBridge	172:65be27845400	1014	* @}
AnnaBridge	172:65be27845400	1015	*/
AnnaBridge	172:65be27845400	1016
AnnaBridge	172:65be27845400	1017	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	172:65be27845400	1018	* @brief Enable or disable the APB1 peripheral clock.
AnnaBridge	172:65be27845400	1019	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1020	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1021	* using it.
AnnaBridge	172:65be27845400	1022	* @{
AnnaBridge	172:65be27845400	1023	*/
AnnaBridge	172:65be27845400	1024
AnnaBridge	172:65be27845400	1025	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1026	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1027	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
AnnaBridge	172:65be27845400	1028	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1029	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
AnnaBridge	172:65be27845400	1030	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1031	} while(0)
AnnaBridge	172:65be27845400	1032
AnnaBridge	172:65be27845400	1033	#if defined(TIM3)
AnnaBridge	172:65be27845400	1034	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1035	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1036	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
AnnaBridge	172:65be27845400	1037	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1038	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
AnnaBridge	172:65be27845400	1039	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1040	} while(0)
AnnaBridge	172:65be27845400	1041	#endif /* TIM3 */
AnnaBridge	172:65be27845400	1042
AnnaBridge	172:65be27845400	1043	#if defined(TIM4)
AnnaBridge	172:65be27845400	1044	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1045	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1046	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
AnnaBridge	172:65be27845400	1047	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1048	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
AnnaBridge	172:65be27845400	1049	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1050	} while(0)
AnnaBridge	172:65be27845400	1051	#endif /* TIM4 */
AnnaBridge	172:65be27845400	1052
AnnaBridge	172:65be27845400	1053	#if defined(TIM5)
AnnaBridge	172:65be27845400	1054	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1055	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1056	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
AnnaBridge	172:65be27845400	1057	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1058	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
AnnaBridge	172:65be27845400	1059	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1060	} while(0)
AnnaBridge	172:65be27845400	1061	#endif /* TIM5 */
AnnaBridge	172:65be27845400	1062
AnnaBridge	172:65be27845400	1063	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1064	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1065	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
AnnaBridge	172:65be27845400	1066	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1067	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
AnnaBridge	172:65be27845400	1068	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1069	} while(0)
AnnaBridge	172:65be27845400	1070
AnnaBridge	172:65be27845400	1071	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1072	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1073	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
AnnaBridge	172:65be27845400	1074	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1075	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
AnnaBridge	172:65be27845400	1076	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1077	} while(0)
AnnaBridge	172:65be27845400	1078
AnnaBridge	172:65be27845400	1079	#if defined(LCD)
AnnaBridge	172:65be27845400	1080	#define __HAL_RCC_LCD_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1081	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1082	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
AnnaBridge	172:65be27845400	1083	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1084	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
AnnaBridge	172:65be27845400	1085	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1086	} while(0)
AnnaBridge	172:65be27845400	1087	#endif /* LCD */
AnnaBridge	172:65be27845400	1088
AnnaBridge	172:65be27845400	1089	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	172:65be27845400	1090	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1091	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1092	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
AnnaBridge	172:65be27845400	1093	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1094	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
AnnaBridge	172:65be27845400	1095	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1096	} while(0)
AnnaBridge	172:65be27845400	1097	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	172:65be27845400	1098
AnnaBridge	172:65be27845400	1099	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1100	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1101	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
AnnaBridge	172:65be27845400	1102	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1103	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
AnnaBridge	172:65be27845400	1104	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1105	} while(0)
AnnaBridge	172:65be27845400	1106
AnnaBridge	172:65be27845400	1107	#if defined(SPI2)
AnnaBridge	172:65be27845400	1108	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1109	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1110	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
AnnaBridge	172:65be27845400	1111	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1112	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
AnnaBridge	172:65be27845400	1113	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1114	} while(0)
AnnaBridge	172:65be27845400	1115	#endif /* SPI2 */
AnnaBridge	172:65be27845400	1116
AnnaBridge	172:65be27845400	1117	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1118	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1119	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
AnnaBridge	172:65be27845400	1120	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1121	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
AnnaBridge	172:65be27845400	1122	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1123	} while(0)
AnnaBridge	172:65be27845400	1124
AnnaBridge	172:65be27845400	1125	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1126	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1127	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
AnnaBridge	172:65be27845400	1128	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1129	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
AnnaBridge	172:65be27845400	1130	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1131	} while(0)
AnnaBridge	172:65be27845400	1132
AnnaBridge	172:65be27845400	1133	#if defined(USART3)
AnnaBridge	172:65be27845400	1134	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1135	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1136	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
AnnaBridge	172:65be27845400	1137	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1138	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
AnnaBridge	172:65be27845400	1139	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1140	} while(0)
AnnaBridge	172:65be27845400	1141	#endif /* USART3 */
AnnaBridge	172:65be27845400	1142
AnnaBridge	172:65be27845400	1143	#if defined(UART4)
AnnaBridge	172:65be27845400	1144	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1145	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1146	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
AnnaBridge	172:65be27845400	1147	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1148	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
AnnaBridge	172:65be27845400	1149	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1150	} while(0)
AnnaBridge	172:65be27845400	1151	#endif /* UART4 */
AnnaBridge	172:65be27845400	1152
AnnaBridge	172:65be27845400	1153	#if defined(UART5)
AnnaBridge	172:65be27845400	1154	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1155	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1156	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
AnnaBridge	172:65be27845400	1157	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1158	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
AnnaBridge	172:65be27845400	1159	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1160	} while(0)
AnnaBridge	172:65be27845400	1161	#endif /* UART5 */
AnnaBridge	172:65be27845400	1162
AnnaBridge	172:65be27845400	1163	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1164	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1165	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
AnnaBridge	172:65be27845400	1166	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1167	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
AnnaBridge	172:65be27845400	1168	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1169	} while(0)
AnnaBridge	172:65be27845400	1170
AnnaBridge	172:65be27845400	1171	#if defined(I2C2)
AnnaBridge	172:65be27845400	1172	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1173	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1174	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
AnnaBridge	172:65be27845400	1175	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1176	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
AnnaBridge	172:65be27845400	1177	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1178	} while(0)
AnnaBridge	172:65be27845400	1179	#endif /* I2C2 */
AnnaBridge	172:65be27845400	1180
AnnaBridge	172:65be27845400	1181	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1182	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1183	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
AnnaBridge	172:65be27845400	1184	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1185	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
AnnaBridge	172:65be27845400	1186	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1187	} while(0)
AnnaBridge	172:65be27845400	1188
AnnaBridge	172:65be27845400	1189	#if defined(I2C4)
AnnaBridge	172:65be27845400	1190	#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1191	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1192	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge	172:65be27845400	1193	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1194	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge	172:65be27845400	1195	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1196	} while(0)
AnnaBridge	172:65be27845400	1197	#endif /* I2C4 */
AnnaBridge	172:65be27845400	1198
AnnaBridge	172:65be27845400	1199	#if defined(CRS)
AnnaBridge	172:65be27845400	1200	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1201	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1202	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
AnnaBridge	172:65be27845400	1203	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1204	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
AnnaBridge	172:65be27845400	1205	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1206	} while(0)
AnnaBridge	172:65be27845400	1207	#endif /* CRS */
AnnaBridge	172:65be27845400	1208
AnnaBridge	172:65be27845400	1209	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1210	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1211	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
AnnaBridge	172:65be27845400	1212	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1213	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
AnnaBridge	172:65be27845400	1214	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1215	} while(0)
AnnaBridge	172:65be27845400	1216
AnnaBridge	172:65be27845400	1217	#if defined(CAN2)
AnnaBridge	172:65be27845400	1218	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1219	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1220	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge	172:65be27845400	1221	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1222	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge	172:65be27845400	1223	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1224	} while(0)
AnnaBridge	172:65be27845400	1225	#endif /* CAN2 */
AnnaBridge	172:65be27845400	1226
AnnaBridge	172:65be27845400	1227	#if defined(USB)
AnnaBridge	172:65be27845400	1228	#define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1229	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1230	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
AnnaBridge	172:65be27845400	1231	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1232	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
AnnaBridge	172:65be27845400	1233	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1234	} while(0)
AnnaBridge	172:65be27845400	1235	#endif /* USB */
AnnaBridge	172:65be27845400	1236
AnnaBridge	172:65be27845400	1237	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1238	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1239	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
AnnaBridge	172:65be27845400	1240	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1241	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
AnnaBridge	172:65be27845400	1242	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1243	} while(0)
AnnaBridge	172:65be27845400	1244
AnnaBridge	172:65be27845400	1245	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1246	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1247	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
AnnaBridge	172:65be27845400	1248	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1249	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
AnnaBridge	172:65be27845400	1250	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1251	} while(0)
AnnaBridge	172:65be27845400	1252
AnnaBridge	172:65be27845400	1253	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1254	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1255	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
AnnaBridge	172:65be27845400	1256	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1257	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
AnnaBridge	172:65be27845400	1258	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1259	} while(0)
AnnaBridge	172:65be27845400	1260
AnnaBridge	172:65be27845400	1261	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1262	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1263	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
AnnaBridge	172:65be27845400	1264	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1265	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
AnnaBridge	172:65be27845400	1266	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1267	} while(0)
AnnaBridge	172:65be27845400	1268
AnnaBridge	172:65be27845400	1269	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1270	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1271	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
AnnaBridge	172:65be27845400	1272	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1273	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
AnnaBridge	172:65be27845400	1274	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1275	} while(0)
AnnaBridge	172:65be27845400	1276
AnnaBridge	172:65be27845400	1277	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	1278	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1279	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1280	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
AnnaBridge	172:65be27845400	1281	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1282	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
AnnaBridge	172:65be27845400	1283	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1284	} while(0)
AnnaBridge	172:65be27845400	1285	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	1286
AnnaBridge	172:65be27845400	1287	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1288	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1289	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
AnnaBridge	172:65be27845400	1290	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1291	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
AnnaBridge	172:65be27845400	1292	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1293	} while(0)
AnnaBridge	172:65be27845400	1294
AnnaBridge	172:65be27845400	1295
AnnaBridge	172:65be27845400	1296	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
AnnaBridge	172:65be27845400	1297
AnnaBridge	172:65be27845400	1298	#if defined(TIM3)
AnnaBridge	172:65be27845400	1299	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
AnnaBridge	172:65be27845400	1300	#endif /* TIM3 */
AnnaBridge	172:65be27845400	1301
AnnaBridge	172:65be27845400	1302	#if defined(TIM4)
AnnaBridge	172:65be27845400	1303	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
AnnaBridge	172:65be27845400	1304	#endif /* TIM4 */
AnnaBridge	172:65be27845400	1305
AnnaBridge	172:65be27845400	1306	#if defined(TIM5)
AnnaBridge	172:65be27845400	1307	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
AnnaBridge	172:65be27845400	1308	#endif /* TIM5 */
AnnaBridge	172:65be27845400	1309
AnnaBridge	172:65be27845400	1310	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
AnnaBridge	172:65be27845400	1311
AnnaBridge	172:65be27845400	1312	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
AnnaBridge	172:65be27845400	1313
AnnaBridge	172:65be27845400	1314	#if defined(LCD)
AnnaBridge	172:65be27845400	1315	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
AnnaBridge	172:65be27845400	1316	#endif /* LCD */
AnnaBridge	172:65be27845400	1317
AnnaBridge	172:65be27845400	1318	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	172:65be27845400	1319	#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
AnnaBridge	172:65be27845400	1320	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	172:65be27845400	1321
AnnaBridge	172:65be27845400	1322	#if defined(SPI2)
AnnaBridge	172:65be27845400	1323	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
AnnaBridge	172:65be27845400	1324	#endif /* SPI2 */
AnnaBridge	172:65be27845400	1325
AnnaBridge	172:65be27845400	1326	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
AnnaBridge	172:65be27845400	1327
AnnaBridge	172:65be27845400	1328	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
AnnaBridge	172:65be27845400	1329
AnnaBridge	172:65be27845400	1330	#if defined(USART3)
AnnaBridge	172:65be27845400	1331	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
AnnaBridge	172:65be27845400	1332	#endif /* USART3 */
AnnaBridge	172:65be27845400	1333
AnnaBridge	172:65be27845400	1334	#if defined(UART4)
AnnaBridge	172:65be27845400	1335	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
AnnaBridge	172:65be27845400	1336	#endif /* UART4 */
AnnaBridge	172:65be27845400	1337
AnnaBridge	172:65be27845400	1338	#if defined(UART5)
AnnaBridge	172:65be27845400	1339	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
AnnaBridge	172:65be27845400	1340	#endif /* UART5 */
AnnaBridge	172:65be27845400	1341
AnnaBridge	172:65be27845400	1342	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
AnnaBridge	172:65be27845400	1343
AnnaBridge	172:65be27845400	1344	#if defined(I2C2)
AnnaBridge	172:65be27845400	1345	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
AnnaBridge	172:65be27845400	1346	#endif /* I2C2 */
AnnaBridge	172:65be27845400	1347
AnnaBridge	172:65be27845400	1348	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
AnnaBridge	172:65be27845400	1349
AnnaBridge	172:65be27845400	1350	#if defined(I2C4)
AnnaBridge	172:65be27845400	1351	#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
AnnaBridge	172:65be27845400	1352	#endif /* I2C4 */
AnnaBridge	172:65be27845400	1353
AnnaBridge	172:65be27845400	1354	#if defined(CRS)
AnnaBridge	172:65be27845400	1355	#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
AnnaBridge	172:65be27845400	1356	#endif /* CRS */
AnnaBridge	172:65be27845400	1357
AnnaBridge	172:65be27845400	1358	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
AnnaBridge	172:65be27845400	1359
AnnaBridge	172:65be27845400	1360	#if defined(CAN2)
AnnaBridge	172:65be27845400	1361	#define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
AnnaBridge	172:65be27845400	1362	#endif /* CAN2 */
AnnaBridge	172:65be27845400	1363
AnnaBridge	172:65be27845400	1364	#if defined(USB)
AnnaBridge	172:65be27845400	1365	#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
AnnaBridge	172:65be27845400	1366	#endif /* USB */
AnnaBridge	172:65be27845400	1367
AnnaBridge	172:65be27845400	1368	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
AnnaBridge	172:65be27845400	1369
AnnaBridge	172:65be27845400	1370	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
AnnaBridge	172:65be27845400	1371
AnnaBridge	172:65be27845400	1372	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
AnnaBridge	172:65be27845400	1373
AnnaBridge	172:65be27845400	1374	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
AnnaBridge	172:65be27845400	1375
AnnaBridge	172:65be27845400	1376	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
AnnaBridge	172:65be27845400	1377
AnnaBridge	172:65be27845400	1378	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	1379	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
AnnaBridge	172:65be27845400	1380	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	1381
AnnaBridge	172:65be27845400	1382	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
AnnaBridge	172:65be27845400	1383
AnnaBridge	172:65be27845400	1384	/**
AnnaBridge	172:65be27845400	1385	* @}
AnnaBridge	172:65be27845400	1386	*/
AnnaBridge	172:65be27845400	1387
AnnaBridge	172:65be27845400	1388	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	172:65be27845400	1389	* @brief Enable or disable the APB2 peripheral clock.
AnnaBridge	172:65be27845400	1390	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1391	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1392	* using it.
AnnaBridge	172:65be27845400	1393	* @{
AnnaBridge	172:65be27845400	1394	*/
AnnaBridge	172:65be27845400	1395
AnnaBridge	172:65be27845400	1396	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1397	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1398	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge	172:65be27845400	1399	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1400	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge	172:65be27845400	1401	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1402	} while(0)
AnnaBridge	172:65be27845400	1403
AnnaBridge	172:65be27845400	1404	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1405	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1406	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
AnnaBridge	172:65be27845400	1407	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1408	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
AnnaBridge	172:65be27845400	1409	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1410	} while(0)
AnnaBridge	172:65be27845400	1411
AnnaBridge	172:65be27845400	1412	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	1413	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1414	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1415	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
AnnaBridge	172:65be27845400	1416	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1417	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
AnnaBridge	172:65be27845400	1418	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1419	} while(0)
AnnaBridge	172:65be27845400	1420	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
AnnaBridge	172:65be27845400	1421
AnnaBridge	172:65be27845400	1422	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1423	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1424	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
AnnaBridge	172:65be27845400	1425	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1426	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
AnnaBridge	172:65be27845400	1427	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1428	} while(0)
AnnaBridge	172:65be27845400	1429
AnnaBridge	172:65be27845400	1430	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1431	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1432	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
AnnaBridge	172:65be27845400	1433	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1434	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
AnnaBridge	172:65be27845400	1435	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1436	} while(0)
AnnaBridge	172:65be27845400	1437
AnnaBridge	172:65be27845400	1438	#if defined(TIM8)
AnnaBridge	172:65be27845400	1439	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1440	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1441	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
AnnaBridge	172:65be27845400	1442	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1443	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
AnnaBridge	172:65be27845400	1444	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1445	} while(0)
AnnaBridge	172:65be27845400	1446	#endif /* TIM8 */
AnnaBridge	172:65be27845400	1447
AnnaBridge	172:65be27845400	1448	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1449	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1450	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
AnnaBridge	172:65be27845400	1451	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1452	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
AnnaBridge	172:65be27845400	1453	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1454	} while(0)
AnnaBridge	172:65be27845400	1455
AnnaBridge	172:65be27845400	1456
AnnaBridge	172:65be27845400	1457	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1458	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1459	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
AnnaBridge	172:65be27845400	1460	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1461	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
AnnaBridge	172:65be27845400	1462	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1463	} while(0)
AnnaBridge	172:65be27845400	1464
AnnaBridge	172:65be27845400	1465	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1466	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1467	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
AnnaBridge	172:65be27845400	1468	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1469	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
AnnaBridge	172:65be27845400	1470	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1471	} while(0)
AnnaBridge	172:65be27845400	1472
AnnaBridge	172:65be27845400	1473	#if defined(TIM17)
AnnaBridge	172:65be27845400	1474	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1475	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1476	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
AnnaBridge	172:65be27845400	1477	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1478	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
AnnaBridge	172:65be27845400	1479	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1480	} while(0)
AnnaBridge	172:65be27845400	1481	#endif /* TIM17 */
AnnaBridge	172:65be27845400	1482
AnnaBridge	172:65be27845400	1483	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1484	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1485	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
AnnaBridge	172:65be27845400	1486	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1487	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
AnnaBridge	172:65be27845400	1488	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1489	} while(0)
AnnaBridge	172:65be27845400	1490
AnnaBridge	172:65be27845400	1491	#if defined(SAI2)
AnnaBridge	172:65be27845400	1492	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1493	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1494	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
AnnaBridge	172:65be27845400	1495	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1496	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
AnnaBridge	172:65be27845400	1497	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1498	} while(0)
AnnaBridge	172:65be27845400	1499	#endif /* SAI2 */
AnnaBridge	172:65be27845400	1500
AnnaBridge	172:65be27845400	1501	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	1502	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1503	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1504	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
AnnaBridge	172:65be27845400	1505	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1506	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
AnnaBridge	172:65be27845400	1507	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1508	} while(0)
AnnaBridge	172:65be27845400	1509	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	1510
AnnaBridge	172:65be27845400	1511	#if defined(LTDC)
AnnaBridge	172:65be27845400	1512	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1513	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1514	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
AnnaBridge	172:65be27845400	1515	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1516	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
AnnaBridge	172:65be27845400	1517	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1518	} while(0)
AnnaBridge	172:65be27845400	1519	#endif /* LTDC */
AnnaBridge	172:65be27845400	1520
AnnaBridge	172:65be27845400	1521	#if defined(DSI)
AnnaBridge	172:65be27845400	1522	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
AnnaBridge	172:65be27845400	1523	__IO uint32_t tmpreg; \
AnnaBridge	172:65be27845400	1524	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
AnnaBridge	172:65be27845400	1525	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	172:65be27845400	1526	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
AnnaBridge	172:65be27845400	1527	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	1528	} while(0)
AnnaBridge	172:65be27845400	1529	#endif /* DSI */
AnnaBridge	172:65be27845400	1530
AnnaBridge	172:65be27845400	1531
AnnaBridge	172:65be27845400	1532	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
AnnaBridge	172:65be27845400	1533
AnnaBridge	172:65be27845400	1534	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	1535	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	1536	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
AnnaBridge	172:65be27845400	1537
AnnaBridge	172:65be27845400	1538	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
AnnaBridge	172:65be27845400	1539
AnnaBridge	172:65be27845400	1540	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
AnnaBridge	172:65be27845400	1541
AnnaBridge	172:65be27845400	1542	#if defined(TIM8)
AnnaBridge	172:65be27845400	1543	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
AnnaBridge	172:65be27845400	1544	#endif /* TIM8 */
AnnaBridge	172:65be27845400	1545
AnnaBridge	172:65be27845400	1546	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
AnnaBridge	172:65be27845400	1547
AnnaBridge	172:65be27845400	1548	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
AnnaBridge	172:65be27845400	1549
AnnaBridge	172:65be27845400	1550	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
AnnaBridge	172:65be27845400	1551
AnnaBridge	172:65be27845400	1552	#if defined(TIM17)
AnnaBridge	172:65be27845400	1553	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
AnnaBridge	172:65be27845400	1554	#endif /* TIM17 */
AnnaBridge	172:65be27845400	1555
AnnaBridge	172:65be27845400	1556	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
AnnaBridge	172:65be27845400	1557
AnnaBridge	172:65be27845400	1558	#if defined(SAI2)
AnnaBridge	172:65be27845400	1559	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
AnnaBridge	172:65be27845400	1560	#endif /* SAI2 */
AnnaBridge	172:65be27845400	1561
AnnaBridge	172:65be27845400	1562	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	1563	#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
AnnaBridge	172:65be27845400	1564	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	1565
AnnaBridge	172:65be27845400	1566	#if defined(LTDC)
AnnaBridge	172:65be27845400	1567	#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)
AnnaBridge	172:65be27845400	1568	#endif /* LTDC */
AnnaBridge	172:65be27845400	1569
AnnaBridge	172:65be27845400	1570	#if defined(DSI)
AnnaBridge	172:65be27845400	1571	#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)
AnnaBridge	172:65be27845400	1572	#endif /* DSI */
AnnaBridge	172:65be27845400	1573
AnnaBridge	172:65be27845400	1574	/**
AnnaBridge	172:65be27845400	1575	* @}
AnnaBridge	172:65be27845400	1576	*/
AnnaBridge	172:65be27845400	1577
AnnaBridge	172:65be27845400	1578	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge	172:65be27845400	1579	* @brief Check whether the AHB1 peripheral clock is enabled or not.
AnnaBridge	172:65be27845400	1580	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1581	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1582	* using it.
AnnaBridge	172:65be27845400	1583	* @{
AnnaBridge	172:65be27845400	1584	*/
AnnaBridge	172:65be27845400	1585
AnnaBridge	172:65be27845400	1586	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
AnnaBridge	172:65be27845400	1587
AnnaBridge	172:65be27845400	1588	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
AnnaBridge	172:65be27845400	1589
AnnaBridge	172:65be27845400	1590	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	1591	#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET)
AnnaBridge	172:65be27845400	1592	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	1593
AnnaBridge	172:65be27845400	1594	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
AnnaBridge	172:65be27845400	1595
AnnaBridge	172:65be27845400	1596	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
AnnaBridge	172:65be27845400	1597
AnnaBridge	172:65be27845400	1598	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
AnnaBridge	172:65be27845400	1599
AnnaBridge	172:65be27845400	1600	#if defined(DMA2D)
AnnaBridge	172:65be27845400	1601	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET)
AnnaBridge	172:65be27845400	1602	#endif /* DMA2D */
AnnaBridge	172:65be27845400	1603
AnnaBridge	172:65be27845400	1604	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	1605	#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET)
AnnaBridge	172:65be27845400	1606	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	1607
AnnaBridge	172:65be27845400	1608
AnnaBridge	172:65be27845400	1609	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
AnnaBridge	172:65be27845400	1610
AnnaBridge	172:65be27845400	1611	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
AnnaBridge	172:65be27845400	1612
AnnaBridge	172:65be27845400	1613	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	1614	#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET)
AnnaBridge	172:65be27845400	1615	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	1616
AnnaBridge	172:65be27845400	1617	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
AnnaBridge	172:65be27845400	1618
AnnaBridge	172:65be27845400	1619	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
AnnaBridge	172:65be27845400	1620
AnnaBridge	172:65be27845400	1621	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
AnnaBridge	172:65be27845400	1622
AnnaBridge	172:65be27845400	1623	#if defined(DMA2D)
AnnaBridge	172:65be27845400	1624	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET)
AnnaBridge	172:65be27845400	1625	#endif /* DMA2D */
AnnaBridge	172:65be27845400	1626
AnnaBridge	172:65be27845400	1627	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	1628	#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET)
AnnaBridge	172:65be27845400	1629	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	1630
AnnaBridge	172:65be27845400	1631	/**
AnnaBridge	172:65be27845400	1632	* @}
AnnaBridge	172:65be27845400	1633	*/
AnnaBridge	172:65be27845400	1634
AnnaBridge	172:65be27845400	1635	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge	172:65be27845400	1636	* @brief Check whether the AHB2 peripheral clock is enabled or not.
AnnaBridge	172:65be27845400	1637	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1638	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1639	* using it.
AnnaBridge	172:65be27845400	1640	* @{
AnnaBridge	172:65be27845400	1641	*/
AnnaBridge	172:65be27845400	1642
AnnaBridge	172:65be27845400	1643	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
AnnaBridge	172:65be27845400	1644
AnnaBridge	172:65be27845400	1645	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET)
AnnaBridge	172:65be27845400	1646
AnnaBridge	172:65be27845400	1647	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
AnnaBridge	172:65be27845400	1648
AnnaBridge	172:65be27845400	1649	#if defined(GPIOD)
AnnaBridge	172:65be27845400	1650	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
AnnaBridge	172:65be27845400	1651	#endif /* GPIOD */
AnnaBridge	172:65be27845400	1652
AnnaBridge	172:65be27845400	1653	#if defined(GPIOE)
AnnaBridge	172:65be27845400	1654	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
AnnaBridge	172:65be27845400	1655	#endif /* GPIOE */
AnnaBridge	172:65be27845400	1656
AnnaBridge	172:65be27845400	1657	#if defined(GPIOF)
AnnaBridge	172:65be27845400	1658	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
AnnaBridge	172:65be27845400	1659	#endif /* GPIOF */
AnnaBridge	172:65be27845400	1660
AnnaBridge	172:65be27845400	1661	#if defined(GPIOG)
AnnaBridge	172:65be27845400	1662	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
AnnaBridge	172:65be27845400	1663	#endif /* GPIOG */
AnnaBridge	172:65be27845400	1664
AnnaBridge	172:65be27845400	1665	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
AnnaBridge	172:65be27845400	1666
AnnaBridge	172:65be27845400	1667	#if defined(GPIOI)
AnnaBridge	172:65be27845400	1668	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET)
AnnaBridge	172:65be27845400	1669	#endif /* GPIOI */
AnnaBridge	172:65be27845400	1670
AnnaBridge	172:65be27845400	1671	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	1672	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
AnnaBridge	172:65be27845400	1673	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	1674
AnnaBridge	172:65be27845400	1675	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
AnnaBridge	172:65be27845400	1676
AnnaBridge	172:65be27845400	1677	#if defined(DCMI)
AnnaBridge	172:65be27845400	1678	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET)
AnnaBridge	172:65be27845400	1679	#endif /* DCMI */
AnnaBridge	172:65be27845400	1680
AnnaBridge	172:65be27845400	1681	#if defined(AES)
AnnaBridge	172:65be27845400	1682	#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
AnnaBridge	172:65be27845400	1683	#endif /* AES */
AnnaBridge	172:65be27845400	1684
AnnaBridge	172:65be27845400	1685	#if defined(HASH)
AnnaBridge	172:65be27845400	1686	#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET)
AnnaBridge	172:65be27845400	1687	#endif /* HASH */
AnnaBridge	172:65be27845400	1688
AnnaBridge	172:65be27845400	1689	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
AnnaBridge	172:65be27845400	1690
AnnaBridge	172:65be27845400	1691
AnnaBridge	172:65be27845400	1692	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
AnnaBridge	172:65be27845400	1693
AnnaBridge	172:65be27845400	1694	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
AnnaBridge	172:65be27845400	1695
AnnaBridge	172:65be27845400	1696	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
AnnaBridge	172:65be27845400	1697
AnnaBridge	172:65be27845400	1698	#if defined(GPIOD)
AnnaBridge	172:65be27845400	1699	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
AnnaBridge	172:65be27845400	1700	#endif /* GPIOD */
AnnaBridge	172:65be27845400	1701
AnnaBridge	172:65be27845400	1702	#if defined(GPIOE)
AnnaBridge	172:65be27845400	1703	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
AnnaBridge	172:65be27845400	1704	#endif /* GPIOE */
AnnaBridge	172:65be27845400	1705
AnnaBridge	172:65be27845400	1706	#if defined(GPIOF)
AnnaBridge	172:65be27845400	1707	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
AnnaBridge	172:65be27845400	1708	#endif /* GPIOF */
AnnaBridge	172:65be27845400	1709
AnnaBridge	172:65be27845400	1710	#if defined(GPIOG)
AnnaBridge	172:65be27845400	1711	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
AnnaBridge	172:65be27845400	1712	#endif /* GPIOG */
AnnaBridge	172:65be27845400	1713
AnnaBridge	172:65be27845400	1714	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
AnnaBridge	172:65be27845400	1715
AnnaBridge	172:65be27845400	1716	#if defined(GPIOI)
AnnaBridge	172:65be27845400	1717	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET)
AnnaBridge	172:65be27845400	1718	#endif /* GPIOI */
AnnaBridge	172:65be27845400	1719
AnnaBridge	172:65be27845400	1720	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	1721	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
AnnaBridge	172:65be27845400	1722	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	1723
AnnaBridge	172:65be27845400	1724	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
AnnaBridge	172:65be27845400	1725
AnnaBridge	172:65be27845400	1726	#if defined(DCMI)
AnnaBridge	172:65be27845400	1727	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET)
AnnaBridge	172:65be27845400	1728	#endif /* DCMI */
AnnaBridge	172:65be27845400	1729
AnnaBridge	172:65be27845400	1730	#if defined(AES)
AnnaBridge	172:65be27845400	1731	#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
AnnaBridge	172:65be27845400	1732	#endif /* AES */
AnnaBridge	172:65be27845400	1733
AnnaBridge	172:65be27845400	1734	#if defined(HASH)
AnnaBridge	172:65be27845400	1735	#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET)
AnnaBridge	172:65be27845400	1736	#endif /* HASH */
AnnaBridge	172:65be27845400	1737
AnnaBridge	172:65be27845400	1738	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
AnnaBridge	172:65be27845400	1739
AnnaBridge	172:65be27845400	1740	/**
AnnaBridge	172:65be27845400	1741	* @}
AnnaBridge	172:65be27845400	1742	*/
AnnaBridge	172:65be27845400	1743
AnnaBridge	172:65be27845400	1744	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
AnnaBridge	172:65be27845400	1745	* @brief Check whether the AHB3 peripheral clock is enabled or not.
AnnaBridge	172:65be27845400	1746	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1747	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1748	* using it.
AnnaBridge	172:65be27845400	1749	* @{
AnnaBridge	172:65be27845400	1750	*/
AnnaBridge	172:65be27845400	1751
AnnaBridge	172:65be27845400	1752	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	1753	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
AnnaBridge	172:65be27845400	1754	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	1755
AnnaBridge	172:65be27845400	1756	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	1757	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
AnnaBridge	172:65be27845400	1758	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	1759
AnnaBridge	172:65be27845400	1760	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	1761	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
AnnaBridge	172:65be27845400	1762	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	1763
AnnaBridge	172:65be27845400	1764	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	1765	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
AnnaBridge	172:65be27845400	1766	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	1767
AnnaBridge	172:65be27845400	1768	/**
AnnaBridge	172:65be27845400	1769	* @}
AnnaBridge	172:65be27845400	1770	*/
AnnaBridge	172:65be27845400	1771
AnnaBridge	172:65be27845400	1772	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge	172:65be27845400	1773	* @brief Check whether the APB1 peripheral clock is enabled or not.
AnnaBridge	172:65be27845400	1774	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1775	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1776	* using it.
AnnaBridge	172:65be27845400	1777	* @{
AnnaBridge	172:65be27845400	1778	*/
AnnaBridge	172:65be27845400	1779
AnnaBridge	172:65be27845400	1780	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
AnnaBridge	172:65be27845400	1781
AnnaBridge	172:65be27845400	1782	#if defined(TIM3)
AnnaBridge	172:65be27845400	1783	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
AnnaBridge	172:65be27845400	1784	#endif /* TIM3 */
AnnaBridge	172:65be27845400	1785
AnnaBridge	172:65be27845400	1786	#if defined(TIM4)
AnnaBridge	172:65be27845400	1787	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
AnnaBridge	172:65be27845400	1788	#endif /* TIM4 */
AnnaBridge	172:65be27845400	1789
AnnaBridge	172:65be27845400	1790	#if defined(TIM5)
AnnaBridge	172:65be27845400	1791	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
AnnaBridge	172:65be27845400	1792	#endif /* TIM5 */
AnnaBridge	172:65be27845400	1793
AnnaBridge	172:65be27845400	1794	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
AnnaBridge	172:65be27845400	1795
AnnaBridge	172:65be27845400	1796	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
AnnaBridge	172:65be27845400	1797
AnnaBridge	172:65be27845400	1798	#if defined(LCD)
AnnaBridge	172:65be27845400	1799	#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
AnnaBridge	172:65be27845400	1800	#endif /* LCD */
AnnaBridge	172:65be27845400	1801
AnnaBridge	172:65be27845400	1802	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	172:65be27845400	1803	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
AnnaBridge	172:65be27845400	1804	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	172:65be27845400	1805
AnnaBridge	172:65be27845400	1806	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
AnnaBridge	172:65be27845400	1807
AnnaBridge	172:65be27845400	1808	#if defined(SPI2)
AnnaBridge	172:65be27845400	1809	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
AnnaBridge	172:65be27845400	1810	#endif /* SPI2 */
AnnaBridge	172:65be27845400	1811
AnnaBridge	172:65be27845400	1812	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
AnnaBridge	172:65be27845400	1813
AnnaBridge	172:65be27845400	1814	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
AnnaBridge	172:65be27845400	1815
AnnaBridge	172:65be27845400	1816	#if defined(USART3)
AnnaBridge	172:65be27845400	1817	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
AnnaBridge	172:65be27845400	1818	#endif /* USART3 */
AnnaBridge	172:65be27845400	1819
AnnaBridge	172:65be27845400	1820	#if defined(UART4)
AnnaBridge	172:65be27845400	1821	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
AnnaBridge	172:65be27845400	1822	#endif /* UART4 */
AnnaBridge	172:65be27845400	1823
AnnaBridge	172:65be27845400	1824	#if defined(UART5)
AnnaBridge	172:65be27845400	1825	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
AnnaBridge	172:65be27845400	1826	#endif /* UART5 */
AnnaBridge	172:65be27845400	1827
AnnaBridge	172:65be27845400	1828	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
AnnaBridge	172:65be27845400	1829
AnnaBridge	172:65be27845400	1830	#if defined(I2C2)
AnnaBridge	172:65be27845400	1831	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
AnnaBridge	172:65be27845400	1832	#endif /* I2C2 */
AnnaBridge	172:65be27845400	1833
AnnaBridge	172:65be27845400	1834	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
AnnaBridge	172:65be27845400	1835
AnnaBridge	172:65be27845400	1836	#if defined(I2C4)
AnnaBridge	172:65be27845400	1837	#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET)
AnnaBridge	172:65be27845400	1838	#endif /* I2C4 */
AnnaBridge	172:65be27845400	1839
AnnaBridge	172:65be27845400	1840	#if defined(CRS)
AnnaBridge	172:65be27845400	1841	#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
AnnaBridge	172:65be27845400	1842	#endif /* CRS */
AnnaBridge	172:65be27845400	1843
AnnaBridge	172:65be27845400	1844	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
AnnaBridge	172:65be27845400	1845
AnnaBridge	172:65be27845400	1846	#if defined(CAN2)
AnnaBridge	172:65be27845400	1847	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET)
AnnaBridge	172:65be27845400	1848	#endif /* CAN2 */
AnnaBridge	172:65be27845400	1849
AnnaBridge	172:65be27845400	1850	#if defined(USB)
AnnaBridge	172:65be27845400	1851	#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
AnnaBridge	172:65be27845400	1852	#endif /* USB */
AnnaBridge	172:65be27845400	1853
AnnaBridge	172:65be27845400	1854	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
AnnaBridge	172:65be27845400	1855
AnnaBridge	172:65be27845400	1856	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
AnnaBridge	172:65be27845400	1857
AnnaBridge	172:65be27845400	1858	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
AnnaBridge	172:65be27845400	1859
AnnaBridge	172:65be27845400	1860	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
AnnaBridge	172:65be27845400	1861
AnnaBridge	172:65be27845400	1862	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
AnnaBridge	172:65be27845400	1863
AnnaBridge	172:65be27845400	1864	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	1865	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
AnnaBridge	172:65be27845400	1866	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	1867
AnnaBridge	172:65be27845400	1868	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
AnnaBridge	172:65be27845400	1869
AnnaBridge	172:65be27845400	1870
AnnaBridge	172:65be27845400	1871	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
AnnaBridge	172:65be27845400	1872
AnnaBridge	172:65be27845400	1873	#if defined(TIM3)
AnnaBridge	172:65be27845400	1874	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
AnnaBridge	172:65be27845400	1875	#endif /* TIM3 */
AnnaBridge	172:65be27845400	1876
AnnaBridge	172:65be27845400	1877	#if defined(TIM4)
AnnaBridge	172:65be27845400	1878	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
AnnaBridge	172:65be27845400	1879	#endif /* TIM4 */
AnnaBridge	172:65be27845400	1880
AnnaBridge	172:65be27845400	1881	#if defined(TIM5)
AnnaBridge	172:65be27845400	1882	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
AnnaBridge	172:65be27845400	1883	#endif /* TIM5 */
AnnaBridge	172:65be27845400	1884
AnnaBridge	172:65be27845400	1885	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
AnnaBridge	172:65be27845400	1886
AnnaBridge	172:65be27845400	1887	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
AnnaBridge	172:65be27845400	1888
AnnaBridge	172:65be27845400	1889	#if defined(LCD)
AnnaBridge	172:65be27845400	1890	#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
AnnaBridge	172:65be27845400	1891	#endif /* LCD */
AnnaBridge	172:65be27845400	1892
AnnaBridge	172:65be27845400	1893	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	172:65be27845400	1894	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
AnnaBridge	172:65be27845400	1895	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	172:65be27845400	1896
AnnaBridge	172:65be27845400	1897	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
AnnaBridge	172:65be27845400	1898
AnnaBridge	172:65be27845400	1899	#if defined(SPI2)
AnnaBridge	172:65be27845400	1900	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
AnnaBridge	172:65be27845400	1901	#endif /* SPI2 */
AnnaBridge	172:65be27845400	1902
AnnaBridge	172:65be27845400	1903	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
AnnaBridge	172:65be27845400	1904
AnnaBridge	172:65be27845400	1905	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
AnnaBridge	172:65be27845400	1906
AnnaBridge	172:65be27845400	1907	#if defined(USART3)
AnnaBridge	172:65be27845400	1908	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
AnnaBridge	172:65be27845400	1909	#endif /* USART3 */
AnnaBridge	172:65be27845400	1910
AnnaBridge	172:65be27845400	1911	#if defined(UART4)
AnnaBridge	172:65be27845400	1912	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
AnnaBridge	172:65be27845400	1913	#endif /* UART4 */
AnnaBridge	172:65be27845400	1914
AnnaBridge	172:65be27845400	1915	#if defined(UART5)
AnnaBridge	172:65be27845400	1916	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
AnnaBridge	172:65be27845400	1917	#endif /* UART5 */
AnnaBridge	172:65be27845400	1918
AnnaBridge	172:65be27845400	1919	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
AnnaBridge	172:65be27845400	1920
AnnaBridge	172:65be27845400	1921	#if defined(I2C2)
AnnaBridge	172:65be27845400	1922	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
AnnaBridge	172:65be27845400	1923	#endif /* I2C2 */
AnnaBridge	172:65be27845400	1924
AnnaBridge	172:65be27845400	1925	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
AnnaBridge	172:65be27845400	1926
AnnaBridge	172:65be27845400	1927	#if defined(I2C4)
AnnaBridge	172:65be27845400	1928	#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET)
AnnaBridge	172:65be27845400	1929	#endif /* I2C4 */
AnnaBridge	172:65be27845400	1930
AnnaBridge	172:65be27845400	1931	#if defined(CRS)
AnnaBridge	172:65be27845400	1932	#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
AnnaBridge	172:65be27845400	1933	#endif /* CRS */
AnnaBridge	172:65be27845400	1934
AnnaBridge	172:65be27845400	1935	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
AnnaBridge	172:65be27845400	1936
AnnaBridge	172:65be27845400	1937	#if defined(CAN2)
AnnaBridge	172:65be27845400	1938	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET)
AnnaBridge	172:65be27845400	1939	#endif /* CAN2 */
AnnaBridge	172:65be27845400	1940
AnnaBridge	172:65be27845400	1941	#if defined(USB)
AnnaBridge	172:65be27845400	1942	#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
AnnaBridge	172:65be27845400	1943	#endif /* USB */
AnnaBridge	172:65be27845400	1944
AnnaBridge	172:65be27845400	1945	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
AnnaBridge	172:65be27845400	1946
AnnaBridge	172:65be27845400	1947	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
AnnaBridge	172:65be27845400	1948
AnnaBridge	172:65be27845400	1949	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
AnnaBridge	172:65be27845400	1950
AnnaBridge	172:65be27845400	1951	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
AnnaBridge	172:65be27845400	1952
AnnaBridge	172:65be27845400	1953	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
AnnaBridge	172:65be27845400	1954
AnnaBridge	172:65be27845400	1955	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	1956	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
AnnaBridge	172:65be27845400	1957	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	1958
AnnaBridge	172:65be27845400	1959	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
AnnaBridge	172:65be27845400	1960
AnnaBridge	172:65be27845400	1961	/**
AnnaBridge	172:65be27845400	1962	* @}
AnnaBridge	172:65be27845400	1963	*/
AnnaBridge	172:65be27845400	1964
AnnaBridge	172:65be27845400	1965	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge	172:65be27845400	1966	* @brief Check whether the APB2 peripheral clock is enabled or not.
AnnaBridge	172:65be27845400	1967	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	172:65be27845400	1968	* is disabled and the application software has to enable this clock before
AnnaBridge	172:65be27845400	1969	* using it.
AnnaBridge	172:65be27845400	1970	* @{
AnnaBridge	172:65be27845400	1971	*/
AnnaBridge	172:65be27845400	1972
AnnaBridge	172:65be27845400	1973	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
AnnaBridge	172:65be27845400	1974
AnnaBridge	172:65be27845400	1975	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
AnnaBridge	172:65be27845400	1976
AnnaBridge	172:65be27845400	1977	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	1978	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
AnnaBridge	172:65be27845400	1979	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
AnnaBridge	172:65be27845400	1980
AnnaBridge	172:65be27845400	1981	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
AnnaBridge	172:65be27845400	1982
AnnaBridge	172:65be27845400	1983	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
AnnaBridge	172:65be27845400	1984
AnnaBridge	172:65be27845400	1985	#if defined(TIM8)
AnnaBridge	172:65be27845400	1986	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
AnnaBridge	172:65be27845400	1987	#endif /* TIM8 */
AnnaBridge	172:65be27845400	1988
AnnaBridge	172:65be27845400	1989	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
AnnaBridge	172:65be27845400	1990
AnnaBridge	172:65be27845400	1991	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
AnnaBridge	172:65be27845400	1992
AnnaBridge	172:65be27845400	1993	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
AnnaBridge	172:65be27845400	1994
AnnaBridge	172:65be27845400	1995	#if defined(TIM17)
AnnaBridge	172:65be27845400	1996	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
AnnaBridge	172:65be27845400	1997	#endif /* TIM17 */
AnnaBridge	172:65be27845400	1998
AnnaBridge	172:65be27845400	1999	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
AnnaBridge	172:65be27845400	2000
AnnaBridge	172:65be27845400	2001	#if defined(SAI2)
AnnaBridge	172:65be27845400	2002	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
AnnaBridge	172:65be27845400	2003	#endif /* SAI2 */
AnnaBridge	172:65be27845400	2004
AnnaBridge	172:65be27845400	2005	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	2006	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
AnnaBridge	172:65be27845400	2007	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	2008
AnnaBridge	172:65be27845400	2009	#if defined(LTDC)
AnnaBridge	172:65be27845400	2010	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET)
AnnaBridge	172:65be27845400	2011	#endif /* LTDC */
AnnaBridge	172:65be27845400	2012
AnnaBridge	172:65be27845400	2013	#if defined(DSI)
AnnaBridge	172:65be27845400	2014	#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET)
AnnaBridge	172:65be27845400	2015	#endif /* DSI */
AnnaBridge	172:65be27845400	2016
AnnaBridge	172:65be27845400	2017
AnnaBridge	172:65be27845400	2018	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
AnnaBridge	172:65be27845400	2019
AnnaBridge	172:65be27845400	2020	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
AnnaBridge	172:65be27845400	2021	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
AnnaBridge	172:65be27845400	2022	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
AnnaBridge	172:65be27845400	2023
AnnaBridge	172:65be27845400	2024	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
AnnaBridge	172:65be27845400	2025
AnnaBridge	172:65be27845400	2026	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
AnnaBridge	172:65be27845400	2027
AnnaBridge	172:65be27845400	2028	#if defined(TIM8)
AnnaBridge	172:65be27845400	2029	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
AnnaBridge	172:65be27845400	2030	#endif /* TIM8 */
AnnaBridge	172:65be27845400	2031
AnnaBridge	172:65be27845400	2032	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
AnnaBridge	172:65be27845400	2033
AnnaBridge	172:65be27845400	2034	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
AnnaBridge	172:65be27845400	2035
AnnaBridge	172:65be27845400	2036	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
AnnaBridge	172:65be27845400	2037
AnnaBridge	172:65be27845400	2038	#if defined(TIM17)
AnnaBridge	172:65be27845400	2039	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
AnnaBridge	172:65be27845400	2040	#endif /* TIM17 */
AnnaBridge	172:65be27845400	2041
AnnaBridge	172:65be27845400	2042	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
AnnaBridge	172:65be27845400	2043
AnnaBridge	172:65be27845400	2044	#if defined(SAI2)
AnnaBridge	172:65be27845400	2045	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
AnnaBridge	172:65be27845400	2046	#endif /* SAI2 */
AnnaBridge	172:65be27845400	2047
AnnaBridge	172:65be27845400	2048	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	2049	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
AnnaBridge	172:65be27845400	2050	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	2051
AnnaBridge	172:65be27845400	2052	#if defined(LTDC)
AnnaBridge	172:65be27845400	2053	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET)
AnnaBridge	172:65be27845400	2054	#endif /* LTDC */
AnnaBridge	172:65be27845400	2055
AnnaBridge	172:65be27845400	2056	#if defined(DSI)
AnnaBridge	172:65be27845400	2057	#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET)
AnnaBridge	172:65be27845400	2058	#endif /* DSI */
AnnaBridge	172:65be27845400	2059
AnnaBridge	172:65be27845400	2060	/**
AnnaBridge	172:65be27845400	2061	* @}
AnnaBridge	172:65be27845400	2062	*/
AnnaBridge	172:65be27845400	2063
AnnaBridge	172:65be27845400	2064	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
AnnaBridge	172:65be27845400	2065	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	172:65be27845400	2066	* @{
AnnaBridge	172:65be27845400	2067	*/
AnnaBridge	172:65be27845400	2068	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
AnnaBridge	172:65be27845400	2069
AnnaBridge	172:65be27845400	2070	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
AnnaBridge	172:65be27845400	2071
AnnaBridge	172:65be27845400	2072	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
AnnaBridge	172:65be27845400	2073
AnnaBridge	172:65be27845400	2074	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	2075	#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
AnnaBridge	172:65be27845400	2076	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	2077
AnnaBridge	172:65be27845400	2078	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
AnnaBridge	172:65be27845400	2079
AnnaBridge	172:65be27845400	2080	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
AnnaBridge	172:65be27845400	2081
AnnaBridge	172:65be27845400	2082	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
AnnaBridge	172:65be27845400	2083
AnnaBridge	172:65be27845400	2084	#if defined(DMA2D)
AnnaBridge	172:65be27845400	2085	#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge	172:65be27845400	2086	#endif /* DMA2D */
AnnaBridge	172:65be27845400	2087
AnnaBridge	172:65be27845400	2088	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	2089	#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
AnnaBridge	172:65be27845400	2090	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	2091
AnnaBridge	172:65be27845400	2092
AnnaBridge	172:65be27845400	2093	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
AnnaBridge	172:65be27845400	2094
AnnaBridge	172:65be27845400	2095	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
AnnaBridge	172:65be27845400	2096
AnnaBridge	172:65be27845400	2097	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
AnnaBridge	172:65be27845400	2098
AnnaBridge	172:65be27845400	2099	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	2100	#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
AnnaBridge	172:65be27845400	2101	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	2102
AnnaBridge	172:65be27845400	2103	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
AnnaBridge	172:65be27845400	2104
AnnaBridge	172:65be27845400	2105	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
AnnaBridge	172:65be27845400	2106
AnnaBridge	172:65be27845400	2107	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
AnnaBridge	172:65be27845400	2108
AnnaBridge	172:65be27845400	2109	#if defined(DMA2D)
AnnaBridge	172:65be27845400	2110	#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge	172:65be27845400	2111	#endif /* DMA2D */
AnnaBridge	172:65be27845400	2112
AnnaBridge	172:65be27845400	2113	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	2114	#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
AnnaBridge	172:65be27845400	2115	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	2116
AnnaBridge	172:65be27845400	2117	/**
AnnaBridge	172:65be27845400	2118	* @}
AnnaBridge	172:65be27845400	2119	*/
AnnaBridge	172:65be27845400	2120
AnnaBridge	172:65be27845400	2121	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
AnnaBridge	172:65be27845400	2122	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	172:65be27845400	2123	* @{
AnnaBridge	172:65be27845400	2124	*/
AnnaBridge	172:65be27845400	2125	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
AnnaBridge	172:65be27845400	2126
AnnaBridge	172:65be27845400	2127	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
AnnaBridge	172:65be27845400	2128
AnnaBridge	172:65be27845400	2129	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
AnnaBridge	172:65be27845400	2130
AnnaBridge	172:65be27845400	2131	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
AnnaBridge	172:65be27845400	2132
AnnaBridge	172:65be27845400	2133	#if defined(GPIOD)
AnnaBridge	172:65be27845400	2134	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
AnnaBridge	172:65be27845400	2135	#endif /* GPIOD */
AnnaBridge	172:65be27845400	2136
AnnaBridge	172:65be27845400	2137	#if defined(GPIOE)
AnnaBridge	172:65be27845400	2138	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
AnnaBridge	172:65be27845400	2139	#endif /* GPIOE */
AnnaBridge	172:65be27845400	2140
AnnaBridge	172:65be27845400	2141	#if defined(GPIOF)
AnnaBridge	172:65be27845400	2142	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
AnnaBridge	172:65be27845400	2143	#endif /* GPIOF */
AnnaBridge	172:65be27845400	2144
AnnaBridge	172:65be27845400	2145	#if defined(GPIOG)
AnnaBridge	172:65be27845400	2146	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
AnnaBridge	172:65be27845400	2147	#endif /* GPIOG */
AnnaBridge	172:65be27845400	2148
AnnaBridge	172:65be27845400	2149	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
AnnaBridge	172:65be27845400	2150
AnnaBridge	172:65be27845400	2151	#if defined(GPIOI)
AnnaBridge	172:65be27845400	2152	#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge	172:65be27845400	2153	#endif /* GPIOI */
AnnaBridge	172:65be27845400	2154
AnnaBridge	172:65be27845400	2155	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	2156	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
AnnaBridge	172:65be27845400	2157	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	2158
AnnaBridge	172:65be27845400	2159	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
AnnaBridge	172:65be27845400	2160
AnnaBridge	172:65be27845400	2161	#if defined(DCMI)
AnnaBridge	172:65be27845400	2162	#define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge	172:65be27845400	2163	#endif /* DCMI */
AnnaBridge	172:65be27845400	2164
AnnaBridge	172:65be27845400	2165	#if defined(AES)
AnnaBridge	172:65be27845400	2166	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
AnnaBridge	172:65be27845400	2167	#endif /* AES */
AnnaBridge	172:65be27845400	2168
AnnaBridge	172:65be27845400	2169	#if defined(HASH)
AnnaBridge	172:65be27845400	2170	#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge	172:65be27845400	2171	#endif /* HASH */
AnnaBridge	172:65be27845400	2172
AnnaBridge	172:65be27845400	2173	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
AnnaBridge	172:65be27845400	2174
AnnaBridge	172:65be27845400	2175	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	2176	#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
AnnaBridge	172:65be27845400	2177	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	2178
AnnaBridge	172:65be27845400	2179	#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2180	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2181	#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
AnnaBridge	172:65be27845400	2182
AnnaBridge	172:65be27845400	2183
AnnaBridge	172:65be27845400	2184	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
AnnaBridge	172:65be27845400	2185
AnnaBridge	172:65be27845400	2186	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
AnnaBridge	172:65be27845400	2187
AnnaBridge	172:65be27845400	2188	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
AnnaBridge	172:65be27845400	2189
AnnaBridge	172:65be27845400	2190	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
AnnaBridge	172:65be27845400	2191
AnnaBridge	172:65be27845400	2192	#if defined(GPIOD)
AnnaBridge	172:65be27845400	2193	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
AnnaBridge	172:65be27845400	2194	#endif /* GPIOD */
AnnaBridge	172:65be27845400	2195
AnnaBridge	172:65be27845400	2196	#if defined(GPIOE)
AnnaBridge	172:65be27845400	2197	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
AnnaBridge	172:65be27845400	2198	#endif /* GPIOE */
AnnaBridge	172:65be27845400	2199
AnnaBridge	172:65be27845400	2200	#if defined(GPIOF)
AnnaBridge	172:65be27845400	2201	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
AnnaBridge	172:65be27845400	2202	#endif /* GPIOF */
AnnaBridge	172:65be27845400	2203
AnnaBridge	172:65be27845400	2204	#if defined(GPIOG)
AnnaBridge	172:65be27845400	2205	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
AnnaBridge	172:65be27845400	2206	#endif /* GPIOG */
AnnaBridge	172:65be27845400	2207
AnnaBridge	172:65be27845400	2208	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
AnnaBridge	172:65be27845400	2209
AnnaBridge	172:65be27845400	2210	#if defined(GPIOI)
AnnaBridge	172:65be27845400	2211	#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge	172:65be27845400	2212	#endif /* GPIOI */
AnnaBridge	172:65be27845400	2213
AnnaBridge	172:65be27845400	2214	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	2215	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
AnnaBridge	172:65be27845400	2216	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	2217
AnnaBridge	172:65be27845400	2218	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
AnnaBridge	172:65be27845400	2219
AnnaBridge	172:65be27845400	2220	#if defined(DCMI)
AnnaBridge	172:65be27845400	2221	#define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge	172:65be27845400	2222	#endif /* DCMI */
AnnaBridge	172:65be27845400	2223
AnnaBridge	172:65be27845400	2224	#if defined(AES)
AnnaBridge	172:65be27845400	2225	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
AnnaBridge	172:65be27845400	2226	#endif /* AES */
AnnaBridge	172:65be27845400	2227
AnnaBridge	172:65be27845400	2228	#if defined(HASH)
AnnaBridge	172:65be27845400	2229	#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge	172:65be27845400	2230	#endif /* HASH */
AnnaBridge	172:65be27845400	2231
AnnaBridge	172:65be27845400	2232	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
AnnaBridge	172:65be27845400	2233
AnnaBridge	172:65be27845400	2234	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	2235	#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
AnnaBridge	172:65be27845400	2236	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	2237
AnnaBridge	172:65be27845400	2238	#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2239	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2240	#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
AnnaBridge	172:65be27845400	2241
AnnaBridge	172:65be27845400	2242	/**
AnnaBridge	172:65be27845400	2243	* @}
AnnaBridge	172:65be27845400	2244	*/
AnnaBridge	172:65be27845400	2245
AnnaBridge	172:65be27845400	2246	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
AnnaBridge	172:65be27845400	2247	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	172:65be27845400	2248	* @{
AnnaBridge	172:65be27845400	2249	*/
AnnaBridge	172:65be27845400	2250	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
AnnaBridge	172:65be27845400	2251
AnnaBridge	172:65be27845400	2252	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	2253	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
AnnaBridge	172:65be27845400	2254	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	2255
AnnaBridge	172:65be27845400	2256	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	2257	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
AnnaBridge	172:65be27845400	2258	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	2259
AnnaBridge	172:65be27845400	2260	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	2261	#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
AnnaBridge	172:65be27845400	2262	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	2263
AnnaBridge	172:65be27845400	2264	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	2265	#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
AnnaBridge	172:65be27845400	2266	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	2267
AnnaBridge	172:65be27845400	2268	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
AnnaBridge	172:65be27845400	2269
AnnaBridge	172:65be27845400	2270	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	2271	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
AnnaBridge	172:65be27845400	2272	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	2273
AnnaBridge	172:65be27845400	2274	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	2275	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
AnnaBridge	172:65be27845400	2276	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	2277
AnnaBridge	172:65be27845400	2278	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	2279	#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
AnnaBridge	172:65be27845400	2280	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	2281
AnnaBridge	172:65be27845400	2282	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	2283	#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
AnnaBridge	172:65be27845400	2284	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	2285
AnnaBridge	172:65be27845400	2286	/**
AnnaBridge	172:65be27845400	2287	* @}
AnnaBridge	172:65be27845400	2288	*/
AnnaBridge	172:65be27845400	2289
AnnaBridge	172:65be27845400	2290	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge	172:65be27845400	2291	* @brief Force or release APB1 peripheral reset.
AnnaBridge	172:65be27845400	2292	* @{
AnnaBridge	172:65be27845400	2293	*/
AnnaBridge	172:65be27845400	2294	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
AnnaBridge	172:65be27845400	2295
AnnaBridge	172:65be27845400	2296	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
AnnaBridge	172:65be27845400	2297
AnnaBridge	172:65be27845400	2298	#if defined(TIM3)
AnnaBridge	172:65be27845400	2299	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
AnnaBridge	172:65be27845400	2300	#endif /* TIM3 */
AnnaBridge	172:65be27845400	2301
AnnaBridge	172:65be27845400	2302	#if defined(TIM4)
AnnaBridge	172:65be27845400	2303	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
AnnaBridge	172:65be27845400	2304	#endif /* TIM4 */
AnnaBridge	172:65be27845400	2305
AnnaBridge	172:65be27845400	2306	#if defined(TIM5)
AnnaBridge	172:65be27845400	2307	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
AnnaBridge	172:65be27845400	2308	#endif /* TIM5 */
AnnaBridge	172:65be27845400	2309
AnnaBridge	172:65be27845400	2310	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
AnnaBridge	172:65be27845400	2311
AnnaBridge	172:65be27845400	2312	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
AnnaBridge	172:65be27845400	2313
AnnaBridge	172:65be27845400	2314	#if defined(LCD)
AnnaBridge	172:65be27845400	2315	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
AnnaBridge	172:65be27845400	2316	#endif /* LCD */
AnnaBridge	172:65be27845400	2317
AnnaBridge	172:65be27845400	2318	#if defined(SPI2)
AnnaBridge	172:65be27845400	2319	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
AnnaBridge	172:65be27845400	2320	#endif /* SPI2 */
AnnaBridge	172:65be27845400	2321
AnnaBridge	172:65be27845400	2322	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
AnnaBridge	172:65be27845400	2323
AnnaBridge	172:65be27845400	2324	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
AnnaBridge	172:65be27845400	2325
AnnaBridge	172:65be27845400	2326	#if defined(USART3)
AnnaBridge	172:65be27845400	2327	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
AnnaBridge	172:65be27845400	2328	#endif /* USART3 */
AnnaBridge	172:65be27845400	2329
AnnaBridge	172:65be27845400	2330	#if defined(UART4)
AnnaBridge	172:65be27845400	2331	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
AnnaBridge	172:65be27845400	2332	#endif /* UART4 */
AnnaBridge	172:65be27845400	2333
AnnaBridge	172:65be27845400	2334	#if defined(UART5)
AnnaBridge	172:65be27845400	2335	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
AnnaBridge	172:65be27845400	2336	#endif /* UART5 */
AnnaBridge	172:65be27845400	2337
AnnaBridge	172:65be27845400	2338	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
AnnaBridge	172:65be27845400	2339
AnnaBridge	172:65be27845400	2340	#if defined(I2C2)
AnnaBridge	172:65be27845400	2341	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
AnnaBridge	172:65be27845400	2342	#endif /* I2C2 */
AnnaBridge	172:65be27845400	2343
AnnaBridge	172:65be27845400	2344	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
AnnaBridge	172:65be27845400	2345
AnnaBridge	172:65be27845400	2346	#if defined(I2C4)
AnnaBridge	172:65be27845400	2347	#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge	172:65be27845400	2348	#endif /* I2C4 */
AnnaBridge	172:65be27845400	2349
AnnaBridge	172:65be27845400	2350	#if defined(CRS)
AnnaBridge	172:65be27845400	2351	#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
AnnaBridge	172:65be27845400	2352	#endif /* CRS */
AnnaBridge	172:65be27845400	2353
AnnaBridge	172:65be27845400	2354	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
AnnaBridge	172:65be27845400	2355
AnnaBridge	172:65be27845400	2356	#if defined(CAN2)
AnnaBridge	172:65be27845400	2357	#define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge	172:65be27845400	2358	#endif /* CAN2 */
AnnaBridge	172:65be27845400	2359
AnnaBridge	172:65be27845400	2360	#if defined(USB)
AnnaBridge	172:65be27845400	2361	#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
AnnaBridge	172:65be27845400	2362	#endif /* USB */
AnnaBridge	172:65be27845400	2363
AnnaBridge	172:65be27845400	2364	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
AnnaBridge	172:65be27845400	2365
AnnaBridge	172:65be27845400	2366	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
AnnaBridge	172:65be27845400	2367
AnnaBridge	172:65be27845400	2368	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
AnnaBridge	172:65be27845400	2369
AnnaBridge	172:65be27845400	2370	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
AnnaBridge	172:65be27845400	2371
AnnaBridge	172:65be27845400	2372	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
AnnaBridge	172:65be27845400	2373
AnnaBridge	172:65be27845400	2374	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	2375	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge	172:65be27845400	2376	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	2377
AnnaBridge	172:65be27845400	2378	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
AnnaBridge	172:65be27845400	2379
AnnaBridge	172:65be27845400	2380
AnnaBridge	172:65be27845400	2381	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
AnnaBridge	172:65be27845400	2382
AnnaBridge	172:65be27845400	2383	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
AnnaBridge	172:65be27845400	2384
AnnaBridge	172:65be27845400	2385	#if defined(TIM3)
AnnaBridge	172:65be27845400	2386	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
AnnaBridge	172:65be27845400	2387	#endif /* TIM3 */
AnnaBridge	172:65be27845400	2388
AnnaBridge	172:65be27845400	2389	#if defined(TIM4)
AnnaBridge	172:65be27845400	2390	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
AnnaBridge	172:65be27845400	2391	#endif /* TIM4 */
AnnaBridge	172:65be27845400	2392
AnnaBridge	172:65be27845400	2393	#if defined(TIM5)
AnnaBridge	172:65be27845400	2394	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
AnnaBridge	172:65be27845400	2395	#endif /* TIM5 */
AnnaBridge	172:65be27845400	2396
AnnaBridge	172:65be27845400	2397	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
AnnaBridge	172:65be27845400	2398
AnnaBridge	172:65be27845400	2399	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
AnnaBridge	172:65be27845400	2400
AnnaBridge	172:65be27845400	2401	#if defined(LCD)
AnnaBridge	172:65be27845400	2402	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
AnnaBridge	172:65be27845400	2403	#endif /* LCD */
AnnaBridge	172:65be27845400	2404
AnnaBridge	172:65be27845400	2405	#if defined(SPI2)
AnnaBridge	172:65be27845400	2406	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
AnnaBridge	172:65be27845400	2407	#endif /* SPI2 */
AnnaBridge	172:65be27845400	2408
AnnaBridge	172:65be27845400	2409	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
AnnaBridge	172:65be27845400	2410
AnnaBridge	172:65be27845400	2411	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
AnnaBridge	172:65be27845400	2412
AnnaBridge	172:65be27845400	2413	#if defined(USART3)
AnnaBridge	172:65be27845400	2414	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
AnnaBridge	172:65be27845400	2415	#endif /* USART3 */
AnnaBridge	172:65be27845400	2416
AnnaBridge	172:65be27845400	2417	#if defined(UART4)
AnnaBridge	172:65be27845400	2418	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
AnnaBridge	172:65be27845400	2419	#endif /* UART4 */
AnnaBridge	172:65be27845400	2420
AnnaBridge	172:65be27845400	2421	#if defined(UART5)
AnnaBridge	172:65be27845400	2422	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
AnnaBridge	172:65be27845400	2423	#endif /* UART5 */
AnnaBridge	172:65be27845400	2424
AnnaBridge	172:65be27845400	2425	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
AnnaBridge	172:65be27845400	2426
AnnaBridge	172:65be27845400	2427	#if defined(I2C2)
AnnaBridge	172:65be27845400	2428	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
AnnaBridge	172:65be27845400	2429	#endif /* I2C2 */
AnnaBridge	172:65be27845400	2430
AnnaBridge	172:65be27845400	2431	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
AnnaBridge	172:65be27845400	2432
AnnaBridge	172:65be27845400	2433	#if defined(I2C4)
AnnaBridge	172:65be27845400	2434	#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge	172:65be27845400	2435	#endif /* I2C4 */
AnnaBridge	172:65be27845400	2436
AnnaBridge	172:65be27845400	2437	#if defined(CRS)
AnnaBridge	172:65be27845400	2438	#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
AnnaBridge	172:65be27845400	2439	#endif /* CRS */
AnnaBridge	172:65be27845400	2440
AnnaBridge	172:65be27845400	2441	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
AnnaBridge	172:65be27845400	2442
AnnaBridge	172:65be27845400	2443	#if defined(CAN2)
AnnaBridge	172:65be27845400	2444	#define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge	172:65be27845400	2445	#endif /* CAN2 */
AnnaBridge	172:65be27845400	2446
AnnaBridge	172:65be27845400	2447	#if defined(USB)
AnnaBridge	172:65be27845400	2448	#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
AnnaBridge	172:65be27845400	2449	#endif /* USB */
AnnaBridge	172:65be27845400	2450
AnnaBridge	172:65be27845400	2451	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
AnnaBridge	172:65be27845400	2452
AnnaBridge	172:65be27845400	2453	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
AnnaBridge	172:65be27845400	2454
AnnaBridge	172:65be27845400	2455	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
AnnaBridge	172:65be27845400	2456
AnnaBridge	172:65be27845400	2457	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
AnnaBridge	172:65be27845400	2458
AnnaBridge	172:65be27845400	2459	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
AnnaBridge	172:65be27845400	2460
AnnaBridge	172:65be27845400	2461	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	2462	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge	172:65be27845400	2463	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	2464
AnnaBridge	172:65be27845400	2465	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
AnnaBridge	172:65be27845400	2466
AnnaBridge	172:65be27845400	2467	/**
AnnaBridge	172:65be27845400	2468	* @}
AnnaBridge	172:65be27845400	2469	*/
AnnaBridge	172:65be27845400	2470
AnnaBridge	172:65be27845400	2471	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge	172:65be27845400	2472	* @brief Force or release APB2 peripheral reset.
AnnaBridge	172:65be27845400	2473	* @{
AnnaBridge	172:65be27845400	2474	*/
AnnaBridge	172:65be27845400	2475	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
AnnaBridge	172:65be27845400	2476
AnnaBridge	172:65be27845400	2477	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
AnnaBridge	172:65be27845400	2478
AnnaBridge	172:65be27845400	2479	#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2480	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2481	#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
AnnaBridge	172:65be27845400	2482
AnnaBridge	172:65be27845400	2483	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
AnnaBridge	172:65be27845400	2484
AnnaBridge	172:65be27845400	2485	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
AnnaBridge	172:65be27845400	2486
AnnaBridge	172:65be27845400	2487	#if defined(TIM8)
AnnaBridge	172:65be27845400	2488	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
AnnaBridge	172:65be27845400	2489	#endif /* TIM8 */
AnnaBridge	172:65be27845400	2490
AnnaBridge	172:65be27845400	2491	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
AnnaBridge	172:65be27845400	2492
AnnaBridge	172:65be27845400	2493	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
AnnaBridge	172:65be27845400	2494
AnnaBridge	172:65be27845400	2495	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
AnnaBridge	172:65be27845400	2496
AnnaBridge	172:65be27845400	2497	#if defined(TIM17)
AnnaBridge	172:65be27845400	2498	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
AnnaBridge	172:65be27845400	2499	#endif /* TIM17 */
AnnaBridge	172:65be27845400	2500
AnnaBridge	172:65be27845400	2501	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
AnnaBridge	172:65be27845400	2502
AnnaBridge	172:65be27845400	2503	#if defined(SAI2)
AnnaBridge	172:65be27845400	2504	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
AnnaBridge	172:65be27845400	2505	#endif /* SAI2 */
AnnaBridge	172:65be27845400	2506
AnnaBridge	172:65be27845400	2507	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	2508	#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
AnnaBridge	172:65be27845400	2509	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	2510
AnnaBridge	172:65be27845400	2511	#if defined(LTDC)
AnnaBridge	172:65be27845400	2512	#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
AnnaBridge	172:65be27845400	2513	#endif /* LTDC */
AnnaBridge	172:65be27845400	2514
AnnaBridge	172:65be27845400	2515	#if defined(DSI)
AnnaBridge	172:65be27845400	2516	#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
AnnaBridge	172:65be27845400	2517	#endif /* DSI */
AnnaBridge	172:65be27845400	2518
AnnaBridge	172:65be27845400	2519
AnnaBridge	172:65be27845400	2520	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
AnnaBridge	172:65be27845400	2521
AnnaBridge	172:65be27845400	2522	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
AnnaBridge	172:65be27845400	2523
AnnaBridge	172:65be27845400	2524	#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2525	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge	172:65be27845400	2526	#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
AnnaBridge	172:65be27845400	2527
AnnaBridge	172:65be27845400	2528	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
AnnaBridge	172:65be27845400	2529
AnnaBridge	172:65be27845400	2530	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
AnnaBridge	172:65be27845400	2531
AnnaBridge	172:65be27845400	2532	#if defined(TIM8)
AnnaBridge	172:65be27845400	2533	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
AnnaBridge	172:65be27845400	2534	#endif /* TIM8 */
AnnaBridge	172:65be27845400	2535
AnnaBridge	172:65be27845400	2536	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
AnnaBridge	172:65be27845400	2537
AnnaBridge	172:65be27845400	2538	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
AnnaBridge	172:65be27845400	2539
AnnaBridge	172:65be27845400	2540	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
AnnaBridge	172:65be27845400	2541
AnnaBridge	172:65be27845400	2542	#if defined(TIM17)
AnnaBridge	172:65be27845400	2543	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
AnnaBridge	172:65be27845400	2544	#endif /* TIM17 */
AnnaBridge	172:65be27845400	2545
AnnaBridge	172:65be27845400	2546	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
AnnaBridge	172:65be27845400	2547
AnnaBridge	172:65be27845400	2548	#if defined(SAI2)
AnnaBridge	172:65be27845400	2549	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
AnnaBridge	172:65be27845400	2550	#endif /* SAI2 */
AnnaBridge	172:65be27845400	2551
AnnaBridge	172:65be27845400	2552	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	2553	#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
AnnaBridge	172:65be27845400	2554	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	2555
AnnaBridge	172:65be27845400	2556	#if defined(LTDC)
AnnaBridge	172:65be27845400	2557	#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
AnnaBridge	172:65be27845400	2558	#endif /* LTDC */
AnnaBridge	172:65be27845400	2559
AnnaBridge	172:65be27845400	2560	#if defined(DSI)
AnnaBridge	172:65be27845400	2561	#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
AnnaBridge	172:65be27845400	2562	#endif /* DSI */
AnnaBridge	172:65be27845400	2563
AnnaBridge	172:65be27845400	2564	/**
AnnaBridge	172:65be27845400	2565	* @}
AnnaBridge	172:65be27845400	2566	*/
AnnaBridge	172:65be27845400	2567
AnnaBridge	172:65be27845400	2568	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	172:65be27845400	2569	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2570	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	2571	* power consumption.
AnnaBridge	172:65be27845400	2572	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	2573	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	2574	* @{
AnnaBridge	172:65be27845400	2575	*/
AnnaBridge	172:65be27845400	2576
AnnaBridge	172:65be27845400	2577	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
AnnaBridge	172:65be27845400	2578
AnnaBridge	172:65be27845400	2579	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
AnnaBridge	172:65be27845400	2580
AnnaBridge	172:65be27845400	2581	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	2582	#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
AnnaBridge	172:65be27845400	2583	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	2584
AnnaBridge	172:65be27845400	2585	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
AnnaBridge	172:65be27845400	2586
AnnaBridge	172:65be27845400	2587	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
AnnaBridge	172:65be27845400	2588
AnnaBridge	172:65be27845400	2589	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
AnnaBridge	172:65be27845400	2590
AnnaBridge	172:65be27845400	2591	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
AnnaBridge	172:65be27845400	2592
AnnaBridge	172:65be27845400	2593	#if defined(DMA2D)
AnnaBridge	172:65be27845400	2594	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge	172:65be27845400	2595	#endif /* DMA2D */
AnnaBridge	172:65be27845400	2596
AnnaBridge	172:65be27845400	2597	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	2598	#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
AnnaBridge	172:65be27845400	2599	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	2600
AnnaBridge	172:65be27845400	2601
AnnaBridge	172:65be27845400	2602	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
AnnaBridge	172:65be27845400	2603
AnnaBridge	172:65be27845400	2604	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
AnnaBridge	172:65be27845400	2605
AnnaBridge	172:65be27845400	2606	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	2607	#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
AnnaBridge	172:65be27845400	2608	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	2609
AnnaBridge	172:65be27845400	2610	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
AnnaBridge	172:65be27845400	2611
AnnaBridge	172:65be27845400	2612	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
AnnaBridge	172:65be27845400	2613
AnnaBridge	172:65be27845400	2614	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
AnnaBridge	172:65be27845400	2615
AnnaBridge	172:65be27845400	2616	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
AnnaBridge	172:65be27845400	2617
AnnaBridge	172:65be27845400	2618	#if defined(DMA2D)
AnnaBridge	172:65be27845400	2619	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge	172:65be27845400	2620	#endif /* DMA2D */
AnnaBridge	172:65be27845400	2621
AnnaBridge	172:65be27845400	2622	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	2623	#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
AnnaBridge	172:65be27845400	2624	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	2625
AnnaBridge	172:65be27845400	2626	/**
AnnaBridge	172:65be27845400	2627	* @}
AnnaBridge	172:65be27845400	2628	*/
AnnaBridge	172:65be27845400	2629
AnnaBridge	172:65be27845400	2630	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	172:65be27845400	2631	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2632	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	2633	* power consumption.
AnnaBridge	172:65be27845400	2634	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	2635	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	2636	* @{
AnnaBridge	172:65be27845400	2637	*/
AnnaBridge	172:65be27845400	2638
AnnaBridge	172:65be27845400	2639	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
AnnaBridge	172:65be27845400	2640
AnnaBridge	172:65be27845400	2641	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
AnnaBridge	172:65be27845400	2642
AnnaBridge	172:65be27845400	2643	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
AnnaBridge	172:65be27845400	2644
AnnaBridge	172:65be27845400	2645	#if defined(GPIOD)
AnnaBridge	172:65be27845400	2646	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
AnnaBridge	172:65be27845400	2647	#endif /* GPIOD */
AnnaBridge	172:65be27845400	2648
AnnaBridge	172:65be27845400	2649	#if defined(GPIOE)
AnnaBridge	172:65be27845400	2650	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
AnnaBridge	172:65be27845400	2651	#endif /* GPIOE */
AnnaBridge	172:65be27845400	2652
AnnaBridge	172:65be27845400	2653	#if defined(GPIOF)
AnnaBridge	172:65be27845400	2654	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
AnnaBridge	172:65be27845400	2655	#endif /* GPIOF */
AnnaBridge	172:65be27845400	2656
AnnaBridge	172:65be27845400	2657	#if defined(GPIOG)
AnnaBridge	172:65be27845400	2658	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
AnnaBridge	172:65be27845400	2659	#endif /* GPIOG */
AnnaBridge	172:65be27845400	2660
AnnaBridge	172:65be27845400	2661	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
AnnaBridge	172:65be27845400	2662
AnnaBridge	172:65be27845400	2663	#if defined(GPIOI)
AnnaBridge	172:65be27845400	2664	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge	172:65be27845400	2665	#endif /* GPIOI */
AnnaBridge	172:65be27845400	2666
AnnaBridge	172:65be27845400	2667	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
AnnaBridge	172:65be27845400	2668
AnnaBridge	172:65be27845400	2669	#if defined(SRAM3)
AnnaBridge	172:65be27845400	2670	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
AnnaBridge	172:65be27845400	2671	#endif /* SRAM3 */
AnnaBridge	172:65be27845400	2672
AnnaBridge	172:65be27845400	2673	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	2674	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
AnnaBridge	172:65be27845400	2675	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	2676
AnnaBridge	172:65be27845400	2677	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
AnnaBridge	172:65be27845400	2678
AnnaBridge	172:65be27845400	2679	#if defined(DCMI)
AnnaBridge	172:65be27845400	2680	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge	172:65be27845400	2681	#endif /* DCMI */
AnnaBridge	172:65be27845400	2682
AnnaBridge	172:65be27845400	2683	#if defined(AES)
AnnaBridge	172:65be27845400	2684	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
AnnaBridge	172:65be27845400	2685	#endif /* AES */
AnnaBridge	172:65be27845400	2686
AnnaBridge	172:65be27845400	2687	#if defined(HASH)
AnnaBridge	172:65be27845400	2688	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge	172:65be27845400	2689	#endif /* HASH */
AnnaBridge	172:65be27845400	2690
AnnaBridge	172:65be27845400	2691	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
AnnaBridge	172:65be27845400	2692
AnnaBridge	172:65be27845400	2693	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	2694	#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
AnnaBridge	172:65be27845400	2695	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	2696
AnnaBridge	172:65be27845400	2697	#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	2698	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	2699	#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	2700
AnnaBridge	172:65be27845400	2701
AnnaBridge	172:65be27845400	2702	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
AnnaBridge	172:65be27845400	2703
AnnaBridge	172:65be27845400	2704	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
AnnaBridge	172:65be27845400	2705
AnnaBridge	172:65be27845400	2706	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
AnnaBridge	172:65be27845400	2707
AnnaBridge	172:65be27845400	2708	#if defined(GPIOD)
AnnaBridge	172:65be27845400	2709	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
AnnaBridge	172:65be27845400	2710	#endif /* GPIOD */
AnnaBridge	172:65be27845400	2711
AnnaBridge	172:65be27845400	2712	#if defined(GPIOE)
AnnaBridge	172:65be27845400	2713	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
AnnaBridge	172:65be27845400	2714	#endif /* GPIOE */
AnnaBridge	172:65be27845400	2715
AnnaBridge	172:65be27845400	2716	#if defined(GPIOF)
AnnaBridge	172:65be27845400	2717	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
AnnaBridge	172:65be27845400	2718	#endif /* GPIOF */
AnnaBridge	172:65be27845400	2719
AnnaBridge	172:65be27845400	2720	#if defined(GPIOG)
AnnaBridge	172:65be27845400	2721	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
AnnaBridge	172:65be27845400	2722	#endif /* GPIOG */
AnnaBridge	172:65be27845400	2723
AnnaBridge	172:65be27845400	2724	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
AnnaBridge	172:65be27845400	2725
AnnaBridge	172:65be27845400	2726	#if defined(GPIOI)
AnnaBridge	172:65be27845400	2727	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge	172:65be27845400	2728	#endif /* GPIOI */
AnnaBridge	172:65be27845400	2729
AnnaBridge	172:65be27845400	2730	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
AnnaBridge	172:65be27845400	2731
AnnaBridge	172:65be27845400	2732	#if defined(SRAM3)
AnnaBridge	172:65be27845400	2733	#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
AnnaBridge	172:65be27845400	2734	#endif /* SRAM3 */
AnnaBridge	172:65be27845400	2735
AnnaBridge	172:65be27845400	2736	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	2737	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
AnnaBridge	172:65be27845400	2738	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	2739
AnnaBridge	172:65be27845400	2740	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
AnnaBridge	172:65be27845400	2741
AnnaBridge	172:65be27845400	2742	#if defined(DCMI)
AnnaBridge	172:65be27845400	2743	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge	172:65be27845400	2744	#endif /* DCMI */
AnnaBridge	172:65be27845400	2745
AnnaBridge	172:65be27845400	2746	#if defined(AES)
AnnaBridge	172:65be27845400	2747	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
AnnaBridge	172:65be27845400	2748	#endif /* AES */
AnnaBridge	172:65be27845400	2749
AnnaBridge	172:65be27845400	2750	#if defined(HASH)
AnnaBridge	172:65be27845400	2751	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge	172:65be27845400	2752	#endif /* HASH */
AnnaBridge	172:65be27845400	2753
AnnaBridge	172:65be27845400	2754	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
AnnaBridge	172:65be27845400	2755
AnnaBridge	172:65be27845400	2756	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	2757	#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
AnnaBridge	172:65be27845400	2758	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	2759
AnnaBridge	172:65be27845400	2760	#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	2761	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	2762	#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	2763
AnnaBridge	172:65be27845400	2764	/**
AnnaBridge	172:65be27845400	2765	* @}
AnnaBridge	172:65be27845400	2766	*/
AnnaBridge	172:65be27845400	2767
AnnaBridge	172:65be27845400	2768	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
AnnaBridge	172:65be27845400	2769	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2770	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	2771	* power consumption.
AnnaBridge	172:65be27845400	2772	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	2773	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	2774	* @{
AnnaBridge	172:65be27845400	2775	*/
AnnaBridge	172:65be27845400	2776
AnnaBridge	172:65be27845400	2777	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	2778	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
AnnaBridge	172:65be27845400	2779	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	2780
AnnaBridge	172:65be27845400	2781	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	2782	#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
AnnaBridge	172:65be27845400	2783	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	2784
AnnaBridge	172:65be27845400	2785	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	2786	#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
AnnaBridge	172:65be27845400	2787	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	2788
AnnaBridge	172:65be27845400	2789	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	2790	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
AnnaBridge	172:65be27845400	2791	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	2792
AnnaBridge	172:65be27845400	2793	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	2794	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
AnnaBridge	172:65be27845400	2795	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	2796
AnnaBridge	172:65be27845400	2797	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	2798	#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
AnnaBridge	172:65be27845400	2799	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	2800
AnnaBridge	172:65be27845400	2801	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	2802	#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
AnnaBridge	172:65be27845400	2803	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	2804
AnnaBridge	172:65be27845400	2805	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	2806	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
AnnaBridge	172:65be27845400	2807	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	2808
AnnaBridge	172:65be27845400	2809	/**
AnnaBridge	172:65be27845400	2810	* @}
AnnaBridge	172:65be27845400	2811	*/
AnnaBridge	172:65be27845400	2812
AnnaBridge	172:65be27845400	2813	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	172:65be27845400	2814	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	2816	* power consumption.
AnnaBridge	172:65be27845400	2817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	2818	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	2819	* @{
AnnaBridge	172:65be27845400	2820	*/
AnnaBridge	172:65be27845400	2821
AnnaBridge	172:65be27845400	2822	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
AnnaBridge	172:65be27845400	2823
AnnaBridge	172:65be27845400	2824	#if defined(TIM3)
AnnaBridge	172:65be27845400	2825	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
AnnaBridge	172:65be27845400	2826	#endif /* TIM3 */
AnnaBridge	172:65be27845400	2827
AnnaBridge	172:65be27845400	2828	#if defined(TIM4)
AnnaBridge	172:65be27845400	2829	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
AnnaBridge	172:65be27845400	2830	#endif /* TIM4 */
AnnaBridge	172:65be27845400	2831
AnnaBridge	172:65be27845400	2832	#if defined(TIM5)
AnnaBridge	172:65be27845400	2833	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
AnnaBridge	172:65be27845400	2834	#endif /* TIM5 */
AnnaBridge	172:65be27845400	2835
AnnaBridge	172:65be27845400	2836	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
AnnaBridge	172:65be27845400	2837
AnnaBridge	172:65be27845400	2838	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
AnnaBridge	172:65be27845400	2839
AnnaBridge	172:65be27845400	2840	#if defined(LCD)
AnnaBridge	172:65be27845400	2841	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
AnnaBridge	172:65be27845400	2842	#endif /* LCD */
AnnaBridge	172:65be27845400	2843
AnnaBridge	172:65be27845400	2844	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	172:65be27845400	2845	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	172:65be27845400	2846	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	172:65be27845400	2847
AnnaBridge	172:65be27845400	2848	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
AnnaBridge	172:65be27845400	2849
AnnaBridge	172:65be27845400	2850	#if defined(SPI2)
AnnaBridge	172:65be27845400	2851	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
AnnaBridge	172:65be27845400	2852	#endif /* SPI2 */
AnnaBridge	172:65be27845400	2853
AnnaBridge	172:65be27845400	2854	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
AnnaBridge	172:65be27845400	2855
AnnaBridge	172:65be27845400	2856	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
AnnaBridge	172:65be27845400	2857
AnnaBridge	172:65be27845400	2858	#if defined(USART3)
AnnaBridge	172:65be27845400	2859	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
AnnaBridge	172:65be27845400	2860	#endif /* USART3 */
AnnaBridge	172:65be27845400	2861
AnnaBridge	172:65be27845400	2862	#if defined(UART4)
AnnaBridge	172:65be27845400	2863	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
AnnaBridge	172:65be27845400	2864	#endif /* UART4 */
AnnaBridge	172:65be27845400	2865
AnnaBridge	172:65be27845400	2866	#if defined(UART5)
AnnaBridge	172:65be27845400	2867	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
AnnaBridge	172:65be27845400	2868	#endif /* UART5 */
AnnaBridge	172:65be27845400	2869
AnnaBridge	172:65be27845400	2870	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
AnnaBridge	172:65be27845400	2871
AnnaBridge	172:65be27845400	2872	#if defined(I2C2)
AnnaBridge	172:65be27845400	2873	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
AnnaBridge	172:65be27845400	2874	#endif /* I2C2 */
AnnaBridge	172:65be27845400	2875
AnnaBridge	172:65be27845400	2876	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
AnnaBridge	172:65be27845400	2877
AnnaBridge	172:65be27845400	2878	#if defined(I2C4)
AnnaBridge	172:65be27845400	2879	#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge	172:65be27845400	2880	#endif /* I2C4 */
AnnaBridge	172:65be27845400	2881
AnnaBridge	172:65be27845400	2882	#if defined(CRS)
AnnaBridge	172:65be27845400	2883	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
AnnaBridge	172:65be27845400	2884	#endif /* CRS */
AnnaBridge	172:65be27845400	2885
AnnaBridge	172:65be27845400	2886	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
AnnaBridge	172:65be27845400	2887
AnnaBridge	172:65be27845400	2888	#if defined(CAN2)
AnnaBridge	172:65be27845400	2889	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge	172:65be27845400	2890	#endif /* CAN2 */
AnnaBridge	172:65be27845400	2891
AnnaBridge	172:65be27845400	2892	#if defined(USB)
AnnaBridge	172:65be27845400	2893	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
AnnaBridge	172:65be27845400	2894	#endif /* USB */
AnnaBridge	172:65be27845400	2895
AnnaBridge	172:65be27845400	2896	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
AnnaBridge	172:65be27845400	2897
AnnaBridge	172:65be27845400	2898	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
AnnaBridge	172:65be27845400	2899
AnnaBridge	172:65be27845400	2900	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
AnnaBridge	172:65be27845400	2901
AnnaBridge	172:65be27845400	2902	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
AnnaBridge	172:65be27845400	2903
AnnaBridge	172:65be27845400	2904	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
AnnaBridge	172:65be27845400	2905
AnnaBridge	172:65be27845400	2906	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	2907	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge	172:65be27845400	2908	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	2909
AnnaBridge	172:65be27845400	2910	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
AnnaBridge	172:65be27845400	2911
AnnaBridge	172:65be27845400	2912
AnnaBridge	172:65be27845400	2913	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
AnnaBridge	172:65be27845400	2914
AnnaBridge	172:65be27845400	2915	#if defined(TIM3)
AnnaBridge	172:65be27845400	2916	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
AnnaBridge	172:65be27845400	2917	#endif /* TIM3 */
AnnaBridge	172:65be27845400	2918
AnnaBridge	172:65be27845400	2919	#if defined(TIM4)
AnnaBridge	172:65be27845400	2920	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
AnnaBridge	172:65be27845400	2921	#endif /* TIM4 */
AnnaBridge	172:65be27845400	2922
AnnaBridge	172:65be27845400	2923	#if defined(TIM5)
AnnaBridge	172:65be27845400	2924	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
AnnaBridge	172:65be27845400	2925	#endif /* TIM5 */
AnnaBridge	172:65be27845400	2926
AnnaBridge	172:65be27845400	2927	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
AnnaBridge	172:65be27845400	2928
AnnaBridge	172:65be27845400	2929	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
AnnaBridge	172:65be27845400	2930
AnnaBridge	172:65be27845400	2931	#if defined(LCD)
AnnaBridge	172:65be27845400	2932	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
AnnaBridge	172:65be27845400	2933	#endif /* LCD */
AnnaBridge	172:65be27845400	2934
AnnaBridge	172:65be27845400	2935	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	172:65be27845400	2936	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	172:65be27845400	2937	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	172:65be27845400	2938
AnnaBridge	172:65be27845400	2939	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
AnnaBridge	172:65be27845400	2940
AnnaBridge	172:65be27845400	2941	#if defined(SPI2)
AnnaBridge	172:65be27845400	2942	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
AnnaBridge	172:65be27845400	2943	#endif /* SPI2 */
AnnaBridge	172:65be27845400	2944
AnnaBridge	172:65be27845400	2945	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
AnnaBridge	172:65be27845400	2946
AnnaBridge	172:65be27845400	2947	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
AnnaBridge	172:65be27845400	2948
AnnaBridge	172:65be27845400	2949	#if defined(USART3)
AnnaBridge	172:65be27845400	2950	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
AnnaBridge	172:65be27845400	2951	#endif /* USART3 */
AnnaBridge	172:65be27845400	2952
AnnaBridge	172:65be27845400	2953	#if defined(UART4)
AnnaBridge	172:65be27845400	2954	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
AnnaBridge	172:65be27845400	2955	#endif /* UART4 */
AnnaBridge	172:65be27845400	2956
AnnaBridge	172:65be27845400	2957	#if defined(UART5)
AnnaBridge	172:65be27845400	2958	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
AnnaBridge	172:65be27845400	2959	#endif /* UART5 */
AnnaBridge	172:65be27845400	2960
AnnaBridge	172:65be27845400	2961	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
AnnaBridge	172:65be27845400	2962
AnnaBridge	172:65be27845400	2963	#if defined(I2C2)
AnnaBridge	172:65be27845400	2964	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
AnnaBridge	172:65be27845400	2965	#endif /* I2C2 */
AnnaBridge	172:65be27845400	2966
AnnaBridge	172:65be27845400	2967	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
AnnaBridge	172:65be27845400	2968
AnnaBridge	172:65be27845400	2969	#if defined(I2C4)
AnnaBridge	172:65be27845400	2970	#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge	172:65be27845400	2971	#endif /* I2C4 */
AnnaBridge	172:65be27845400	2972
AnnaBridge	172:65be27845400	2973	#if defined(CRS)
AnnaBridge	172:65be27845400	2974	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
AnnaBridge	172:65be27845400	2975	#endif /* CRS */
AnnaBridge	172:65be27845400	2976
AnnaBridge	172:65be27845400	2977	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
AnnaBridge	172:65be27845400	2978
AnnaBridge	172:65be27845400	2979	#if defined(CAN2)
AnnaBridge	172:65be27845400	2980	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge	172:65be27845400	2981	#endif /* CAN2 */
AnnaBridge	172:65be27845400	2982
AnnaBridge	172:65be27845400	2983	#if defined(USB)
AnnaBridge	172:65be27845400	2984	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
AnnaBridge	172:65be27845400	2985	#endif /* USB */
AnnaBridge	172:65be27845400	2986
AnnaBridge	172:65be27845400	2987	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
AnnaBridge	172:65be27845400	2988
AnnaBridge	172:65be27845400	2989	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
AnnaBridge	172:65be27845400	2990
AnnaBridge	172:65be27845400	2991	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
AnnaBridge	172:65be27845400	2992
AnnaBridge	172:65be27845400	2993	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
AnnaBridge	172:65be27845400	2994
AnnaBridge	172:65be27845400	2995	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
AnnaBridge	172:65be27845400	2996
AnnaBridge	172:65be27845400	2997	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	2998	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge	172:65be27845400	2999	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	3000
AnnaBridge	172:65be27845400	3001	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
AnnaBridge	172:65be27845400	3002
AnnaBridge	172:65be27845400	3003	/**
AnnaBridge	172:65be27845400	3004	* @}
AnnaBridge	172:65be27845400	3005	*/
AnnaBridge	172:65be27845400	3006
AnnaBridge	172:65be27845400	3007	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	172:65be27845400	3008	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	3009	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	3010	* power consumption.
AnnaBridge	172:65be27845400	3011	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	3012	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	3013	* @{
AnnaBridge	172:65be27845400	3014	*/
AnnaBridge	172:65be27845400	3015
AnnaBridge	172:65be27845400	3016	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
AnnaBridge	172:65be27845400	3017
AnnaBridge	172:65be27845400	3018	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3019	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3020	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	3021
AnnaBridge	172:65be27845400	3022	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
AnnaBridge	172:65be27845400	3023
AnnaBridge	172:65be27845400	3024	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
AnnaBridge	172:65be27845400	3025
AnnaBridge	172:65be27845400	3026	#if defined(TIM8)
AnnaBridge	172:65be27845400	3027	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
AnnaBridge	172:65be27845400	3028	#endif /* TIM8 */
AnnaBridge	172:65be27845400	3029
AnnaBridge	172:65be27845400	3030	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
AnnaBridge	172:65be27845400	3031
AnnaBridge	172:65be27845400	3032	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
AnnaBridge	172:65be27845400	3033
AnnaBridge	172:65be27845400	3034	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
AnnaBridge	172:65be27845400	3035
AnnaBridge	172:65be27845400	3036	#if defined(TIM17)
AnnaBridge	172:65be27845400	3037	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
AnnaBridge	172:65be27845400	3038	#endif /* TIM17 */
AnnaBridge	172:65be27845400	3039
AnnaBridge	172:65be27845400	3040	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
AnnaBridge	172:65be27845400	3041
AnnaBridge	172:65be27845400	3042	#if defined(SAI2)
AnnaBridge	172:65be27845400	3043	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
AnnaBridge	172:65be27845400	3044	#endif /* SAI2 */
AnnaBridge	172:65be27845400	3045
AnnaBridge	172:65be27845400	3046	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	3047	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
AnnaBridge	172:65be27845400	3048	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	3049
AnnaBridge	172:65be27845400	3050	#if defined(LTDC)
AnnaBridge	172:65be27845400	3051	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
AnnaBridge	172:65be27845400	3052	#endif /* LTDC */
AnnaBridge	172:65be27845400	3053
AnnaBridge	172:65be27845400	3054	#if defined(DSI)
AnnaBridge	172:65be27845400	3055	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
AnnaBridge	172:65be27845400	3056	#endif /* DSI */
AnnaBridge	172:65be27845400	3057
AnnaBridge	172:65be27845400	3058
AnnaBridge	172:65be27845400	3059	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
AnnaBridge	172:65be27845400	3060
AnnaBridge	172:65be27845400	3061	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3062	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3063	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	3064
AnnaBridge	172:65be27845400	3065	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
AnnaBridge	172:65be27845400	3066
AnnaBridge	172:65be27845400	3067	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
AnnaBridge	172:65be27845400	3068
AnnaBridge	172:65be27845400	3069	#if defined(TIM8)
AnnaBridge	172:65be27845400	3070	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
AnnaBridge	172:65be27845400	3071	#endif /* TIM8 */
AnnaBridge	172:65be27845400	3072
AnnaBridge	172:65be27845400	3073	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
AnnaBridge	172:65be27845400	3074
AnnaBridge	172:65be27845400	3075	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
AnnaBridge	172:65be27845400	3076
AnnaBridge	172:65be27845400	3077	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
AnnaBridge	172:65be27845400	3078
AnnaBridge	172:65be27845400	3079	#if defined(TIM17)
AnnaBridge	172:65be27845400	3080	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
AnnaBridge	172:65be27845400	3081	#endif /* TIM17 */
AnnaBridge	172:65be27845400	3082
AnnaBridge	172:65be27845400	3083	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
AnnaBridge	172:65be27845400	3084
AnnaBridge	172:65be27845400	3085	#if defined(SAI2)
AnnaBridge	172:65be27845400	3086	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
AnnaBridge	172:65be27845400	3087	#endif /* SAI2 */
AnnaBridge	172:65be27845400	3088
AnnaBridge	172:65be27845400	3089	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	3090	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
AnnaBridge	172:65be27845400	3091	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	3092
AnnaBridge	172:65be27845400	3093	#if defined(LTDC)
AnnaBridge	172:65be27845400	3094	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
AnnaBridge	172:65be27845400	3095	#endif /* LTDC */
AnnaBridge	172:65be27845400	3096
AnnaBridge	172:65be27845400	3097	#if defined(DSI)
AnnaBridge	172:65be27845400	3098	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
AnnaBridge	172:65be27845400	3099	#endif /* DSI */
AnnaBridge	172:65be27845400	3100
AnnaBridge	172:65be27845400	3101	/**
AnnaBridge	172:65be27845400	3102	* @}
AnnaBridge	172:65be27845400	3103	*/
AnnaBridge	172:65be27845400	3104
AnnaBridge	172:65be27845400	3105	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	172:65be27845400	3106	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	172:65be27845400	3107	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	3108	* power consumption.
AnnaBridge	172:65be27845400	3109	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	3110	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	3111	* @{
AnnaBridge	172:65be27845400	3112	*/
AnnaBridge	172:65be27845400	3113
AnnaBridge	172:65be27845400	3114	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
AnnaBridge	172:65be27845400	3115
AnnaBridge	172:65be27845400	3116	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
AnnaBridge	172:65be27845400	3117
AnnaBridge	172:65be27845400	3118	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	3119	#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET)
AnnaBridge	172:65be27845400	3120	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	3121
AnnaBridge	172:65be27845400	3122	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
AnnaBridge	172:65be27845400	3123
AnnaBridge	172:65be27845400	3124	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
AnnaBridge	172:65be27845400	3125
AnnaBridge	172:65be27845400	3126	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
AnnaBridge	172:65be27845400	3127
AnnaBridge	172:65be27845400	3128	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
AnnaBridge	172:65be27845400	3129
AnnaBridge	172:65be27845400	3130	#if defined(DMA2D)
AnnaBridge	172:65be27845400	3131	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET)
AnnaBridge	172:65be27845400	3132	#endif /* DMA2D */
AnnaBridge	172:65be27845400	3133
AnnaBridge	172:65be27845400	3134	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	3135	#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET)
AnnaBridge	172:65be27845400	3136	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	3137
AnnaBridge	172:65be27845400	3138
AnnaBridge	172:65be27845400	3139	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
AnnaBridge	172:65be27845400	3140
AnnaBridge	172:65be27845400	3141	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
AnnaBridge	172:65be27845400	3142
AnnaBridge	172:65be27845400	3143	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	3144	#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET)
AnnaBridge	172:65be27845400	3145	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	3146
AnnaBridge	172:65be27845400	3147	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
AnnaBridge	172:65be27845400	3148
AnnaBridge	172:65be27845400	3149	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
AnnaBridge	172:65be27845400	3150
AnnaBridge	172:65be27845400	3151	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
AnnaBridge	172:65be27845400	3152
AnnaBridge	172:65be27845400	3153	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
AnnaBridge	172:65be27845400	3154
AnnaBridge	172:65be27845400	3155	#if defined(DMA2D)
AnnaBridge	172:65be27845400	3156	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET)
AnnaBridge	172:65be27845400	3157	#endif /* DMA2D */
AnnaBridge	172:65be27845400	3158
AnnaBridge	172:65be27845400	3159	#if defined(GFXMMU)
AnnaBridge	172:65be27845400	3160	#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET)
AnnaBridge	172:65be27845400	3161	#endif /* GFXMMU */
AnnaBridge	172:65be27845400	3162
AnnaBridge	172:65be27845400	3163	/**
AnnaBridge	172:65be27845400	3164	* @}
AnnaBridge	172:65be27845400	3165	*/
AnnaBridge	172:65be27845400	3166
AnnaBridge	172:65be27845400	3167	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	172:65be27845400	3168	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	172:65be27845400	3169	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	3170	* power consumption.
AnnaBridge	172:65be27845400	3171	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	3172	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	3173	* @{
AnnaBridge	172:65be27845400	3174	*/
AnnaBridge	172:65be27845400	3175
AnnaBridge	172:65be27845400	3176	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
AnnaBridge	172:65be27845400	3177
AnnaBridge	172:65be27845400	3178	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
AnnaBridge	172:65be27845400	3179
AnnaBridge	172:65be27845400	3180	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
AnnaBridge	172:65be27845400	3181
AnnaBridge	172:65be27845400	3182	#if defined(GPIOD)
AnnaBridge	172:65be27845400	3183	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
AnnaBridge	172:65be27845400	3184	#endif /* GPIOD */
AnnaBridge	172:65be27845400	3185
AnnaBridge	172:65be27845400	3186	#if defined(GPIOE)
AnnaBridge	172:65be27845400	3187	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
AnnaBridge	172:65be27845400	3188	#endif /* GPIOE */
AnnaBridge	172:65be27845400	3189
AnnaBridge	172:65be27845400	3190	#if defined(GPIOF)
AnnaBridge	172:65be27845400	3191	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
AnnaBridge	172:65be27845400	3192	#endif /* GPIOF */
AnnaBridge	172:65be27845400	3193
AnnaBridge	172:65be27845400	3194	#if defined(GPIOG)
AnnaBridge	172:65be27845400	3195	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
AnnaBridge	172:65be27845400	3196	#endif /* GPIOG */
AnnaBridge	172:65be27845400	3197
AnnaBridge	172:65be27845400	3198	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
AnnaBridge	172:65be27845400	3199
AnnaBridge	172:65be27845400	3200	#if defined(GPIOI)
AnnaBridge	172:65be27845400	3201	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET)
AnnaBridge	172:65be27845400	3202	#endif /* GPIOI */
AnnaBridge	172:65be27845400	3203
AnnaBridge	172:65be27845400	3204	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
AnnaBridge	172:65be27845400	3205
AnnaBridge	172:65be27845400	3206	#if defined(SRAM3)
AnnaBridge	172:65be27845400	3207	#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET)
AnnaBridge	172:65be27845400	3208	#endif /* SRAM3 */
AnnaBridge	172:65be27845400	3209
AnnaBridge	172:65be27845400	3210	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	3211	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
AnnaBridge	172:65be27845400	3212	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	3213
AnnaBridge	172:65be27845400	3214	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
AnnaBridge	172:65be27845400	3215
AnnaBridge	172:65be27845400	3216	#if defined(DCMI)
AnnaBridge	172:65be27845400	3217	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET)
AnnaBridge	172:65be27845400	3218	#endif /* DCMI */
AnnaBridge	172:65be27845400	3219
AnnaBridge	172:65be27845400	3220	#if defined(AES)
AnnaBridge	172:65be27845400	3221	#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
AnnaBridge	172:65be27845400	3222	#endif /* AES */
AnnaBridge	172:65be27845400	3223
AnnaBridge	172:65be27845400	3224	#if defined(HASH)
AnnaBridge	172:65be27845400	3225	#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET)
AnnaBridge	172:65be27845400	3226	#endif /* HASH */
AnnaBridge	172:65be27845400	3227
AnnaBridge	172:65be27845400	3228	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
AnnaBridge	172:65be27845400	3229
AnnaBridge	172:65be27845400	3230	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	3231	#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET)
AnnaBridge	172:65be27845400	3232	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	3233
AnnaBridge	172:65be27845400	3234	#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3235	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET)
AnnaBridge	172:65be27845400	3236	#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	3237
AnnaBridge	172:65be27845400	3238
AnnaBridge	172:65be27845400	3239	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
AnnaBridge	172:65be27845400	3240
AnnaBridge	172:65be27845400	3241	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
AnnaBridge	172:65be27845400	3242
AnnaBridge	172:65be27845400	3243	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
AnnaBridge	172:65be27845400	3244
AnnaBridge	172:65be27845400	3245	#if defined(GPIOD)
AnnaBridge	172:65be27845400	3246	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
AnnaBridge	172:65be27845400	3247	#endif /* GPIOD */
AnnaBridge	172:65be27845400	3248
AnnaBridge	172:65be27845400	3249	#if defined(GPIOE)
AnnaBridge	172:65be27845400	3250	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
AnnaBridge	172:65be27845400	3251	#endif /* GPIOE */
AnnaBridge	172:65be27845400	3252
AnnaBridge	172:65be27845400	3253	#if defined(GPIOF)
AnnaBridge	172:65be27845400	3254	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
AnnaBridge	172:65be27845400	3255	#endif /* GPIOF */
AnnaBridge	172:65be27845400	3256
AnnaBridge	172:65be27845400	3257	#if defined(GPIOG)
AnnaBridge	172:65be27845400	3258	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
AnnaBridge	172:65be27845400	3259	#endif /* GPIOG */
AnnaBridge	172:65be27845400	3260
AnnaBridge	172:65be27845400	3261	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
AnnaBridge	172:65be27845400	3262
AnnaBridge	172:65be27845400	3263	#if defined(GPIOI)
AnnaBridge	172:65be27845400	3264	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET)
AnnaBridge	172:65be27845400	3265	#endif /* GPIOI */
AnnaBridge	172:65be27845400	3266
AnnaBridge	172:65be27845400	3267	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
AnnaBridge	172:65be27845400	3268
AnnaBridge	172:65be27845400	3269	#if defined(SRAM3)
AnnaBridge	172:65be27845400	3270	#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET)
AnnaBridge	172:65be27845400	3271	#endif /* SRAM3 */
AnnaBridge	172:65be27845400	3272
AnnaBridge	172:65be27845400	3273	#if defined(USB_OTG_FS)
AnnaBridge	172:65be27845400	3274	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
AnnaBridge	172:65be27845400	3275	#endif /* USB_OTG_FS */
AnnaBridge	172:65be27845400	3276
AnnaBridge	172:65be27845400	3277	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
AnnaBridge	172:65be27845400	3278
AnnaBridge	172:65be27845400	3279	#if defined(DCMI)
AnnaBridge	172:65be27845400	3280	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET)
AnnaBridge	172:65be27845400	3281	#endif /* DCMI */
AnnaBridge	172:65be27845400	3282
AnnaBridge	172:65be27845400	3283	#if defined(AES)
AnnaBridge	172:65be27845400	3284	#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
AnnaBridge	172:65be27845400	3285	#endif /* AES */
AnnaBridge	172:65be27845400	3286
AnnaBridge	172:65be27845400	3287	#if defined(HASH)
AnnaBridge	172:65be27845400	3288	#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET)
AnnaBridge	172:65be27845400	3289	#endif /* HASH */
AnnaBridge	172:65be27845400	3290
AnnaBridge	172:65be27845400	3291	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
AnnaBridge	172:65be27845400	3292
AnnaBridge	172:65be27845400	3293	#if defined(OCTOSPIM)
AnnaBridge	172:65be27845400	3294	#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET)
AnnaBridge	172:65be27845400	3295	#endif /* OCTOSPIM */
AnnaBridge	172:65be27845400	3296
AnnaBridge	172:65be27845400	3297	#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3298	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET)
AnnaBridge	172:65be27845400	3299	#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	3300
AnnaBridge	172:65be27845400	3301	/**
AnnaBridge	172:65be27845400	3302	* @}
AnnaBridge	172:65be27845400	3303	*/
AnnaBridge	172:65be27845400	3304
AnnaBridge	172:65be27845400	3305	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	172:65be27845400	3306	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	172:65be27845400	3307	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	3308	* power consumption.
AnnaBridge	172:65be27845400	3309	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	3310	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	3311	* @{
AnnaBridge	172:65be27845400	3312	*/
AnnaBridge	172:65be27845400	3313
AnnaBridge	172:65be27845400	3314	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	3315	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
AnnaBridge	172:65be27845400	3316	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	3317
AnnaBridge	172:65be27845400	3318	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	3319	#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET)
AnnaBridge	172:65be27845400	3320	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	3321
AnnaBridge	172:65be27845400	3322	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	3323	#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET)
AnnaBridge	172:65be27845400	3324	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	3325
AnnaBridge	172:65be27845400	3326	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	3327	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
AnnaBridge	172:65be27845400	3328	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	3329
AnnaBridge	172:65be27845400	3330
AnnaBridge	172:65be27845400	3331	#if defined(QUADSPI)
AnnaBridge	172:65be27845400	3332	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
AnnaBridge	172:65be27845400	3333	#endif /* QUADSPI */
AnnaBridge	172:65be27845400	3334
AnnaBridge	172:65be27845400	3335	#if defined(OCTOSPI1)
AnnaBridge	172:65be27845400	3336	#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET)
AnnaBridge	172:65be27845400	3337	#endif /* OCTOSPI1 */
AnnaBridge	172:65be27845400	3338
AnnaBridge	172:65be27845400	3339	#if defined(OCTOSPI2)
AnnaBridge	172:65be27845400	3340	#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET)
AnnaBridge	172:65be27845400	3341	#endif /* OCTOSPI2 */
AnnaBridge	172:65be27845400	3342
AnnaBridge	172:65be27845400	3343	#if defined(FMC_BANK1)
AnnaBridge	172:65be27845400	3344	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
AnnaBridge	172:65be27845400	3345	#endif /* FMC_BANK1 */
AnnaBridge	172:65be27845400	3346
AnnaBridge	172:65be27845400	3347	/**
AnnaBridge	172:65be27845400	3348	* @}
AnnaBridge	172:65be27845400	3349	*/
AnnaBridge	172:65be27845400	3350
AnnaBridge	172:65be27845400	3351	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	172:65be27845400	3352	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	172:65be27845400	3353	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	3354	* power consumption.
AnnaBridge	172:65be27845400	3355	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	3356	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	3357	* @{
AnnaBridge	172:65be27845400	3358	*/
AnnaBridge	172:65be27845400	3359
AnnaBridge	172:65be27845400	3360	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
AnnaBridge	172:65be27845400	3361
AnnaBridge	172:65be27845400	3362	#if defined(TIM3)
AnnaBridge	172:65be27845400	3363	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
AnnaBridge	172:65be27845400	3364	#endif /* TIM3 */
AnnaBridge	172:65be27845400	3365
AnnaBridge	172:65be27845400	3366	#if defined(TIM4)
AnnaBridge	172:65be27845400	3367	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
AnnaBridge	172:65be27845400	3368	#endif /* TIM4 */
AnnaBridge	172:65be27845400	3369
AnnaBridge	172:65be27845400	3370	#if defined(TIM5)
AnnaBridge	172:65be27845400	3371	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
AnnaBridge	172:65be27845400	3372	#endif /* TIM5 */
AnnaBridge	172:65be27845400	3373
AnnaBridge	172:65be27845400	3374	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
AnnaBridge	172:65be27845400	3375
AnnaBridge	172:65be27845400	3376	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
AnnaBridge	172:65be27845400	3377
AnnaBridge	172:65be27845400	3378	#if defined(LCD)
AnnaBridge	172:65be27845400	3379	#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
AnnaBridge	172:65be27845400	3380	#endif /* LCD */
AnnaBridge	172:65be27845400	3381
AnnaBridge	172:65be27845400	3382	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	172:65be27845400	3383	#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
AnnaBridge	172:65be27845400	3384	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	172:65be27845400	3385
AnnaBridge	172:65be27845400	3386	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
AnnaBridge	172:65be27845400	3387
AnnaBridge	172:65be27845400	3388	#if defined(SPI2)
AnnaBridge	172:65be27845400	3389	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
AnnaBridge	172:65be27845400	3390	#endif /* SPI2 */
AnnaBridge	172:65be27845400	3391
AnnaBridge	172:65be27845400	3392	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
AnnaBridge	172:65be27845400	3393
AnnaBridge	172:65be27845400	3394	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
AnnaBridge	172:65be27845400	3395
AnnaBridge	172:65be27845400	3396	#if defined(USART3)
AnnaBridge	172:65be27845400	3397	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
AnnaBridge	172:65be27845400	3398	#endif /* USART3 */
AnnaBridge	172:65be27845400	3399
AnnaBridge	172:65be27845400	3400	#if defined(UART4)
AnnaBridge	172:65be27845400	3401	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
AnnaBridge	172:65be27845400	3402	#endif /* UART4 */
AnnaBridge	172:65be27845400	3403
AnnaBridge	172:65be27845400	3404	#if defined(UART5)
AnnaBridge	172:65be27845400	3405	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
AnnaBridge	172:65be27845400	3406	#endif /* UART5 */
AnnaBridge	172:65be27845400	3407
AnnaBridge	172:65be27845400	3408	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
AnnaBridge	172:65be27845400	3409
AnnaBridge	172:65be27845400	3410	#if defined(I2C2)
AnnaBridge	172:65be27845400	3411	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
AnnaBridge	172:65be27845400	3412	#endif /* I2C2 */
AnnaBridge	172:65be27845400	3413
AnnaBridge	172:65be27845400	3414	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
AnnaBridge	172:65be27845400	3415
AnnaBridge	172:65be27845400	3416	#if defined(I2C4)
AnnaBridge	172:65be27845400	3417	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET)
AnnaBridge	172:65be27845400	3418	#endif /* I2C4 */
AnnaBridge	172:65be27845400	3419
AnnaBridge	172:65be27845400	3420	#if defined(CRS)
AnnaBridge	172:65be27845400	3421	#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
AnnaBridge	172:65be27845400	3422	#endif /* CRS */
AnnaBridge	172:65be27845400	3423
AnnaBridge	172:65be27845400	3424	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
AnnaBridge	172:65be27845400	3425
AnnaBridge	172:65be27845400	3426	#if defined(CAN2)
AnnaBridge	172:65be27845400	3427	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET)
AnnaBridge	172:65be27845400	3428	#endif /* CAN2 */
AnnaBridge	172:65be27845400	3429
AnnaBridge	172:65be27845400	3430	#if defined(USB)
AnnaBridge	172:65be27845400	3431	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
AnnaBridge	172:65be27845400	3432	#endif /* USB */
AnnaBridge	172:65be27845400	3433
AnnaBridge	172:65be27845400	3434	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
AnnaBridge	172:65be27845400	3435
AnnaBridge	172:65be27845400	3436	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
AnnaBridge	172:65be27845400	3437
AnnaBridge	172:65be27845400	3438	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
AnnaBridge	172:65be27845400	3439
AnnaBridge	172:65be27845400	3440	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
AnnaBridge	172:65be27845400	3441
AnnaBridge	172:65be27845400	3442	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
AnnaBridge	172:65be27845400	3443
AnnaBridge	172:65be27845400	3444	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	3445	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
AnnaBridge	172:65be27845400	3446	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	3447
AnnaBridge	172:65be27845400	3448	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
AnnaBridge	172:65be27845400	3449
AnnaBridge	172:65be27845400	3450
AnnaBridge	172:65be27845400	3451	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
AnnaBridge	172:65be27845400	3452
AnnaBridge	172:65be27845400	3453	#if defined(TIM3)
AnnaBridge	172:65be27845400	3454	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
AnnaBridge	172:65be27845400	3455	#endif /* TIM3 */
AnnaBridge	172:65be27845400	3456
AnnaBridge	172:65be27845400	3457	#if defined(TIM4)
AnnaBridge	172:65be27845400	3458	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
AnnaBridge	172:65be27845400	3459	#endif /* TIM4 */
AnnaBridge	172:65be27845400	3460
AnnaBridge	172:65be27845400	3461	#if defined(TIM5)
AnnaBridge	172:65be27845400	3462	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
AnnaBridge	172:65be27845400	3463	#endif /* TIM5 */
AnnaBridge	172:65be27845400	3464
AnnaBridge	172:65be27845400	3465	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
AnnaBridge	172:65be27845400	3466
AnnaBridge	172:65be27845400	3467	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
AnnaBridge	172:65be27845400	3468
AnnaBridge	172:65be27845400	3469	#if defined(LCD)
AnnaBridge	172:65be27845400	3470	#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
AnnaBridge	172:65be27845400	3471	#endif /* LCD */
AnnaBridge	172:65be27845400	3472
AnnaBridge	172:65be27845400	3473	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	172:65be27845400	3474	#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
AnnaBridge	172:65be27845400	3475	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	172:65be27845400	3476
AnnaBridge	172:65be27845400	3477	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
AnnaBridge	172:65be27845400	3478
AnnaBridge	172:65be27845400	3479	#if defined(SPI2)
AnnaBridge	172:65be27845400	3480	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
AnnaBridge	172:65be27845400	3481	#endif /* SPI2 */
AnnaBridge	172:65be27845400	3482
AnnaBridge	172:65be27845400	3483	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
AnnaBridge	172:65be27845400	3484
AnnaBridge	172:65be27845400	3485	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
AnnaBridge	172:65be27845400	3486
AnnaBridge	172:65be27845400	3487	#if defined(USART3)
AnnaBridge	172:65be27845400	3488	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
AnnaBridge	172:65be27845400	3489	#endif /* USART3 */
AnnaBridge	172:65be27845400	3490
AnnaBridge	172:65be27845400	3491	#if defined(UART4)
AnnaBridge	172:65be27845400	3492	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
AnnaBridge	172:65be27845400	3493	#endif /* UART4 */
AnnaBridge	172:65be27845400	3494
AnnaBridge	172:65be27845400	3495	#if defined(UART5)
AnnaBridge	172:65be27845400	3496	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
AnnaBridge	172:65be27845400	3497	#endif /* UART5 */
AnnaBridge	172:65be27845400	3498
AnnaBridge	172:65be27845400	3499	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
AnnaBridge	172:65be27845400	3500
AnnaBridge	172:65be27845400	3501	#if defined(I2C2)
AnnaBridge	172:65be27845400	3502	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
AnnaBridge	172:65be27845400	3503	#endif /* I2C2 */
AnnaBridge	172:65be27845400	3504
AnnaBridge	172:65be27845400	3505	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
AnnaBridge	172:65be27845400	3506
AnnaBridge	172:65be27845400	3507	#if defined(I2C4)
AnnaBridge	172:65be27845400	3508	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET)
AnnaBridge	172:65be27845400	3509	#endif /* I2C4 */
AnnaBridge	172:65be27845400	3510
AnnaBridge	172:65be27845400	3511	#if defined(CRS)
AnnaBridge	172:65be27845400	3512	#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
AnnaBridge	172:65be27845400	3513	#endif /* CRS */
AnnaBridge	172:65be27845400	3514
AnnaBridge	172:65be27845400	3515	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
AnnaBridge	172:65be27845400	3516
AnnaBridge	172:65be27845400	3517	#if defined(CAN2)
AnnaBridge	172:65be27845400	3518	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET)
AnnaBridge	172:65be27845400	3519	#endif /* CAN2 */
AnnaBridge	172:65be27845400	3520
AnnaBridge	172:65be27845400	3521	#if defined(USB)
AnnaBridge	172:65be27845400	3522	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
AnnaBridge	172:65be27845400	3523	#endif /* USB */
AnnaBridge	172:65be27845400	3524
AnnaBridge	172:65be27845400	3525	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
AnnaBridge	172:65be27845400	3526
AnnaBridge	172:65be27845400	3527	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
AnnaBridge	172:65be27845400	3528
AnnaBridge	172:65be27845400	3529	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
AnnaBridge	172:65be27845400	3530
AnnaBridge	172:65be27845400	3531	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
AnnaBridge	172:65be27845400	3532
AnnaBridge	172:65be27845400	3533	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
AnnaBridge	172:65be27845400	3534
AnnaBridge	172:65be27845400	3535	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	3536	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
AnnaBridge	172:65be27845400	3537	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	3538
AnnaBridge	172:65be27845400	3539	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
AnnaBridge	172:65be27845400	3540
AnnaBridge	172:65be27845400	3541	/**
AnnaBridge	172:65be27845400	3542	* @}
AnnaBridge	172:65be27845400	3543	*/
AnnaBridge	172:65be27845400	3544
AnnaBridge	172:65be27845400	3545	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	172:65be27845400	3546	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	172:65be27845400	3547	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	172:65be27845400	3548	* power consumption.
AnnaBridge	172:65be27845400	3549	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	172:65be27845400	3550	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	172:65be27845400	3551	* @{
AnnaBridge	172:65be27845400	3552	*/
AnnaBridge	172:65be27845400	3553
AnnaBridge	172:65be27845400	3554	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
AnnaBridge	172:65be27845400	3555
AnnaBridge	172:65be27845400	3556	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3557	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
AnnaBridge	172:65be27845400	3558	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	3559
AnnaBridge	172:65be27845400	3560	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
AnnaBridge	172:65be27845400	3561
AnnaBridge	172:65be27845400	3562	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
AnnaBridge	172:65be27845400	3563
AnnaBridge	172:65be27845400	3564	#if defined(TIM8)
AnnaBridge	172:65be27845400	3565	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
AnnaBridge	172:65be27845400	3566	#endif /* TIM8 */
AnnaBridge	172:65be27845400	3567
AnnaBridge	172:65be27845400	3568	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
AnnaBridge	172:65be27845400	3569
AnnaBridge	172:65be27845400	3570	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
AnnaBridge	172:65be27845400	3571
AnnaBridge	172:65be27845400	3572	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
AnnaBridge	172:65be27845400	3573
AnnaBridge	172:65be27845400	3574	#if defined(TIM17)
AnnaBridge	172:65be27845400	3575	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
AnnaBridge	172:65be27845400	3576	#endif /* TIM17 */
AnnaBridge	172:65be27845400	3577
AnnaBridge	172:65be27845400	3578	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
AnnaBridge	172:65be27845400	3579
AnnaBridge	172:65be27845400	3580	#if defined(SAI2)
AnnaBridge	172:65be27845400	3581	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
AnnaBridge	172:65be27845400	3582	#endif /* SAI2 */
AnnaBridge	172:65be27845400	3583
AnnaBridge	172:65be27845400	3584	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	3585	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
AnnaBridge	172:65be27845400	3586	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	3587
AnnaBridge	172:65be27845400	3588	#if defined(LTDC)
AnnaBridge	172:65be27845400	3589	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET)
AnnaBridge	172:65be27845400	3590	#endif /* LTDC */
AnnaBridge	172:65be27845400	3591
AnnaBridge	172:65be27845400	3592	#if defined(DSI)
AnnaBridge	172:65be27845400	3593	#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET)
AnnaBridge	172:65be27845400	3594	#endif /* DSI */
AnnaBridge	172:65be27845400	3595
AnnaBridge	172:65be27845400	3596
AnnaBridge	172:65be27845400	3597	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
AnnaBridge	172:65be27845400	3598
AnnaBridge	172:65be27845400	3599	#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	172:65be27845400	3600	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
AnnaBridge	172:65be27845400	3601	#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
AnnaBridge	172:65be27845400	3602
AnnaBridge	172:65be27845400	3603	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
AnnaBridge	172:65be27845400	3604
AnnaBridge	172:65be27845400	3605	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
AnnaBridge	172:65be27845400	3606
AnnaBridge	172:65be27845400	3607	#if defined(TIM8)
AnnaBridge	172:65be27845400	3608	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
AnnaBridge	172:65be27845400	3609	#endif /* TIM8 */
AnnaBridge	172:65be27845400	3610
AnnaBridge	172:65be27845400	3611	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
AnnaBridge	172:65be27845400	3612
AnnaBridge	172:65be27845400	3613	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
AnnaBridge	172:65be27845400	3614
AnnaBridge	172:65be27845400	3615	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
AnnaBridge	172:65be27845400	3616
AnnaBridge	172:65be27845400	3617	#if defined(TIM17)
AnnaBridge	172:65be27845400	3618	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
AnnaBridge	172:65be27845400	3619	#endif /* TIM17 */
AnnaBridge	172:65be27845400	3620
AnnaBridge	172:65be27845400	3621	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
AnnaBridge	172:65be27845400	3622
AnnaBridge	172:65be27845400	3623	#if defined(SAI2)
AnnaBridge	172:65be27845400	3624	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
AnnaBridge	172:65be27845400	3625	#endif /* SAI2 */
AnnaBridge	172:65be27845400	3626
AnnaBridge	172:65be27845400	3627	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	3628	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
AnnaBridge	172:65be27845400	3629	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	3630
AnnaBridge	172:65be27845400	3631	#if defined(LTDC)
AnnaBridge	172:65be27845400	3632	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET)
AnnaBridge	172:65be27845400	3633	#endif /* LTDC */
AnnaBridge	172:65be27845400	3634
AnnaBridge	172:65be27845400	3635	#if defined(DSI)
AnnaBridge	172:65be27845400	3636	#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET)
AnnaBridge	172:65be27845400	3637	#endif /* DSI */
AnnaBridge	172:65be27845400	3638
AnnaBridge	172:65be27845400	3639	/**
AnnaBridge	172:65be27845400	3640	* @}
AnnaBridge	172:65be27845400	3641	*/
AnnaBridge	172:65be27845400	3642
AnnaBridge	172:65be27845400	3643	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
AnnaBridge	172:65be27845400	3644	* @{
AnnaBridge	172:65be27845400	3645	*/
AnnaBridge	172:65be27845400	3646
AnnaBridge	172:65be27845400	3647	/** @brief Macros to force or release the Backup domain reset.
AnnaBridge	172:65be27845400	3648	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	172:65be27845400	3649	* and the RTC clock source selection in RCC_CSR register.
AnnaBridge	172:65be27845400	3650	* @note The BKPSRAM is not affected by this reset.
AnnaBridge	172:65be27845400	3651	* @retval None
AnnaBridge	172:65be27845400	3652	*/
AnnaBridge	172:65be27845400	3653	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge	172:65be27845400	3654
AnnaBridge	172:65be27845400	3655	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge	172:65be27845400	3656
AnnaBridge	172:65be27845400	3657	/**
AnnaBridge	172:65be27845400	3658	* @}
AnnaBridge	172:65be27845400	3659	*/
AnnaBridge	172:65be27845400	3660
AnnaBridge	172:65be27845400	3661	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	172:65be27845400	3662	* @{
AnnaBridge	172:65be27845400	3663	*/
AnnaBridge	172:65be27845400	3664
AnnaBridge	172:65be27845400	3665	/** @brief Macros to enable or disable the RTC clock.
AnnaBridge	172:65be27845400	3666	* @note As the RTC is in the Backup domain and write access is denied to
AnnaBridge	172:65be27845400	3667	* this domain after reset, you have to enable write access using
AnnaBridge	172:65be27845400	3668	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
AnnaBridge	172:65be27845400	3669	* (to be done once after reset).
AnnaBridge	172:65be27845400	3670	* @note These macros must be used after the RTC clock source was selected.
AnnaBridge	172:65be27845400	3671	* @retval None
AnnaBridge	172:65be27845400	3672	*/
AnnaBridge	172:65be27845400	3673	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge	172:65be27845400	3674
AnnaBridge	172:65be27845400	3675	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge	172:65be27845400	3676
AnnaBridge	172:65be27845400	3677	/**
AnnaBridge	172:65be27845400	3678	* @}
AnnaBridge	172:65be27845400	3679	*/
AnnaBridge	172:65be27845400	3680
AnnaBridge	172:65be27845400	3681	/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
AnnaBridge	172:65be27845400	3682	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	3683	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	172:65be27845400	3684	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	172:65be27845400	3685	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	172:65be27845400	3686	* Security System CSS is enabled).
AnnaBridge	172:65be27845400	3687	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	172:65be27845400	3688	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	172:65be27845400	3689	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	172:65be27845400	3690	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	172:65be27845400	3691	* system clock source.
AnnaBridge	172:65be27845400	3692	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	172:65be27845400	3693	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	172:65be27845400	3694	* clock cycles.
AnnaBridge	172:65be27845400	3695	* @retval None
AnnaBridge	172:65be27845400	3696	*/
AnnaBridge	172:65be27845400	3697	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	172:65be27845400	3698
AnnaBridge	172:65be27845400	3699	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	172:65be27845400	3700
AnnaBridge	172:65be27845400	3701	/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
AnnaBridge	172:65be27845400	3702	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	172:65be27845400	3703	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	172:65be27845400	3704	* @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
AnnaBridge	172:65be27845400	3705	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	172:65be27845400	3706	* This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
AnnaBridge	172:65be27845400	3707	* @retval None
AnnaBridge	172:65be27845400	3708	*/
AnnaBridge	172:65be27845400	3709	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
AnnaBridge	172:65be27845400	3710	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
AnnaBridge	172:65be27845400	3711
AnnaBridge	172:65be27845400	3712	/**
AnnaBridge	172:65be27845400	3713	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
AnnaBridge	172:65be27845400	3714	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
AnnaBridge	172:65be27845400	3715	* @note The enable of this function has not effect on the HSION bit.
AnnaBridge	172:65be27845400	3716	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	172:65be27845400	3717	* @retval None
AnnaBridge	172:65be27845400	3718	*/
AnnaBridge	172:65be27845400	3719	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
AnnaBridge	172:65be27845400	3720
AnnaBridge	172:65be27845400	3721	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
AnnaBridge	172:65be27845400	3722
AnnaBridge	172:65be27845400	3723	/**
AnnaBridge	172:65be27845400	3724	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
AnnaBridge	172:65be27845400	3725	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
AnnaBridge	172:65be27845400	3726	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
AnnaBridge	172:65be27845400	3727	* speed because of the HSI startup time.
AnnaBridge	172:65be27845400	3728	* @note The enable of this function has not effect on the HSION bit.
AnnaBridge	172:65be27845400	3729	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	172:65be27845400	3730	* @retval None
AnnaBridge	172:65be27845400	3731	*/
AnnaBridge	172:65be27845400	3732	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge	172:65be27845400	3733
AnnaBridge	172:65be27845400	3734	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge	172:65be27845400	3735
AnnaBridge	172:65be27845400	3736	/**
AnnaBridge	172:65be27845400	3737	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
AnnaBridge	172:65be27845400	3738	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	3739	* It is used (enabled by hardware) as system clock source after
AnnaBridge	172:65be27845400	3740	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
AnnaBridge	172:65be27845400	3741	* of failure of the HSE used directly or indirectly as system clock
AnnaBridge	172:65be27845400	3742	* (if the Clock Security System CSS is enabled).
AnnaBridge	172:65be27845400	3743	* @note MSI can not be stopped if it is used as system clock source.
AnnaBridge	172:65be27845400	3744	* In this case, you have to select another source of the system
AnnaBridge	172:65be27845400	3745	* clock then stop the MSI.
AnnaBridge	172:65be27845400	3746	* @note After enabling the MSI, the application software should wait on
AnnaBridge	172:65be27845400	3747	* MSIRDY flag to be set indicating that MSI clock is stable and can
AnnaBridge	172:65be27845400	3748	* be used as system clock source.
AnnaBridge	172:65be27845400	3749	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
AnnaBridge	172:65be27845400	3750	* clock cycles.
AnnaBridge	172:65be27845400	3751	* @retval None
AnnaBridge	172:65be27845400	3752	*/
AnnaBridge	172:65be27845400	3753	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	172:65be27845400	3754
AnnaBridge	172:65be27845400	3755	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	172:65be27845400	3756
AnnaBridge	172:65be27845400	3757	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
AnnaBridge	172:65be27845400	3758	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	172:65be27845400	3759	* and temperature that influence the frequency of the internal MSI RC.
AnnaBridge	172:65be27845400	3760	* Refer to the Application Note AN3300 for more details on how to
AnnaBridge	172:65be27845400	3761	* calibrate the MSI.
AnnaBridge	172:65be27845400	3762	* @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value
AnnaBridge	172:65be27845400	3763	* (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	172:65be27845400	3764	* This parameter must be a number between 0 and 255.
AnnaBridge	172:65be27845400	3765	* @retval None
AnnaBridge	172:65be27845400	3766	*/
AnnaBridge	172:65be27845400	3767	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
AnnaBridge	172:65be27845400	3768	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
AnnaBridge	172:65be27845400	3769
AnnaBridge	172:65be27845400	3770	/**
AnnaBridge	172:65be27845400	3771	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge	172:65be27845400	3772	* @note After restart from Reset , the MSI clock is around 4 MHz.
AnnaBridge	172:65be27845400	3773	* After stop the startup clock can be MSI (at any of its possible
AnnaBridge	172:65be27845400	3774	* frequencies, the one that was used before entering stop mode) or HSI.
AnnaBridge	172:65be27845400	3775	* After Standby its frequency can be selected between 4 possible values
AnnaBridge	172:65be27845400	3776	* (1, 2, 4 or 8 MHz).
AnnaBridge	172:65be27845400	3777	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
AnnaBridge	172:65be27845400	3778	* (MSIRDY=1).
AnnaBridge	172:65be27845400	3779	* @note The MSI clock range after reset can be modified on the fly.
AnnaBridge	172:65be27845400	3780	* @param __MSIRANGEVALUE__ specifies the MSI clock range.
AnnaBridge	172:65be27845400	3781	* This parameter must be one of the following values:
AnnaBridge	172:65be27845400	3782	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
AnnaBridge	172:65be27845400	3783	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
AnnaBridge	172:65be27845400	3784	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
AnnaBridge	172:65be27845400	3785	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
AnnaBridge	172:65be27845400	3786	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge	172:65be27845400	3787	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge	172:65be27845400	3788	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge	172:65be27845400	3789	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge	172:65be27845400	3790	* @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
AnnaBridge	172:65be27845400	3791	* @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
AnnaBridge	172:65be27845400	3792	* @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
AnnaBridge	172:65be27845400	3793	* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
AnnaBridge	172:65be27845400	3794	* @retval None
AnnaBridge	172:65be27845400	3795	*/
AnnaBridge	172:65be27845400	3796	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
AnnaBridge	172:65be27845400	3797	do { \
AnnaBridge	172:65be27845400	3798	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
AnnaBridge	172:65be27845400	3799	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
AnnaBridge	172:65be27845400	3800	} while(0)
AnnaBridge	172:65be27845400	3801
AnnaBridge	172:65be27845400	3802	/**
AnnaBridge	172:65be27845400	3803	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
AnnaBridge	172:65be27845400	3804	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
AnnaBridge	172:65be27845400	3805	* @param __MSIRANGEVALUE__ specifies the MSI clock range.
AnnaBridge	172:65be27845400	3806	* This parameter must be one of the following values:
AnnaBridge	172:65be27845400	3807	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge	172:65be27845400	3808	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge	172:65be27845400	3809	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge	172:65be27845400	3810	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge	172:65be27845400	3811	* @retval None
AnnaBridge	172:65be27845400	3812	*/
AnnaBridge	172:65be27845400	3813	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
AnnaBridge	172:65be27845400	3814	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
AnnaBridge	172:65be27845400	3815
AnnaBridge	172:65be27845400	3816	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge	172:65be27845400	3817	* @retval MSI clock range.
AnnaBridge	172:65be27845400	3818	* This parameter must be one of the following values:
AnnaBridge	172:65be27845400	3819	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
AnnaBridge	172:65be27845400	3820	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
AnnaBridge	172:65be27845400	3821	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
AnnaBridge	172:65be27845400	3822	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
AnnaBridge	172:65be27845400	3823	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge	172:65be27845400	3824	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge	172:65be27845400	3825	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge	172:65be27845400	3826	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge	172:65be27845400	3827	* @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
AnnaBridge	172:65be27845400	3828	* @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
AnnaBridge	172:65be27845400	3829	* @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
AnnaBridge	172:65be27845400	3830	* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
AnnaBridge	172:65be27845400	3831	*/
AnnaBridge	172:65be27845400	3832	#define __HAL_RCC_GET_MSI_RANGE() \
AnnaBridge	172:65be27845400	3833	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
AnnaBridge	172:65be27845400	3834	READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \
AnnaBridge	172:65be27845400	3835	READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)
AnnaBridge	172:65be27845400	3836
AnnaBridge	172:65be27845400	3837	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge	172:65be27845400	3838	* @note After enabling the LSI, the application software should wait on
AnnaBridge	172:65be27845400	3839	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	172:65be27845400	3840	* be used to clock the IWDG and/or the RTC.
AnnaBridge	172:65be27845400	3841	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	172:65be27845400	3842	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	172:65be27845400	3843	* clock cycles.
AnnaBridge	172:65be27845400	3844	* @retval None
AnnaBridge	172:65be27845400	3845	*/
AnnaBridge	172:65be27845400	3846	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	172:65be27845400	3847
AnnaBridge	172:65be27845400	3848	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	172:65be27845400	3849
AnnaBridge	172:65be27845400	3850	/**
AnnaBridge	172:65be27845400	3851	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	172:65be27845400	3852	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	172:65be27845400	3853	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	172:65be27845400	3854	* first and then HSE On or HSE Bypass.
AnnaBridge	172:65be27845400	3855	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	172:65be27845400	3856	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	172:65be27845400	3857	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	172:65be27845400	3858	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	172:65be27845400	3859	* PLL as system clock. In this case, you have to select another source
AnnaBridge	172:65be27845400	3860	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	172:65be27845400	3861	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	3862	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	172:65be27845400	3863	* was previously enabled you have to enable it again after calling this
AnnaBridge	172:65be27845400	3864	* function.
AnnaBridge	172:65be27845400	3865	* @param __STATE__ specifies the new state of the HSE.
AnnaBridge	172:65be27845400	3866	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3867	* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	172:65be27845400	3868	* 6 HSE oscillator clock cycles.
AnnaBridge	172:65be27845400	3869	* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
AnnaBridge	172:65be27845400	3870	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
AnnaBridge	172:65be27845400	3871	* @retval None
AnnaBridge	172:65be27845400	3872	*/
AnnaBridge	172:65be27845400	3873	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	172:65be27845400	3874	do { \
AnnaBridge	172:65be27845400	3875	if((__STATE__) == RCC_HSE_ON) \
AnnaBridge	172:65be27845400	3876	{ \
AnnaBridge	172:65be27845400	3877	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	172:65be27845400	3878	} \
AnnaBridge	172:65be27845400	3879	else if((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	172:65be27845400	3880	{ \
AnnaBridge	172:65be27845400	3881	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	172:65be27845400	3882	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	172:65be27845400	3883	} \
AnnaBridge	172:65be27845400	3884	else \
AnnaBridge	172:65be27845400	3885	{ \
AnnaBridge	172:65be27845400	3886	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	172:65be27845400	3887	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	172:65be27845400	3888	} \
AnnaBridge	172:65be27845400	3889	} while(0)
AnnaBridge	172:65be27845400	3890
AnnaBridge	172:65be27845400	3891	/**
AnnaBridge	172:65be27845400	3892	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	172:65be27845400	3893	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
AnnaBridge	172:65be27845400	3894	* supported by this macro. User should request a transition to LSE Off
AnnaBridge	172:65be27845400	3895	* first and then LSE On or LSE Bypass.
AnnaBridge	172:65be27845400	3896	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	172:65be27845400	3897	* this domain after reset, you have to enable write access using
AnnaBridge	172:65be27845400	3898	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	172:65be27845400	3899	* (to be done once after reset).
AnnaBridge	172:65be27845400	3900	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	172:65be27845400	3901	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	172:65be27845400	3902	* is stable and can be used to clock the RTC.
AnnaBridge	172:65be27845400	3903	* @param __STATE__ specifies the new state of the LSE.
AnnaBridge	172:65be27845400	3904	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3905	* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	172:65be27845400	3906	* 6 LSE oscillator clock cycles.
AnnaBridge	172:65be27845400	3907	* @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
AnnaBridge	172:65be27845400	3908	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge	172:65be27845400	3909	* @retval None
AnnaBridge	172:65be27845400	3910	*/
AnnaBridge	172:65be27845400	3911	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	172:65be27845400	3912	do { \
AnnaBridge	172:65be27845400	3913	if((__STATE__) == RCC_LSE_ON) \
AnnaBridge	172:65be27845400	3914	{ \
AnnaBridge	172:65be27845400	3915	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	172:65be27845400	3916	} \
AnnaBridge	172:65be27845400	3917	else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	172:65be27845400	3918	{ \
AnnaBridge	172:65be27845400	3919	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	172:65be27845400	3920	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	172:65be27845400	3921	} \
AnnaBridge	172:65be27845400	3922	else \
AnnaBridge	172:65be27845400	3923	{ \
AnnaBridge	172:65be27845400	3924	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	172:65be27845400	3925	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	172:65be27845400	3926	} \
AnnaBridge	172:65be27845400	3927	} while(0)
AnnaBridge	172:65be27845400	3928
AnnaBridge	172:65be27845400	3929	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	3930
AnnaBridge	172:65be27845400	3931	/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
AnnaBridge	172:65be27845400	3932	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	3933	* @note After enabling the HSI48, the application software should wait on HSI48RDY
AnnaBridge	172:65be27845400	3934	* flag to be set indicating that HSI48 clock is stable.
AnnaBridge	172:65be27845400	3935	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	172:65be27845400	3936	* @retval None
AnnaBridge	172:65be27845400	3937	*/
AnnaBridge	172:65be27845400	3938	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
AnnaBridge	172:65be27845400	3939
AnnaBridge	172:65be27845400	3940	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
AnnaBridge	172:65be27845400	3941
AnnaBridge	172:65be27845400	3942	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	3943
AnnaBridge	172:65be27845400	3944	/** @brief Macros to configure the RTC clock (RTCCLK).
AnnaBridge	172:65be27845400	3945	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	172:65be27845400	3946	* access is denied to this domain after reset, you have to enable write
AnnaBridge	172:65be27845400	3947	* access using the Power Backup Access macro before to configure
AnnaBridge	172:65be27845400	3948	* the RTC clock source (to be done once after reset).
AnnaBridge	172:65be27845400	3949	* @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge	172:65be27845400	3950	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge	172:65be27845400	3951	* a Power On Reset (POR).
AnnaBridge	172:65be27845400	3952	*
AnnaBridge	172:65be27845400	3953	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge	172:65be27845400	3954	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3955	* @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
AnnaBridge	172:65be27845400	3956	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
AnnaBridge	172:65be27845400	3957	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
AnnaBridge	172:65be27845400	3958	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
AnnaBridge	172:65be27845400	3959	*
AnnaBridge	172:65be27845400	3960	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	172:65be27845400	3961	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	172:65be27845400	3962	* However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge	172:65be27845400	3963	* cannot be used in STOP and STANDBY modes.
AnnaBridge	172:65be27845400	3964	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge	172:65be27845400	3965	* RTC clock source).
AnnaBridge	172:65be27845400	3966	* @retval None
AnnaBridge	172:65be27845400	3967	*/
AnnaBridge	172:65be27845400	3968	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
AnnaBridge	172:65be27845400	3969	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge	172:65be27845400	3970
AnnaBridge	172:65be27845400	3971
AnnaBridge	172:65be27845400	3972	/** @brief Macro to get the RTC clock source.
AnnaBridge	172:65be27845400	3973	* @retval The returned value can be one of the following:
AnnaBridge	172:65be27845400	3974	* @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
AnnaBridge	172:65be27845400	3975	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
AnnaBridge	172:65be27845400	3976	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
AnnaBridge	172:65be27845400	3977	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
AnnaBridge	172:65be27845400	3978	*/
AnnaBridge	172:65be27845400	3979	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge	172:65be27845400	3980
AnnaBridge	172:65be27845400	3981	/** @brief Macros to enable or disable the main PLL.
AnnaBridge	172:65be27845400	3982	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	172:65be27845400	3983	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	172:65be27845400	3984	* be used as system clock source.
AnnaBridge	172:65be27845400	3985	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	172:65be27845400	3986	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	3987	* @retval None
AnnaBridge	172:65be27845400	3988	*/
AnnaBridge	172:65be27845400	3989	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	172:65be27845400	3990
AnnaBridge	172:65be27845400	3991	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	172:65be27845400	3992
AnnaBridge	172:65be27845400	3993	/** @brief Macro to configure the PLL clock source.
AnnaBridge	172:65be27845400	3994	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	172:65be27845400	3995	* @param __PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge	172:65be27845400	3996	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3997	* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
AnnaBridge	172:65be27845400	3998	* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
AnnaBridge	172:65be27845400	3999	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	172:65be27845400	4000	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	172:65be27845400	4001	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
AnnaBridge	172:65be27845400	4002	* @retval None
AnnaBridge	172:65be27845400	4003	*
AnnaBridge	172:65be27845400	4004	*/
AnnaBridge	172:65be27845400	4005	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
AnnaBridge	172:65be27845400	4006	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
AnnaBridge	172:65be27845400	4007
AnnaBridge	172:65be27845400	4008	/** @brief Macro to configure the PLL source division factor M.
AnnaBridge	172:65be27845400	4009	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	172:65be27845400	4010	* @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge	172:65be27845400	4011	* This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
AnnaBridge	172:65be27845400	4012	* This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
AnnaBridge	172:65be27845400	4013	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	172:65be27845400	4014	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
AnnaBridge	172:65be27845400	4015	* of 16 MHz to limit PLL jitter.
AnnaBridge	172:65be27845400	4016	* @retval None
AnnaBridge	172:65be27845400	4017	*
AnnaBridge	172:65be27845400	4018	*/
AnnaBridge	172:65be27845400	4019	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
AnnaBridge	172:65be27845400	4020	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
AnnaBridge	172:65be27845400	4021
AnnaBridge	172:65be27845400	4022	/**
AnnaBridge	172:65be27845400	4023	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	172:65be27845400	4024	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	172:65be27845400	4025	*
AnnaBridge	172:65be27845400	4026	* @param __PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge	172:65be27845400	4027	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4028	* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
AnnaBridge	172:65be27845400	4029	* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
AnnaBridge	172:65be27845400	4030	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	172:65be27845400	4031	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	172:65be27845400	4032	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
AnnaBridge	172:65be27845400	4033	*
AnnaBridge	172:65be27845400	4034	* @param __PLLM__ specifies the division factor for PLL VCO input clock.
AnnaBridge	172:65be27845400	4035	* This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
AnnaBridge	172:65be27845400	4036	* This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
AnnaBridge	172:65be27845400	4037	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	172:65be27845400	4038	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
AnnaBridge	172:65be27845400	4039	* of 16 MHz to limit PLL jitter.
AnnaBridge	172:65be27845400	4040	*
AnnaBridge	172:65be27845400	4041	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
AnnaBridge	172:65be27845400	4042	* This parameter must be a number between 8 and 86.
AnnaBridge	172:65be27845400	4043	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	4044	* output frequency is between 64 and 344 MHz.
AnnaBridge	172:65be27845400	4045	*
AnnaBridge	172:65be27845400	4046	* @param __PLLP__ specifies the division factor for SAI clock.
AnnaBridge	172:65be27845400	4047	* This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
AnnaBridge	172:65be27845400	4048	* else (2 to 31).
AnnaBridge	172:65be27845400	4049	*
AnnaBridge	172:65be27845400	4050	* @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
AnnaBridge	172:65be27845400	4051	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	4052	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	172:65be27845400	4053	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	172:65be27845400	4054	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	172:65be27845400	4055	* correctly.
AnnaBridge	172:65be27845400	4056	* @param __PLLR__ specifies the division factor for the main system clock.
AnnaBridge	172:65be27845400	4057	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
AnnaBridge	172:65be27845400	4058	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	4059	* @retval None
AnnaBridge	172:65be27845400	4060	*/
AnnaBridge	172:65be27845400	4061	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	4062
AnnaBridge	172:65be27845400	4063	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
AnnaBridge	172:65be27845400	4064	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| \
AnnaBridge	172:65be27845400	4065	(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) \| \
AnnaBridge	172:65be27845400	4066	((uint32_t)(__PLLP__) << 27U))
AnnaBridge	172:65be27845400	4067	#else
AnnaBridge	172:65be27845400	4068
AnnaBridge	172:65be27845400	4069	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
AnnaBridge	172:65be27845400	4070	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| \
AnnaBridge	172:65be27845400	4071	(uint32_t)(((__PLLP__) >> 4U ) << 17U) \| \
AnnaBridge	172:65be27845400	4072	(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
AnnaBridge	172:65be27845400	4073
AnnaBridge	172:65be27845400	4074	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	4075
AnnaBridge	172:65be27845400	4076	/** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge	172:65be27845400	4077	* @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge	172:65be27845400	4078	* of the following:
AnnaBridge	172:65be27845400	4079	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
AnnaBridge	172:65be27845400	4080	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
AnnaBridge	172:65be27845400	4081	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge	172:65be27845400	4082	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge	172:65be27845400	4083	*/
AnnaBridge	172:65be27845400	4084	#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
AnnaBridge	172:65be27845400	4085
AnnaBridge	172:65be27845400	4086	/**
AnnaBridge	172:65be27845400	4087	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
AnnaBridge	172:65be27845400	4088	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
AnnaBridge	172:65be27845400	4089	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
AnnaBridge	172:65be27845400	4090	* be stopped if used as System Clock.
AnnaBridge	172:65be27845400	4091	* @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
AnnaBridge	172:65be27845400	4092	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	4093	* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	4094	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	4095	* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge	172:65be27845400	4096	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
AnnaBridge	172:65be27845400	4097	* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
AnnaBridge	172:65be27845400	4098	* @retval None
AnnaBridge	172:65be27845400	4099	*/
AnnaBridge	172:65be27845400	4100	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge	172:65be27845400	4101
AnnaBridge	172:65be27845400	4102	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge	172:65be27845400	4103
AnnaBridge	172:65be27845400	4104	/**
AnnaBridge	172:65be27845400	4105	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
AnnaBridge	172:65be27845400	4106	* @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
AnnaBridge	172:65be27845400	4107	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4108	* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	4109	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	4110	* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge	172:65be27845400	4111	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
AnnaBridge	172:65be27845400	4112	* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
AnnaBridge	172:65be27845400	4113	* @retval SET / RESET
AnnaBridge	172:65be27845400	4114	*/
AnnaBridge	172:65be27845400	4115	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge	172:65be27845400	4116
AnnaBridge	172:65be27845400	4117	/**
AnnaBridge	172:65be27845400	4118	* @brief Macro to configure the system clock source.
AnnaBridge	172:65be27845400	4119	* @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge	172:65be27845400	4120	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4121	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
AnnaBridge	172:65be27845400	4122	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge	172:65be27845400	4123	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge	172:65be27845400	4124	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge	172:65be27845400	4125	* @retval None
AnnaBridge	172:65be27845400	4126	*/
AnnaBridge	172:65be27845400	4127	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	172:65be27845400	4128	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	172:65be27845400	4129
AnnaBridge	172:65be27845400	4130	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	172:65be27845400	4131	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	172:65be27845400	4132	* of the following:
AnnaBridge	172:65be27845400	4133	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
AnnaBridge	172:65be27845400	4134	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge	172:65be27845400	4135	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge	172:65be27845400	4136	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge	172:65be27845400	4137	*/
AnnaBridge	172:65be27845400	4138	#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
AnnaBridge	172:65be27845400	4139
AnnaBridge	172:65be27845400	4140	/**
AnnaBridge	172:65be27845400	4141	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
AnnaBridge	172:65be27845400	4142	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	172:65be27845400	4143	* this domain after reset, you have to enable write access using
AnnaBridge	172:65be27845400	4144	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	172:65be27845400	4145	* (to be done once after reset).
AnnaBridge	172:65be27845400	4146	* @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
AnnaBridge	172:65be27845400	4147	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4148	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge	172:65be27845400	4149	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge	172:65be27845400	4150	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge	172:65be27845400	4151	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge	172:65be27845400	4152	* @retval None
AnnaBridge	172:65be27845400	4153	*/
AnnaBridge	172:65be27845400	4154	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
AnnaBridge	172:65be27845400	4155	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
AnnaBridge	172:65be27845400	4156
AnnaBridge	172:65be27845400	4157	/**
AnnaBridge	172:65be27845400	4158	* @brief Macro to configure the wake up from stop clock.
AnnaBridge	172:65be27845400	4159	* @param __STOPWUCLK__ specifies the clock source used after wake up from stop.
AnnaBridge	172:65be27845400	4160	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4161	* @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
AnnaBridge	172:65be27845400	4162	* @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
AnnaBridge	172:65be27845400	4163	* @retval None
AnnaBridge	172:65be27845400	4164	*/
AnnaBridge	172:65be27845400	4165	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
AnnaBridge	172:65be27845400	4166	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
AnnaBridge	172:65be27845400	4167
AnnaBridge	172:65be27845400	4168
AnnaBridge	172:65be27845400	4169	/** @brief Macro to configure the MCO clock.
AnnaBridge	172:65be27845400	4170	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	172:65be27845400	4171	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4172	* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
AnnaBridge	172:65be27845400	4173	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
AnnaBridge	172:65be27845400	4174	* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
AnnaBridge	172:65be27845400	4175	* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
AnnaBridge	172:65be27845400	4176	* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
AnnaBridge	172:65be27845400	4177	* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
AnnaBridge	172:65be27845400	4178	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
AnnaBridge	172:65be27845400	4179	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
AnnaBridge	172:65be27845400	4180	@if STM32L443xx
AnnaBridge	172:65be27845400	4181	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge	172:65be27845400	4182	@endif
AnnaBridge	172:65be27845400	4183	@if STM32L4A6xx
AnnaBridge	172:65be27845400	4184	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge	172:65be27845400	4185	@endif
AnnaBridge	172:65be27845400	4186	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	172:65be27845400	4187	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4188	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge	172:65be27845400	4189	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge	172:65be27845400	4190	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge	172:65be27845400	4191	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge	172:65be27845400	4192	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge	172:65be27845400	4193	*/
AnnaBridge	172:65be27845400	4194	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	172:65be27845400	4195	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	172:65be27845400	4196
AnnaBridge	172:65be27845400	4197	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	172:65be27845400	4198	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	172:65be27845400	4199	* @{
AnnaBridge	172:65be27845400	4200	*/
AnnaBridge	172:65be27845400	4201
AnnaBridge	172:65be27845400	4202	/** @brief Enable RCC interrupt(s).
AnnaBridge	172:65be27845400	4203	* @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.
AnnaBridge	172:65be27845400	4204	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	4205	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	172:65be27845400	4206	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	172:65be27845400	4207	* @arg @ref RCC_IT_MSIRDY HSI ready interrupt
AnnaBridge	172:65be27845400	4208	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	172:65be27845400	4209	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	172:65be27845400	4210	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	172:65be27845400	4211	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	172:65be27845400	4212	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	172:65be27845400	4213	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	172:65be27845400	4214	@if STM32L443xx
AnnaBridge	172:65be27845400	4215	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4216	@endif
AnnaBridge	172:65be27845400	4217	@if STM32L4A6xx
AnnaBridge	172:65be27845400	4218	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4219	@endif
AnnaBridge	172:65be27845400	4220	* @retval None
AnnaBridge	172:65be27845400	4221	*/
AnnaBridge	172:65be27845400	4222	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	172:65be27845400	4223
AnnaBridge	172:65be27845400	4224	/** @brief Disable RCC interrupt(s).
AnnaBridge	172:65be27845400	4225	* @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.
AnnaBridge	172:65be27845400	4226	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	4227	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	172:65be27845400	4228	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	172:65be27845400	4229	* @arg @ref RCC_IT_MSIRDY HSI ready interrupt
AnnaBridge	172:65be27845400	4230	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	172:65be27845400	4231	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	172:65be27845400	4232	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	172:65be27845400	4233	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	172:65be27845400	4234	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	172:65be27845400	4235	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	172:65be27845400	4236	@if STM32L443xx
AnnaBridge	172:65be27845400	4237	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4238	@endif
AnnaBridge	172:65be27845400	4239	@if STM32L4A6xx
AnnaBridge	172:65be27845400	4240	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4241	@endif
AnnaBridge	172:65be27845400	4242	* @retval None
AnnaBridge	172:65be27845400	4243	*/
AnnaBridge	172:65be27845400	4244	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	172:65be27845400	4245
AnnaBridge	172:65be27845400	4246	/** @brief Clear the RCC's interrupt pending bits.
AnnaBridge	172:65be27845400	4247	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	4248	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	4249	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	172:65be27845400	4250	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	172:65be27845400	4251	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	172:65be27845400	4252	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	172:65be27845400	4253	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	172:65be27845400	4254	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	172:65be27845400	4255	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	172:65be27845400	4256	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	172:65be27845400	4257	* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
AnnaBridge	172:65be27845400	4258	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	172:65be27845400	4259	@if STM32L443xx
AnnaBridge	172:65be27845400	4260	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4261	@endif
AnnaBridge	172:65be27845400	4262	@if STM32L4A6xx
AnnaBridge	172:65be27845400	4263	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4264	@endif
AnnaBridge	172:65be27845400	4265	* @retval None
AnnaBridge	172:65be27845400	4266	*/
AnnaBridge	172:65be27845400	4267	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
AnnaBridge	172:65be27845400	4268
AnnaBridge	172:65be27845400	4269	/** @brief Check whether the RCC interrupt has occurred or not.
AnnaBridge	172:65be27845400	4270	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge	172:65be27845400	4271	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4272	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	172:65be27845400	4273	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	172:65be27845400	4274	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	172:65be27845400	4275	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	172:65be27845400	4276	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	172:65be27845400	4277	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	172:65be27845400	4278	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	172:65be27845400	4279	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	172:65be27845400	4280	* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
AnnaBridge	172:65be27845400	4281	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	172:65be27845400	4282	@if STM32L443xx
AnnaBridge	172:65be27845400	4283	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4284	@endif
AnnaBridge	172:65be27845400	4285	@if STM32L4A6xx
AnnaBridge	172:65be27845400	4286	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	172:65be27845400	4287	@endif
AnnaBridge	172:65be27845400	4288	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	4289	*/
AnnaBridge	172:65be27845400	4290	#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	172:65be27845400	4291
AnnaBridge	172:65be27845400	4292	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	172:65be27845400	4293	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
AnnaBridge	172:65be27845400	4294	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
AnnaBridge	172:65be27845400	4295	* @retval None
AnnaBridge	172:65be27845400	4296	*/
AnnaBridge	172:65be27845400	4297	#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
AnnaBridge	172:65be27845400	4298
AnnaBridge	172:65be27845400	4299	/** @brief Check whether the selected RCC flag is set or not.
AnnaBridge	172:65be27845400	4300	* @param __FLAG__ specifies the flag to check.
AnnaBridge	172:65be27845400	4301	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4302	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
AnnaBridge	172:65be27845400	4303	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
AnnaBridge	172:65be27845400	4304	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
AnnaBridge	172:65be27845400	4305	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
AnnaBridge	172:65be27845400	4306	* @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
AnnaBridge	172:65be27845400	4307	* @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
AnnaBridge	172:65be27845400	4308	@if STM32L443xx
AnnaBridge	172:65be27845400	4309	* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge	172:65be27845400	4310	@endif
AnnaBridge	172:65be27845400	4311	@if STM32L4A6xx
AnnaBridge	172:65be27845400	4312	* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge	172:65be27845400	4313	@endif
AnnaBridge	172:65be27845400	4314	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
AnnaBridge	172:65be27845400	4315	* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
AnnaBridge	172:65be27845400	4316	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
AnnaBridge	172:65be27845400	4317	* @arg @ref RCC_FLAG_BORRST BOR reset
AnnaBridge	172:65be27845400	4318	* @arg @ref RCC_FLAG_OBLRST OBLRST reset
AnnaBridge	172:65be27845400	4319	* @arg @ref RCC_FLAG_PINRST Pin reset
AnnaBridge	172:65be27845400	4320	* @arg @ref RCC_FLAG_FWRST FIREWALL reset
AnnaBridge	172:65be27845400	4321	* @arg @ref RCC_FLAG_RMVF Remove reset Flag
AnnaBridge	172:65be27845400	4322	* @arg @ref RCC_FLAG_SFTRST Software reset
AnnaBridge	172:65be27845400	4323	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
AnnaBridge	172:65be27845400	4324	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
AnnaBridge	172:65be27845400	4325	* @arg @ref RCC_FLAG_LPWRRST Low Power reset
AnnaBridge	172:65be27845400	4326	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	4327	*/
AnnaBridge	172:65be27845400	4328	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	4329	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
AnnaBridge	172:65be27845400	4330	((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
AnnaBridge	172:65be27845400	4331	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
AnnaBridge	172:65be27845400	4332	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
AnnaBridge	172:65be27845400	4333	(1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
AnnaBridge	172:65be27845400	4334	#else
AnnaBridge	172:65be27845400	4335	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
AnnaBridge	172:65be27845400	4336	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
AnnaBridge	172:65be27845400	4337	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
AnnaBridge	172:65be27845400	4338	(1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
AnnaBridge	172:65be27845400	4339	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	4340
AnnaBridge	172:65be27845400	4341	/**
AnnaBridge	172:65be27845400	4342	* @}
AnnaBridge	172:65be27845400	4343	*/
AnnaBridge	172:65be27845400	4344
AnnaBridge	172:65be27845400	4345	/**
AnnaBridge	172:65be27845400	4346	* @}
AnnaBridge	172:65be27845400	4347	*/
AnnaBridge	172:65be27845400	4348
AnnaBridge	172:65be27845400	4349	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	4350	/** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge	172:65be27845400	4351	* @{
AnnaBridge	172:65be27845400	4352	*/
AnnaBridge	172:65be27845400	4353	/* Defines used for Flags */
AnnaBridge	172:65be27845400	4354	#define CR_REG_INDEX 1U
AnnaBridge	172:65be27845400	4355	#define BDCR_REG_INDEX 2U
AnnaBridge	172:65be27845400	4356	#define CSR_REG_INDEX 3U
AnnaBridge	172:65be27845400	4357	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	4358	#define CRRCR_REG_INDEX 4U
AnnaBridge	172:65be27845400	4359	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	4360
AnnaBridge	172:65be27845400	4361	#define RCC_FLAG_MASK 0x1FU
AnnaBridge	172:65be27845400	4362	/**
AnnaBridge	172:65be27845400	4363	* @}
AnnaBridge	172:65be27845400	4364	*/
AnnaBridge	172:65be27845400	4365
AnnaBridge	172:65be27845400	4366	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	4367	/** @addtogroup RCC_Private_Macros
AnnaBridge	172:65be27845400	4368	* @{
AnnaBridge	172:65be27845400	4369	*/
AnnaBridge	172:65be27845400	4370
AnnaBridge	172:65be27845400	4371	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	4372	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	172:65be27845400	4373	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	172:65be27845400	4374	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	172:65be27845400	4375	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) \|\| \
AnnaBridge	172:65be27845400	4376	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
AnnaBridge	172:65be27845400	4377	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	172:65be27845400	4378	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge	172:65be27845400	4379	#else
AnnaBridge	172:65be27845400	4380	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	172:65be27845400	4381	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	172:65be27845400	4382	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	172:65be27845400	4383	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
AnnaBridge	172:65be27845400	4384	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	172:65be27845400	4385	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge	172:65be27845400	4386	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	4387
AnnaBridge	172:65be27845400	4388	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	172:65be27845400	4389	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	172:65be27845400	4390
AnnaBridge	172:65be27845400	4391	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	172:65be27845400	4392	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	172:65be27845400	4393
AnnaBridge	172:65be27845400	4394	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
AnnaBridge	172:65be27845400	4395
AnnaBridge	172:65be27845400	4396	#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
AnnaBridge	172:65be27845400	4397
AnnaBridge	172:65be27845400	4398	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	172:65be27845400	4399
AnnaBridge	172:65be27845400	4400	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
AnnaBridge	172:65be27845400	4401
AnnaBridge	172:65be27845400	4402	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
AnnaBridge	172:65be27845400	4403
AnnaBridge	172:65be27845400	4404	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	4405	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
AnnaBridge	172:65be27845400	4406	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	4407
AnnaBridge	172:65be27845400	4408	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	172:65be27845400	4409	((__PLL__) == RCC_PLL_ON))
AnnaBridge	172:65be27845400	4410
AnnaBridge	172:65be27845400	4411	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	4412	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
AnnaBridge	172:65be27845400	4413	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	4414	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	172:65be27845400	4415
AnnaBridge	172:65be27845400	4416	#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	4417	#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
AnnaBridge	172:65be27845400	4418	#else
AnnaBridge	172:65be27845400	4419	#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge	172:65be27845400	4420	#endif /RCC_PLLM_DIV_1_16_SUPPORT /
AnnaBridge	172:65be27845400	4421
AnnaBridge	172:65be27845400	4422	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge	172:65be27845400	4423
AnnaBridge	172:65be27845400	4424	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	4425	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge	172:65be27845400	4426	#else
AnnaBridge	172:65be27845400	4427	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
AnnaBridge	172:65be27845400	4428	#endif /RCC_PLLP_DIV_2_31_SUPPORT /
AnnaBridge	172:65be27845400	4429
AnnaBridge	172:65be27845400	4430	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	172:65be27845400	4431	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	172:65be27845400	4432
AnnaBridge	172:65be27845400	4433	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	172:65be27845400	4434	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	172:65be27845400	4435
AnnaBridge	172:65be27845400	4436	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
AnnaBridge	172:65be27845400	4437	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
AnnaBridge	172:65be27845400	4438	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
AnnaBridge	172:65be27845400	4439	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0U))
AnnaBridge	172:65be27845400	4440
AnnaBridge	172:65be27845400	4441	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	4442	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	172:65be27845400	4443	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) \|\| \
AnnaBridge	172:65be27845400	4444	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
AnnaBridge	172:65be27845400	4445	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0U))
AnnaBridge	172:65be27845400	4446	#elif defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	4447	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) \|\| \
AnnaBridge	172:65be27845400	4448	(((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) \|\| \
AnnaBridge	172:65be27845400	4449	(((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \
AnnaBridge	172:65be27845400	4450	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_DSICLK\|RCC_PLLSAI2_LTDCCLK)) == 0U))
AnnaBridge	172:65be27845400	4451	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	4452	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	4453
AnnaBridge	172:65be27845400	4454	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
AnnaBridge	172:65be27845400	4455	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
AnnaBridge	172:65be27845400	4456	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
AnnaBridge	172:65be27845400	4457	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
AnnaBridge	172:65be27845400	4458	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	172:65be27845400	4459	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	172:65be27845400	4460	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
AnnaBridge	172:65be27845400	4461	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
AnnaBridge	172:65be27845400	4462	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
AnnaBridge	172:65be27845400	4463	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
AnnaBridge	172:65be27845400	4464	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
AnnaBridge	172:65be27845400	4465	((__RANGE__) == RCC_MSIRANGE_11))
AnnaBridge	172:65be27845400	4466
AnnaBridge	172:65be27845400	4467	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	172:65be27845400	4468	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	172:65be27845400	4469	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
AnnaBridge	172:65be27845400	4470	((__RANGE__) == RCC_MSIRANGE_7))
AnnaBridge	172:65be27845400	4471
AnnaBridge	172:65be27845400	4472	#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
AnnaBridge	172:65be27845400	4473
AnnaBridge	172:65be27845400	4474	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
AnnaBridge	172:65be27845400	4475	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	4476	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	172:65be27845400	4477	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	172:65be27845400	4478
AnnaBridge	172:65be27845400	4479	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	172:65be27845400	4480	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	172:65be27845400	4481	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	172:65be27845400	4482	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	172:65be27845400	4483	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	172:65be27845400	4484
AnnaBridge	172:65be27845400	4485	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	172:65be27845400	4486	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	172:65be27845400	4487	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	172:65be27845400	4488
AnnaBridge	172:65be27845400	4489	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	4490	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	4491	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	4492	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
AnnaBridge	172:65be27845400	4493
AnnaBridge	172:65be27845400	4494	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
AnnaBridge	172:65be27845400	4495
AnnaBridge	172:65be27845400	4496	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	4497	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	172:65be27845400	4498	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	4499	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	172:65be27845400	4500	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	4501	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	172:65be27845400	4502	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	172:65be27845400	4503	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	4504	((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	4505	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
AnnaBridge	172:65be27845400	4506	#else
AnnaBridge	172:65be27845400	4507	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	172:65be27845400	4508	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	4509	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	172:65be27845400	4510	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	4511	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	172:65be27845400	4512	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	172:65be27845400	4513	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	4514	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
AnnaBridge	172:65be27845400	4515	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	4516
AnnaBridge	172:65be27845400	4517	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
AnnaBridge	172:65be27845400	4518	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
AnnaBridge	172:65be27845400	4519	((__DIV__) == RCC_MCODIV_16))
AnnaBridge	172:65be27845400	4520
AnnaBridge	172:65be27845400	4521	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
AnnaBridge	172:65be27845400	4522	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
AnnaBridge	172:65be27845400	4523	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
AnnaBridge	172:65be27845400	4524	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge	172:65be27845400	4525
AnnaBridge	172:65be27845400	4526	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
AnnaBridge	172:65be27845400	4527	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
AnnaBridge	172:65be27845400	4528	/**
AnnaBridge	172:65be27845400	4529	* @}
AnnaBridge	172:65be27845400	4530	*/
AnnaBridge	172:65be27845400	4531
AnnaBridge	172:65be27845400	4532	/* Include RCC HAL Extended module */
AnnaBridge	172:65be27845400	4533	#include "stm32l4xx_hal_rcc_ex.h"
AnnaBridge	172:65be27845400	4534
AnnaBridge	172:65be27845400	4535	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	4536	/** @addtogroup RCC_Exported_Functions
AnnaBridge	172:65be27845400	4537	* @{
AnnaBridge	172:65be27845400	4538	*/
AnnaBridge	172:65be27845400	4539
AnnaBridge	172:65be27845400	4540
AnnaBridge	172:65be27845400	4541	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	172:65be27845400	4542	* @{
AnnaBridge	172:65be27845400	4543	*/
AnnaBridge	172:65be27845400	4544
AnnaBridge	172:65be27845400	4545	/* Initialization and de-initialization functions ******************************/
AnnaBridge	172:65be27845400	4546	HAL_StatusTypeDef HAL_RCC_DeInit(void);
AnnaBridge	172:65be27845400	4547	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	172:65be27845400	4548	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	172:65be27845400	4549
AnnaBridge	172:65be27845400	4550	/**
AnnaBridge	172:65be27845400	4551	* @}
AnnaBridge	172:65be27845400	4552	*/
AnnaBridge	172:65be27845400	4553
AnnaBridge	172:65be27845400	4554	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	172:65be27845400	4555	* @{
AnnaBridge	172:65be27845400	4556	*/
AnnaBridge	172:65be27845400	4557
AnnaBridge	172:65be27845400	4558	/* Peripheral Control functions ************************************************/
AnnaBridge	172:65be27845400	4559	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	172:65be27845400	4560	void HAL_RCC_EnableCSS(void);
AnnaBridge	172:65be27845400	4561	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	172:65be27845400	4562	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	172:65be27845400	4563	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	172:65be27845400	4564	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	172:65be27845400	4565	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	172:65be27845400	4566	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	172:65be27845400	4567	/* CSS NMI IRQ handler */
AnnaBridge	172:65be27845400	4568	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	172:65be27845400	4569	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	172:65be27845400	4570	void HAL_RCC_CSSCallback(void);
AnnaBridge	172:65be27845400	4571
AnnaBridge	172:65be27845400	4572	/**
AnnaBridge	172:65be27845400	4573	* @}
AnnaBridge	172:65be27845400	4574	*/
AnnaBridge	172:65be27845400	4575
AnnaBridge	172:65be27845400	4576	/**
AnnaBridge	172:65be27845400	4577	* @}
AnnaBridge	172:65be27845400	4578	*/
AnnaBridge	172:65be27845400	4579
AnnaBridge	172:65be27845400	4580	/**
AnnaBridge	172:65be27845400	4581	* @}
AnnaBridge	172:65be27845400	4582	*/
AnnaBridge	172:65be27845400	4583
AnnaBridge	172:65be27845400	4584	/**
AnnaBridge	172:65be27845400	4585	* @}
AnnaBridge	172:65be27845400	4586	*/
AnnaBridge	172:65be27845400	4587
AnnaBridge	172:65be27845400	4588	#ifdef __cplusplus
AnnaBridge	172:65be27845400	4589	}
AnnaBridge	172:65be27845400	4590	#endif
AnnaBridge	172:65be27845400	4591
AnnaBridge	172:65be27845400	4592	#endif /* __STM32L4xx_HAL_RCC_H */
AnnaBridge	172:65be27845400	4593
AnnaBridge	172:65be27845400	4594	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/