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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_hal_flash.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32l4xx_hal_flash.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief Header file of FLASH HAL module. |
| AnnaBridge | 172:65be27845400 | 6 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 7 | * @attention |
| AnnaBridge | 172:65be27845400 | 8 | * |
| AnnaBridge | 172:65be27845400 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 172:65be27845400 | 10 | * |
| AnnaBridge | 172:65be27845400 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 172:65be27845400 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 172:65be27845400 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 172:65be27845400 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 172:65be27845400 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 172:65be27845400 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 172:65be27845400 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 172:65be27845400 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 172:65be27845400 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 172:65be27845400 | 20 | * without specific prior written permission. |
| AnnaBridge | 172:65be27845400 | 21 | * |
| AnnaBridge | 172:65be27845400 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 172:65be27845400 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 172:65be27845400 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 172:65be27845400 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 172:65be27845400 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 172:65be27845400 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 172:65be27845400 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 172:65be27845400 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 172:65be27845400 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 172:65be27845400 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 172:65be27845400 | 32 | * |
| AnnaBridge | 172:65be27845400 | 33 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 34 | */ |
| AnnaBridge | 172:65be27845400 | 35 | |
| AnnaBridge | 172:65be27845400 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 37 | #ifndef __STM32L4xx_HAL_FLASH_H |
| AnnaBridge | 172:65be27845400 | 38 | #define __STM32L4xx_HAL_FLASH_H |
| AnnaBridge | 172:65be27845400 | 39 | |
| AnnaBridge | 172:65be27845400 | 40 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 41 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 42 | #endif |
| AnnaBridge | 172:65be27845400 | 43 | |
| AnnaBridge | 172:65be27845400 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 172:65be27845400 | 46 | |
| AnnaBridge | 172:65be27845400 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 172:65be27845400 | 48 | * @{ |
| AnnaBridge | 172:65be27845400 | 49 | */ |
| AnnaBridge | 172:65be27845400 | 50 | |
| AnnaBridge | 172:65be27845400 | 51 | /** @addtogroup FLASH |
| AnnaBridge | 172:65be27845400 | 52 | * @{ |
| AnnaBridge | 172:65be27845400 | 53 | */ |
| AnnaBridge | 172:65be27845400 | 54 | |
| AnnaBridge | 172:65be27845400 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 56 | /** @defgroup FLASH_Exported_Types FLASH Exported Types |
| AnnaBridge | 172:65be27845400 | 57 | * @{ |
| AnnaBridge | 172:65be27845400 | 58 | */ |
| AnnaBridge | 172:65be27845400 | 59 | |
| AnnaBridge | 172:65be27845400 | 60 | /** |
| AnnaBridge | 172:65be27845400 | 61 | * @brief FLASH Erase structure definition |
| AnnaBridge | 172:65be27845400 | 62 | */ |
| AnnaBridge | 172:65be27845400 | 63 | typedef struct |
| AnnaBridge | 172:65be27845400 | 64 | { |
| AnnaBridge | 172:65be27845400 | 65 | uint32_t TypeErase; /*!< Mass erase or page erase. |
| AnnaBridge | 172:65be27845400 | 66 | This parameter can be a value of @ref FLASH_Type_Erase */ |
| AnnaBridge | 172:65be27845400 | 67 | uint32_t Banks; /*!< Select bank to erase. |
| AnnaBridge | 172:65be27845400 | 68 | This parameter must be a value of @ref FLASH_Banks |
| AnnaBridge | 172:65be27845400 | 69 | (FLASH_BANK_BOTH should be used only for mass erase) */ |
| AnnaBridge | 172:65be27845400 | 70 | uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled |
| AnnaBridge | 172:65be27845400 | 71 | This parameter must be a value between 0 and (max number of pages in the bank - 1) |
| AnnaBridge | 172:65be27845400 | 72 | (eg : 255 for 1MB dual bank) */ |
| AnnaBridge | 172:65be27845400 | 73 | uint32_t NbPages; /*!< Number of pages to be erased. |
| AnnaBridge | 172:65be27845400 | 74 | This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ |
| AnnaBridge | 172:65be27845400 | 75 | } FLASH_EraseInitTypeDef; |
| AnnaBridge | 172:65be27845400 | 76 | |
| AnnaBridge | 172:65be27845400 | 77 | /** |
| AnnaBridge | 172:65be27845400 | 78 | * @brief FLASH Option Bytes Program structure definition |
| AnnaBridge | 172:65be27845400 | 79 | */ |
| AnnaBridge | 172:65be27845400 | 80 | typedef struct |
| AnnaBridge | 172:65be27845400 | 81 | { |
| AnnaBridge | 172:65be27845400 | 82 | uint32_t OptionType; /*!< Option byte to be configured. |
| AnnaBridge | 172:65be27845400 | 83 | This parameter can be a combination of the values of @ref FLASH_OB_Type */ |
| AnnaBridge | 172:65be27845400 | 84 | uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). |
| AnnaBridge | 172:65be27845400 | 85 | Only one WRP area could be programmed at the same time. |
| AnnaBridge | 172:65be27845400 | 86 | This parameter can be value of @ref FLASH_OB_WRP_Area */ |
| AnnaBridge | 172:65be27845400 | 87 | uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). |
| AnnaBridge | 172:65be27845400 | 88 | This parameter must be a value between 0 and (max number of pages in the bank - 1) |
| AnnaBridge | 172:65be27845400 | 89 | (eg : 25 for 1MB dual bank) */ |
| AnnaBridge | 172:65be27845400 | 90 | uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). |
| AnnaBridge | 172:65be27845400 | 91 | This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ |
| AnnaBridge | 172:65be27845400 | 92 | uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). |
| AnnaBridge | 172:65be27845400 | 93 | This parameter can be a value of @ref FLASH_OB_Read_Protection */ |
| AnnaBridge | 172:65be27845400 | 94 | uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). |
| AnnaBridge | 172:65be27845400 | 95 | This parameter can be a combination of @ref FLASH_OB_USER_Type */ |
| AnnaBridge | 172:65be27845400 | 96 | uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). |
| AnnaBridge | 172:65be27845400 | 97 | This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, |
| AnnaBridge | 172:65be27845400 | 98 | @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, |
| AnnaBridge | 172:65be27845400 | 99 | @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, |
| AnnaBridge | 172:65be27845400 | 100 | @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, |
| AnnaBridge | 172:65be27845400 | 101 | @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, |
| AnnaBridge | 172:65be27845400 | 102 | @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, |
| AnnaBridge | 172:65be27845400 | 103 | @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ |
| AnnaBridge | 172:65be27845400 | 104 | uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). |
| AnnaBridge | 172:65be27845400 | 105 | This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) |
| AnnaBridge | 172:65be27845400 | 106 | and @ref FLASH_OB_PCROP_RDP */ |
| AnnaBridge | 172:65be27845400 | 107 | uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). |
| AnnaBridge | 172:65be27845400 | 108 | This parameter must be a value between begin and end of bank |
| AnnaBridge | 172:65be27845400 | 109 | => Be careful of the bank swapping for the address */ |
| AnnaBridge | 172:65be27845400 | 110 | uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). |
| AnnaBridge | 172:65be27845400 | 111 | This parameter must be a value between PCROP Start address and end of bank */ |
| AnnaBridge | 172:65be27845400 | 112 | } FLASH_OBProgramInitTypeDef; |
| AnnaBridge | 172:65be27845400 | 113 | |
| AnnaBridge | 172:65be27845400 | 114 | /** |
| AnnaBridge | 172:65be27845400 | 115 | * @brief FLASH Procedure structure definition |
| AnnaBridge | 172:65be27845400 | 116 | */ |
| AnnaBridge | 172:65be27845400 | 117 | typedef enum |
| AnnaBridge | 172:65be27845400 | 118 | { |
| AnnaBridge | 172:65be27845400 | 119 | FLASH_PROC_NONE = 0, |
| AnnaBridge | 172:65be27845400 | 120 | FLASH_PROC_PAGE_ERASE, |
| AnnaBridge | 172:65be27845400 | 121 | FLASH_PROC_MASS_ERASE, |
| AnnaBridge | 172:65be27845400 | 122 | FLASH_PROC_PROGRAM, |
| AnnaBridge | 172:65be27845400 | 123 | FLASH_PROC_PROGRAM_LAST |
| AnnaBridge | 172:65be27845400 | 124 | } FLASH_ProcedureTypeDef; |
| AnnaBridge | 172:65be27845400 | 125 | |
| AnnaBridge | 172:65be27845400 | 126 | /** |
| AnnaBridge | 172:65be27845400 | 127 | * @brief FLASH Cache structure definition |
| AnnaBridge | 172:65be27845400 | 128 | */ |
| AnnaBridge | 172:65be27845400 | 129 | typedef enum |
| AnnaBridge | 172:65be27845400 | 130 | { |
| AnnaBridge | 172:65be27845400 | 131 | FLASH_CACHE_DISABLED = 0, |
| AnnaBridge | 172:65be27845400 | 132 | FLASH_CACHE_ICACHE_ENABLED, |
| AnnaBridge | 172:65be27845400 | 133 | FLASH_CACHE_DCACHE_ENABLED, |
| AnnaBridge | 172:65be27845400 | 134 | FLASH_CACHE_ICACHE_DCACHE_ENABLED |
| AnnaBridge | 172:65be27845400 | 135 | } FLASH_CacheTypeDef; |
| AnnaBridge | 172:65be27845400 | 136 | |
| AnnaBridge | 172:65be27845400 | 137 | /** |
| AnnaBridge | 172:65be27845400 | 138 | * @brief FLASH handle Structure definition |
| AnnaBridge | 172:65be27845400 | 139 | */ |
| AnnaBridge | 172:65be27845400 | 140 | typedef struct |
| AnnaBridge | 172:65be27845400 | 141 | { |
| AnnaBridge | 172:65be27845400 | 142 | HAL_LockTypeDef Lock; /* FLASH locking object */ |
| AnnaBridge | 172:65be27845400 | 143 | __IO uint32_t ErrorCode; /* FLASH error code */ |
| AnnaBridge | 172:65be27845400 | 144 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ |
| AnnaBridge | 172:65be27845400 | 145 | __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ |
| AnnaBridge | 172:65be27845400 | 146 | __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ |
| AnnaBridge | 172:65be27845400 | 147 | __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ |
| AnnaBridge | 172:65be27845400 | 148 | __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ |
| AnnaBridge | 172:65be27845400 | 149 | __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ |
| AnnaBridge | 172:65be27845400 | 150 | }FLASH_ProcessTypeDef; |
| AnnaBridge | 172:65be27845400 | 151 | |
| AnnaBridge | 172:65be27845400 | 152 | /** |
| AnnaBridge | 172:65be27845400 | 153 | * @} |
| AnnaBridge | 172:65be27845400 | 154 | */ |
| AnnaBridge | 172:65be27845400 | 155 | |
| AnnaBridge | 172:65be27845400 | 156 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 157 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants |
| AnnaBridge | 172:65be27845400 | 158 | * @{ |
| AnnaBridge | 172:65be27845400 | 159 | */ |
| AnnaBridge | 172:65be27845400 | 160 | |
| AnnaBridge | 172:65be27845400 | 161 | /** @defgroup FLASH_Error FLASH Error |
| AnnaBridge | 172:65be27845400 | 162 | * @{ |
| AnnaBridge | 172:65be27845400 | 163 | */ |
| AnnaBridge | 172:65be27845400 | 164 | #define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) |
| AnnaBridge | 172:65be27845400 | 165 | #define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001) |
| AnnaBridge | 172:65be27845400 | 166 | #define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002) |
| AnnaBridge | 172:65be27845400 | 167 | #define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004) |
| AnnaBridge | 172:65be27845400 | 168 | #define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) |
| AnnaBridge | 172:65be27845400 | 169 | #define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010) |
| AnnaBridge | 172:65be27845400 | 170 | #define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020) |
| AnnaBridge | 172:65be27845400 | 171 | #define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040) |
| AnnaBridge | 172:65be27845400 | 172 | #define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080) |
| AnnaBridge | 172:65be27845400 | 173 | #define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100) |
| AnnaBridge | 172:65be27845400 | 174 | #define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) |
| AnnaBridge | 172:65be27845400 | 175 | #define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) |
| AnnaBridge | 172:65be27845400 | 176 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 172:65be27845400 | 177 | defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 178 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 179 | #define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) |
| AnnaBridge | 172:65be27845400 | 180 | #endif |
| AnnaBridge | 172:65be27845400 | 181 | /** |
| AnnaBridge | 172:65be27845400 | 182 | * @} |
| AnnaBridge | 172:65be27845400 | 183 | */ |
| AnnaBridge | 172:65be27845400 | 184 | |
| AnnaBridge | 172:65be27845400 | 185 | /** @defgroup FLASH_Type_Erase FLASH Erase Type |
| AnnaBridge | 172:65be27845400 | 186 | * @{ |
| AnnaBridge | 172:65be27845400 | 187 | */ |
| AnnaBridge | 172:65be27845400 | 188 | #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ |
| AnnaBridge | 172:65be27845400 | 189 | #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/ |
| AnnaBridge | 172:65be27845400 | 190 | /** |
| AnnaBridge | 172:65be27845400 | 191 | * @} |
| AnnaBridge | 172:65be27845400 | 192 | */ |
| AnnaBridge | 172:65be27845400 | 193 | |
| AnnaBridge | 172:65be27845400 | 194 | /** @defgroup FLASH_Banks FLASH Banks |
| AnnaBridge | 172:65be27845400 | 195 | * @{ |
| AnnaBridge | 172:65be27845400 | 196 | */ |
| AnnaBridge | 172:65be27845400 | 197 | #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ |
| AnnaBridge | 172:65be27845400 | 198 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 199 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 200 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 201 | #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ |
| AnnaBridge | 172:65be27845400 | 202 | #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ |
| AnnaBridge | 172:65be27845400 | 203 | #else |
| AnnaBridge | 172:65be27845400 | 204 | #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */ |
| AnnaBridge | 172:65be27845400 | 205 | #endif |
| AnnaBridge | 172:65be27845400 | 206 | /** |
| AnnaBridge | 172:65be27845400 | 207 | * @} |
| AnnaBridge | 172:65be27845400 | 208 | */ |
| AnnaBridge | 172:65be27845400 | 209 | |
| AnnaBridge | 172:65be27845400 | 210 | |
| AnnaBridge | 172:65be27845400 | 211 | /** @defgroup FLASH_Type_Program FLASH Program Type |
| AnnaBridge | 172:65be27845400 | 212 | * @{ |
| AnnaBridge | 172:65be27845400 | 213 | */ |
| AnnaBridge | 172:65be27845400 | 214 | #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/ |
| AnnaBridge | 172:65be27845400 | 215 | #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address. |
| AnnaBridge | 172:65be27845400 | 216 | And another 32 row double-word (64-bit) will be programmed */ |
| AnnaBridge | 172:65be27845400 | 217 | #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address. |
| AnnaBridge | 172:65be27845400 | 218 | And this is the last 32 row double-word (64-bit) programmed */ |
| AnnaBridge | 172:65be27845400 | 219 | /** |
| AnnaBridge | 172:65be27845400 | 220 | * @} |
| AnnaBridge | 172:65be27845400 | 221 | */ |
| AnnaBridge | 172:65be27845400 | 222 | |
| AnnaBridge | 172:65be27845400 | 223 | /** @defgroup FLASH_OB_Type FLASH Option Bytes Type |
| AnnaBridge | 172:65be27845400 | 224 | * @{ |
| AnnaBridge | 172:65be27845400 | 225 | */ |
| AnnaBridge | 172:65be27845400 | 226 | #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 227 | #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 228 | #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 229 | #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 230 | /** |
| AnnaBridge | 172:65be27845400 | 231 | * @} |
| AnnaBridge | 172:65be27845400 | 232 | */ |
| AnnaBridge | 172:65be27845400 | 233 | |
| AnnaBridge | 172:65be27845400 | 234 | /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area |
| AnnaBridge | 172:65be27845400 | 235 | * @{ |
| AnnaBridge | 172:65be27845400 | 236 | */ |
| AnnaBridge | 172:65be27845400 | 237 | #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ |
| AnnaBridge | 172:65be27845400 | 238 | #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ |
| AnnaBridge | 172:65be27845400 | 239 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 240 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 241 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 242 | #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ |
| AnnaBridge | 172:65be27845400 | 243 | #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ |
| AnnaBridge | 172:65be27845400 | 244 | #endif |
| AnnaBridge | 172:65be27845400 | 245 | /** |
| AnnaBridge | 172:65be27845400 | 246 | * @} |
| AnnaBridge | 172:65be27845400 | 247 | */ |
| AnnaBridge | 172:65be27845400 | 248 | |
| AnnaBridge | 172:65be27845400 | 249 | /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection |
| AnnaBridge | 172:65be27845400 | 250 | * @{ |
| AnnaBridge | 172:65be27845400 | 251 | */ |
| AnnaBridge | 172:65be27845400 | 252 | #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) |
| AnnaBridge | 172:65be27845400 | 253 | #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) |
| AnnaBridge | 172:65be27845400 | 254 | #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 |
| AnnaBridge | 172:65be27845400 | 255 | it's no more possible to go back to level 1 or 0 */ |
| AnnaBridge | 172:65be27845400 | 256 | /** |
| AnnaBridge | 172:65be27845400 | 257 | * @} |
| AnnaBridge | 172:65be27845400 | 258 | */ |
| AnnaBridge | 172:65be27845400 | 259 | |
| AnnaBridge | 172:65be27845400 | 260 | /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type |
| AnnaBridge | 172:65be27845400 | 261 | * @{ |
| AnnaBridge | 172:65be27845400 | 262 | */ |
| AnnaBridge | 172:65be27845400 | 263 | #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */ |
| AnnaBridge | 172:65be27845400 | 264 | #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */ |
| AnnaBridge | 172:65be27845400 | 265 | #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */ |
| AnnaBridge | 172:65be27845400 | 266 | #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */ |
| AnnaBridge | 172:65be27845400 | 267 | #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */ |
| AnnaBridge | 172:65be27845400 | 268 | #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ |
| AnnaBridge | 172:65be27845400 | 269 | #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ |
| AnnaBridge | 172:65be27845400 | 270 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 271 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 272 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 273 | #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ |
| AnnaBridge | 172:65be27845400 | 274 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 275 | #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ |
| AnnaBridge | 172:65be27845400 | 276 | #else |
| AnnaBridge | 172:65be27845400 | 277 | #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ |
| AnnaBridge | 172:65be27845400 | 278 | #endif |
| AnnaBridge | 172:65be27845400 | 279 | #endif |
| AnnaBridge | 172:65be27845400 | 280 | #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ |
| AnnaBridge | 172:65be27845400 | 281 | #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ |
| AnnaBridge | 172:65be27845400 | 282 | #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ |
| AnnaBridge | 172:65be27845400 | 283 | #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ |
| AnnaBridge | 172:65be27845400 | 284 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ |
| AnnaBridge | 172:65be27845400 | 285 | defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 172:65be27845400 | 286 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 287 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 288 | #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ |
| AnnaBridge | 172:65be27845400 | 289 | #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ |
| AnnaBridge | 172:65be27845400 | 290 | #endif |
| AnnaBridge | 172:65be27845400 | 291 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 292 | #define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ |
| AnnaBridge | 172:65be27845400 | 293 | #endif |
| AnnaBridge | 172:65be27845400 | 294 | /** |
| AnnaBridge | 172:65be27845400 | 295 | * @} |
| AnnaBridge | 172:65be27845400 | 296 | */ |
| AnnaBridge | 172:65be27845400 | 297 | |
| AnnaBridge | 172:65be27845400 | 298 | /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level |
| AnnaBridge | 172:65be27845400 | 299 | * @{ |
| AnnaBridge | 172:65be27845400 | 300 | */ |
| AnnaBridge | 172:65be27845400 | 301 | #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */ |
| AnnaBridge | 172:65be27845400 | 302 | #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */ |
| AnnaBridge | 172:65be27845400 | 303 | #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */ |
| AnnaBridge | 172:65be27845400 | 304 | #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */ |
| AnnaBridge | 172:65be27845400 | 305 | #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */ |
| AnnaBridge | 172:65be27845400 | 306 | /** |
| AnnaBridge | 172:65be27845400 | 307 | * @} |
| AnnaBridge | 172:65be27845400 | 308 | */ |
| AnnaBridge | 172:65be27845400 | 309 | |
| AnnaBridge | 172:65be27845400 | 310 | /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop |
| AnnaBridge | 172:65be27845400 | 311 | * @{ |
| AnnaBridge | 172:65be27845400 | 312 | */ |
| AnnaBridge | 172:65be27845400 | 313 | #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */ |
| AnnaBridge | 172:65be27845400 | 314 | #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ |
| AnnaBridge | 172:65be27845400 | 315 | /** |
| AnnaBridge | 172:65be27845400 | 316 | * @} |
| AnnaBridge | 172:65be27845400 | 317 | */ |
| AnnaBridge | 172:65be27845400 | 318 | |
| AnnaBridge | 172:65be27845400 | 319 | /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby |
| AnnaBridge | 172:65be27845400 | 320 | * @{ |
| AnnaBridge | 172:65be27845400 | 321 | */ |
| AnnaBridge | 172:65be27845400 | 322 | #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */ |
| AnnaBridge | 172:65be27845400 | 323 | #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ |
| AnnaBridge | 172:65be27845400 | 324 | /** |
| AnnaBridge | 172:65be27845400 | 325 | * @} |
| AnnaBridge | 172:65be27845400 | 326 | */ |
| AnnaBridge | 172:65be27845400 | 327 | |
| AnnaBridge | 172:65be27845400 | 328 | /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown |
| AnnaBridge | 172:65be27845400 | 329 | * @{ |
| AnnaBridge | 172:65be27845400 | 330 | */ |
| AnnaBridge | 172:65be27845400 | 331 | #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */ |
| AnnaBridge | 172:65be27845400 | 332 | #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ |
| AnnaBridge | 172:65be27845400 | 333 | /** |
| AnnaBridge | 172:65be27845400 | 334 | * @} |
| AnnaBridge | 172:65be27845400 | 335 | */ |
| AnnaBridge | 172:65be27845400 | 336 | |
| AnnaBridge | 172:65be27845400 | 337 | /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type |
| AnnaBridge | 172:65be27845400 | 338 | * @{ |
| AnnaBridge | 172:65be27845400 | 339 | */ |
| AnnaBridge | 172:65be27845400 | 340 | #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */ |
| AnnaBridge | 172:65be27845400 | 341 | #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ |
| AnnaBridge | 172:65be27845400 | 342 | /** |
| AnnaBridge | 172:65be27845400 | 343 | * @} |
| AnnaBridge | 172:65be27845400 | 344 | */ |
| AnnaBridge | 172:65be27845400 | 345 | |
| AnnaBridge | 172:65be27845400 | 346 | /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop |
| AnnaBridge | 172:65be27845400 | 347 | * @{ |
| AnnaBridge | 172:65be27845400 | 348 | */ |
| AnnaBridge | 172:65be27845400 | 349 | #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */ |
| AnnaBridge | 172:65be27845400 | 350 | #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ |
| AnnaBridge | 172:65be27845400 | 351 | /** |
| AnnaBridge | 172:65be27845400 | 352 | * @} |
| AnnaBridge | 172:65be27845400 | 353 | */ |
| AnnaBridge | 172:65be27845400 | 354 | |
| AnnaBridge | 172:65be27845400 | 355 | /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby |
| AnnaBridge | 172:65be27845400 | 356 | * @{ |
| AnnaBridge | 172:65be27845400 | 357 | */ |
| AnnaBridge | 172:65be27845400 | 358 | #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */ |
| AnnaBridge | 172:65be27845400 | 359 | #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ |
| AnnaBridge | 172:65be27845400 | 360 | /** |
| AnnaBridge | 172:65be27845400 | 361 | * @} |
| AnnaBridge | 172:65be27845400 | 362 | */ |
| AnnaBridge | 172:65be27845400 | 363 | |
| AnnaBridge | 172:65be27845400 | 364 | /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type |
| AnnaBridge | 172:65be27845400 | 365 | * @{ |
| AnnaBridge | 172:65be27845400 | 366 | */ |
| AnnaBridge | 172:65be27845400 | 367 | #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */ |
| AnnaBridge | 172:65be27845400 | 368 | #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ |
| AnnaBridge | 172:65be27845400 | 369 | /** |
| AnnaBridge | 172:65be27845400 | 370 | * @} |
| AnnaBridge | 172:65be27845400 | 371 | */ |
| AnnaBridge | 172:65be27845400 | 372 | |
| AnnaBridge | 172:65be27845400 | 373 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 374 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 375 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 376 | /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode |
| AnnaBridge | 172:65be27845400 | 377 | * @{ |
| AnnaBridge | 172:65be27845400 | 378 | */ |
| AnnaBridge | 172:65be27845400 | 379 | #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */ |
| AnnaBridge | 172:65be27845400 | 380 | #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */ |
| AnnaBridge | 172:65be27845400 | 381 | /** |
| AnnaBridge | 172:65be27845400 | 382 | * @} |
| AnnaBridge | 172:65be27845400 | 383 | */ |
| AnnaBridge | 172:65be27845400 | 384 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 385 | /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type |
| AnnaBridge | 172:65be27845400 | 386 | * @{ |
| AnnaBridge | 172:65be27845400 | 387 | */ |
| AnnaBridge | 172:65be27845400 | 388 | #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ |
| AnnaBridge | 172:65be27845400 | 389 | #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ |
| AnnaBridge | 172:65be27845400 | 390 | /** |
| AnnaBridge | 172:65be27845400 | 391 | * @} |
| AnnaBridge | 172:65be27845400 | 392 | */ |
| AnnaBridge | 172:65be27845400 | 393 | #else |
| AnnaBridge | 172:65be27845400 | 394 | /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type |
| AnnaBridge | 172:65be27845400 | 395 | * @{ |
| AnnaBridge | 172:65be27845400 | 396 | */ |
| AnnaBridge | 172:65be27845400 | 397 | #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */ |
| AnnaBridge | 172:65be27845400 | 398 | #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */ |
| AnnaBridge | 172:65be27845400 | 399 | /** |
| AnnaBridge | 172:65be27845400 | 400 | * @} |
| AnnaBridge | 172:65be27845400 | 401 | */ |
| AnnaBridge | 172:65be27845400 | 402 | #endif |
| AnnaBridge | 172:65be27845400 | 403 | #endif |
| AnnaBridge | 172:65be27845400 | 404 | |
| AnnaBridge | 172:65be27845400 | 405 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 406 | /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type |
| AnnaBridge | 172:65be27845400 | 407 | * @{ |
| AnnaBridge | 172:65be27845400 | 408 | */ |
| AnnaBridge | 172:65be27845400 | 409 | #define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ |
| AnnaBridge | 172:65be27845400 | 410 | #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ |
| AnnaBridge | 172:65be27845400 | 411 | #endif |
| AnnaBridge | 172:65be27845400 | 412 | /** |
| AnnaBridge | 172:65be27845400 | 413 | * @} |
| AnnaBridge | 172:65be27845400 | 414 | */ |
| AnnaBridge | 172:65be27845400 | 415 | /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type |
| AnnaBridge | 172:65be27845400 | 416 | * @{ |
| AnnaBridge | 172:65be27845400 | 417 | */ |
| AnnaBridge | 172:65be27845400 | 418 | #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ |
| AnnaBridge | 172:65be27845400 | 419 | #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ |
| AnnaBridge | 172:65be27845400 | 420 | /** |
| AnnaBridge | 172:65be27845400 | 421 | * @} |
| AnnaBridge | 172:65be27845400 | 422 | */ |
| AnnaBridge | 172:65be27845400 | 423 | |
| AnnaBridge | 172:65be27845400 | 424 | /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type |
| AnnaBridge | 172:65be27845400 | 425 | * @{ |
| AnnaBridge | 172:65be27845400 | 426 | */ |
| AnnaBridge | 172:65be27845400 | 427 | #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */ |
| AnnaBridge | 172:65be27845400 | 428 | #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */ |
| AnnaBridge | 172:65be27845400 | 429 | /** |
| AnnaBridge | 172:65be27845400 | 430 | * @} |
| AnnaBridge | 172:65be27845400 | 431 | */ |
| AnnaBridge | 172:65be27845400 | 432 | |
| AnnaBridge | 172:65be27845400 | 433 | /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type |
| AnnaBridge | 172:65be27845400 | 434 | * @{ |
| AnnaBridge | 172:65be27845400 | 435 | */ |
| AnnaBridge | 172:65be27845400 | 436 | #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */ |
| AnnaBridge | 172:65be27845400 | 437 | #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */ |
| AnnaBridge | 172:65be27845400 | 438 | /** |
| AnnaBridge | 172:65be27845400 | 439 | * @} |
| AnnaBridge | 172:65be27845400 | 440 | */ |
| AnnaBridge | 172:65be27845400 | 441 | |
| AnnaBridge | 172:65be27845400 | 442 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ |
| AnnaBridge | 172:65be27845400 | 443 | defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 172:65be27845400 | 444 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 445 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 446 | /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 |
| AnnaBridge | 172:65be27845400 | 447 | * @{ |
| AnnaBridge | 172:65be27845400 | 448 | */ |
| AnnaBridge | 172:65be27845400 | 449 | #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */ |
| AnnaBridge | 172:65be27845400 | 450 | #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ |
| AnnaBridge | 172:65be27845400 | 451 | /** |
| AnnaBridge | 172:65be27845400 | 452 | * @} |
| AnnaBridge | 172:65be27845400 | 453 | */ |
| AnnaBridge | 172:65be27845400 | 454 | |
| AnnaBridge | 172:65be27845400 | 455 | /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit |
| AnnaBridge | 172:65be27845400 | 456 | * @{ |
| AnnaBridge | 172:65be27845400 | 457 | */ |
| AnnaBridge | 172:65be27845400 | 458 | #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */ |
| AnnaBridge | 172:65be27845400 | 459 | #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ |
| AnnaBridge | 172:65be27845400 | 460 | /** |
| AnnaBridge | 172:65be27845400 | 461 | * @} |
| AnnaBridge | 172:65be27845400 | 462 | */ |
| AnnaBridge | 172:65be27845400 | 463 | #endif |
| AnnaBridge | 172:65be27845400 | 464 | |
| AnnaBridge | 172:65be27845400 | 465 | /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type |
| AnnaBridge | 172:65be27845400 | 466 | * @{ |
| AnnaBridge | 172:65be27845400 | 467 | */ |
| AnnaBridge | 172:65be27845400 | 468 | #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level |
| AnnaBridge | 172:65be27845400 | 469 | is decreased from Level 1 to Level 0 */ |
| AnnaBridge | 172:65be27845400 | 470 | #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is |
| AnnaBridge | 172:65be27845400 | 471 | decreased from Level 1 to Level 0 (full mass erase) */ |
| AnnaBridge | 172:65be27845400 | 472 | /** |
| AnnaBridge | 172:65be27845400 | 473 | * @} |
| AnnaBridge | 172:65be27845400 | 474 | */ |
| AnnaBridge | 172:65be27845400 | 475 | |
| AnnaBridge | 172:65be27845400 | 476 | /** @defgroup FLASH_Latency FLASH Latency |
| AnnaBridge | 172:65be27845400 | 477 | * @{ |
| AnnaBridge | 172:65be27845400 | 478 | */ |
| AnnaBridge | 172:65be27845400 | 479 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ |
| AnnaBridge | 172:65be27845400 | 480 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ |
| AnnaBridge | 172:65be27845400 | 481 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ |
| AnnaBridge | 172:65be27845400 | 482 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ |
| AnnaBridge | 172:65be27845400 | 483 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ |
| AnnaBridge | 172:65be27845400 | 484 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 485 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ |
| AnnaBridge | 172:65be27845400 | 486 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ |
| AnnaBridge | 172:65be27845400 | 487 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ |
| AnnaBridge | 172:65be27845400 | 488 | #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ |
| AnnaBridge | 172:65be27845400 | 489 | #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ |
| AnnaBridge | 172:65be27845400 | 490 | #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ |
| AnnaBridge | 172:65be27845400 | 491 | #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ |
| AnnaBridge | 172:65be27845400 | 492 | #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ |
| AnnaBridge | 172:65be27845400 | 493 | #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ |
| AnnaBridge | 172:65be27845400 | 494 | #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ |
| AnnaBridge | 172:65be27845400 | 495 | #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ |
| AnnaBridge | 172:65be27845400 | 496 | #endif |
| AnnaBridge | 172:65be27845400 | 497 | /** |
| AnnaBridge | 172:65be27845400 | 498 | * @} |
| AnnaBridge | 172:65be27845400 | 499 | */ |
| AnnaBridge | 172:65be27845400 | 500 | |
| AnnaBridge | 172:65be27845400 | 501 | /** @defgroup FLASH_Keys FLASH Keys |
| AnnaBridge | 172:65be27845400 | 502 | * @{ |
| AnnaBridge | 172:65be27845400 | 503 | */ |
| AnnaBridge | 172:65be27845400 | 504 | #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ |
| AnnaBridge | 172:65be27845400 | 505 | #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 |
| AnnaBridge | 172:65be27845400 | 506 | to unlock the FLASH registers access */ |
| AnnaBridge | 172:65be27845400 | 507 | |
| AnnaBridge | 172:65be27845400 | 508 | #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ |
| AnnaBridge | 172:65be27845400 | 509 | #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 |
| AnnaBridge | 172:65be27845400 | 510 | to unlock the RUN_PD bit in FLASH_ACR */ |
| AnnaBridge | 172:65be27845400 | 511 | |
| AnnaBridge | 172:65be27845400 | 512 | #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ |
| AnnaBridge | 172:65be27845400 | 513 | #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 |
| AnnaBridge | 172:65be27845400 | 514 | to allow option bytes operations */ |
| AnnaBridge | 172:65be27845400 | 515 | /** |
| AnnaBridge | 172:65be27845400 | 516 | * @} |
| AnnaBridge | 172:65be27845400 | 517 | */ |
| AnnaBridge | 172:65be27845400 | 518 | |
| AnnaBridge | 172:65be27845400 | 519 | /** @defgroup FLASH_Flags FLASH Flags Definition |
| AnnaBridge | 172:65be27845400 | 520 | * @{ |
| AnnaBridge | 172:65be27845400 | 521 | */ |
| AnnaBridge | 172:65be27845400 | 522 | #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ |
| AnnaBridge | 172:65be27845400 | 523 | #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ |
| AnnaBridge | 172:65be27845400 | 524 | #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ |
| AnnaBridge | 172:65be27845400 | 525 | #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ |
| AnnaBridge | 172:65be27845400 | 526 | #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ |
| AnnaBridge | 172:65be27845400 | 527 | #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ |
| AnnaBridge | 172:65be27845400 | 528 | #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ |
| AnnaBridge | 172:65be27845400 | 529 | #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ |
| AnnaBridge | 172:65be27845400 | 530 | #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ |
| AnnaBridge | 172:65be27845400 | 531 | #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ |
| AnnaBridge | 172:65be27845400 | 532 | #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ |
| AnnaBridge | 172:65be27845400 | 533 | #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ |
| AnnaBridge | 172:65be27845400 | 534 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 172:65be27845400 | 535 | defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 536 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 537 | #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ |
| AnnaBridge | 172:65be27845400 | 538 | #endif |
| AnnaBridge | 172:65be27845400 | 539 | #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ |
| AnnaBridge | 172:65be27845400 | 540 | #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ |
| AnnaBridge | 172:65be27845400 | 541 | |
| AnnaBridge | 172:65be27845400 | 542 | #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ |
| AnnaBridge | 172:65be27845400 | 543 | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ |
| AnnaBridge | 172:65be27845400 | 544 | FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ |
| AnnaBridge | 172:65be27845400 | 545 | FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD) |
| AnnaBridge | 172:65be27845400 | 546 | /** |
| AnnaBridge | 172:65be27845400 | 547 | * @} |
| AnnaBridge | 172:65be27845400 | 548 | */ |
| AnnaBridge | 172:65be27845400 | 549 | |
| AnnaBridge | 172:65be27845400 | 550 | /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition |
| AnnaBridge | 172:65be27845400 | 551 | * @brief FLASH Interrupt definition |
| AnnaBridge | 172:65be27845400 | 552 | * @{ |
| AnnaBridge | 172:65be27845400 | 553 | */ |
| AnnaBridge | 172:65be27845400 | 554 | #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ |
| AnnaBridge | 172:65be27845400 | 555 | #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ |
| AnnaBridge | 172:65be27845400 | 556 | #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ |
| AnnaBridge | 172:65be27845400 | 557 | #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ |
| AnnaBridge | 172:65be27845400 | 558 | /** |
| AnnaBridge | 172:65be27845400 | 559 | * @} |
| AnnaBridge | 172:65be27845400 | 560 | */ |
| AnnaBridge | 172:65be27845400 | 561 | |
| AnnaBridge | 172:65be27845400 | 562 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 563 | /** @defgroup FLASH_Exported_Macros FLASH Exported Macros |
| AnnaBridge | 172:65be27845400 | 564 | * @brief macros to control FLASH features |
| AnnaBridge | 172:65be27845400 | 565 | * @{ |
| AnnaBridge | 172:65be27845400 | 566 | */ |
| AnnaBridge | 172:65be27845400 | 567 | |
| AnnaBridge | 172:65be27845400 | 568 | /** |
| AnnaBridge | 172:65be27845400 | 569 | * @brief Set the FLASH Latency. |
| AnnaBridge | 172:65be27845400 | 570 | * @param __LATENCY__: FLASH Latency |
| AnnaBridge | 172:65be27845400 | 571 | * This parameter can be one of the following values : |
| AnnaBridge | 172:65be27845400 | 572 | * @arg FLASH_LATENCY_0: FLASH Zero wait state |
| AnnaBridge | 172:65be27845400 | 573 | * @arg FLASH_LATENCY_1: FLASH One wait state |
| AnnaBridge | 172:65be27845400 | 574 | * @arg FLASH_LATENCY_2: FLASH Two wait states |
| AnnaBridge | 172:65be27845400 | 575 | * @arg FLASH_LATENCY_3: FLASH Three wait states |
| AnnaBridge | 172:65be27845400 | 576 | * @arg FLASH_LATENCY_4: FLASH Four wait states |
| AnnaBridge | 172:65be27845400 | 577 | * @retval None |
| AnnaBridge | 172:65be27845400 | 578 | */ |
| AnnaBridge | 172:65be27845400 | 579 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) |
| AnnaBridge | 172:65be27845400 | 580 | |
| AnnaBridge | 172:65be27845400 | 581 | /** |
| AnnaBridge | 172:65be27845400 | 582 | * @brief Get the FLASH Latency. |
| AnnaBridge | 172:65be27845400 | 583 | * @retval FLASH Latency |
| AnnaBridge | 172:65be27845400 | 584 | * This parameter can be one of the following values : |
| AnnaBridge | 172:65be27845400 | 585 | * @arg FLASH_LATENCY_0: FLASH Zero wait state |
| AnnaBridge | 172:65be27845400 | 586 | * @arg FLASH_LATENCY_1: FLASH One wait state |
| AnnaBridge | 172:65be27845400 | 587 | * @arg FLASH_LATENCY_2: FLASH Two wait states |
| AnnaBridge | 172:65be27845400 | 588 | * @arg FLASH_LATENCY_3: FLASH Three wait states |
| AnnaBridge | 172:65be27845400 | 589 | * @arg FLASH_LATENCY_4: FLASH Four wait states |
| AnnaBridge | 172:65be27845400 | 590 | */ |
| AnnaBridge | 172:65be27845400 | 591 | #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) |
| AnnaBridge | 172:65be27845400 | 592 | |
| AnnaBridge | 172:65be27845400 | 593 | /** |
| AnnaBridge | 172:65be27845400 | 594 | * @brief Enable the FLASH prefetch buffer. |
| AnnaBridge | 172:65be27845400 | 595 | * @retval None |
| AnnaBridge | 172:65be27845400 | 596 | */ |
| AnnaBridge | 172:65be27845400 | 597 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) |
| AnnaBridge | 172:65be27845400 | 598 | |
| AnnaBridge | 172:65be27845400 | 599 | /** |
| AnnaBridge | 172:65be27845400 | 600 | * @brief Disable the FLASH prefetch buffer. |
| AnnaBridge | 172:65be27845400 | 601 | * @retval None |
| AnnaBridge | 172:65be27845400 | 602 | */ |
| AnnaBridge | 172:65be27845400 | 603 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) |
| AnnaBridge | 172:65be27845400 | 604 | |
| AnnaBridge | 172:65be27845400 | 605 | /** |
| AnnaBridge | 172:65be27845400 | 606 | * @brief Enable the FLASH instruction cache. |
| AnnaBridge | 172:65be27845400 | 607 | * @retval none |
| AnnaBridge | 172:65be27845400 | 608 | */ |
| AnnaBridge | 172:65be27845400 | 609 | #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) |
| AnnaBridge | 172:65be27845400 | 610 | |
| AnnaBridge | 172:65be27845400 | 611 | /** |
| AnnaBridge | 172:65be27845400 | 612 | * @brief Disable the FLASH instruction cache. |
| AnnaBridge | 172:65be27845400 | 613 | * @retval none |
| AnnaBridge | 172:65be27845400 | 614 | */ |
| AnnaBridge | 172:65be27845400 | 615 | #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) |
| AnnaBridge | 172:65be27845400 | 616 | |
| AnnaBridge | 172:65be27845400 | 617 | /** |
| AnnaBridge | 172:65be27845400 | 618 | * @brief Enable the FLASH data cache. |
| AnnaBridge | 172:65be27845400 | 619 | * @retval none |
| AnnaBridge | 172:65be27845400 | 620 | */ |
| AnnaBridge | 172:65be27845400 | 621 | #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) |
| AnnaBridge | 172:65be27845400 | 622 | |
| AnnaBridge | 172:65be27845400 | 623 | /** |
| AnnaBridge | 172:65be27845400 | 624 | * @brief Disable the FLASH data cache. |
| AnnaBridge | 172:65be27845400 | 625 | * @retval none |
| AnnaBridge | 172:65be27845400 | 626 | */ |
| AnnaBridge | 172:65be27845400 | 627 | #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) |
| AnnaBridge | 172:65be27845400 | 628 | |
| AnnaBridge | 172:65be27845400 | 629 | /** |
| AnnaBridge | 172:65be27845400 | 630 | * @brief Reset the FLASH instruction Cache. |
| AnnaBridge | 172:65be27845400 | 631 | * @note This function must be used only when the Instruction Cache is disabled. |
| AnnaBridge | 172:65be27845400 | 632 | * @retval None |
| AnnaBridge | 172:65be27845400 | 633 | */ |
| AnnaBridge | 172:65be27845400 | 634 | #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ |
| AnnaBridge | 172:65be27845400 | 635 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ |
| AnnaBridge | 172:65be27845400 | 636 | } while (0) |
| AnnaBridge | 172:65be27845400 | 637 | |
| AnnaBridge | 172:65be27845400 | 638 | /** |
| AnnaBridge | 172:65be27845400 | 639 | * @brief Reset the FLASH data Cache. |
| AnnaBridge | 172:65be27845400 | 640 | * @note This function must be used only when the data Cache is disabled. |
| AnnaBridge | 172:65be27845400 | 641 | * @retval None |
| AnnaBridge | 172:65be27845400 | 642 | */ |
| AnnaBridge | 172:65be27845400 | 643 | #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ |
| AnnaBridge | 172:65be27845400 | 644 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ |
| AnnaBridge | 172:65be27845400 | 645 | } while (0) |
| AnnaBridge | 172:65be27845400 | 646 | |
| AnnaBridge | 172:65be27845400 | 647 | /** |
| AnnaBridge | 172:65be27845400 | 648 | * @brief Enable the FLASH power down during Low-power run mode. |
| AnnaBridge | 172:65be27845400 | 649 | * @note Writing this bit to 0 this bit, automatically the keys are |
| AnnaBridge | 172:65be27845400 | 650 | * loss and a new unlock sequence is necessary to re-write it to 1. |
| AnnaBridge | 172:65be27845400 | 651 | */ |
| AnnaBridge | 172:65be27845400 | 652 | #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ |
| AnnaBridge | 172:65be27845400 | 653 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ |
| AnnaBridge | 172:65be27845400 | 654 | SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ |
| AnnaBridge | 172:65be27845400 | 655 | } while (0) |
| AnnaBridge | 172:65be27845400 | 656 | |
| AnnaBridge | 172:65be27845400 | 657 | /** |
| AnnaBridge | 172:65be27845400 | 658 | * @brief Disable the FLASH power down during Low-power run mode. |
| AnnaBridge | 172:65be27845400 | 659 | * @note Writing this bit to 0 this bit, automatically the keys are |
| AnnaBridge | 172:65be27845400 | 660 | * loss and a new unlock sequence is necessary to re-write it to 1. |
| AnnaBridge | 172:65be27845400 | 661 | */ |
| AnnaBridge | 172:65be27845400 | 662 | #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ |
| AnnaBridge | 172:65be27845400 | 663 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ |
| AnnaBridge | 172:65be27845400 | 664 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ |
| AnnaBridge | 172:65be27845400 | 665 | } while (0) |
| AnnaBridge | 172:65be27845400 | 666 | |
| AnnaBridge | 172:65be27845400 | 667 | /** |
| AnnaBridge | 172:65be27845400 | 668 | * @brief Enable the FLASH power down during Low-Power sleep mode |
| AnnaBridge | 172:65be27845400 | 669 | * @retval none |
| AnnaBridge | 172:65be27845400 | 670 | */ |
| AnnaBridge | 172:65be27845400 | 671 | #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) |
| AnnaBridge | 172:65be27845400 | 672 | |
| AnnaBridge | 172:65be27845400 | 673 | /** |
| AnnaBridge | 172:65be27845400 | 674 | * @brief Disable the FLASH power down during Low-Power sleep mode |
| AnnaBridge | 172:65be27845400 | 675 | * @retval none |
| AnnaBridge | 172:65be27845400 | 676 | */ |
| AnnaBridge | 172:65be27845400 | 677 | #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) |
| AnnaBridge | 172:65be27845400 | 678 | |
| AnnaBridge | 172:65be27845400 | 679 | /** |
| AnnaBridge | 172:65be27845400 | 680 | * @} |
| AnnaBridge | 172:65be27845400 | 681 | */ |
| AnnaBridge | 172:65be27845400 | 682 | |
| AnnaBridge | 172:65be27845400 | 683 | /** @defgroup FLASH_Interrupt FLASH Interrupts Macros |
| AnnaBridge | 172:65be27845400 | 684 | * @brief macros to handle FLASH interrupts |
| AnnaBridge | 172:65be27845400 | 685 | * @{ |
| AnnaBridge | 172:65be27845400 | 686 | */ |
| AnnaBridge | 172:65be27845400 | 687 | |
| AnnaBridge | 172:65be27845400 | 688 | /** |
| AnnaBridge | 172:65be27845400 | 689 | * @brief Enable the specified FLASH interrupt. |
| AnnaBridge | 172:65be27845400 | 690 | * @param __INTERRUPT__: FLASH interrupt |
| AnnaBridge | 172:65be27845400 | 691 | * This parameter can be any combination of the following values: |
| AnnaBridge | 172:65be27845400 | 692 | * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt |
| AnnaBridge | 172:65be27845400 | 693 | * @arg FLASH_IT_OPERR: Error Interrupt |
| AnnaBridge | 172:65be27845400 | 694 | * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt |
| AnnaBridge | 172:65be27845400 | 695 | * @arg FLASH_IT_ECCC: ECC Correction Interrupt |
| AnnaBridge | 172:65be27845400 | 696 | * @retval none |
| AnnaBridge | 172:65be27845400 | 697 | */ |
| AnnaBridge | 172:65be27845400 | 698 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ |
| AnnaBridge | 172:65be27845400 | 699 | if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ |
| AnnaBridge | 172:65be27845400 | 700 | } while(0) |
| AnnaBridge | 172:65be27845400 | 701 | |
| AnnaBridge | 172:65be27845400 | 702 | /** |
| AnnaBridge | 172:65be27845400 | 703 | * @brief Disable the specified FLASH interrupt. |
| AnnaBridge | 172:65be27845400 | 704 | * @param __INTERRUPT__: FLASH interrupt |
| AnnaBridge | 172:65be27845400 | 705 | * This parameter can be any combination of the following values: |
| AnnaBridge | 172:65be27845400 | 706 | * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt |
| AnnaBridge | 172:65be27845400 | 707 | * @arg FLASH_IT_OPERR: Error Interrupt |
| AnnaBridge | 172:65be27845400 | 708 | * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt |
| AnnaBridge | 172:65be27845400 | 709 | * @arg FLASH_IT_ECCC: ECC Correction Interrupt |
| AnnaBridge | 172:65be27845400 | 710 | * @retval none |
| AnnaBridge | 172:65be27845400 | 711 | */ |
| AnnaBridge | 172:65be27845400 | 712 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ |
| AnnaBridge | 172:65be27845400 | 713 | if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ |
| AnnaBridge | 172:65be27845400 | 714 | } while(0) |
| AnnaBridge | 172:65be27845400 | 715 | |
| AnnaBridge | 172:65be27845400 | 716 | /** |
| AnnaBridge | 172:65be27845400 | 717 | * @brief Check whether the specified FLASH flag is set or not. |
| AnnaBridge | 172:65be27845400 | 718 | * @param __FLAG__: specifies the FLASH flag to check. |
| AnnaBridge | 172:65be27845400 | 719 | * This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 720 | * @arg FLASH_FLAG_EOP: FLASH End of Operation flag |
| AnnaBridge | 172:65be27845400 | 721 | * @arg FLASH_FLAG_OPERR: FLASH Operation error flag |
| AnnaBridge | 172:65be27845400 | 722 | * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag |
| AnnaBridge | 172:65be27845400 | 723 | * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag |
| AnnaBridge | 172:65be27845400 | 724 | * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag |
| AnnaBridge | 172:65be27845400 | 725 | * @arg FLASH_FLAG_SIZERR: FLASH Size error flag |
| AnnaBridge | 172:65be27845400 | 726 | * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag |
| AnnaBridge | 172:65be27845400 | 727 | * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag |
| AnnaBridge | 172:65be27845400 | 728 | * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag |
| AnnaBridge | 172:65be27845400 | 729 | * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag |
| AnnaBridge | 172:65be27845400 | 730 | * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag |
| AnnaBridge | 172:65be27845400 | 731 | * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag |
| AnnaBridge | 172:65be27845400 | 732 | * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) |
| AnnaBridge | 172:65be27845400 | 733 | * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected |
| AnnaBridge | 172:65be27845400 | 734 | * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected |
| AnnaBridge | 172:65be27845400 | 735 | * @retval The new state of FLASH_FLAG (SET or RESET). |
| AnnaBridge | 172:65be27845400 | 736 | */ |
| AnnaBridge | 172:65be27845400 | 737 | #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \ |
| AnnaBridge | 172:65be27845400 | 738 | (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ |
| AnnaBridge | 172:65be27845400 | 739 | (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) |
| AnnaBridge | 172:65be27845400 | 740 | |
| AnnaBridge | 172:65be27845400 | 741 | /** |
| AnnaBridge | 172:65be27845400 | 742 | * @brief Clear the FLASH's pending flags. |
| AnnaBridge | 172:65be27845400 | 743 | * @param __FLAG__: specifies the FLASH flags to clear. |
| AnnaBridge | 172:65be27845400 | 744 | * This parameter can be any combination of the following values: |
| AnnaBridge | 172:65be27845400 | 745 | * @arg FLASH_FLAG_EOP: FLASH End of Operation flag |
| AnnaBridge | 172:65be27845400 | 746 | * @arg FLASH_FLAG_OPERR: FLASH Operation error flag |
| AnnaBridge | 172:65be27845400 | 747 | * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag |
| AnnaBridge | 172:65be27845400 | 748 | * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag |
| AnnaBridge | 172:65be27845400 | 749 | * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag |
| AnnaBridge | 172:65be27845400 | 750 | * @arg FLASH_FLAG_SIZERR: FLASH Size error flag |
| AnnaBridge | 172:65be27845400 | 751 | * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag |
| AnnaBridge | 172:65be27845400 | 752 | * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag |
| AnnaBridge | 172:65be27845400 | 753 | * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag |
| AnnaBridge | 172:65be27845400 | 754 | * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag |
| AnnaBridge | 172:65be27845400 | 755 | * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag |
| AnnaBridge | 172:65be27845400 | 756 | * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected |
| AnnaBridge | 172:65be27845400 | 757 | * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected |
| AnnaBridge | 172:65be27845400 | 758 | * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags |
| AnnaBridge | 172:65be27845400 | 759 | * @retval None |
| AnnaBridge | 172:65be27845400 | 760 | */ |
| AnnaBridge | 172:65be27845400 | 761 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ |
| AnnaBridge | 172:65be27845400 | 762 | if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ |
| AnnaBridge | 172:65be27845400 | 763 | } while(0) |
| AnnaBridge | 172:65be27845400 | 764 | /** |
| AnnaBridge | 172:65be27845400 | 765 | * @} |
| AnnaBridge | 172:65be27845400 | 766 | */ |
| AnnaBridge | 172:65be27845400 | 767 | |
| AnnaBridge | 172:65be27845400 | 768 | /* Include FLASH HAL Extended module */ |
| AnnaBridge | 172:65be27845400 | 769 | #include "stm32l4xx_hal_flash_ex.h" |
| AnnaBridge | 172:65be27845400 | 770 | #include "stm32l4xx_hal_flash_ramfunc.h" |
| AnnaBridge | 172:65be27845400 | 771 | |
| AnnaBridge | 172:65be27845400 | 772 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 773 | /** @addtogroup FLASH_Exported_Functions |
| AnnaBridge | 172:65be27845400 | 774 | * @{ |
| AnnaBridge | 172:65be27845400 | 775 | */ |
| AnnaBridge | 172:65be27845400 | 776 | |
| AnnaBridge | 172:65be27845400 | 777 | /* Program operation functions ***********************************************/ |
| AnnaBridge | 172:65be27845400 | 778 | /** @addtogroup FLASH_Exported_Functions_Group1 |
| AnnaBridge | 172:65be27845400 | 779 | * @{ |
| AnnaBridge | 172:65be27845400 | 780 | */ |
| AnnaBridge | 172:65be27845400 | 781 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); |
| AnnaBridge | 172:65be27845400 | 782 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); |
| AnnaBridge | 172:65be27845400 | 783 | /* FLASH IRQ handler method */ |
| AnnaBridge | 172:65be27845400 | 784 | void HAL_FLASH_IRQHandler(void); |
| AnnaBridge | 172:65be27845400 | 785 | /* Callbacks in non blocking modes */ |
| AnnaBridge | 172:65be27845400 | 786 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); |
| AnnaBridge | 172:65be27845400 | 787 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); |
| AnnaBridge | 172:65be27845400 | 788 | /** |
| AnnaBridge | 172:65be27845400 | 789 | * @} |
| AnnaBridge | 172:65be27845400 | 790 | */ |
| AnnaBridge | 172:65be27845400 | 791 | |
| AnnaBridge | 172:65be27845400 | 792 | /* Peripheral Control functions **********************************************/ |
| AnnaBridge | 172:65be27845400 | 793 | /** @addtogroup FLASH_Exported_Functions_Group2 |
| AnnaBridge | 172:65be27845400 | 794 | * @{ |
| AnnaBridge | 172:65be27845400 | 795 | */ |
| AnnaBridge | 172:65be27845400 | 796 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); |
| AnnaBridge | 172:65be27845400 | 797 | HAL_StatusTypeDef HAL_FLASH_Lock(void); |
| AnnaBridge | 172:65be27845400 | 798 | /* Option bytes control */ |
| AnnaBridge | 172:65be27845400 | 799 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); |
| AnnaBridge | 172:65be27845400 | 800 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); |
| AnnaBridge | 172:65be27845400 | 801 | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); |
| AnnaBridge | 172:65be27845400 | 802 | /** |
| AnnaBridge | 172:65be27845400 | 803 | * @} |
| AnnaBridge | 172:65be27845400 | 804 | */ |
| AnnaBridge | 172:65be27845400 | 805 | |
| AnnaBridge | 172:65be27845400 | 806 | /* Peripheral State functions ************************************************/ |
| AnnaBridge | 172:65be27845400 | 807 | /** @addtogroup FLASH_Exported_Functions_Group3 |
| AnnaBridge | 172:65be27845400 | 808 | * @{ |
| AnnaBridge | 172:65be27845400 | 809 | */ |
| AnnaBridge | 172:65be27845400 | 810 | uint32_t HAL_FLASH_GetError(void); |
| AnnaBridge | 172:65be27845400 | 811 | /** |
| AnnaBridge | 172:65be27845400 | 812 | * @} |
| AnnaBridge | 172:65be27845400 | 813 | */ |
| AnnaBridge | 172:65be27845400 | 814 | |
| AnnaBridge | 172:65be27845400 | 815 | /** |
| AnnaBridge | 172:65be27845400 | 816 | * @} |
| AnnaBridge | 172:65be27845400 | 817 | */ |
| AnnaBridge | 172:65be27845400 | 818 | |
| AnnaBridge | 172:65be27845400 | 819 | /* Private constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 820 | /** @defgroup FLASH_Private_Constants FLASH Private Constants |
| AnnaBridge | 172:65be27845400 | 821 | * @{ |
| AnnaBridge | 172:65be27845400 | 822 | */ |
| AnnaBridge | 172:65be27845400 | 823 | #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) |
| AnnaBridge | 172:65be27845400 | 824 | |
| AnnaBridge | 172:65be27845400 | 825 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 826 | #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ |
| AnnaBridge | 172:65be27845400 | 827 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) |
| AnnaBridge | 172:65be27845400 | 828 | #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 172:65be27845400 | 829 | #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ |
| AnnaBridge | 172:65be27845400 | 830 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) |
| AnnaBridge | 172:65be27845400 | 831 | #else |
| AnnaBridge | 172:65be27845400 | 832 | #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \ |
| AnnaBridge | 172:65be27845400 | 833 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) |
| AnnaBridge | 172:65be27845400 | 834 | #endif |
| AnnaBridge | 172:65be27845400 | 835 | |
| AnnaBridge | 172:65be27845400 | 836 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 837 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 838 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 839 | #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) |
| AnnaBridge | 172:65be27845400 | 840 | #else |
| AnnaBridge | 172:65be27845400 | 841 | #define FLASH_BANK_SIZE (FLASH_SIZE) |
| AnnaBridge | 172:65be27845400 | 842 | #endif |
| AnnaBridge | 172:65be27845400 | 843 | |
| AnnaBridge | 172:65be27845400 | 844 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 845 | #define FLASH_PAGE_SIZE ((uint32_t)0x1000) |
| AnnaBridge | 172:65be27845400 | 846 | #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) |
| AnnaBridge | 172:65be27845400 | 847 | #else |
| AnnaBridge | 172:65be27845400 | 848 | #define FLASH_PAGE_SIZE ((uint32_t)0x800) |
| AnnaBridge | 172:65be27845400 | 849 | #endif |
| AnnaBridge | 172:65be27845400 | 850 | |
| AnnaBridge | 172:65be27845400 | 851 | #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ |
| AnnaBridge | 172:65be27845400 | 852 | /** |
| AnnaBridge | 172:65be27845400 | 853 | * @} |
| AnnaBridge | 172:65be27845400 | 854 | */ |
| AnnaBridge | 172:65be27845400 | 855 | |
| AnnaBridge | 172:65be27845400 | 856 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 857 | /** @defgroup FLASH_Private_Macros FLASH Private Macros |
| AnnaBridge | 172:65be27845400 | 858 | * @{ |
| AnnaBridge | 172:65be27845400 | 859 | */ |
| AnnaBridge | 172:65be27845400 | 860 | |
| AnnaBridge | 172:65be27845400 | 861 | #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ |
| AnnaBridge | 172:65be27845400 | 862 | ((VALUE) == FLASH_TYPEERASE_MASSERASE)) |
| AnnaBridge | 172:65be27845400 | 863 | |
| AnnaBridge | 172:65be27845400 | 864 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 865 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 866 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 867 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
| AnnaBridge | 172:65be27845400 | 868 | ((BANK) == FLASH_BANK_2) || \ |
| AnnaBridge | 172:65be27845400 | 869 | ((BANK) == FLASH_BANK_BOTH)) |
| AnnaBridge | 172:65be27845400 | 870 | |
| AnnaBridge | 172:65be27845400 | 871 | #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ |
| AnnaBridge | 172:65be27845400 | 872 | ((BANK) == FLASH_BANK_2)) |
| AnnaBridge | 172:65be27845400 | 873 | #else |
| AnnaBridge | 172:65be27845400 | 874 | #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) |
| AnnaBridge | 172:65be27845400 | 875 | |
| AnnaBridge | 172:65be27845400 | 876 | #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) |
| AnnaBridge | 172:65be27845400 | 877 | #endif |
| AnnaBridge | 172:65be27845400 | 878 | |
| AnnaBridge | 172:65be27845400 | 879 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ |
| AnnaBridge | 172:65be27845400 | 880 | ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ |
| AnnaBridge | 172:65be27845400 | 881 | ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) |
| AnnaBridge | 172:65be27845400 | 882 | |
| AnnaBridge | 172:65be27845400 | 883 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 884 | #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) |
| AnnaBridge | 172:65be27845400 | 885 | #else |
| AnnaBridge | 172:65be27845400 | 886 | #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ |
| AnnaBridge | 172:65be27845400 | 887 | ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ |
| AnnaBridge | 172:65be27845400 | 888 | ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ |
| AnnaBridge | 172:65be27845400 | 889 | ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ |
| AnnaBridge | 172:65be27845400 | 890 | ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) |
| AnnaBridge | 172:65be27845400 | 891 | #endif |
| AnnaBridge | 172:65be27845400 | 892 | |
| AnnaBridge | 172:65be27845400 | 893 | #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) |
| AnnaBridge | 172:65be27845400 | 894 | |
| AnnaBridge | 172:65be27845400 | 895 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) |
| AnnaBridge | 172:65be27845400 | 896 | |
| AnnaBridge | 172:65be27845400 | 897 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 898 | #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) |
| AnnaBridge | 172:65be27845400 | 899 | #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
| AnnaBridge | 172:65be27845400 | 900 | #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ |
| AnnaBridge | 172:65be27845400 | 901 | ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ |
| AnnaBridge | 172:65be27845400 | 902 | ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ |
| AnnaBridge | 172:65be27845400 | 903 | ((PAGE) < 256))))) |
| AnnaBridge | 172:65be27845400 | 904 | #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 172:65be27845400 | 905 | #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \ |
| AnnaBridge | 172:65be27845400 | 906 | ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ |
| AnnaBridge | 172:65be27845400 | 907 | ((PAGE) < 256)))) |
| AnnaBridge | 172:65be27845400 | 908 | #else |
| AnnaBridge | 172:65be27845400 | 909 | #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ |
| AnnaBridge | 172:65be27845400 | 910 | ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \ |
| AnnaBridge | 172:65be27845400 | 911 | ((PAGE) < 128)))) |
| AnnaBridge | 172:65be27845400 | 912 | #endif |
| AnnaBridge | 172:65be27845400 | 913 | |
| AnnaBridge | 172:65be27845400 | 914 | #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) |
| AnnaBridge | 172:65be27845400 | 915 | |
| AnnaBridge | 172:65be27845400 | 916 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 917 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 918 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 919 | #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ |
| AnnaBridge | 172:65be27845400 | 920 | ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) |
| AnnaBridge | 172:65be27845400 | 921 | #else |
| AnnaBridge | 172:65be27845400 | 922 | #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) |
| AnnaBridge | 172:65be27845400 | 923 | #endif |
| AnnaBridge | 172:65be27845400 | 924 | |
| AnnaBridge | 172:65be27845400 | 925 | #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ |
| AnnaBridge | 172:65be27845400 | 926 | ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ |
| AnnaBridge | 172:65be27845400 | 927 | ((LEVEL) == OB_RDP_LEVEL_2)*/) |
| AnnaBridge | 172:65be27845400 | 928 | |
| AnnaBridge | 172:65be27845400 | 929 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 930 | #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) |
| AnnaBridge | 172:65be27845400 | 931 | #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
| AnnaBridge | 172:65be27845400 | 932 | #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) |
| AnnaBridge | 172:65be27845400 | 933 | #else |
| AnnaBridge | 172:65be27845400 | 934 | #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) |
| AnnaBridge | 172:65be27845400 | 935 | #endif |
| AnnaBridge | 172:65be27845400 | 936 | |
| AnnaBridge | 172:65be27845400 | 937 | #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 938 | ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 939 | ((LEVEL) == OB_BOR_LEVEL_4)) |
| AnnaBridge | 172:65be27845400 | 940 | |
| AnnaBridge | 172:65be27845400 | 941 | #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) |
| AnnaBridge | 172:65be27845400 | 942 | |
| AnnaBridge | 172:65be27845400 | 943 | #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) |
| AnnaBridge | 172:65be27845400 | 944 | |
| AnnaBridge | 172:65be27845400 | 945 | #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) |
| AnnaBridge | 172:65be27845400 | 946 | |
| AnnaBridge | 172:65be27845400 | 947 | #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) |
| AnnaBridge | 172:65be27845400 | 948 | |
| AnnaBridge | 172:65be27845400 | 949 | #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) |
| AnnaBridge | 172:65be27845400 | 950 | |
| AnnaBridge | 172:65be27845400 | 951 | #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) |
| AnnaBridge | 172:65be27845400 | 952 | |
| AnnaBridge | 172:65be27845400 | 953 | #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) |
| AnnaBridge | 172:65be27845400 | 954 | |
| AnnaBridge | 172:65be27845400 | 955 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 956 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 957 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 958 | #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) |
| AnnaBridge | 172:65be27845400 | 959 | |
| AnnaBridge | 172:65be27845400 | 960 | #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) |
| AnnaBridge | 172:65be27845400 | 961 | #endif |
| AnnaBridge | 172:65be27845400 | 962 | |
| AnnaBridge | 172:65be27845400 | 963 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 964 | #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) |
| AnnaBridge | 172:65be27845400 | 965 | #endif |
| AnnaBridge | 172:65be27845400 | 966 | |
| AnnaBridge | 172:65be27845400 | 967 | #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) |
| AnnaBridge | 172:65be27845400 | 968 | |
| AnnaBridge | 172:65be27845400 | 969 | #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) |
| AnnaBridge | 172:65be27845400 | 970 | |
| AnnaBridge | 172:65be27845400 | 971 | #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) |
| AnnaBridge | 172:65be27845400 | 972 | |
| AnnaBridge | 172:65be27845400 | 973 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ |
| AnnaBridge | 172:65be27845400 | 974 | defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 172:65be27845400 | 975 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 976 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 977 | #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) |
| AnnaBridge | 172:65be27845400 | 978 | |
| AnnaBridge | 172:65be27845400 | 979 | #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) |
| AnnaBridge | 172:65be27845400 | 980 | #endif |
| AnnaBridge | 172:65be27845400 | 981 | |
| AnnaBridge | 172:65be27845400 | 982 | #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) |
| AnnaBridge | 172:65be27845400 | 983 | |
| AnnaBridge | 172:65be27845400 | 984 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 985 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ |
| AnnaBridge | 172:65be27845400 | 986 | ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ |
| AnnaBridge | 172:65be27845400 | 987 | ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ |
| AnnaBridge | 172:65be27845400 | 988 | ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ |
| AnnaBridge | 172:65be27845400 | 989 | ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ |
| AnnaBridge | 172:65be27845400 | 990 | ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ |
| AnnaBridge | 172:65be27845400 | 991 | ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ |
| AnnaBridge | 172:65be27845400 | 992 | ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) |
| AnnaBridge | 172:65be27845400 | 993 | #else |
| AnnaBridge | 172:65be27845400 | 994 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| AnnaBridge | 172:65be27845400 | 995 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| AnnaBridge | 172:65be27845400 | 996 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| AnnaBridge | 172:65be27845400 | 997 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| AnnaBridge | 172:65be27845400 | 998 | ((LATENCY) == FLASH_LATENCY_4)) |
| AnnaBridge | 172:65be27845400 | 999 | #endif |
| AnnaBridge | 172:65be27845400 | 1000 | /** |
| AnnaBridge | 172:65be27845400 | 1001 | * @} |
| AnnaBridge | 172:65be27845400 | 1002 | */ |
| AnnaBridge | 172:65be27845400 | 1003 | |
| AnnaBridge | 172:65be27845400 | 1004 | /** |
| AnnaBridge | 172:65be27845400 | 1005 | * @} |
| AnnaBridge | 172:65be27845400 | 1006 | */ |
| AnnaBridge | 172:65be27845400 | 1007 | |
| AnnaBridge | 172:65be27845400 | 1008 | /** |
| AnnaBridge | 172:65be27845400 | 1009 | * @} |
| AnnaBridge | 172:65be27845400 | 1010 | */ |
| AnnaBridge | 172:65be27845400 | 1011 | |
| AnnaBridge | 172:65be27845400 | 1012 | /** |
| AnnaBridge | 172:65be27845400 | 1013 | * @} |
| AnnaBridge | 172:65be27845400 | 1014 | */ |
| AnnaBridge | 172:65be27845400 | 1015 | |
| AnnaBridge | 172:65be27845400 | 1016 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 1017 | } |
| AnnaBridge | 172:65be27845400 | 1018 | #endif |
| AnnaBridge | 172:65be27845400 | 1019 | |
| AnnaBridge | 172:65be27845400 | 1020 | #endif /* __STM32L4xx_HAL_FLASH_H */ |
| AnnaBridge | 172:65be27845400 | 1021 | |
| AnnaBridge | 172:65be27845400 | 1022 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
