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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_hal_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_hal_dma.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of DMA HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 12 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 14 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 17 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 19 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 20 * without specific prior written permission.
AnnaBridge 172:65be27845400 21 *
AnnaBridge 172:65be27845400 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 32 *
AnnaBridge 172:65be27845400 33 ******************************************************************************
AnnaBridge 172:65be27845400 34 */
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 37 #ifndef __STM32L4xx_HAL_DMA_H
AnnaBridge 172:65be27845400 38 #define __STM32L4xx_HAL_DMA_H
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 #ifdef __cplusplus
AnnaBridge 172:65be27845400 41 extern "C" {
AnnaBridge 172:65be27845400 42 #endif
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 45 #include "stm32l4xx_hal_def.h"
AnnaBridge 172:65be27845400 46
AnnaBridge 172:65be27845400 47 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 172:65be27845400 48 * @{
AnnaBridge 172:65be27845400 49 */
AnnaBridge 172:65be27845400 50
AnnaBridge 172:65be27845400 51 /** @addtogroup DMA
AnnaBridge 172:65be27845400 52 * @{
AnnaBridge 172:65be27845400 53 */
AnnaBridge 172:65be27845400 54
AnnaBridge 172:65be27845400 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 56 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 172:65be27845400 57 * @{
AnnaBridge 172:65be27845400 58 */
AnnaBridge 172:65be27845400 59
AnnaBridge 172:65be27845400 60 /**
AnnaBridge 172:65be27845400 61 * @brief DMA Configuration Structure definition
AnnaBridge 172:65be27845400 62 */
AnnaBridge 172:65be27845400 63 typedef struct
AnnaBridge 172:65be27845400 64 {
AnnaBridge 172:65be27845400 65 uint32_t Request; /*!< Specifies the request selected for the specified channel.
AnnaBridge 172:65be27845400 66 This parameter can be a value of @ref DMA_request */
AnnaBridge 172:65be27845400 67
AnnaBridge 172:65be27845400 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 172:65be27845400 69 from memory to memory or from peripheral to memory.
AnnaBridge 172:65be27845400 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 172:65be27845400 71
AnnaBridge 172:65be27845400 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 172:65be27845400 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 172:65be27845400 74
AnnaBridge 172:65be27845400 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 172:65be27845400 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 172:65be27845400 77
AnnaBridge 172:65be27845400 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 172:65be27845400 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 172:65be27845400 80
AnnaBridge 172:65be27845400 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 172:65be27845400 82 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 172:65be27845400 83
AnnaBridge 172:65be27845400 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
AnnaBridge 172:65be27845400 85 This parameter can be a value of @ref DMA_mode
AnnaBridge 172:65be27845400 86 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 172:65be27845400 87 data transfer is configured on the selected Channel */
AnnaBridge 172:65be27845400 88
AnnaBridge 172:65be27845400 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
AnnaBridge 172:65be27845400 90 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 172:65be27845400 91 } DMA_InitTypeDef;
AnnaBridge 172:65be27845400 92
AnnaBridge 172:65be27845400 93 /**
AnnaBridge 172:65be27845400 94 * @brief HAL DMA State structures definition
AnnaBridge 172:65be27845400 95 */
AnnaBridge 172:65be27845400 96 typedef enum
AnnaBridge 172:65be27845400 97 {
AnnaBridge 172:65be27845400 98 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
AnnaBridge 172:65be27845400 99 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
AnnaBridge 172:65be27845400 100 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
AnnaBridge 172:65be27845400 101 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
AnnaBridge 172:65be27845400 102 }HAL_DMA_StateTypeDef;
AnnaBridge 172:65be27845400 103
AnnaBridge 172:65be27845400 104 /**
AnnaBridge 172:65be27845400 105 * @brief HAL DMA Error Code structure definition
AnnaBridge 172:65be27845400 106 */
AnnaBridge 172:65be27845400 107 typedef enum
AnnaBridge 172:65be27845400 108 {
AnnaBridge 172:65be27845400 109 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
AnnaBridge 172:65be27845400 110 HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
AnnaBridge 172:65be27845400 111 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 172:65be27845400 112
AnnaBridge 172:65be27845400 113
AnnaBridge 172:65be27845400 114 /**
AnnaBridge 172:65be27845400 115 * @brief HAL DMA Callback ID structure definition
AnnaBridge 172:65be27845400 116 */
AnnaBridge 172:65be27845400 117 typedef enum
AnnaBridge 172:65be27845400 118 {
AnnaBridge 172:65be27845400 119 HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
AnnaBridge 172:65be27845400 120 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
AnnaBridge 172:65be27845400 121 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
AnnaBridge 172:65be27845400 122 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
AnnaBridge 172:65be27845400 123 HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
AnnaBridge 172:65be27845400 124
AnnaBridge 172:65be27845400 125 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 172:65be27845400 126
AnnaBridge 172:65be27845400 127 /**
AnnaBridge 172:65be27845400 128 * @brief DMA handle Structure definition
AnnaBridge 172:65be27845400 129 */
AnnaBridge 172:65be27845400 130 typedef struct __DMA_HandleTypeDef
AnnaBridge 172:65be27845400 131 {
AnnaBridge 172:65be27845400 132 DMA_Channel_TypeDef *Instance; /*!< Register base address */
AnnaBridge 172:65be27845400 133
AnnaBridge 172:65be27845400 134 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 172:65be27845400 135
AnnaBridge 172:65be27845400 136 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 172:65be27845400 137
AnnaBridge 172:65be27845400 138 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 172:65be27845400 139
AnnaBridge 172:65be27845400 140 void *Parent; /*!< Parent object state */
AnnaBridge 172:65be27845400 141
AnnaBridge 172:65be27845400 142 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 172:65be27845400 143
AnnaBridge 172:65be27845400 144 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 172:65be27845400 145
AnnaBridge 172:65be27845400 146 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 172:65be27845400 147
AnnaBridge 172:65be27845400 148 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
AnnaBridge 172:65be27845400 149
AnnaBridge 172:65be27845400 150 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 172:65be27845400 151
AnnaBridge 172:65be27845400 152 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
AnnaBridge 172:65be27845400 153
AnnaBridge 172:65be27845400 154 uint32_t ChannelIndex; /*!< DMA Channel Index */
AnnaBridge 172:65be27845400 155
AnnaBridge 172:65be27845400 156 #if defined(DMAMUX1)
AnnaBridge 172:65be27845400 157 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
AnnaBridge 172:65be27845400 158
AnnaBridge 172:65be27845400 159 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
AnnaBridge 172:65be27845400 160
AnnaBridge 172:65be27845400 161 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
AnnaBridge 172:65be27845400 162
AnnaBridge 172:65be27845400 163 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
AnnaBridge 172:65be27845400 164
AnnaBridge 172:65be27845400 165 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
AnnaBridge 172:65be27845400 166
AnnaBridge 172:65be27845400 167 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
AnnaBridge 172:65be27845400 168
AnnaBridge 172:65be27845400 169 #endif /* DMAMUX1 */
AnnaBridge 172:65be27845400 170
AnnaBridge 172:65be27845400 171 }DMA_HandleTypeDef;
AnnaBridge 172:65be27845400 172 /**
AnnaBridge 172:65be27845400 173 * @}
AnnaBridge 172:65be27845400 174 */
AnnaBridge 172:65be27845400 175
AnnaBridge 172:65be27845400 176 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 177
AnnaBridge 172:65be27845400 178 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 172:65be27845400 179 * @{
AnnaBridge 172:65be27845400 180 */
AnnaBridge 172:65be27845400 181
AnnaBridge 172:65be27845400 182 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 172:65be27845400 183 * @{
AnnaBridge 172:65be27845400 184 */
AnnaBridge 172:65be27845400 185 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
AnnaBridge 172:65be27845400 186 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
AnnaBridge 172:65be27845400 187 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */
AnnaBridge 172:65be27845400 188 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
AnnaBridge 172:65be27845400 189 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
AnnaBridge 172:65be27845400 190 #define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */
AnnaBridge 172:65be27845400 191 #define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */
AnnaBridge 172:65be27845400 192
AnnaBridge 172:65be27845400 193 /**
AnnaBridge 172:65be27845400 194 * @}
AnnaBridge 172:65be27845400 195 */
AnnaBridge 172:65be27845400 196
AnnaBridge 172:65be27845400 197 /** @defgroup DMA_request DMA request
AnnaBridge 172:65be27845400 198 * @{
AnnaBridge 172:65be27845400 199 */
AnnaBridge 172:65be27845400 200 #if !defined (DMAMUX1)
AnnaBridge 172:65be27845400 201
AnnaBridge 172:65be27845400 202 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
AnnaBridge 172:65be27845400 203 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
AnnaBridge 172:65be27845400 204 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
AnnaBridge 172:65be27845400 205 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
AnnaBridge 172:65be27845400 206 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
AnnaBridge 172:65be27845400 207 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
AnnaBridge 172:65be27845400 208 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
AnnaBridge 172:65be27845400 209 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
AnnaBridge 172:65be27845400 210
AnnaBridge 172:65be27845400 211 #endif
AnnaBridge 172:65be27845400 212
AnnaBridge 172:65be27845400 213 #if defined(DMAMUX1)
AnnaBridge 172:65be27845400 214
AnnaBridge 172:65be27845400 215 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
AnnaBridge 172:65be27845400 216
AnnaBridge 172:65be27845400 217 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
AnnaBridge 172:65be27845400 218 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
AnnaBridge 172:65be27845400 219 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
AnnaBridge 172:65be27845400 220 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
AnnaBridge 172:65be27845400 221
AnnaBridge 172:65be27845400 222 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */
AnnaBridge 172:65be27845400 223
AnnaBridge 172:65be27845400 224 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */
AnnaBridge 172:65be27845400 225 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */
AnnaBridge 172:65be27845400 226
AnnaBridge 172:65be27845400 227 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */
AnnaBridge 172:65be27845400 228 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */
AnnaBridge 172:65be27845400 229
AnnaBridge 172:65be27845400 230 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */
AnnaBridge 172:65be27845400 231 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */
AnnaBridge 172:65be27845400 232 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */
AnnaBridge 172:65be27845400 233 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */
AnnaBridge 172:65be27845400 234 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */
AnnaBridge 172:65be27845400 235 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */
AnnaBridge 172:65be27845400 236
AnnaBridge 172:65be27845400 237 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */
AnnaBridge 172:65be27845400 238 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */
AnnaBridge 172:65be27845400 239 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */
AnnaBridge 172:65be27845400 240 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */
AnnaBridge 172:65be27845400 241 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */
AnnaBridge 172:65be27845400 242 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */
AnnaBridge 172:65be27845400 243 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */
AnnaBridge 172:65be27845400 244 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */
AnnaBridge 172:65be27845400 245
AnnaBridge 172:65be27845400 246 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */
AnnaBridge 172:65be27845400 247 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */
AnnaBridge 172:65be27845400 248 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */
AnnaBridge 172:65be27845400 249 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */
AnnaBridge 172:65be27845400 250 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */
AnnaBridge 172:65be27845400 251 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */
AnnaBridge 172:65be27845400 252
AnnaBridge 172:65be27845400 253 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */
AnnaBridge 172:65be27845400 254 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */
AnnaBridge 172:65be27845400 255 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */
AnnaBridge 172:65be27845400 256 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */
AnnaBridge 172:65be27845400 257
AnnaBridge 172:65be27845400 258 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */
AnnaBridge 172:65be27845400 259 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */
AnnaBridge 172:65be27845400 260
AnnaBridge 172:65be27845400 261 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */
AnnaBridge 172:65be27845400 262 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */
AnnaBridge 172:65be27845400 263 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */
AnnaBridge 172:65be27845400 264 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */
AnnaBridge 172:65be27845400 265
AnnaBridge 172:65be27845400 266 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */
AnnaBridge 172:65be27845400 267 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */
AnnaBridge 172:65be27845400 268
AnnaBridge 172:65be27845400 269 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */
AnnaBridge 172:65be27845400 270 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */
AnnaBridge 172:65be27845400 271 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */
AnnaBridge 172:65be27845400 272 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */
AnnaBridge 172:65be27845400 273 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */
AnnaBridge 172:65be27845400 274 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */
AnnaBridge 172:65be27845400 275 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */
AnnaBridge 172:65be27845400 276
AnnaBridge 172:65be27845400 277 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */
AnnaBridge 172:65be27845400 278 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */
AnnaBridge 172:65be27845400 279 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */
AnnaBridge 172:65be27845400 280 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */
AnnaBridge 172:65be27845400 281 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */
AnnaBridge 172:65be27845400 282 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */
AnnaBridge 172:65be27845400 283 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */
AnnaBridge 172:65be27845400 284
AnnaBridge 172:65be27845400 285 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */
AnnaBridge 172:65be27845400 286 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */
AnnaBridge 172:65be27845400 287 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */
AnnaBridge 172:65be27845400 288 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */
AnnaBridge 172:65be27845400 289 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */
AnnaBridge 172:65be27845400 290
AnnaBridge 172:65be27845400 291 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */
AnnaBridge 172:65be27845400 292 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */
AnnaBridge 172:65be27845400 293 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */
AnnaBridge 172:65be27845400 294 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */
AnnaBridge 172:65be27845400 295 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */
AnnaBridge 172:65be27845400 296 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */
AnnaBridge 172:65be27845400 297
AnnaBridge 172:65be27845400 298 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */
AnnaBridge 172:65be27845400 299 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */
AnnaBridge 172:65be27845400 300 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */
AnnaBridge 172:65be27845400 301 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */
AnnaBridge 172:65be27845400 302 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */
AnnaBridge 172:65be27845400 303
AnnaBridge 172:65be27845400 304 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */
AnnaBridge 172:65be27845400 305 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */
AnnaBridge 172:65be27845400 306 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */
AnnaBridge 172:65be27845400 307 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */
AnnaBridge 172:65be27845400 308 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */
AnnaBridge 172:65be27845400 309 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */
AnnaBridge 172:65be27845400 310
AnnaBridge 172:65be27845400 311 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */
AnnaBridge 172:65be27845400 312 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */
AnnaBridge 172:65be27845400 313 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */
AnnaBridge 172:65be27845400 314 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */
AnnaBridge 172:65be27845400 315
AnnaBridge 172:65be27845400 316 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */
AnnaBridge 172:65be27845400 317 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */
AnnaBridge 172:65be27845400 318 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */
AnnaBridge 172:65be27845400 319 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */
AnnaBridge 172:65be27845400 320
AnnaBridge 172:65be27845400 321 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */
AnnaBridge 172:65be27845400 322 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */
AnnaBridge 172:65be27845400 323 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */
AnnaBridge 172:65be27845400 324 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */
AnnaBridge 172:65be27845400 325
AnnaBridge 172:65be27845400 326 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */
AnnaBridge 172:65be27845400 327
AnnaBridge 172:65be27845400 328 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */
AnnaBridge 172:65be27845400 329 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */
AnnaBridge 172:65be27845400 330
AnnaBridge 172:65be27845400 331 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */
AnnaBridge 172:65be27845400 332
AnnaBridge 172:65be27845400 333 #endif /* DMAMUX1 */
AnnaBridge 172:65be27845400 334
AnnaBridge 172:65be27845400 335 /**
AnnaBridge 172:65be27845400 336 * @}
AnnaBridge 172:65be27845400 337 */
AnnaBridge 172:65be27845400 338
AnnaBridge 172:65be27845400 339 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 172:65be27845400 340 * @{
AnnaBridge 172:65be27845400 341 */
AnnaBridge 172:65be27845400 342 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
AnnaBridge 172:65be27845400 343 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
AnnaBridge 172:65be27845400 344 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
AnnaBridge 172:65be27845400 345 /**
AnnaBridge 172:65be27845400 346 * @}
AnnaBridge 172:65be27845400 347 */
AnnaBridge 172:65be27845400 348
AnnaBridge 172:65be27845400 349 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 172:65be27845400 350 * @{
AnnaBridge 172:65be27845400 351 */
AnnaBridge 172:65be27845400 352 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
AnnaBridge 172:65be27845400 353 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
AnnaBridge 172:65be27845400 354 /**
AnnaBridge 172:65be27845400 355 * @}
AnnaBridge 172:65be27845400 356 */
AnnaBridge 172:65be27845400 357
AnnaBridge 172:65be27845400 358 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 172:65be27845400 359 * @{
AnnaBridge 172:65be27845400 360 */
AnnaBridge 172:65be27845400 361 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
AnnaBridge 172:65be27845400 362 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
AnnaBridge 172:65be27845400 363 /**
AnnaBridge 172:65be27845400 364 * @}
AnnaBridge 172:65be27845400 365 */
AnnaBridge 172:65be27845400 366
AnnaBridge 172:65be27845400 367 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 172:65be27845400 368 * @{
AnnaBridge 172:65be27845400 369 */
AnnaBridge 172:65be27845400 370 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
AnnaBridge 172:65be27845400 371 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
AnnaBridge 172:65be27845400 372 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
AnnaBridge 172:65be27845400 373 /**
AnnaBridge 172:65be27845400 374 * @}
AnnaBridge 172:65be27845400 375 */
AnnaBridge 172:65be27845400 376
AnnaBridge 172:65be27845400 377 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 172:65be27845400 378 * @{
AnnaBridge 172:65be27845400 379 */
AnnaBridge 172:65be27845400 380 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
AnnaBridge 172:65be27845400 381 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
AnnaBridge 172:65be27845400 382 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
AnnaBridge 172:65be27845400 383 /**
AnnaBridge 172:65be27845400 384 * @}
AnnaBridge 172:65be27845400 385 */
AnnaBridge 172:65be27845400 386
AnnaBridge 172:65be27845400 387 /** @defgroup DMA_mode DMA mode
AnnaBridge 172:65be27845400 388 * @{
AnnaBridge 172:65be27845400 389 */
AnnaBridge 172:65be27845400 390 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
AnnaBridge 172:65be27845400 391 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
AnnaBridge 172:65be27845400 392 /**
AnnaBridge 172:65be27845400 393 * @}
AnnaBridge 172:65be27845400 394 */
AnnaBridge 172:65be27845400 395
AnnaBridge 172:65be27845400 396 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 172:65be27845400 397 * @{
AnnaBridge 172:65be27845400 398 */
AnnaBridge 172:65be27845400 399 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
AnnaBridge 172:65be27845400 400 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
AnnaBridge 172:65be27845400 401 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
AnnaBridge 172:65be27845400 402 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
AnnaBridge 172:65be27845400 403 /**
AnnaBridge 172:65be27845400 404 * @}
AnnaBridge 172:65be27845400 405 */
AnnaBridge 172:65be27845400 406
AnnaBridge 172:65be27845400 407
AnnaBridge 172:65be27845400 408 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 172:65be27845400 409 * @{
AnnaBridge 172:65be27845400 410 */
AnnaBridge 172:65be27845400 411 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
AnnaBridge 172:65be27845400 412 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
AnnaBridge 172:65be27845400 413 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
AnnaBridge 172:65be27845400 414 /**
AnnaBridge 172:65be27845400 415 * @}
AnnaBridge 172:65be27845400 416 */
AnnaBridge 172:65be27845400 417
AnnaBridge 172:65be27845400 418 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 172:65be27845400 419 * @{
AnnaBridge 172:65be27845400 420 */
AnnaBridge 172:65be27845400 421 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
AnnaBridge 172:65be27845400 422 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
AnnaBridge 172:65be27845400 423 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
AnnaBridge 172:65be27845400 424 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
AnnaBridge 172:65be27845400 425 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
AnnaBridge 172:65be27845400 426 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
AnnaBridge 172:65be27845400 427 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
AnnaBridge 172:65be27845400 428 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
AnnaBridge 172:65be27845400 429 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
AnnaBridge 172:65be27845400 430 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
AnnaBridge 172:65be27845400 431 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
AnnaBridge 172:65be27845400 432 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
AnnaBridge 172:65be27845400 433 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
AnnaBridge 172:65be27845400 434 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
AnnaBridge 172:65be27845400 435 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
AnnaBridge 172:65be27845400 436 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
AnnaBridge 172:65be27845400 437 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
AnnaBridge 172:65be27845400 438 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
AnnaBridge 172:65be27845400 439 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
AnnaBridge 172:65be27845400 440 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
AnnaBridge 172:65be27845400 441 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
AnnaBridge 172:65be27845400 442 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
AnnaBridge 172:65be27845400 443 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
AnnaBridge 172:65be27845400 444 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
AnnaBridge 172:65be27845400 445 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
AnnaBridge 172:65be27845400 446 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
AnnaBridge 172:65be27845400 447 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
AnnaBridge 172:65be27845400 448 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
AnnaBridge 172:65be27845400 449 /**
AnnaBridge 172:65be27845400 450 * @}
AnnaBridge 172:65be27845400 451 */
AnnaBridge 172:65be27845400 452
AnnaBridge 172:65be27845400 453 /**
AnnaBridge 172:65be27845400 454 * @}
AnnaBridge 172:65be27845400 455 */
AnnaBridge 172:65be27845400 456
AnnaBridge 172:65be27845400 457 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 172:65be27845400 458 /** @defgroup DMA_Exported_Macros DMA Exported Macros
AnnaBridge 172:65be27845400 459 * @{
AnnaBridge 172:65be27845400 460 */
AnnaBridge 172:65be27845400 461
AnnaBridge 172:65be27845400 462 /** @brief Reset DMA handle state.
AnnaBridge 172:65be27845400 463 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 464 * @retval None
AnnaBridge 172:65be27845400 465 */
AnnaBridge 172:65be27845400 466 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 172:65be27845400 467
AnnaBridge 172:65be27845400 468 /**
AnnaBridge 172:65be27845400 469 * @brief Enable the specified DMA Channel.
AnnaBridge 172:65be27845400 470 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 471 * @retval None
AnnaBridge 172:65be27845400 472 */
AnnaBridge 172:65be27845400 473 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
AnnaBridge 172:65be27845400 474
AnnaBridge 172:65be27845400 475 /**
AnnaBridge 172:65be27845400 476 * @brief Disable the specified DMA Channel.
AnnaBridge 172:65be27845400 477 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 478 * @retval None
AnnaBridge 172:65be27845400 479 */
AnnaBridge 172:65be27845400 480 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
AnnaBridge 172:65be27845400 481
AnnaBridge 172:65be27845400 482
AnnaBridge 172:65be27845400 483 /* Interrupt & Flag management */
AnnaBridge 172:65be27845400 484
AnnaBridge 172:65be27845400 485 /**
AnnaBridge 172:65be27845400 486 * @brief Return the current DMA Channel transfer complete flag.
AnnaBridge 172:65be27845400 487 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 488 * @retval The specified transfer complete flag index.
AnnaBridge 172:65be27845400 489 */
AnnaBridge 172:65be27845400 490
AnnaBridge 172:65be27845400 491 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 172:65be27845400 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 172:65be27845400 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 172:65be27845400 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 172:65be27845400 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 172:65be27845400 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 172:65be27845400 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 172:65be27845400 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 172:65be27845400 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 172:65be27845400 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 172:65be27845400 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 172:65be27845400 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
AnnaBridge 172:65be27845400 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
AnnaBridge 172:65be27845400 504 DMA_FLAG_TC7)
AnnaBridge 172:65be27845400 505
AnnaBridge 172:65be27845400 506 /**
AnnaBridge 172:65be27845400 507 * @brief Return the current DMA Channel half transfer complete flag.
AnnaBridge 172:65be27845400 508 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 509 * @retval The specified half transfer complete flag index.
AnnaBridge 172:65be27845400 510 */
AnnaBridge 172:65be27845400 511 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 512 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 172:65be27845400 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 172:65be27845400 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 172:65be27845400 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 172:65be27845400 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 172:65be27845400 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 172:65be27845400 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 172:65be27845400 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 172:65be27845400 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 172:65be27845400 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 172:65be27845400 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
AnnaBridge 172:65be27845400 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
AnnaBridge 172:65be27845400 524 DMA_FLAG_HT7)
AnnaBridge 172:65be27845400 525
AnnaBridge 172:65be27845400 526 /**
AnnaBridge 172:65be27845400 527 * @brief Return the current DMA Channel transfer error flag.
AnnaBridge 172:65be27845400 528 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 529 * @retval The specified transfer error flag index.
AnnaBridge 172:65be27845400 530 */
AnnaBridge 172:65be27845400 531 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 532 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 172:65be27845400 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 172:65be27845400 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 172:65be27845400 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 172:65be27845400 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 172:65be27845400 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 172:65be27845400 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 172:65be27845400 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 172:65be27845400 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 172:65be27845400 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 172:65be27845400 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
AnnaBridge 172:65be27845400 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
AnnaBridge 172:65be27845400 544 DMA_FLAG_TE7)
AnnaBridge 172:65be27845400 545
AnnaBridge 172:65be27845400 546 /**
AnnaBridge 172:65be27845400 547 * @brief Return the current DMA Channel Global interrupt flag.
AnnaBridge 172:65be27845400 548 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 549 * @retval The specified transfer error flag index.
AnnaBridge 172:65be27845400 550 */
AnnaBridge 172:65be27845400 551 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 552 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 172:65be27845400 553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 172:65be27845400 554 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 172:65be27845400 555 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 172:65be27845400 556 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 172:65be27845400 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 172:65be27845400 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 172:65be27845400 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 172:65be27845400 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 172:65be27845400 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 172:65be27845400 562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
AnnaBridge 172:65be27845400 563 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
AnnaBridge 172:65be27845400 564 DMA_ISR_GIF7)
AnnaBridge 172:65be27845400 565
AnnaBridge 172:65be27845400 566 /**
AnnaBridge 172:65be27845400 567 * @brief Get the DMA Channel pending flags.
AnnaBridge 172:65be27845400 568 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 569 * @param __FLAG__: Get the specified flag.
AnnaBridge 172:65be27845400 570 * This parameter can be any combination of the following values:
AnnaBridge 172:65be27845400 571 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 172:65be27845400 572 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 172:65be27845400 573 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 172:65be27845400 574 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 172:65be27845400 575 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 172:65be27845400 576 * @retval The state of FLAG (SET or RESET).
AnnaBridge 172:65be27845400 577 */
AnnaBridge 172:65be27845400 578 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
AnnaBridge 172:65be27845400 579 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
AnnaBridge 172:65be27845400 580
AnnaBridge 172:65be27845400 581 /**
AnnaBridge 172:65be27845400 582 * @brief Clear the DMA Channel pending flags.
AnnaBridge 172:65be27845400 583 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 584 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 172:65be27845400 585 * This parameter can be any combination of the following values:
AnnaBridge 172:65be27845400 586 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 172:65be27845400 587 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 172:65be27845400 588 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 172:65be27845400 589 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 172:65be27845400 590 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 172:65be27845400 591 * @retval None
AnnaBridge 172:65be27845400 592 */
AnnaBridge 172:65be27845400 593 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
AnnaBridge 172:65be27845400 594 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
AnnaBridge 172:65be27845400 595
AnnaBridge 172:65be27845400 596 /**
AnnaBridge 172:65be27845400 597 * @brief Enable the specified DMA Channel interrupts.
AnnaBridge 172:65be27845400 598 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 599 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 172:65be27845400 600 * This parameter can be any combination of the following values:
AnnaBridge 172:65be27845400 601 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 172:65be27845400 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 172:65be27845400 603 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 172:65be27845400 604 * @retval None
AnnaBridge 172:65be27845400 605 */
AnnaBridge 172:65be27845400 606 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
AnnaBridge 172:65be27845400 607
AnnaBridge 172:65be27845400 608 /**
AnnaBridge 172:65be27845400 609 * @brief Disable the specified DMA Channel interrupts.
AnnaBridge 172:65be27845400 610 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 611 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 172:65be27845400 612 * This parameter can be any combination of the following values:
AnnaBridge 172:65be27845400 613 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 172:65be27845400 614 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 172:65be27845400 615 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 172:65be27845400 616 * @retval None
AnnaBridge 172:65be27845400 617 */
AnnaBridge 172:65be27845400 618 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
AnnaBridge 172:65be27845400 619
AnnaBridge 172:65be27845400 620 /**
AnnaBridge 172:65be27845400 621 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
AnnaBridge 172:65be27845400 622 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 623 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
AnnaBridge 172:65be27845400 624 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 625 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 172:65be27845400 626 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 172:65be27845400 627 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 172:65be27845400 628 * @retval The state of DMA_IT (SET or RESET).
AnnaBridge 172:65be27845400 629 */
AnnaBridge 172:65be27845400 630 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
AnnaBridge 172:65be27845400 631
AnnaBridge 172:65be27845400 632 /**
AnnaBridge 172:65be27845400 633 * @brief Return the number of remaining data units in the current DMA Channel transfer.
AnnaBridge 172:65be27845400 634 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 635 * @retval The number of remaining data units in the current DMA Channel transfer.
AnnaBridge 172:65be27845400 636 */
AnnaBridge 172:65be27845400 637 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
AnnaBridge 172:65be27845400 638
AnnaBridge 172:65be27845400 639 /**
AnnaBridge 172:65be27845400 640 * @}
AnnaBridge 172:65be27845400 641 */
AnnaBridge 172:65be27845400 642
AnnaBridge 172:65be27845400 643 #if defined(DMAMUX1)
AnnaBridge 172:65be27845400 644 /* Include DMA HAL Extension module */
AnnaBridge 172:65be27845400 645 #include "stm32l4xx_hal_dma_ex.h"
AnnaBridge 172:65be27845400 646 #endif /* DMAMUX1 */
AnnaBridge 172:65be27845400 647
AnnaBridge 172:65be27845400 648 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 649
AnnaBridge 172:65be27845400 650 /** @addtogroup DMA_Exported_Functions
AnnaBridge 172:65be27845400 651 * @{
AnnaBridge 172:65be27845400 652 */
AnnaBridge 172:65be27845400 653
AnnaBridge 172:65be27845400 654 /** @addtogroup DMA_Exported_Functions_Group1
AnnaBridge 172:65be27845400 655 * @{
AnnaBridge 172:65be27845400 656 */
AnnaBridge 172:65be27845400 657 /* Initialization and de-initialization functions *****************************/
AnnaBridge 172:65be27845400 658 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 659 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 660 /**
AnnaBridge 172:65be27845400 661 * @}
AnnaBridge 172:65be27845400 662 */
AnnaBridge 172:65be27845400 663
AnnaBridge 172:65be27845400 664 /** @addtogroup DMA_Exported_Functions_Group2
AnnaBridge 172:65be27845400 665 * @{
AnnaBridge 172:65be27845400 666 */
AnnaBridge 172:65be27845400 667 /* IO operation functions *****************************************************/
AnnaBridge 172:65be27845400 668 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 172:65be27845400 669 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 172:65be27845400 670 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 671 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 672 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
AnnaBridge 172:65be27845400 673 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 674 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
AnnaBridge 172:65be27845400 675 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 172:65be27845400 676
AnnaBridge 172:65be27845400 677 /**
AnnaBridge 172:65be27845400 678 * @}
AnnaBridge 172:65be27845400 679 */
AnnaBridge 172:65be27845400 680
AnnaBridge 172:65be27845400 681 /** @addtogroup DMA_Exported_Functions_Group3
AnnaBridge 172:65be27845400 682 * @{
AnnaBridge 172:65be27845400 683 */
AnnaBridge 172:65be27845400 684 /* Peripheral State and Error functions ***************************************/
AnnaBridge 172:65be27845400 685 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 686 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 687 /**
AnnaBridge 172:65be27845400 688 * @}
AnnaBridge 172:65be27845400 689 */
AnnaBridge 172:65be27845400 690
AnnaBridge 172:65be27845400 691 /**
AnnaBridge 172:65be27845400 692 * @}
AnnaBridge 172:65be27845400 693 */
AnnaBridge 172:65be27845400 694
AnnaBridge 172:65be27845400 695 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 696 /** @defgroup DMA_Private_Macros DMA Private Macros
AnnaBridge 172:65be27845400 697 * @{
AnnaBridge 172:65be27845400 698 */
AnnaBridge 172:65be27845400 699
AnnaBridge 172:65be27845400 700 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 172:65be27845400 701 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 172:65be27845400 702 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 172:65be27845400 703
AnnaBridge 172:65be27845400 704 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
AnnaBridge 172:65be27845400 705
AnnaBridge 172:65be27845400 706 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 172:65be27845400 707 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 172:65be27845400 708
AnnaBridge 172:65be27845400 709 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 172:65be27845400 710 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 172:65be27845400 711
AnnaBridge 172:65be27845400 712 #if !defined (DMAMUX1)
AnnaBridge 172:65be27845400 713
AnnaBridge 172:65be27845400 714 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
AnnaBridge 172:65be27845400 715 ((REQUEST) == DMA_REQUEST_1) || \
AnnaBridge 172:65be27845400 716 ((REQUEST) == DMA_REQUEST_2) || \
AnnaBridge 172:65be27845400 717 ((REQUEST) == DMA_REQUEST_3) || \
AnnaBridge 172:65be27845400 718 ((REQUEST) == DMA_REQUEST_4) || \
AnnaBridge 172:65be27845400 719 ((REQUEST) == DMA_REQUEST_5) || \
AnnaBridge 172:65be27845400 720 ((REQUEST) == DMA_REQUEST_6) || \
AnnaBridge 172:65be27845400 721 ((REQUEST) == DMA_REQUEST_7))
AnnaBridge 172:65be27845400 722 #endif
AnnaBridge 172:65be27845400 723
AnnaBridge 172:65be27845400 724 #if defined(DMAMUX1)
AnnaBridge 172:65be27845400 725
AnnaBridge 172:65be27845400 726 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)
AnnaBridge 172:65be27845400 727
AnnaBridge 172:65be27845400 728 #endif /* DMAMUX1 */
AnnaBridge 172:65be27845400 729
AnnaBridge 172:65be27845400 730 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 172:65be27845400 731 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 172:65be27845400 732 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 172:65be27845400 733
AnnaBridge 172:65be27845400 734 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 172:65be27845400 735 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 172:65be27845400 736 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 172:65be27845400 737
AnnaBridge 172:65be27845400 738 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 172:65be27845400 739 ((MODE) == DMA_CIRCULAR))
AnnaBridge 172:65be27845400 740
AnnaBridge 172:65be27845400 741 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 172:65be27845400 742 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 172:65be27845400 743 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 172:65be27845400 744 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 172:65be27845400 745
AnnaBridge 172:65be27845400 746 /**
AnnaBridge 172:65be27845400 747 * @}
AnnaBridge 172:65be27845400 748 */
AnnaBridge 172:65be27845400 749
AnnaBridge 172:65be27845400 750 /* Private functions ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 751
AnnaBridge 172:65be27845400 752 /**
AnnaBridge 172:65be27845400 753 * @}
AnnaBridge 172:65be27845400 754 */
AnnaBridge 172:65be27845400 755
AnnaBridge 172:65be27845400 756 /**
AnnaBridge 172:65be27845400 757 * @}
AnnaBridge 172:65be27845400 758 */
AnnaBridge 172:65be27845400 759
AnnaBridge 172:65be27845400 760 #ifdef __cplusplus
AnnaBridge 172:65be27845400 761 }
AnnaBridge 172:65be27845400 762 #endif
AnnaBridge 172:65be27845400 763
AnnaBridge 172:65be27845400 764 #endif /* __STM32L4xx_HAL_DMA_H */
AnnaBridge 172:65be27845400 765
AnnaBridge 172:65be27845400 766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/