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TARGET_NUCLEO_L432KC/TOOLCHAIN_GCC_ARM/stm32l432xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l432xx.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * This file contains:
AnnaBridge 171:3a7713b1edbc 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 171:3a7713b1edbc 9 * - Peripheral's registers declarations and bits definition
AnnaBridge 171:3a7713b1edbc 10 * - Macros to access peripheral’s registers hardware
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 13 * @attention
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 18 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 20 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 23 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 25 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 26 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 38 *
AnnaBridge 171:3a7713b1edbc 39 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 40 */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /** @addtogroup CMSIS_Device
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /** @addtogroup stm32l432xx
AnnaBridge 171:3a7713b1edbc 47 * @{
AnnaBridge 171:3a7713b1edbc 48 */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 #ifndef __STM32L432xx_H
AnnaBridge 171:3a7713b1edbc 51 #define __STM32L432xx_H
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 54 extern "C" {
AnnaBridge 171:3a7713b1edbc 55 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
AnnaBridge 171:3a7713b1edbc 65 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
AnnaBridge 171:3a7713b1edbc 66 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
AnnaBridge 171:3a7713b1edbc 67 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 68 #define __FPU_PRESENT 1 /*!< FPU present */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 /**
AnnaBridge 171:3a7713b1edbc 71 * @}
AnnaBridge 171:3a7713b1edbc 72 */
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 171:3a7713b1edbc 75 * @{
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /**
AnnaBridge 171:3a7713b1edbc 79 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
AnnaBridge 171:3a7713b1edbc 80 * in @ref Library_configuration_section
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82 typedef enum
AnnaBridge 171:3a7713b1edbc 83 {
AnnaBridge 171:3a7713b1edbc 84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 171:3a7713b1edbc 85 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 86 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 88 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 89 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 90 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 92 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 93 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 94 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 171:3a7713b1edbc 95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 171:3a7713b1edbc 96 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
AnnaBridge 171:3a7713b1edbc 97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 171:3a7713b1edbc 98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 171:3a7713b1edbc 99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 171:3a7713b1edbc 100 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 171:3a7713b1edbc 101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 171:3a7713b1edbc 102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 171:3a7713b1edbc 103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 171:3a7713b1edbc 104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 171:3a7713b1edbc 105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 171:3a7713b1edbc 106 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 107 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 108 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 109 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 110 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 111 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
AnnaBridge 171:3a7713b1edbc 112 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
AnnaBridge 171:3a7713b1edbc 113 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
AnnaBridge 171:3a7713b1edbc 116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
AnnaBridge 171:3a7713b1edbc 117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
AnnaBridge 171:3a7713b1edbc 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 171:3a7713b1edbc 119 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
AnnaBridge 171:3a7713b1edbc 120 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
AnnaBridge 171:3a7713b1edbc 121 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
AnnaBridge 171:3a7713b1edbc 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 171:3a7713b1edbc 123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 126 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 127 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 128 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 129 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 171:3a7713b1edbc 130 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 131 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 132 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 171:3a7713b1edbc 133 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 171:3a7713b1edbc 134 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 135 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 136 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 137 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 138 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 139 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
AnnaBridge 171:3a7713b1edbc 140 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
AnnaBridge 171:3a7713b1edbc 141 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
AnnaBridge 171:3a7713b1edbc 142 USB_IRQn = 67, /*!< USB event Interrupt */
AnnaBridge 171:3a7713b1edbc 143 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
AnnaBridge 171:3a7713b1edbc 144 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
AnnaBridge 171:3a7713b1edbc 145 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
AnnaBridge 171:3a7713b1edbc 146 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
AnnaBridge 171:3a7713b1edbc 147 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 171:3a7713b1edbc 148 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 171:3a7713b1edbc 149 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
AnnaBridge 171:3a7713b1edbc 150 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
AnnaBridge 171:3a7713b1edbc 151 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
AnnaBridge 171:3a7713b1edbc 152 RNG_IRQn = 80, /*!< RNG global interrupt */
AnnaBridge 171:3a7713b1edbc 153 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 171:3a7713b1edbc 154 CRS_IRQn = 82 /*!< CRS global interrupt */
AnnaBridge 171:3a7713b1edbc 155 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /**
AnnaBridge 171:3a7713b1edbc 158 * @}
AnnaBridge 171:3a7713b1edbc 159 */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 162 #include "system_stm32l4xx.h"
AnnaBridge 171:3a7713b1edbc 163 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /** @addtogroup Peripheral_registers_structures
AnnaBridge 171:3a7713b1edbc 166 * @{
AnnaBridge 171:3a7713b1edbc 167 */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /**
AnnaBridge 171:3a7713b1edbc 170 * @brief Analog to Digital Converter
AnnaBridge 171:3a7713b1edbc 171 */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 typedef struct
AnnaBridge 171:3a7713b1edbc 174 {
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 182 uint32_t RESERVED1; /*!< Reserved, 0x1C */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 186 uint32_t RESERVED2; /*!< Reserved, 0x2C */
AnnaBridge 171:3a7713b1edbc 187 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 192 uint32_t RESERVED3; /*!< Reserved, 0x44 */
AnnaBridge 171:3a7713b1edbc 193 uint32_t RESERVED4; /*!< Reserved, 0x48 */
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 195 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 197 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 199 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 200 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 205 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
AnnaBridge 171:3a7713b1edbc 206 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 207 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 208 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
AnnaBridge 171:3a7713b1edbc 209 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 } ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 typedef struct
AnnaBridge 171:3a7713b1edbc 216 {
AnnaBridge 171:3a7713b1edbc 217 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
AnnaBridge 171:3a7713b1edbc 218 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
AnnaBridge 171:3a7713b1edbc 220 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
AnnaBridge 171:3a7713b1edbc 221 } ADC_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /**
AnnaBridge 171:3a7713b1edbc 225 * @brief Controller Area Network TxMailBox
AnnaBridge 171:3a7713b1edbc 226 */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 typedef struct
AnnaBridge 171:3a7713b1edbc 229 {
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 171:3a7713b1edbc 231 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 171:3a7713b1edbc 232 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 171:3a7713b1edbc 233 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 171:3a7713b1edbc 234 } CAN_TxMailBox_TypeDef;
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /**
AnnaBridge 171:3a7713b1edbc 237 * @brief Controller Area Network FIFOMailBox
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 typedef struct
AnnaBridge 171:3a7713b1edbc 241 {
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 171:3a7713b1edbc 246 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /**
AnnaBridge 171:3a7713b1edbc 249 * @brief Controller Area Network FilterRegister
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 typedef struct
AnnaBridge 171:3a7713b1edbc 253 {
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 171:3a7713b1edbc 256 } CAN_FilterRegister_TypeDef;
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 /**
AnnaBridge 171:3a7713b1edbc 259 * @brief Controller Area Network
AnnaBridge 171:3a7713b1edbc 260 */
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 typedef struct
AnnaBridge 171:3a7713b1edbc 263 {
AnnaBridge 171:3a7713b1edbc 264 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 265 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 266 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 267 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 268 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 269 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 271 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 272 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 171:3a7713b1edbc 273 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 171:3a7713b1edbc 274 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 171:3a7713b1edbc 275 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 171:3a7713b1edbc 276 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 277 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 171:3a7713b1edbc 278 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 171:3a7713b1edbc 280 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 171:3a7713b1edbc 282 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 171:3a7713b1edbc 283 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 171:3a7713b1edbc 284 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 171:3a7713b1edbc 285 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 171:3a7713b1edbc 286 } CAN_TypeDef;
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /**
AnnaBridge 171:3a7713b1edbc 290 * @brief Comparator
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 typedef struct
AnnaBridge 171:3a7713b1edbc 294 {
AnnaBridge 171:3a7713b1edbc 295 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 296 } COMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 typedef struct
AnnaBridge 171:3a7713b1edbc 299 {
AnnaBridge 171:3a7713b1edbc 300 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 301 } COMP_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /**
AnnaBridge 171:3a7713b1edbc 304 * @brief CRC calculation unit
AnnaBridge 171:3a7713b1edbc 305 */
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 typedef struct
AnnaBridge 171:3a7713b1edbc 308 {
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 310 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 311 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 171:3a7713b1edbc 312 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 314 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 317 } CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /**
AnnaBridge 171:3a7713b1edbc 320 * @brief Clock Recovery System
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322 typedef struct
AnnaBridge 171:3a7713b1edbc 323 {
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 325 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 326 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 327 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 328 } CRS_TypeDef;
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /**
AnnaBridge 171:3a7713b1edbc 331 * @brief Digital to Analog Converter
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 typedef struct
AnnaBridge 171:3a7713b1edbc 335 {
AnnaBridge 171:3a7713b1edbc 336 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 342 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 348 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 349 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 351 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 356 } DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 357
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 /**
AnnaBridge 171:3a7713b1edbc 360 * @brief Debug MCU
AnnaBridge 171:3a7713b1edbc 361 */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 typedef struct
AnnaBridge 171:3a7713b1edbc 364 {
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 366 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 367 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 368 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 369 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 370 } DBGMCU_TypeDef;
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372
AnnaBridge 171:3a7713b1edbc 373 /**
AnnaBridge 171:3a7713b1edbc 374 * @brief DMA Controller
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 typedef struct
AnnaBridge 171:3a7713b1edbc 378 {
AnnaBridge 171:3a7713b1edbc 379 __IO uint32_t CCR; /*!< DMA channel x configuration register */
AnnaBridge 171:3a7713b1edbc 380 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
AnnaBridge 171:3a7713b1edbc 381 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
AnnaBridge 171:3a7713b1edbc 382 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
AnnaBridge 171:3a7713b1edbc 383 } DMA_Channel_TypeDef;
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 typedef struct
AnnaBridge 171:3a7713b1edbc 386 {
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 389 } DMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 typedef struct
AnnaBridge 171:3a7713b1edbc 392 {
AnnaBridge 171:3a7713b1edbc 393 __IO uint32_t CSELR; /*!< DMA channel selection register */
AnnaBridge 171:3a7713b1edbc 394 } DMA_Request_TypeDef;
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 397 #define DMA_request_TypeDef DMA_Request_TypeDef
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /**
AnnaBridge 171:3a7713b1edbc 401 * @brief External Interrupt/Event Controller
AnnaBridge 171:3a7713b1edbc 402 */
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 typedef struct
AnnaBridge 171:3a7713b1edbc 405 {
AnnaBridge 171:3a7713b1edbc 406 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 407 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 409 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 410 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 411 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 412 uint32_t RESERVED1; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 413 uint32_t RESERVED2; /*!< Reserved, 0x1C */
AnnaBridge 171:3a7713b1edbc 414 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 415 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 416 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 417 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 418 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 419 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 420 } EXTI_TypeDef;
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 /**
AnnaBridge 171:3a7713b1edbc 424 * @brief Firewall
AnnaBridge 171:3a7713b1edbc 425 */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 typedef struct
AnnaBridge 171:3a7713b1edbc 428 {
AnnaBridge 171:3a7713b1edbc 429 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 430 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 431 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 432 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 433 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 434 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 435 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 436 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 437 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 438 } FIREWALL_TypeDef;
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440
AnnaBridge 171:3a7713b1edbc 441 /**
AnnaBridge 171:3a7713b1edbc 442 * @brief FLASH Registers
AnnaBridge 171:3a7713b1edbc 443 */
AnnaBridge 171:3a7713b1edbc 444
AnnaBridge 171:3a7713b1edbc 445 typedef struct
AnnaBridge 171:3a7713b1edbc 446 {
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 452 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 460 } FLASH_TypeDef;
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /**
AnnaBridge 171:3a7713b1edbc 465 * @brief General Purpose I/O
AnnaBridge 171:3a7713b1edbc 466 */
AnnaBridge 171:3a7713b1edbc 467
AnnaBridge 171:3a7713b1edbc 468 typedef struct
AnnaBridge 171:3a7713b1edbc 469 {
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 476 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 477 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 478 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 } GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 /**
AnnaBridge 171:3a7713b1edbc 485 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 486 */
AnnaBridge 171:3a7713b1edbc 487
AnnaBridge 171:3a7713b1edbc 488 typedef struct
AnnaBridge 171:3a7713b1edbc 489 {
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 491 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 492 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 493 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 494 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 496 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 499 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 501 } I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 /**
AnnaBridge 171:3a7713b1edbc 504 * @brief Independent WATCHDOG
AnnaBridge 171:3a7713b1edbc 505 */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 typedef struct
AnnaBridge 171:3a7713b1edbc 508 {
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 512 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 513 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 514 } IWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /**
AnnaBridge 171:3a7713b1edbc 517 * @brief LPTIMER
AnnaBridge 171:3a7713b1edbc 518 */
AnnaBridge 171:3a7713b1edbc 519 typedef struct
AnnaBridge 171:3a7713b1edbc 520 {
AnnaBridge 171:3a7713b1edbc 521 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 524 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 525 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 526 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 527 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 528 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 529 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 530 } LPTIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /**
AnnaBridge 171:3a7713b1edbc 533 * @brief Operational Amplifier (OPAMP)
AnnaBridge 171:3a7713b1edbc 534 */
AnnaBridge 171:3a7713b1edbc 535
AnnaBridge 171:3a7713b1edbc 536 typedef struct
AnnaBridge 171:3a7713b1edbc 537 {
AnnaBridge 171:3a7713b1edbc 538 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 539 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 541 } OPAMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 typedef struct
AnnaBridge 171:3a7713b1edbc 544 {
AnnaBridge 171:3a7713b1edbc 545 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 546 } OPAMP_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 /**
AnnaBridge 171:3a7713b1edbc 549 * @brief Power Control
AnnaBridge 171:3a7713b1edbc 550 */
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 typedef struct
AnnaBridge 171:3a7713b1edbc 553 {
AnnaBridge 171:3a7713b1edbc 554 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 555 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 556 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 557 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 558 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 559 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 560 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 561 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 562 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 563 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 564 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 565 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 566 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 572 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 573 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 574 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 575 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 576 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 577 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 578 } PWR_TypeDef;
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 /**
AnnaBridge 171:3a7713b1edbc 582 * @brief QUAD Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 583 */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 typedef struct
AnnaBridge 171:3a7713b1edbc 586 {
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 589 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 590 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 591 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 592 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 593 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 594 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 595 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 596 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 597 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 598 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 599 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 600 } QUADSPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 /**
AnnaBridge 171:3a7713b1edbc 604 * @brief Reset and Clock Control
AnnaBridge 171:3a7713b1edbc 605 */
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 typedef struct
AnnaBridge 171:3a7713b1edbc 608 {
AnnaBridge 171:3a7713b1edbc 609 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 610 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 611 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 612 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 613 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 614 uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 615 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 616 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 617 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 618 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 619 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 620 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 621 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 622 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 623 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 624 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 625 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 626 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 627 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 628 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 629 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 630 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 631 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 632 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 633 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 634 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 635 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 636 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 637 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 638 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 639 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 640 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 641 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 642 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 643 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 644 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 645 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 647 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 648 } RCC_TypeDef;
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /**
AnnaBridge 171:3a7713b1edbc 651 * @brief Real-Time Clock
AnnaBridge 171:3a7713b1edbc 652 */
AnnaBridge 171:3a7713b1edbc 653
AnnaBridge 171:3a7713b1edbc 654 typedef struct
AnnaBridge 171:3a7713b1edbc 655 {
AnnaBridge 171:3a7713b1edbc 656 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 657 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 658 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 659 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 660 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 661 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 662 uint32_t reserved; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 663 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 664 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 665 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 666 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 667 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 668 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 669 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 670 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 671 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 672 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 673 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 674 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 675 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 676 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 677 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 678 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 679 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 680 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 681 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 682 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 683 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 684 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 685 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 686 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 687 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 688 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 689 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 690 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 691 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 692 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 693 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 694 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 695 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 696 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 697 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 698 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 699 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 700 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 701 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 702 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
AnnaBridge 171:3a7713b1edbc 703 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
AnnaBridge 171:3a7713b1edbc 704 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 705 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 706 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 707 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
AnnaBridge 171:3a7713b1edbc 708 } RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 709
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 /**
AnnaBridge 171:3a7713b1edbc 712 * @brief Serial Audio Interface
AnnaBridge 171:3a7713b1edbc 713 */
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 typedef struct
AnnaBridge 171:3a7713b1edbc 716 {
AnnaBridge 171:3a7713b1edbc 717 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 718 } SAI_TypeDef;
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 typedef struct
AnnaBridge 171:3a7713b1edbc 721 {
AnnaBridge 171:3a7713b1edbc 722 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 723 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 724 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 725 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 726 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 727 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 728 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 729 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 730 } SAI_Block_TypeDef;
AnnaBridge 171:3a7713b1edbc 731
AnnaBridge 171:3a7713b1edbc 732
AnnaBridge 171:3a7713b1edbc 733 /**
AnnaBridge 171:3a7713b1edbc 734 * @brief Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 735 */
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737 typedef struct
AnnaBridge 171:3a7713b1edbc 738 {
AnnaBridge 171:3a7713b1edbc 739 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 740 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 741 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 742 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 743 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 744 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 745 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 746 } SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 747
AnnaBridge 171:3a7713b1edbc 748
AnnaBridge 171:3a7713b1edbc 749 /**
AnnaBridge 171:3a7713b1edbc 750 * @brief Single Wire Protocol Master Interface SPWMI
AnnaBridge 171:3a7713b1edbc 751 */
AnnaBridge 171:3a7713b1edbc 752
AnnaBridge 171:3a7713b1edbc 753 typedef struct
AnnaBridge 171:3a7713b1edbc 754 {
AnnaBridge 171:3a7713b1edbc 755 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 756 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 757 uint32_t RESERVED1; /*!< Reserved, 0x08 */
AnnaBridge 171:3a7713b1edbc 758 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 759 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 760 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 761 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 762 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 763 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 764 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 765 } SWPMI_TypeDef;
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767
AnnaBridge 171:3a7713b1edbc 768 /**
AnnaBridge 171:3a7713b1edbc 769 * @brief System configuration controller
AnnaBridge 171:3a7713b1edbc 770 */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 typedef struct
AnnaBridge 171:3a7713b1edbc 773 {
AnnaBridge 171:3a7713b1edbc 774 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 775 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 776 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 171:3a7713b1edbc 777 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 778 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 779 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 780 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 781 } SYSCFG_TypeDef;
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783
AnnaBridge 171:3a7713b1edbc 784 /**
AnnaBridge 171:3a7713b1edbc 785 * @brief TIM
AnnaBridge 171:3a7713b1edbc 786 */
AnnaBridge 171:3a7713b1edbc 787
AnnaBridge 171:3a7713b1edbc 788 typedef struct
AnnaBridge 171:3a7713b1edbc 789 {
AnnaBridge 171:3a7713b1edbc 790 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 791 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 792 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 793 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 794 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 795 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 796 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 797 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 798 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 799 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 800 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 801 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 802 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 803 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 804 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 805 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 806 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 807 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 808 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 809 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 810 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 811 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 812 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 813 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 814 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 815 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 816 } TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818
AnnaBridge 171:3a7713b1edbc 819 /**
AnnaBridge 171:3a7713b1edbc 820 * @brief Touch Sensing Controller (TSC)
AnnaBridge 171:3a7713b1edbc 821 */
AnnaBridge 171:3a7713b1edbc 822
AnnaBridge 171:3a7713b1edbc 823 typedef struct
AnnaBridge 171:3a7713b1edbc 824 {
AnnaBridge 171:3a7713b1edbc 825 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 826 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 827 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 828 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 829 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 830 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 831 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 832 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 833 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 834 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 835 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 836 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 837 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 838 __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
AnnaBridge 171:3a7713b1edbc 839 } TSC_TypeDef;
AnnaBridge 171:3a7713b1edbc 840
AnnaBridge 171:3a7713b1edbc 841 /**
AnnaBridge 171:3a7713b1edbc 842 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 171:3a7713b1edbc 843 */
AnnaBridge 171:3a7713b1edbc 844
AnnaBridge 171:3a7713b1edbc 845 typedef struct
AnnaBridge 171:3a7713b1edbc 846 {
AnnaBridge 171:3a7713b1edbc 847 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 848 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 849 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 850 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 851 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 852 uint16_t RESERVED2; /*!< Reserved, 0x12 */
AnnaBridge 171:3a7713b1edbc 853 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 854 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 855 uint16_t RESERVED3; /*!< Reserved, 0x1A */
AnnaBridge 171:3a7713b1edbc 856 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 857 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 858 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 859 uint16_t RESERVED4; /*!< Reserved, 0x26 */
AnnaBridge 171:3a7713b1edbc 860 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 861 uint16_t RESERVED5; /*!< Reserved, 0x2A */
AnnaBridge 171:3a7713b1edbc 862 } USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 863
AnnaBridge 171:3a7713b1edbc 864 /**
AnnaBridge 171:3a7713b1edbc 865 * @brief Universal Serial Bus Full Speed Device
AnnaBridge 171:3a7713b1edbc 866 */
AnnaBridge 171:3a7713b1edbc 867
AnnaBridge 171:3a7713b1edbc 868 typedef struct
AnnaBridge 171:3a7713b1edbc 869 {
AnnaBridge 171:3a7713b1edbc 870 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 871 __IO uint16_t RESERVED0; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 872 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 873 __IO uint16_t RESERVED1; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 874 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 875 __IO uint16_t RESERVED2; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 876 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 877 __IO uint16_t RESERVED3; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 878 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 879 __IO uint16_t RESERVED4; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 880 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 881 __IO uint16_t RESERVED5; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 882 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 883 __IO uint16_t RESERVED6; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 884 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 885 __IO uint16_t RESERVED7[17]; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 886 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 887 __IO uint16_t RESERVED8; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 888 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 889 __IO uint16_t RESERVED9; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 890 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 891 __IO uint16_t RESERVEDA; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 892 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 893 __IO uint16_t RESERVEDB; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 894 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 895 __IO uint16_t RESERVEDC; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 896 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 897 __IO uint16_t RESERVEDD; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 898 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 899 __IO uint16_t RESERVEDE; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 900 } USB_TypeDef;
AnnaBridge 171:3a7713b1edbc 901
AnnaBridge 171:3a7713b1edbc 902
AnnaBridge 171:3a7713b1edbc 903 /**
AnnaBridge 171:3a7713b1edbc 904 * @brief Window WATCHDOG
AnnaBridge 171:3a7713b1edbc 905 */
AnnaBridge 171:3a7713b1edbc 906
AnnaBridge 171:3a7713b1edbc 907 typedef struct
AnnaBridge 171:3a7713b1edbc 908 {
AnnaBridge 171:3a7713b1edbc 909 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 910 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 911 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 912 } WWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 913
AnnaBridge 171:3a7713b1edbc 914 /**
AnnaBridge 171:3a7713b1edbc 915 * @brief RNG
AnnaBridge 171:3a7713b1edbc 916 */
AnnaBridge 171:3a7713b1edbc 917
AnnaBridge 171:3a7713b1edbc 918 typedef struct
AnnaBridge 171:3a7713b1edbc 919 {
AnnaBridge 171:3a7713b1edbc 920 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 921 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 922 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 923 } RNG_TypeDef;
AnnaBridge 171:3a7713b1edbc 924
AnnaBridge 171:3a7713b1edbc 925 /**
AnnaBridge 171:3a7713b1edbc 926 * @}
AnnaBridge 171:3a7713b1edbc 927 */
AnnaBridge 171:3a7713b1edbc 928
AnnaBridge 171:3a7713b1edbc 929 /** @addtogroup Peripheral_memory_map
AnnaBridge 171:3a7713b1edbc 930 * @{
AnnaBridge 171:3a7713b1edbc 931 */
AnnaBridge 171:3a7713b1edbc 932 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
AnnaBridge 171:3a7713b1edbc 933 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
AnnaBridge 171:3a7713b1edbc 934 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
AnnaBridge 171:3a7713b1edbc 935 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
AnnaBridge 171:3a7713b1edbc 936 #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
AnnaBridge 171:3a7713b1edbc 937
AnnaBridge 171:3a7713b1edbc 938 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
AnnaBridge 171:3a7713b1edbc 939 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 940 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 941
AnnaBridge 171:3a7713b1edbc 942 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 943 #define SRAM_BASE SRAM1_BASE
AnnaBridge 171:3a7713b1edbc 944 #define SRAM_BB_BASE SRAM1_BB_BASE
AnnaBridge 171:3a7713b1edbc 945
AnnaBridge 171:3a7713b1edbc 946 #define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
AnnaBridge 171:3a7713b1edbc 947 #define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
AnnaBridge 171:3a7713b1edbc 948
AnnaBridge 171:3a7713b1edbc 949 /*!< Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 950 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 951 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 171:3a7713b1edbc 952 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 171:3a7713b1edbc 953 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
AnnaBridge 171:3a7713b1edbc 954
AnnaBridge 171:3a7713b1edbc 955
AnnaBridge 171:3a7713b1edbc 956 /*!< APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 957 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 958 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 959 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
AnnaBridge 171:3a7713b1edbc 960 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 171:3a7713b1edbc 961 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 171:3a7713b1edbc 962 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 963 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 171:3a7713b1edbc 964 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 171:3a7713b1edbc 965 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 171:3a7713b1edbc 966 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 171:3a7713b1edbc 967 #define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
AnnaBridge 171:3a7713b1edbc 968 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
AnnaBridge 171:3a7713b1edbc 969 #define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */
AnnaBridge 171:3a7713b1edbc 970 #define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */
AnnaBridge 171:3a7713b1edbc 971 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 171:3a7713b1edbc 972 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 171:3a7713b1edbc 973 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 171:3a7713b1edbc 974 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
AnnaBridge 171:3a7713b1edbc 975 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
AnnaBridge 171:3a7713b1edbc 976 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
AnnaBridge 171:3a7713b1edbc 977 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
AnnaBridge 171:3a7713b1edbc 978 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
AnnaBridge 171:3a7713b1edbc 979 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
AnnaBridge 171:3a7713b1edbc 980
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 /*!< APB2 peripherals */
AnnaBridge 171:3a7713b1edbc 983 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 984 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
AnnaBridge 171:3a7713b1edbc 985 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
AnnaBridge 171:3a7713b1edbc 986 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 987 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
AnnaBridge 171:3a7713b1edbc 988 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 171:3a7713b1edbc 989 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 990 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 991 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 171:3a7713b1edbc 992 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 171:3a7713b1edbc 993 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
AnnaBridge 171:3a7713b1edbc 994 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
AnnaBridge 171:3a7713b1edbc 995 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
AnnaBridge 171:3a7713b1edbc 996
AnnaBridge 171:3a7713b1edbc 997 /*!< AHB1 peripherals */
AnnaBridge 171:3a7713b1edbc 998 #define DMA1_BASE (AHB1PERIPH_BASE)
AnnaBridge 171:3a7713b1edbc 999 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 1000 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 1001 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
AnnaBridge 171:3a7713b1edbc 1002 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 1003 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
AnnaBridge 171:3a7713b1edbc 1004
AnnaBridge 171:3a7713b1edbc 1005
AnnaBridge 171:3a7713b1edbc 1006 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
AnnaBridge 171:3a7713b1edbc 1007 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
AnnaBridge 171:3a7713b1edbc 1008 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
AnnaBridge 171:3a7713b1edbc 1009 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
AnnaBridge 171:3a7713b1edbc 1010 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
AnnaBridge 171:3a7713b1edbc 1011 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
AnnaBridge 171:3a7713b1edbc 1012 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
AnnaBridge 171:3a7713b1edbc 1013 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
AnnaBridge 171:3a7713b1edbc 1014
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
AnnaBridge 171:3a7713b1edbc 1017 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
AnnaBridge 171:3a7713b1edbc 1018 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
AnnaBridge 171:3a7713b1edbc 1019 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
AnnaBridge 171:3a7713b1edbc 1020 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
AnnaBridge 171:3a7713b1edbc 1021 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
AnnaBridge 171:3a7713b1edbc 1022 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
AnnaBridge 171:3a7713b1edbc 1023 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
AnnaBridge 171:3a7713b1edbc 1024
AnnaBridge 171:3a7713b1edbc 1025
AnnaBridge 171:3a7713b1edbc 1026 /*!< AHB2 peripherals */
AnnaBridge 171:3a7713b1edbc 1027 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 1028 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 1029 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
AnnaBridge 171:3a7713b1edbc 1030 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
AnnaBridge 171:3a7713b1edbc 1031
AnnaBridge 171:3a7713b1edbc 1032
AnnaBridge 171:3a7713b1edbc 1033 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
AnnaBridge 171:3a7713b1edbc 1034 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
AnnaBridge 171:3a7713b1edbc 1035
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
AnnaBridge 171:3a7713b1edbc 1038
AnnaBridge 171:3a7713b1edbc 1039
AnnaBridge 171:3a7713b1edbc 1040
AnnaBridge 171:3a7713b1edbc 1041 /* Debug MCU registers base address */
AnnaBridge 171:3a7713b1edbc 1042 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
AnnaBridge 171:3a7713b1edbc 1046 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
AnnaBridge 171:3a7713b1edbc 1047 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
AnnaBridge 171:3a7713b1edbc 1048 /**
AnnaBridge 171:3a7713b1edbc 1049 * @}
AnnaBridge 171:3a7713b1edbc 1050 */
AnnaBridge 171:3a7713b1edbc 1051
AnnaBridge 171:3a7713b1edbc 1052 /** @addtogroup Peripheral_declaration
AnnaBridge 171:3a7713b1edbc 1053 * @{
AnnaBridge 171:3a7713b1edbc 1054 */
AnnaBridge 171:3a7713b1edbc 1055 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 171:3a7713b1edbc 1056 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 171:3a7713b1edbc 1057 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 171:3a7713b1edbc 1058 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 1059 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 171:3a7713b1edbc 1060 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 171:3a7713b1edbc 1061 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 171:3a7713b1edbc 1062 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 171:3a7713b1edbc 1063 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 1064 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 171:3a7713b1edbc 1065 #define CRS ((CRS_TypeDef *) CRS_BASE)
AnnaBridge 171:3a7713b1edbc 1066 //#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API
AnnaBridge 171:3a7713b1edbc 1067 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
AnnaBridge 171:3a7713b1edbc 1068 #define USB ((USB_TypeDef *) USB_BASE)
AnnaBridge 171:3a7713b1edbc 1069 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 171:3a7713b1edbc 1070 #define DAC ((DAC_TypeDef *) DAC1_BASE)
AnnaBridge 171:3a7713b1edbc 1071 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
AnnaBridge 171:3a7713b1edbc 1072 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
AnnaBridge 171:3a7713b1edbc 1073 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
AnnaBridge 171:3a7713b1edbc 1074 #define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
AnnaBridge 171:3a7713b1edbc 1075 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 171:3a7713b1edbc 1076 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
AnnaBridge 171:3a7713b1edbc 1077 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
AnnaBridge 171:3a7713b1edbc 1078 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
AnnaBridge 171:3a7713b1edbc 1079
AnnaBridge 171:3a7713b1edbc 1080 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 171:3a7713b1edbc 1081 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
AnnaBridge 171:3a7713b1edbc 1082 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
AnnaBridge 171:3a7713b1edbc 1083 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
AnnaBridge 171:3a7713b1edbc 1084 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 171:3a7713b1edbc 1085 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
AnnaBridge 171:3a7713b1edbc 1086 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 171:3a7713b1edbc 1087 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 1088 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 171:3a7713b1edbc 1089 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
AnnaBridge 171:3a7713b1edbc 1090 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
AnnaBridge 171:3a7713b1edbc 1091 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
AnnaBridge 171:3a7713b1edbc 1092 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
AnnaBridge 171:3a7713b1edbc 1093 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
AnnaBridge 171:3a7713b1edbc 1094 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 171:3a7713b1edbc 1095 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 171:3a7713b1edbc 1096 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 171:3a7713b1edbc 1097 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 171:3a7713b1edbc 1098 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 1099 #define TSC ((TSC_TypeDef *) TSC_BASE)
AnnaBridge 171:3a7713b1edbc 1100
AnnaBridge 171:3a7713b1edbc 1101 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 1102 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 1103 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 1104 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 171:3a7713b1edbc 1105 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 1106 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
AnnaBridge 171:3a7713b1edbc 1107 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109
AnnaBridge 171:3a7713b1edbc 1110 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
AnnaBridge 171:3a7713b1edbc 1111 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
AnnaBridge 171:3a7713b1edbc 1112 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
AnnaBridge 171:3a7713b1edbc 1113 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
AnnaBridge 171:3a7713b1edbc 1114 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
AnnaBridge 171:3a7713b1edbc 1115 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
AnnaBridge 171:3a7713b1edbc 1116 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
AnnaBridge 171:3a7713b1edbc 1117 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
AnnaBridge 171:3a7713b1edbc 1118
AnnaBridge 171:3a7713b1edbc 1119
AnnaBridge 171:3a7713b1edbc 1120 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
AnnaBridge 171:3a7713b1edbc 1121 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
AnnaBridge 171:3a7713b1edbc 1122 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
AnnaBridge 171:3a7713b1edbc 1123 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
AnnaBridge 171:3a7713b1edbc 1124 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
AnnaBridge 171:3a7713b1edbc 1125 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
AnnaBridge 171:3a7713b1edbc 1126 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
AnnaBridge 171:3a7713b1edbc 1127 #define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
AnnaBridge 171:3a7713b1edbc 1128
AnnaBridge 171:3a7713b1edbc 1129
AnnaBridge 171:3a7713b1edbc 1130
AnnaBridge 171:3a7713b1edbc 1131 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
AnnaBridge 171:3a7713b1edbc 1132
AnnaBridge 171:3a7713b1edbc 1133 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 171:3a7713b1edbc 1134
AnnaBridge 171:3a7713b1edbc 1135 /**
AnnaBridge 171:3a7713b1edbc 1136 * @}
AnnaBridge 171:3a7713b1edbc 1137 */
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 /** @addtogroup Exported_constants
AnnaBridge 171:3a7713b1edbc 1140 * @{
AnnaBridge 171:3a7713b1edbc 1141 */
AnnaBridge 171:3a7713b1edbc 1142
AnnaBridge 171:3a7713b1edbc 1143 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 171:3a7713b1edbc 1144 * @{
AnnaBridge 171:3a7713b1edbc 1145 */
AnnaBridge 171:3a7713b1edbc 1146
AnnaBridge 171:3a7713b1edbc 1147 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1148 /* Peripheral Registers_Bits_Definition */
AnnaBridge 171:3a7713b1edbc 1149 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1150
AnnaBridge 171:3a7713b1edbc 1151 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1152 /* */
AnnaBridge 171:3a7713b1edbc 1153 /* Analog to Digital Converter */
AnnaBridge 171:3a7713b1edbc 1154 /* */
AnnaBridge 171:3a7713b1edbc 1155 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1156
AnnaBridge 171:3a7713b1edbc 1157 /*
AnnaBridge 171:3a7713b1edbc 1158 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
AnnaBridge 171:3a7713b1edbc 1159 */
AnnaBridge 171:3a7713b1edbc 1160 /* Note: No specific macro feature on this device */
AnnaBridge 171:3a7713b1edbc 1161
AnnaBridge 171:3a7713b1edbc 1162 /******************** Bit definition for ADC_ISR register *******************/
AnnaBridge 171:3a7713b1edbc 1163 #define ADC_ISR_ADRDY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1164 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1165 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
AnnaBridge 171:3a7713b1edbc 1166 #define ADC_ISR_EOSMP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1167 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1168 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
AnnaBridge 171:3a7713b1edbc 1169 #define ADC_ISR_EOC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1170 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1171 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 1172 #define ADC_ISR_EOS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1173 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1174 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 1175 #define ADC_ISR_OVR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1176 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1177 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 1178 #define ADC_ISR_JEOC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1179 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1180 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 1181 #define ADC_ISR_JEOS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1182 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1183 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 1184 #define ADC_ISR_AWD1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1185 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1186 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 1187 #define ADC_ISR_AWD2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1188 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1189 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
AnnaBridge 171:3a7713b1edbc 1190 #define ADC_ISR_AWD3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1191 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1192 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
AnnaBridge 171:3a7713b1edbc 1193 #define ADC_ISR_JQOVF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1194 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1195 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
AnnaBridge 171:3a7713b1edbc 1196
AnnaBridge 171:3a7713b1edbc 1197 /******************** Bit definition for ADC_IER register *******************/
AnnaBridge 171:3a7713b1edbc 1198 #define ADC_IER_ADRDYIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1199 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1200 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
AnnaBridge 171:3a7713b1edbc 1201 #define ADC_IER_EOSMPIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1202 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1203 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
AnnaBridge 171:3a7713b1edbc 1204 #define ADC_IER_EOCIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1205 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1206 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
AnnaBridge 171:3a7713b1edbc 1207 #define ADC_IER_EOSIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1208 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1209 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 1210 #define ADC_IER_OVRIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1211 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1212 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
AnnaBridge 171:3a7713b1edbc 1213 #define ADC_IER_JEOCIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1214 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1215 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
AnnaBridge 171:3a7713b1edbc 1216 #define ADC_IER_JEOSIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1217 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1218 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 1219 #define ADC_IER_AWD1IE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1220 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1221 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
AnnaBridge 171:3a7713b1edbc 1222 #define ADC_IER_AWD2IE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1223 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1224 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
AnnaBridge 171:3a7713b1edbc 1225 #define ADC_IER_AWD3IE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1226 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1227 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
AnnaBridge 171:3a7713b1edbc 1228 #define ADC_IER_JQOVFIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1229 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1230 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
AnnaBridge 171:3a7713b1edbc 1231
AnnaBridge 171:3a7713b1edbc 1232 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1233 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
AnnaBridge 171:3a7713b1edbc 1234 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
AnnaBridge 171:3a7713b1edbc 1235 #define ADC_IER_EOC (ADC_IER_EOCIE)
AnnaBridge 171:3a7713b1edbc 1236 #define ADC_IER_EOS (ADC_IER_EOSIE)
AnnaBridge 171:3a7713b1edbc 1237 #define ADC_IER_OVR (ADC_IER_OVRIE)
AnnaBridge 171:3a7713b1edbc 1238 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
AnnaBridge 171:3a7713b1edbc 1239 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
AnnaBridge 171:3a7713b1edbc 1240 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
AnnaBridge 171:3a7713b1edbc 1241 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
AnnaBridge 171:3a7713b1edbc 1242 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
AnnaBridge 171:3a7713b1edbc 1243 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
AnnaBridge 171:3a7713b1edbc 1244
AnnaBridge 171:3a7713b1edbc 1245 /******************** Bit definition for ADC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 1246 #define ADC_CR_ADEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1247 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1248 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
AnnaBridge 171:3a7713b1edbc 1249 #define ADC_CR_ADDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1250 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1251 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
AnnaBridge 171:3a7713b1edbc 1252 #define ADC_CR_ADSTART_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1253 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1254 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
AnnaBridge 171:3a7713b1edbc 1255 #define ADC_CR_JADSTART_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1256 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1257 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
AnnaBridge 171:3a7713b1edbc 1258 #define ADC_CR_ADSTP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1259 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1260 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
AnnaBridge 171:3a7713b1edbc 1261 #define ADC_CR_JADSTP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1262 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1263 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
AnnaBridge 171:3a7713b1edbc 1264 #define ADC_CR_ADVREGEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1265 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1266 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
AnnaBridge 171:3a7713b1edbc 1267 #define ADC_CR_DEEPPWD_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1268 #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1269 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
AnnaBridge 171:3a7713b1edbc 1270 #define ADC_CR_ADCALDIF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1271 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1272 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
AnnaBridge 171:3a7713b1edbc 1273 #define ADC_CR_ADCAL_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1274 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1275 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 /******************** Bit definition for ADC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 1278 #define ADC_CFGR_DMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1279 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1280 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
AnnaBridge 171:3a7713b1edbc 1281 #define ADC_CFGR_DMACFG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1282 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1283 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
AnnaBridge 171:3a7713b1edbc 1284
AnnaBridge 171:3a7713b1edbc 1285 #define ADC_CFGR_RES_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1286 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 1287 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
AnnaBridge 171:3a7713b1edbc 1288 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1289 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1290
AnnaBridge 171:3a7713b1edbc 1291 #define ADC_CFGR_ALIGN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1292 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1293 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
AnnaBridge 171:3a7713b1edbc 1294
AnnaBridge 171:3a7713b1edbc 1295 #define ADC_CFGR_EXTSEL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1296 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
AnnaBridge 171:3a7713b1edbc 1297 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
AnnaBridge 171:3a7713b1edbc 1298 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1299 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1300 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1301 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1302
AnnaBridge 171:3a7713b1edbc 1303 #define ADC_CFGR_EXTEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1304 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 1305 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
AnnaBridge 171:3a7713b1edbc 1306 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1307 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1308
AnnaBridge 171:3a7713b1edbc 1309 #define ADC_CFGR_OVRMOD_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1310 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1311 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
AnnaBridge 171:3a7713b1edbc 1312 #define ADC_CFGR_CONT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1313 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1314 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
AnnaBridge 171:3a7713b1edbc 1315 #define ADC_CFGR_AUTDLY_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1316 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1317 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
AnnaBridge 171:3a7713b1edbc 1318
AnnaBridge 171:3a7713b1edbc 1319 #define ADC_CFGR_DISCEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1320 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1321 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
AnnaBridge 171:3a7713b1edbc 1322
AnnaBridge 171:3a7713b1edbc 1323 #define ADC_CFGR_DISCNUM_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1324 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 1325 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
AnnaBridge 171:3a7713b1edbc 1326 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1327 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1328 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1329
AnnaBridge 171:3a7713b1edbc 1330 #define ADC_CFGR_JDISCEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1331 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1332 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
AnnaBridge 171:3a7713b1edbc 1333 #define ADC_CFGR_JQM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1334 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1335 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
AnnaBridge 171:3a7713b1edbc 1336 #define ADC_CFGR_AWD1SGL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1337 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1338 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
AnnaBridge 171:3a7713b1edbc 1339 #define ADC_CFGR_AWD1EN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1340 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1341 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
AnnaBridge 171:3a7713b1edbc 1342 #define ADC_CFGR_JAWD1EN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1343 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1344 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
AnnaBridge 171:3a7713b1edbc 1345 #define ADC_CFGR_JAUTO_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1346 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1347 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
AnnaBridge 171:3a7713b1edbc 1348
AnnaBridge 171:3a7713b1edbc 1349 #define ADC_CFGR_AWD1CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1350 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1351 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 1352 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1353 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1354 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1355 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1356 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1357
AnnaBridge 171:3a7713b1edbc 1358 #define ADC_CFGR_JQDIS_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1359 #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1360 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
AnnaBridge 171:3a7713b1edbc 1361
AnnaBridge 171:3a7713b1edbc 1362 /******************** Bit definition for ADC_CFGR2 register *****************/
AnnaBridge 171:3a7713b1edbc 1363 #define ADC_CFGR2_ROVSE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1364 #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1365 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
AnnaBridge 171:3a7713b1edbc 1366 #define ADC_CFGR2_JOVSE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1367 #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1368 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
AnnaBridge 171:3a7713b1edbc 1369
AnnaBridge 171:3a7713b1edbc 1370 #define ADC_CFGR2_OVSR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1371 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
AnnaBridge 171:3a7713b1edbc 1372 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
AnnaBridge 171:3a7713b1edbc 1373 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1374 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1375 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1376
AnnaBridge 171:3a7713b1edbc 1377 #define ADC_CFGR2_OVSS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1378 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
AnnaBridge 171:3a7713b1edbc 1379 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
AnnaBridge 171:3a7713b1edbc 1380 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1381 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1382 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1383 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1384
AnnaBridge 171:3a7713b1edbc 1385 #define ADC_CFGR2_TROVS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1386 #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1387 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
AnnaBridge 171:3a7713b1edbc 1388 #define ADC_CFGR2_ROVSM_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1389 #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1390 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
AnnaBridge 171:3a7713b1edbc 1391
AnnaBridge 171:3a7713b1edbc 1392 /******************** Bit definition for ADC_SMPR1 register *****************/
AnnaBridge 171:3a7713b1edbc 1393 #define ADC_SMPR1_SMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1394 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1395 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1396 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1397 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1398 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1399
AnnaBridge 171:3a7713b1edbc 1400 #define ADC_SMPR1_SMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1401 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1402 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1403 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1404 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1405 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1406
AnnaBridge 171:3a7713b1edbc 1407 #define ADC_SMPR1_SMP2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1408 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1409 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1410 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1411 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1412 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1413
AnnaBridge 171:3a7713b1edbc 1414 #define ADC_SMPR1_SMP3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1415 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1416 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1417 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1418 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1419 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1420
AnnaBridge 171:3a7713b1edbc 1421 #define ADC_SMPR1_SMP4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1422 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1423 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1424 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1425 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1426 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1427
AnnaBridge 171:3a7713b1edbc 1428 #define ADC_SMPR1_SMP5_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1429 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1430 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1431 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1432 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1433 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1434
AnnaBridge 171:3a7713b1edbc 1435 #define ADC_SMPR1_SMP6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1436 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1437 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1438 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1439 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1440 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1441
AnnaBridge 171:3a7713b1edbc 1442 #define ADC_SMPR1_SMP7_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1443 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1444 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1445 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1446 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1447 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1448
AnnaBridge 171:3a7713b1edbc 1449 #define ADC_SMPR1_SMP8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1450 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1451 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1452 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1453 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1454 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1455
AnnaBridge 171:3a7713b1edbc 1456 #define ADC_SMPR1_SMP9_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1457 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 1458 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1459 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1460 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1461 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1462
AnnaBridge 171:3a7713b1edbc 1463 /******************** Bit definition for ADC_SMPR2 register *****************/
AnnaBridge 171:3a7713b1edbc 1464 #define ADC_SMPR2_SMP10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1465 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1466 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1467 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1468 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1469 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1470
AnnaBridge 171:3a7713b1edbc 1471 #define ADC_SMPR2_SMP11_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1472 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1473 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1474 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1475 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1476 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1477
AnnaBridge 171:3a7713b1edbc 1478 #define ADC_SMPR2_SMP12_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1479 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1480 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1481 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1482 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1483 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1484
AnnaBridge 171:3a7713b1edbc 1485 #define ADC_SMPR2_SMP13_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1486 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1487 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1488 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1489 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1490 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1491
AnnaBridge 171:3a7713b1edbc 1492 #define ADC_SMPR2_SMP14_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1493 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1494 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1495 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1496 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1497 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1498
AnnaBridge 171:3a7713b1edbc 1499 #define ADC_SMPR2_SMP15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1500 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1501 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1502 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1503 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1504 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1505
AnnaBridge 171:3a7713b1edbc 1506 #define ADC_SMPR2_SMP16_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1507 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1508 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1509 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1510 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1511 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1512
AnnaBridge 171:3a7713b1edbc 1513 #define ADC_SMPR2_SMP17_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1514 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1515 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1516 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1517 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1518 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1519
AnnaBridge 171:3a7713b1edbc 1520 #define ADC_SMPR2_SMP18_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1521 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1522 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1523 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1524 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1525 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1526
AnnaBridge 171:3a7713b1edbc 1527 /******************** Bit definition for ADC_TR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1528 #define ADC_TR1_LT1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1529 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1530 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
AnnaBridge 171:3a7713b1edbc 1531 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1532 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1533 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1534 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1535 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1536 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1537 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1538 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1539 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1540 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1541 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1542 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1543
AnnaBridge 171:3a7713b1edbc 1544 #define ADC_TR1_HT1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1545 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 1546 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
AnnaBridge 171:3a7713b1edbc 1547 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1548 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1549 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1550 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1551 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1552 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1553 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1554 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1555 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1556 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1557 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1558 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1559
AnnaBridge 171:3a7713b1edbc 1560 /******************** Bit definition for ADC_TR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1561 #define ADC_TR2_LT2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1562 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1563 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
AnnaBridge 171:3a7713b1edbc 1564 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1565 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1566 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1567 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1568 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1569 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1570 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1571 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1572
AnnaBridge 171:3a7713b1edbc 1573 #define ADC_TR2_HT2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1574 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 1575 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
AnnaBridge 171:3a7713b1edbc 1576 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1577 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1578 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1579 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1580 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1581 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1582 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1583 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1584
AnnaBridge 171:3a7713b1edbc 1585 /******************** Bit definition for ADC_TR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1586 #define ADC_TR3_LT3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1587 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1588 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
AnnaBridge 171:3a7713b1edbc 1589 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1590 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1591 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1592 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1593 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1594 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1595 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1596 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1597
AnnaBridge 171:3a7713b1edbc 1598 #define ADC_TR3_HT3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1599 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 1600 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
AnnaBridge 171:3a7713b1edbc 1601 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1602 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1603 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1604 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1605 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1606 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1607 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1608 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1609
AnnaBridge 171:3a7713b1edbc 1610 /******************** Bit definition for ADC_SQR1 register ******************/
AnnaBridge 171:3a7713b1edbc 1611 #define ADC_SQR1_L_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1612 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 1613 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
AnnaBridge 171:3a7713b1edbc 1614 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1615 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1616 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1617 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1618
AnnaBridge 171:3a7713b1edbc 1619 #define ADC_SQR1_SQ1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1620 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1621 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
AnnaBridge 171:3a7713b1edbc 1622 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1623 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1624 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1625 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1626 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1627
AnnaBridge 171:3a7713b1edbc 1628 #define ADC_SQR1_SQ2_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1629 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
AnnaBridge 171:3a7713b1edbc 1630 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
AnnaBridge 171:3a7713b1edbc 1631 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1632 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1633 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1634 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1635 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1636
AnnaBridge 171:3a7713b1edbc 1637 #define ADC_SQR1_SQ3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1638 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 1639 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
AnnaBridge 171:3a7713b1edbc 1640 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1641 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1642 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1643 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1644 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1645
AnnaBridge 171:3a7713b1edbc 1646 #define ADC_SQR1_SQ4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1647 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 1648 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
AnnaBridge 171:3a7713b1edbc 1649 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1650 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1651 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1652 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1653 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1654
AnnaBridge 171:3a7713b1edbc 1655 /******************** Bit definition for ADC_SQR2 register ******************/
AnnaBridge 171:3a7713b1edbc 1656 #define ADC_SQR2_SQ5_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1657 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1658 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
AnnaBridge 171:3a7713b1edbc 1659 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1660 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1661 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1662 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1663 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1664
AnnaBridge 171:3a7713b1edbc 1665 #define ADC_SQR2_SQ6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1666 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1667 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
AnnaBridge 171:3a7713b1edbc 1668 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1669 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1670 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1671 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1672 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1673
AnnaBridge 171:3a7713b1edbc 1674 #define ADC_SQR2_SQ7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1675 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
AnnaBridge 171:3a7713b1edbc 1676 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
AnnaBridge 171:3a7713b1edbc 1677 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1678 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1679 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1680 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1681 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1682
AnnaBridge 171:3a7713b1edbc 1683 #define ADC_SQR2_SQ8_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1684 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 1685 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
AnnaBridge 171:3a7713b1edbc 1686 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1687 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1688 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1689 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1690 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1691
AnnaBridge 171:3a7713b1edbc 1692 #define ADC_SQR2_SQ9_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1693 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 1694 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
AnnaBridge 171:3a7713b1edbc 1695 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1696 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1697 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1698 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1699 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1700
AnnaBridge 171:3a7713b1edbc 1701 /******************** Bit definition for ADC_SQR3 register ******************/
AnnaBridge 171:3a7713b1edbc 1702 #define ADC_SQR3_SQ10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1703 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1704 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
AnnaBridge 171:3a7713b1edbc 1705 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1706 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1707 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1708 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1709 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1710
AnnaBridge 171:3a7713b1edbc 1711 #define ADC_SQR3_SQ11_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1712 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1713 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
AnnaBridge 171:3a7713b1edbc 1714 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1715 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1716 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1717 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1718 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1719
AnnaBridge 171:3a7713b1edbc 1720 #define ADC_SQR3_SQ12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1721 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
AnnaBridge 171:3a7713b1edbc 1722 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
AnnaBridge 171:3a7713b1edbc 1723 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1724 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1725 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1726 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1727 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1728
AnnaBridge 171:3a7713b1edbc 1729 #define ADC_SQR3_SQ13_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1730 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 1731 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
AnnaBridge 171:3a7713b1edbc 1732 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1733 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1734 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1735 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1736 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1737
AnnaBridge 171:3a7713b1edbc 1738 #define ADC_SQR3_SQ14_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1739 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 1740 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
AnnaBridge 171:3a7713b1edbc 1741 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1742 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1743 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1744 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1745 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1746
AnnaBridge 171:3a7713b1edbc 1747 /******************** Bit definition for ADC_SQR4 register ******************/
AnnaBridge 171:3a7713b1edbc 1748 #define ADC_SQR4_SQ15_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1749 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1750 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
AnnaBridge 171:3a7713b1edbc 1751 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1752 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1753 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1754 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1755 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1756
AnnaBridge 171:3a7713b1edbc 1757 #define ADC_SQR4_SQ16_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1758 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1759 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
AnnaBridge 171:3a7713b1edbc 1760 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1761 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1762 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1763 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1764 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1765
AnnaBridge 171:3a7713b1edbc 1766 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 171:3a7713b1edbc 1767 #define ADC_DR_RDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1768 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1769 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
AnnaBridge 171:3a7713b1edbc 1770 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1771 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1772 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1773 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1774 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1775 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1776 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1777 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1778 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1779 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1780 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1781 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1782 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1783 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1784 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1785 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1786
AnnaBridge 171:3a7713b1edbc 1787 /******************** Bit definition for ADC_JSQR register ******************/
AnnaBridge 171:3a7713b1edbc 1788 #define ADC_JSQR_JL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1789 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 1790 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
AnnaBridge 171:3a7713b1edbc 1791 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1792 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1793
AnnaBridge 171:3a7713b1edbc 1794 #define ADC_JSQR_JEXTSEL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1795 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
AnnaBridge 171:3a7713b1edbc 1796 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
AnnaBridge 171:3a7713b1edbc 1797 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1798 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1799 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1800 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1801
AnnaBridge 171:3a7713b1edbc 1802 #define ADC_JSQR_JEXTEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1803 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 1804 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
AnnaBridge 171:3a7713b1edbc 1805 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1806 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1807
AnnaBridge 171:3a7713b1edbc 1808 #define ADC_JSQR_JSQ1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1809 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 1810 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
AnnaBridge 171:3a7713b1edbc 1811 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1812 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1813 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1814 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1815 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1816
AnnaBridge 171:3a7713b1edbc 1817 #define ADC_JSQR_JSQ2_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1818 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
AnnaBridge 171:3a7713b1edbc 1819 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
AnnaBridge 171:3a7713b1edbc 1820 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1821 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1822 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1823 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1824 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1825
AnnaBridge 171:3a7713b1edbc 1826 #define ADC_JSQR_JSQ3_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1827 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1828 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
AnnaBridge 171:3a7713b1edbc 1829 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1830 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1831 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1832 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1833 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1834
AnnaBridge 171:3a7713b1edbc 1835 #define ADC_JSQR_JSQ4_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1836 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1837 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
AnnaBridge 171:3a7713b1edbc 1838 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1839 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1840 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1841 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1842 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1843
AnnaBridge 171:3a7713b1edbc 1844 /******************** Bit definition for ADC_OFR1 register ******************/
AnnaBridge 171:3a7713b1edbc 1845 #define ADC_OFR1_OFFSET1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1846 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1847 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
AnnaBridge 171:3a7713b1edbc 1848 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1849 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1850 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1851 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1852 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1853 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1854 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1855 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1856 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1857 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1858 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1859 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1860
AnnaBridge 171:3a7713b1edbc 1861 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1862 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1863 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
AnnaBridge 171:3a7713b1edbc 1864 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1865 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1866 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1867 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1868 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1869
AnnaBridge 171:3a7713b1edbc 1870 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1871 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1872 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
AnnaBridge 171:3a7713b1edbc 1873
AnnaBridge 171:3a7713b1edbc 1874 /******************** Bit definition for ADC_OFR2 register ******************/
AnnaBridge 171:3a7713b1edbc 1875 #define ADC_OFR2_OFFSET2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1876 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1877 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
AnnaBridge 171:3a7713b1edbc 1878 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1879 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1880 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1881 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1882 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1883 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1884 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1885 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1886 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1887 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1888 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1889 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1890
AnnaBridge 171:3a7713b1edbc 1891 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1892 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1893 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
AnnaBridge 171:3a7713b1edbc 1894 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1895 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1896 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1897 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1898 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1899
AnnaBridge 171:3a7713b1edbc 1900 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1901 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1902 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
AnnaBridge 171:3a7713b1edbc 1903
AnnaBridge 171:3a7713b1edbc 1904 /******************** Bit definition for ADC_OFR3 register ******************/
AnnaBridge 171:3a7713b1edbc 1905 #define ADC_OFR3_OFFSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1906 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1907 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
AnnaBridge 171:3a7713b1edbc 1908 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1909 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1910 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1911 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1912 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1913 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1914 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1915 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1916 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1917 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1918 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1919 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1920
AnnaBridge 171:3a7713b1edbc 1921 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1922 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1923 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
AnnaBridge 171:3a7713b1edbc 1924 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1925 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1926 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1927 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1928 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1929
AnnaBridge 171:3a7713b1edbc 1930 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1931 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1932 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
AnnaBridge 171:3a7713b1edbc 1933
AnnaBridge 171:3a7713b1edbc 1934 /******************** Bit definition for ADC_OFR4 register ******************/
AnnaBridge 171:3a7713b1edbc 1935 #define ADC_OFR4_OFFSET4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1936 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1937 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
AnnaBridge 171:3a7713b1edbc 1938 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1939 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1940 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1941 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1942 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1943 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1944 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1945 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1946 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1947 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1948 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1949 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1950
AnnaBridge 171:3a7713b1edbc 1951 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1952 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1953 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
AnnaBridge 171:3a7713b1edbc 1954 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1955 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1956 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1957 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1958 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1959
AnnaBridge 171:3a7713b1edbc 1960 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1961 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1962 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
AnnaBridge 171:3a7713b1edbc 1963
AnnaBridge 171:3a7713b1edbc 1964 /******************** Bit definition for ADC_JDR1 register ******************/
AnnaBridge 171:3a7713b1edbc 1965 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1966 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1967 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
AnnaBridge 171:3a7713b1edbc 1968 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1969 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1970 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1971 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1972 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1973 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1974 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1975 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1976 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1977 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1978 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1979 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1980 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1981 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1982 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1983 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1984
AnnaBridge 171:3a7713b1edbc 1985 /******************** Bit definition for ADC_JDR2 register ******************/
AnnaBridge 171:3a7713b1edbc 1986 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1987 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1988 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
AnnaBridge 171:3a7713b1edbc 1989 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1990 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1991 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1992 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1993 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1994 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1995 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1996 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1997 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1998 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1999 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2000 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2001 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2002 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2003 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2004 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2005
AnnaBridge 171:3a7713b1edbc 2006 /******************** Bit definition for ADC_JDR3 register ******************/
AnnaBridge 171:3a7713b1edbc 2007 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2008 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2009 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
AnnaBridge 171:3a7713b1edbc 2010 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2011 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2012 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2013 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2014 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2015 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2016 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2017 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2018 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2019 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2020 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2021 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2022 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2023 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2024 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2025 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2026
AnnaBridge 171:3a7713b1edbc 2027 /******************** Bit definition for ADC_JDR4 register ******************/
AnnaBridge 171:3a7713b1edbc 2028 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2029 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2030 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
AnnaBridge 171:3a7713b1edbc 2031 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2032 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2033 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2034 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2035 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2036 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2037 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2038 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2039 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2040 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2041 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2042 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2043 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2044 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2045 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2046 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2047
AnnaBridge 171:3a7713b1edbc 2048 /******************** Bit definition for ADC_AWD2CR register ****************/
AnnaBridge 171:3a7713b1edbc 2049 #define ADC_AWD2CR_AWD2CH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2050 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 2051 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 2052 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2053 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2054 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2055 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2056 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2057 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2058 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2059 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2060 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2061 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2062 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2063 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2064 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2065 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2066 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2067 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2068 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2069 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2070 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2071
AnnaBridge 171:3a7713b1edbc 2072 /******************** Bit definition for ADC_AWD3CR register ****************/
AnnaBridge 171:3a7713b1edbc 2073 #define ADC_AWD3CR_AWD3CH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2074 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 2075 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 2076 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2077 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2078 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2079 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2080 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2081 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2082 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2083 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2084 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2085 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2086 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2087 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2088 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2089 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2090 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2091 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2092 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2093 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2094 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2095
AnnaBridge 171:3a7713b1edbc 2096 /******************** Bit definition for ADC_DIFSEL register ****************/
AnnaBridge 171:3a7713b1edbc 2097 #define ADC_DIFSEL_DIFSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2098 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 2099 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
AnnaBridge 171:3a7713b1edbc 2100 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2101 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2102 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2103 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2104 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2105 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2106 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2107 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2108 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2109 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2110 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2111 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2112 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2113 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2114 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2115 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2116 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2117 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2118 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2119
AnnaBridge 171:3a7713b1edbc 2120 /******************** Bit definition for ADC_CALFACT register ***************/
AnnaBridge 171:3a7713b1edbc 2121 #define ADC_CALFACT_CALFACT_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2122 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 2123 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
AnnaBridge 171:3a7713b1edbc 2124 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2125 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2126 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2127 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2128 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2129 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2130 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2131
AnnaBridge 171:3a7713b1edbc 2132 #define ADC_CALFACT_CALFACT_D_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2133 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 2134 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
AnnaBridge 171:3a7713b1edbc 2135 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2136 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2137 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2138 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2139 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2140 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2141 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2142
AnnaBridge 171:3a7713b1edbc 2143 /************************* ADC Common registers *****************************/
AnnaBridge 171:3a7713b1edbc 2144 /******************** Bit definition for ADC_CCR register *******************/
AnnaBridge 171:3a7713b1edbc 2145 #define ADC_CCR_CKMODE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2146 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2147 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
AnnaBridge 171:3a7713b1edbc 2148 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2149 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2150
AnnaBridge 171:3a7713b1edbc 2151 #define ADC_CCR_PRESC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2152 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
AnnaBridge 171:3a7713b1edbc 2153 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
AnnaBridge 171:3a7713b1edbc 2154 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2155 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2156 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2157 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2158
AnnaBridge 171:3a7713b1edbc 2159 #define ADC_CCR_VREFEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2160 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2161 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
AnnaBridge 171:3a7713b1edbc 2162 #define ADC_CCR_TSEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2163 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2164 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
AnnaBridge 171:3a7713b1edbc 2165 #define ADC_CCR_VBATEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2166 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2167 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
AnnaBridge 171:3a7713b1edbc 2168
AnnaBridge 171:3a7713b1edbc 2169 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2170 /* */
AnnaBridge 171:3a7713b1edbc 2171 /* Controller Area Network */
AnnaBridge 171:3a7713b1edbc 2172 /* */
AnnaBridge 171:3a7713b1edbc 2173 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2174 /*!<CAN control and status registers */
AnnaBridge 171:3a7713b1edbc 2175 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 171:3a7713b1edbc 2176 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2177 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2178 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 171:3a7713b1edbc 2179 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2180 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2181 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 171:3a7713b1edbc 2182 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2183 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2184 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 171:3a7713b1edbc 2185 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2186 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2187 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 171:3a7713b1edbc 2188 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2189 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2190 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 171:3a7713b1edbc 2191 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2192 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2193 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 171:3a7713b1edbc 2194 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2195 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2196 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 171:3a7713b1edbc 2197 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2198 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2199 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 171:3a7713b1edbc 2200 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2201 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2202 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 171:3a7713b1edbc 2203
AnnaBridge 171:3a7713b1edbc 2204 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 171:3a7713b1edbc 2205 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2206 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2207 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 171:3a7713b1edbc 2208 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2209 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2210 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 171:3a7713b1edbc 2211 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2212 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2213 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 171:3a7713b1edbc 2214 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2215 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2216 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 2217 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2218 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2219 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 171:3a7713b1edbc 2220 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2221 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2222 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 171:3a7713b1edbc 2223 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2224 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2225 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 171:3a7713b1edbc 2226 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2227 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2228 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 171:3a7713b1edbc 2229 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2230 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2231 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
AnnaBridge 171:3a7713b1edbc 2232
AnnaBridge 171:3a7713b1edbc 2233 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 171:3a7713b1edbc 2234 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2235 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2236 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2237 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2238 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2239 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2240 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2241 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2242 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2243 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2244 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2245 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2246 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2247 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2248 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2249 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2250 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2251 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2252 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2253 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2254 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2255 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2256 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2257 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2258 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2259 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2260 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2261 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2262 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2263 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 171:3a7713b1edbc 2264 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2265 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2266 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 171:3a7713b1edbc 2267 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2268 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2269 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2270 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2271 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2272 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2273 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2274 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2275 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2276 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2277 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2278 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2279 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2280 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2281 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 171:3a7713b1edbc 2282
AnnaBridge 171:3a7713b1edbc 2283 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2284 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 171:3a7713b1edbc 2285 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 171:3a7713b1edbc 2286 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2287 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2288 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 171:3a7713b1edbc 2289 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2290 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2291 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 171:3a7713b1edbc 2292 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2293 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2294 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 171:3a7713b1edbc 2295
AnnaBridge 171:3a7713b1edbc 2296 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2297 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 171:3a7713b1edbc 2298 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 171:3a7713b1edbc 2299 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2300 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2301 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 171:3a7713b1edbc 2302 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2303 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2304 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 171:3a7713b1edbc 2305 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2306 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2307 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2308
AnnaBridge 171:3a7713b1edbc 2309 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 171:3a7713b1edbc 2310 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2311 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2312 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 171:3a7713b1edbc 2313 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2314 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2315 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 171:3a7713b1edbc 2316 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2317 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2318 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 171:3a7713b1edbc 2319 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2320 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2321 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 171:3a7713b1edbc 2322
AnnaBridge 171:3a7713b1edbc 2323 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 171:3a7713b1edbc 2324 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2325 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2326 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 171:3a7713b1edbc 2327 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2328 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2329 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 171:3a7713b1edbc 2330 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2331 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2332 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 171:3a7713b1edbc 2333 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2334 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2335 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 171:3a7713b1edbc 2336
AnnaBridge 171:3a7713b1edbc 2337 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 171:3a7713b1edbc 2338 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2339 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2340 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2341 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2342 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2343 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2344 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2345 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2346 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2347 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2348 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2349 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2350 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2351 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2352 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2353 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2354 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2355 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2356 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2357 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2358 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2359 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2360 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2361 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2362 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2363 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2364 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2365 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2366 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2367 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2368 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2369 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2370 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2371 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2372 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2373 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2374 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2375 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2376 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2377 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2378 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2379 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2380
AnnaBridge 171:3a7713b1edbc 2381 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 171:3a7713b1edbc 2382 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2383 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2384 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 171:3a7713b1edbc 2385 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2386 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2387 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 171:3a7713b1edbc 2388 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2389 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2390 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 171:3a7713b1edbc 2391
AnnaBridge 171:3a7713b1edbc 2392 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2393 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 2394 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 171:3a7713b1edbc 2395 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2396 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2397 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2398
AnnaBridge 171:3a7713b1edbc 2399 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2400 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2401 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 171:3a7713b1edbc 2402 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2403 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2404 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 171:3a7713b1edbc 2405
AnnaBridge 171:3a7713b1edbc 2406 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 171:3a7713b1edbc 2407 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2408 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 2409 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 171:3a7713b1edbc 2410 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2411 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 2412 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 171:3a7713b1edbc 2413 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2414 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2415 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2416 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2417 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2418 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 171:3a7713b1edbc 2419 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 171:3a7713b1edbc 2420 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2421 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2422 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2423 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2424 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2425 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 171:3a7713b1edbc 2426 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2427 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2428 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2429 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2430 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 171:3a7713b1edbc 2431 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2432 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2433 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
AnnaBridge 171:3a7713b1edbc 2434
AnnaBridge 171:3a7713b1edbc 2435 /*!<Mailbox registers */
AnnaBridge 171:3a7713b1edbc 2436 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 171:3a7713b1edbc 2437 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2438 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2439 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2440 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2441 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2442 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2443 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2444 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2445 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2446 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2447 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2448 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2449 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2450 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2451 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2452
AnnaBridge 171:3a7713b1edbc 2453 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 171:3a7713b1edbc 2454 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2455 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2456 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2457 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2458 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2459 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2460 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2461 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2462 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2463
AnnaBridge 171:3a7713b1edbc 2464 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 171:3a7713b1edbc 2465 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2466 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2467 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2468 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2469 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2470 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2471 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2472 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2473 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2474 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2475 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2476 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2477
AnnaBridge 171:3a7713b1edbc 2478 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 171:3a7713b1edbc 2479 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2480 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2481 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2482 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2483 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2484 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2485 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2486 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2487 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2488 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2489 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2490 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2491
AnnaBridge 171:3a7713b1edbc 2492 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 171:3a7713b1edbc 2493 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2494 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2495 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2496 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2497 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2498 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2499 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2500 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2501 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2502 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2503 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2504 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2505 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2506 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2507 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2508
AnnaBridge 171:3a7713b1edbc 2509 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 171:3a7713b1edbc 2510 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2511 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2512 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2513 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2514 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2515 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2516 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2517 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2518 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2519
AnnaBridge 171:3a7713b1edbc 2520 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 171:3a7713b1edbc 2521 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2522 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2523 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2524 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2525 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2526 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2527 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2528 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2529 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2530 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2531 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2532 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2533
AnnaBridge 171:3a7713b1edbc 2534 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 171:3a7713b1edbc 2535 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2536 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2537 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2538 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2539 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2540 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2541 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2542 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2543 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2544 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2545 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2546 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2547
AnnaBridge 171:3a7713b1edbc 2548 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 171:3a7713b1edbc 2549 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2550 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2551 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2552 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2553 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2554 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2555 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2556 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2557 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2558 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2559 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2560 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 171:3a7713b1edbc 2561 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2562 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2563 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2564
AnnaBridge 171:3a7713b1edbc 2565 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 171:3a7713b1edbc 2566 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2567 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2568 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2569 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2570 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2571 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2572 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2573 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2574 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2575
AnnaBridge 171:3a7713b1edbc 2576 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 171:3a7713b1edbc 2577 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2578 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2579 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2580 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2581 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2582 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2583 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2584 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2585 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2586 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2587 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2588 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2589
AnnaBridge 171:3a7713b1edbc 2590 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 171:3a7713b1edbc 2591 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2592 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2593 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2594 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2595 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2596 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2597 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2598 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2599 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2600 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2601 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2602 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2603
AnnaBridge 171:3a7713b1edbc 2604 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 171:3a7713b1edbc 2605 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2606 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2607 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2608 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2609 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2610 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2611 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2612 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2613 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2614 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2615 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2616 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2617
AnnaBridge 171:3a7713b1edbc 2618 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 171:3a7713b1edbc 2619 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2620 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2621 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2622 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2623 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2624 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 171:3a7713b1edbc 2625 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2626 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2627 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2628
AnnaBridge 171:3a7713b1edbc 2629 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 171:3a7713b1edbc 2630 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2631 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2632 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2633 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2634 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2635 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2636 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2637 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2638 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2639 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2640 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2641 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2642
AnnaBridge 171:3a7713b1edbc 2643 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 171:3a7713b1edbc 2644 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2645 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2646 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2647 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2648 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2649 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2650 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2651 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2652 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2653 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2654 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2655 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2656
AnnaBridge 171:3a7713b1edbc 2657 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 171:3a7713b1edbc 2658 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2659 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2660 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2661 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2662 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2663 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2664 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2665 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2666 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 171:3a7713b1edbc 2667 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2668 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2669 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2670
AnnaBridge 171:3a7713b1edbc 2671 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 171:3a7713b1edbc 2672 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2673 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2674 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2675 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2676 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2677 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 171:3a7713b1edbc 2678 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2679 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2680 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2681
AnnaBridge 171:3a7713b1edbc 2682 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 171:3a7713b1edbc 2683 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2684 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2685 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2686 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2687 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2688 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2689 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2690 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2691 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2692 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2693 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2694 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2695
AnnaBridge 171:3a7713b1edbc 2696 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 171:3a7713b1edbc 2697 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2698 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2699 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2700 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2701 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2702 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2703 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2704 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2705 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2706 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2707 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2708 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2709
AnnaBridge 171:3a7713b1edbc 2710 /*!<CAN filter registers */
AnnaBridge 171:3a7713b1edbc 2711 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 171:3a7713b1edbc 2712 #define CAN_FMR_FINIT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2713 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2714 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
AnnaBridge 171:3a7713b1edbc 2715
AnnaBridge 171:3a7713b1edbc 2716 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 171:3a7713b1edbc 2717 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2718 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2719 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 171:3a7713b1edbc 2720 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2721 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2722 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 171:3a7713b1edbc 2723 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2724 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2725 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 171:3a7713b1edbc 2726 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2727 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2728 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 171:3a7713b1edbc 2729 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2730 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2731 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 171:3a7713b1edbc 2732 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2733 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2734 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 171:3a7713b1edbc 2735 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2736 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2737 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 171:3a7713b1edbc 2738 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2739 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2740 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 171:3a7713b1edbc 2741 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2742 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2743 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 171:3a7713b1edbc 2744 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2745 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2746 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 171:3a7713b1edbc 2747 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2748 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2749 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 171:3a7713b1edbc 2750 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2751 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2752 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 171:3a7713b1edbc 2753 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2754 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2755 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 171:3a7713b1edbc 2756 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2757 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2758 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 171:3a7713b1edbc 2759 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2760 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2761 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 171:3a7713b1edbc 2762
AnnaBridge 171:3a7713b1edbc 2763 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 171:3a7713b1edbc 2764 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2765 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2766 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 171:3a7713b1edbc 2767 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2768 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2769 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 171:3a7713b1edbc 2770 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2771 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2772 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 171:3a7713b1edbc 2773 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2774 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2775 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 171:3a7713b1edbc 2776 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2777 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2778 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 171:3a7713b1edbc 2779 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2780 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2781 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 171:3a7713b1edbc 2782 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2783 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2784 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 171:3a7713b1edbc 2785 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2786 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2787 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 171:3a7713b1edbc 2788 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2789 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2790 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 171:3a7713b1edbc 2791 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2792 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2793 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 171:3a7713b1edbc 2794 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2795 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2796 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 171:3a7713b1edbc 2797 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2798 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2799 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 171:3a7713b1edbc 2800 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2801 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2802 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 171:3a7713b1edbc 2803 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2804 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2805 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 171:3a7713b1edbc 2806 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2807 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2808 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 171:3a7713b1edbc 2809
AnnaBridge 171:3a7713b1edbc 2810 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 171:3a7713b1edbc 2811 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2812 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2813 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 171:3a7713b1edbc 2814 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2815 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2816 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
AnnaBridge 171:3a7713b1edbc 2817 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2818 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2819 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
AnnaBridge 171:3a7713b1edbc 2820 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2821 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2822 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
AnnaBridge 171:3a7713b1edbc 2823 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2824 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2825 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
AnnaBridge 171:3a7713b1edbc 2826 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2827 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2828 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
AnnaBridge 171:3a7713b1edbc 2829 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2830 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2831 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
AnnaBridge 171:3a7713b1edbc 2832 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2833 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2834 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
AnnaBridge 171:3a7713b1edbc 2835 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2836 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2837 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
AnnaBridge 171:3a7713b1edbc 2838 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2839 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2840 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
AnnaBridge 171:3a7713b1edbc 2841 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2842 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2843 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
AnnaBridge 171:3a7713b1edbc 2844 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2845 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2846 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
AnnaBridge 171:3a7713b1edbc 2847 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2848 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2849 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
AnnaBridge 171:3a7713b1edbc 2850 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2851 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2852 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
AnnaBridge 171:3a7713b1edbc 2853 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2854 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2855 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
AnnaBridge 171:3a7713b1edbc 2856
AnnaBridge 171:3a7713b1edbc 2857 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 171:3a7713b1edbc 2858 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2859 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2860 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 171:3a7713b1edbc 2861 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2862 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2863 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
AnnaBridge 171:3a7713b1edbc 2864 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2865 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2866 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
AnnaBridge 171:3a7713b1edbc 2867 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2868 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2869 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
AnnaBridge 171:3a7713b1edbc 2870 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2871 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2872 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
AnnaBridge 171:3a7713b1edbc 2873 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2874 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2875 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
AnnaBridge 171:3a7713b1edbc 2876 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2877 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2878 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
AnnaBridge 171:3a7713b1edbc 2879 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2880 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2881 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
AnnaBridge 171:3a7713b1edbc 2882 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2883 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2884 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
AnnaBridge 171:3a7713b1edbc 2885 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2886 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2887 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
AnnaBridge 171:3a7713b1edbc 2888 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2889 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2890 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
AnnaBridge 171:3a7713b1edbc 2891 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2892 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2893 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
AnnaBridge 171:3a7713b1edbc 2894 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2895 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2896 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
AnnaBridge 171:3a7713b1edbc 2897 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2898 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2899 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
AnnaBridge 171:3a7713b1edbc 2900 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2901 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2902 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
AnnaBridge 171:3a7713b1edbc 2903
AnnaBridge 171:3a7713b1edbc 2904 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 171:3a7713b1edbc 2905 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2906 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2907 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 2908 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2909 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2910 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 2911 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2912 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2913 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 2914 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2915 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2916 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 2917 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2918 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2919 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 2920 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2921 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2922 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 2923 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2924 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2925 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 2926 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2927 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2928 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 2929 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2930 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2931 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 2932 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2933 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2934 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 2935 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2936 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2937 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 2938 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2939 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2940 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 2941 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2942 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2943 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 2944 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2945 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2946 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 2947 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2948 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2949 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 2950 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2951 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2952 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 2953 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2954 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2955 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 2956 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2957 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2958 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 2959 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2960 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2961 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 2962 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2963 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2964 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 2965 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2966 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2967 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 2968 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2969 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2970 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 2971 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2972 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2973 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 2974 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2975 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2976 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 2977 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2978 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2979 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 2980 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2981 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2982 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 2983 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2984 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2985 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 2986 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2987 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2988 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 2989 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2990 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2991 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 2992 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2993 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2994 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 2995 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2996 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2997 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 2998 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2999 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3000 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3001
AnnaBridge 171:3a7713b1edbc 3002 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3003 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3004 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3005 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3006 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3007 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3008 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3009 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3010 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3011 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3012 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3013 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3014 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3015 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3016 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3017 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3018 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3019 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3020 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3021 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3022 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3023 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3024 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3025 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3026 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3027 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3028 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3029 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3030 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3031 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3032 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3033 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3034 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3035 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3036 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3037 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3038 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3039 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3040 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3041 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3042 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3043 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3044 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3045 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3046 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3047 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3048 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3049 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3050 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3051 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3052 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3053 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3054 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3055 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3056 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3057 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3058 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3059 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3060 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3061 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3062 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3063 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3064 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3065 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3066 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3067 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3068 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3069 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3070 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3071 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3072 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3073 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3074 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3075 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3076 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3077 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3078 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3079 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3080 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3081 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3082 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3083 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3084 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3085 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3086 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3087 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3088 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3089 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3090 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3091 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3092 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3093 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3094 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3095 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3096 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3097 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3098 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3099
AnnaBridge 171:3a7713b1edbc 3100 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3101 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3102 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3103 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3104 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3105 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3106 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3107 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3108 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3109 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3110 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3111 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3112 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3113 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3114 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3115 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3116 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3117 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3118 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3119 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3120 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3121 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3122 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3123 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3124 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3125 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3126 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3127 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3128 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3129 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3130 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3131 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3132 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3133 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3134 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3135 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3136 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3137 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3138 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3139 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3140 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3141 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3142 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3143 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3144 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3145 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3146 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3147 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3148 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3149 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3150 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3151 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3152 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3153 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3154 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3155 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3156 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3157 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3158 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3159 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3160 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3161 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3162 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3163 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3164 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3165 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3166 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3167 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3168 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3169 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3170 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3171 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3172 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3173 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3174 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3175 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3176 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3177 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3178 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3179 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3180 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3181 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3182 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3183 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3184 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3185 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3186 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3187 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3188 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3189 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3190 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3191 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3192 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3193 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3194 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3195 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3196 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3197
AnnaBridge 171:3a7713b1edbc 3198 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3199 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3200 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3201 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3202 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3203 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3204 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3205 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3206 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3207 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3208 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3209 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3210 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3211 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3212 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3213 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3214 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3215 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3216 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3217 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3218 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3219 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3220 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3221 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3222 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3223 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3224 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3225 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3226 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3227 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3228 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3229 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3230 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3231 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3232 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3233 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3234 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3235 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3236 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3237 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3238 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3239 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3240 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3241 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3242 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3243 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3244 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3245 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3246 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3247 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3248 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3249 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3250 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3251 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3252 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3253 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3254 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3255 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3256 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3257 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3258 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3259 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3260 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3261 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3262 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3263 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3264 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3265 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3266 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3267 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3268 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3269 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3270 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3271 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3272 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3273 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3274 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3275 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3276 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3277 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3278 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3279 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3280 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3281 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3282 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3283 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3284 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3285 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3286 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3287 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3288 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3289 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3290 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3291 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3292 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3293 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3294 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3295
AnnaBridge 171:3a7713b1edbc 3296 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3297 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3298 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3299 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3300 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3301 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3302 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3303 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3304 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3305 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3306 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3307 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3308 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3309 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3310 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3311 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3312 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3313 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3314 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3315 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3316 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3317 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3318 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3319 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3320 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3321 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3322 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3323 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3324 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3325 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3326 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3327 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3328 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3329 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3330 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3331 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3332 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3333 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3334 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3335 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3336 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3337 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3338 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3339 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3340 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3341 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3342 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3343 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3344 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3345 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3346 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3347 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3348 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3349 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3350 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3351 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3352 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3353 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3354 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3355 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3356 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3357 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3358 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3359 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3360 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3361 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3362 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3363 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3364 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3365 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3366 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3367 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3368 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3369 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3370 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3371 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3372 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3373 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3374 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3375 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3376 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3377 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3378 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3379 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3380 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3381 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3382 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3383 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3384 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3385 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3386 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3387 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3388 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3389 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3390 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3391 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3392 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3393
AnnaBridge 171:3a7713b1edbc 3394 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3395 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3396 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3397 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3398 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3399 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3400 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3401 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3402 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3403 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3404 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3405 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3406 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3407 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3408 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3409 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3410 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3411 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3412 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3413 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3414 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3415 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3416 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3417 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3418 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3419 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3420 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3421 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3422 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3423 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3424 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3425 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3426 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3427 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3428 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3429 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3430 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3431 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3432 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3433 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3434 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3435 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3436 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3437 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3438 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3439 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3440 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3441 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3442 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3443 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3444 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3445 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3446 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3447 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3448 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3449 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3450 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3451 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3452 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3453 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3454 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3455 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3456 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3457 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3458 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3459 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3460 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3461 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3462 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3463 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3464 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3465 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3466 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3467 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3468 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3469 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3470 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3471 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3472 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3473 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3474 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3475 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3476 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3477 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3478 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3479 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3480 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3481 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3482 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3483 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3484 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3485 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3486 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3487 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3488 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3489 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3490 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3491
AnnaBridge 171:3a7713b1edbc 3492 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3493 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3494 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3495 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3496 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3497 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3498 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3499 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3500 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3501 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3502 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3503 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3504 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3505 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3506 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3507 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3508 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3509 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3510 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3511 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3512 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3513 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3514 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3515 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3516 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3517 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3518 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3519 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3520 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3521 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3522 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3523 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3524 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3525 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3526 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3527 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3528 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3529 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3530 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3531 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3532 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3533 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3534 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3535 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3536 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3537 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3538 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3539 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3540 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3541 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3542 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3543 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3544 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3545 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3546 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3547 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3548 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3549 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3550 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3551 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3552 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3553 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3554 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3555 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3556 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3557 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3558 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3559 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3560 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3561 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3562 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3563 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3564 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3565 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3566 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3567 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3568 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3569 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3570 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3571 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3572 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3573 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3574 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3575 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3576 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3577 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3578 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3579 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3580 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3581 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3582 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3583 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3584 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3585 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3586 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3587 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3588 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3589
AnnaBridge 171:3a7713b1edbc 3590 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3591 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3592 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3593 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3594 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3595 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3596 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3597 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3598 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3599 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3600 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3601 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3602 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3603 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3604 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3605 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3606 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3607 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3608 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3609 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3610 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3611 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3612 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3613 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3614 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3615 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3616 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3617 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3618 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3619 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3620 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3621 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3622 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3623 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3624 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3625 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3626 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3627 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3628 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3629 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3630 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3631 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3632 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3633 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3634 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3635 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3636 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3637 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3638 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3639 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3640 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3641 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3642 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3643 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3644 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3645 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3646 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3647 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3648 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3649 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3650 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3651 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3652 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3653 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3654 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3655 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3656 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3657 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3658 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3659 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3660 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3661 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3662 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3663 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3664 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3665 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3666 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3667 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3668 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3669 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3670 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3671 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3672 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3673 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3674 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3675 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3676 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3677 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3678 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3679 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3680 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3681 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3682 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3683 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3684 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3685 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3686 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3687
AnnaBridge 171:3a7713b1edbc 3688 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3689 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3690 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3691 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3692 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3693 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3694 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3695 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3696 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3697 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3698 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3699 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3700 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3701 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3702 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3703 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3704 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3705 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3706 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3707 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3708 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3709 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3710 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3711 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3712 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3713 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3714 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3715 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3716 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3717 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3718 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3719 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3720 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3721 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3722 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3723 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3724 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3725 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3726 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3727 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3728 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3729 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3730 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3731 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3732 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3733 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3734 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3735 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3736 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3737 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3738 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3739 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3740 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3741 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3742 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3743 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3744 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3745 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3746 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3747 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3748 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3749 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3750 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3751 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3752 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3753 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3754 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3755 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3756 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3757 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3758 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3759 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3760 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3761 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3762 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3763 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3764 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3765 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3766 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3767 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3768 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3769 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3770 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3771 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3772 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3773 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3774 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3775 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3776 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3777 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3778 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3779 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3780 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3781 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3782 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3783 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3784 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3785
AnnaBridge 171:3a7713b1edbc 3786 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3787 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3788 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3789 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3790 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3791 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3792 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3793 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3794 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3795 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3796 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3797 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3798 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3799 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3800 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3801 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3802 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3803 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3804 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3805 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3806 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3807 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3808 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3809 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3810 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3811 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3812 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3813 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3814 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3815 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3816 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3817 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3818 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3819 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3820 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3821 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3822 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3823 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3824 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3825 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3826 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3827 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3828 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3829 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3830 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3831 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3832 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3833 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3834 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3835 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3836 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3837 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3838 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3839 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3840 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3841 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3842 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3843 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3844 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3845 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3846 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3847 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3848 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3849 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3850 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3851 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3852 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3853 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3854 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3855 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3856 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3857 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3858 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3859 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3860 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3861 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3862 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3863 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3864 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3865 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3866 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3867 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3868 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3869 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3870 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3871 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3872 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3873 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3874 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3875 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3876 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3877 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3878 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3879 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3880 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3881 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3882 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3883
AnnaBridge 171:3a7713b1edbc 3884 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 171:3a7713b1edbc 3885 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3886 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3887 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3888 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3889 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3890 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3891 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3892 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3893 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3894 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3895 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3896 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3897 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3898 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3899 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3900 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3901 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3902 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3903 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3904 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3905 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3906 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3907 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3908 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3909 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3910 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3911 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3912 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3913 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3914 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3915 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3916 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3917 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3918 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3919 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3920 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3921 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3922 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3923 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3924 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3925 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3926 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3927 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3928 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3929 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3930 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3931 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3932 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3933 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3934 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3935 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3936 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3937 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3938 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3939 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3940 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3941 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3942 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3943 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3944 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3945 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3946 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3947 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3948 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3949 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3950 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3951 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3952 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3953 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3954 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3955 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3956 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3957 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3958 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3959 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3960 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3961 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3962 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3963 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3964 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3965 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3966 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3967 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3968 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3969 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3970 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3971 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3972 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3973 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3974 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3975 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3976 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3977 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3978 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3979 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3980 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3981
AnnaBridge 171:3a7713b1edbc 3982 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 171:3a7713b1edbc 3983 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3984 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3985 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3986 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3987 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3988 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3989 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3990 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3991 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3992 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3993 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3994 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3995 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3996 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3997 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3998 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3999 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4000 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4001 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4002 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4003 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4004 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4005 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4006 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4007 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4008 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4009 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4010 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4011 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4012 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4013 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4014 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4015 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4016 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4017 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4018 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4019 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4020 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4021 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4022 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4023 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4024 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4025 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4026 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4027 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4028 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4029 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4030 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4031 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4032 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4033 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4034 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4035 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4036 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4037 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4038 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4039 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4040 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4041 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4042 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4043 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4044 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4045 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4046 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4047 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4048 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4049 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4050 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4051 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4052 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4053 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4054 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4055 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4056 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4057 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4058 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4059 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4060 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4061 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4062 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4063 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4064 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4065 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4066 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4067 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4068 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4069 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4070 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4071 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4072 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4073 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4074 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4075 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4076 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4077 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4078 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4079
AnnaBridge 171:3a7713b1edbc 4080 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4081 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4082 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4083 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4084 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4085 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4086 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4087 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4088 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4089 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4090 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4091 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4092 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4093 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4094 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4095 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4096 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4097 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4098 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4099 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4100 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4101 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4102 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4103 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4104 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4105 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4106 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4107 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4108 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4109 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4110 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4111 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4112 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4113 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4114 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4115 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4116 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4117 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4118 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4119 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4120 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4121 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4122 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4123 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4124 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4125 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4126 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4127 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4128 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4129 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4130 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4131 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4132 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4133 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4134 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4135 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4136 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4137 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4138 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4139 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4140 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4141 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4142 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4143 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4144 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4145 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4146 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4147 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4148 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4149 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4150 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4151 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4152 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4153 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4154 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4155 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4156 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4157 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4158 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4159 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4160 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4161 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4162 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4163 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4164 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4165 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4166 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4167 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4168 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4169 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4170 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4171 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4172 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4173 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4174 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4175 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4176 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4177
AnnaBridge 171:3a7713b1edbc 4178 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4179 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4180 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4181 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4182 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4183 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4184 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4185 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4186 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4187 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4188 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4189 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4190 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4191 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4192 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4193 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4194 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4195 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4196 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4197 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4198 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4199 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4200 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4201 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4202 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4203 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4204 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4205 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4206 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4207 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4208 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4209 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4210 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4211 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4212 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4213 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4214 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4215 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4216 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4217 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4218 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4219 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4220 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4221 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4222 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4223 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4224 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4225 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4226 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4227 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4228 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4229 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4230 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4231 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4232 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4233 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4234 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4235 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4236 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4237 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4238 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4239 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4240 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4241 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4242 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4243 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4244 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4245 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4246 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4247 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4248 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4249 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4250 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4251 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4252 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4253 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4254 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4255 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4256 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4257 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4258 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4259 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4260 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4261 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4262 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4263 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4264 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4265 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4266 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4267 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4268 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4269 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4270 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4271 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4272 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4273 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4274 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4275
AnnaBridge 171:3a7713b1edbc 4276 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4277 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4278 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4279 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4280 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4281 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4282 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4283 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4284 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4285 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4286 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4287 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4288 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4289 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4290 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4291 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4292 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4293 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4294 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4295 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4296 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4297 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4298 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4299 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4300 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4301 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4302 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4303 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4304 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4305 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4306 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4307 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4308 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4309 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4310 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4311 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4312 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4313 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4314 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4315 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4316 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4317 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4318 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4319 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4320 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4321 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4322 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4323 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4324 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4325 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4326 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4327 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4328 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4329 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4330 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4331 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4332 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4333 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4334 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4335 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4336 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4337 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4338 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4339 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4340 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4341 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4342 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4343 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4344 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4345 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4346 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4347 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4348 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4349 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4350 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4351 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4352 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4353 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4354 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4355 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4356 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4357 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4358 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4359 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4360 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4361 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4362 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4363 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4364 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4365 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4366 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4367 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4368 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4369 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4370 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4371 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4372 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4373
AnnaBridge 171:3a7713b1edbc 4374 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4375 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4376 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4377 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4378 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4379 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4380 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4381 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4382 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4383 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4384 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4385 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4386 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4387 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4388 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4389 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4390 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4391 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4392 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4393 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4394 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4395 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4396 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4397 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4398 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4399 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4400 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4401 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4402 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4403 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4404 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4405 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4406 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4407 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4408 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4409 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4410 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4411 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4412 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4413 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4414 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4415 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4416 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4417 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4418 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4419 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4420 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4421 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4422 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4423 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4424 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4425 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4426 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4427 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4428 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4429 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4430 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4431 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4432 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4433 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4434 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4435 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4436 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4437 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4438 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4439 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4440 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4441 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4442 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4443 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4444 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4445 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4446 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4447 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4448 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4449 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4450 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4451 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4452 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4453 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4454 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4455 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4456 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4457 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4458 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4459 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4460 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4461 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4462 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4463 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4464 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4465 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4466 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4467 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4468 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4469 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4470 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4471
AnnaBridge 171:3a7713b1edbc 4472 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4473 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4474 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4475 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4476 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4477 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4478 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4479 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4480 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4481 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4482 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4483 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4484 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4485 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4486 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4487 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4488 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4489 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4490 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4491 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4492 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4493 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4494 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4495 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4496 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4497 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4498 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4499 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4500 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4501 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4502 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4503 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4504 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4505 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4506 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4507 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4508 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4509 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4510 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4511 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4512 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4513 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4514 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4515 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4516 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4517 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4518 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4519 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4520 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4521 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4522 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4523 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4524 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4525 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4526 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4527 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4528 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4529 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4530 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4531 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4532 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4533 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4534 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4535 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4536 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4537 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4538 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4539 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4540 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4541 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4542 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4543 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4544 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4545 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4546 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4547 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4548 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4549 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4550 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4551 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4552 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4553 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4554 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4555 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4556 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4557 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4558 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4559 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4560 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4561 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4562 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4563 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4564 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4565 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4566 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4567 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4568 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4569
AnnaBridge 171:3a7713b1edbc 4570 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4571 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4572 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4573 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4574 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4575 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4576 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4577 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4578 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4579 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4580 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4581 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4582 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4583 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4584 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4585 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4586 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4587 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4588 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4589 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4590 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4591 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4592 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4593 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4594 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4595 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4596 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4597 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4598 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4599 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4600 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4601 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4602 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4603 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4604 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4605 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4606 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4607 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4608 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4609 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4610 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4611 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4612 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4613 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4614 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4615 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4616 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4617 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4618 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4619 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4620 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4621 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4622 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4623 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4624 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4625 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4626 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4627 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4628 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4629 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4630 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4631 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4632 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4633 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4634 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4635 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4636 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4637 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4638 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4639 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4640 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4641 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4642 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4643 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4644 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4645 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4646 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4647 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4648 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4649 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4650 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4651 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4652 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4653 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4654 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4655 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4656 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4657 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4658 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4659 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4660 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4661 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4662 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4663 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4664 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4665 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4666 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4667
AnnaBridge 171:3a7713b1edbc 4668 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4669 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4670 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4671 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4672 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4673 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4674 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4675 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4676 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4677 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4678 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4679 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4680 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4681 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4682 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4683 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4684 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4685 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4686 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4687 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4688 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4689 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4690 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4691 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4692 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4693 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4694 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4695 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4696 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4697 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4698 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4699 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4700 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4701 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4702 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4703 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4704 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4705 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4706 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4707 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4708 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4709 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4710 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4711 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4712 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4713 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4714 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4715 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4716 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4717 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4718 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4719 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4720 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4721 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4722 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4723 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4724 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4725 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4726 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4727 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4728 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4729 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4730 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4731 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4732 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4733 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4734 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4735 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4736 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4737 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4738 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4739 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4740 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4741 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4742 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4743 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4744 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4745 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4746 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4747 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4748 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4749 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4750 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4751 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4752 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4753 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4754 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4755 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4756 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4757 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4758 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4759 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4760 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4761 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4762 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4763 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4764 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4765
AnnaBridge 171:3a7713b1edbc 4766 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4767 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4768 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4769 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4770 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4771 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4772 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4773 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4774 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4775 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4776 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4777 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4778 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4779 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4780 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4781 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4782 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4783 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4784 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4785 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4786 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4787 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4788 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4789 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4790 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4791 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4792 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4793 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4794 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4795 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4796 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4797 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4798 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4799 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4800 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4801 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4802 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4803 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4804 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4805 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4806 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4807 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4808 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4809 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4810 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4811 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4812 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4813 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4814 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4815 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4816 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4817 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4818 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4819 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4820 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4821 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4822 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4823 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4824 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4825 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4826 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4827 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4828 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4829 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4830 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4831 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4832 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4833 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4834 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4835 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4836 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4837 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4838 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4839 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4840 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4841 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4842 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4843 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4844 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4845 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4846 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4847 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4848 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4849 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4850 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4851 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4852 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4853 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4854 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4855 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4856 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4857 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4858 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4859 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4860 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4861 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4862 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4863
AnnaBridge 171:3a7713b1edbc 4864 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4865 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4866 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4867 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4868 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4869 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4870 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4871 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4872 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4873 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4874 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4875 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4876 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4877 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4878 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4879 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4880 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4881 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4882 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4883 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4884 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4885 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4886 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4887 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4888 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4889 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4890 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4891 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4892 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4893 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4894 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4895 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4896 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4897 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4898 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4899 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4900 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4901 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4902 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4903 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4904 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4905 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4906 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4907 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4908 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4909 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4910 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4911 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4912 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4913 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4914 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4915 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4916 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4917 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4918 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4919 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4920 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4921 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4922 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4923 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4924 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4925 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4926 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4927 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4928 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4929 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4930 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4931 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4932 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4933 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4934 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4935 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4936 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4937 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4938 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4939 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4940 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4941 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4942 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4943 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4944 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4945 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4946 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4947 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4948 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4949 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4950 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4951 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4952 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4953 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4954 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4955 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4956 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4957 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4958 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4959 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4960 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4961
AnnaBridge 171:3a7713b1edbc 4962 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4963 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4964 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4965 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4966 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4967 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4968 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4969 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4970 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4971 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4972 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4973 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4974 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4975 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4976 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4977 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4978 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4979 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4980 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4981 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4982 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4983 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4984 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4985 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4986 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4987 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4988 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4989 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4990 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4991 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4992 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4993 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4994 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4995 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4996 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4997 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4998 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4999 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5000 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5001 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5002 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5003 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5004 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5005 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5006 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5007 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5008 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5009 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5010 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5011 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5012 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5013 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5014 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5015 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5016 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5017 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5018 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5019 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5020 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5021 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5022 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5023 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5024 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5025 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5026 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5027 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5028 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5029 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5030 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5031 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5032 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5033 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5034 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5035 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5036 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5037 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5038 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5039 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5040 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5041 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5042 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5043 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5044 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5045 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5046 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5047 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5048 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5049 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5050 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5051 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5052 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5053 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5054 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5055 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5056 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5057 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5058 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5059
AnnaBridge 171:3a7713b1edbc 5060 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5061 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5062 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5063 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5064 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5065 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5066 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5067 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5068 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5069 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5070 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5071 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5072 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5073 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5074 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5075 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5076 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5077 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5078 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5079 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5080 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5081 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5082 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5083 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5084 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5085 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5086 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5087 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5088 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5089 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5090 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5091 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5092 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5093 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5094 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5095 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5096 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5097 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5098 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5099 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5100 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5101 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5102 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5103 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5104 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5105 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5106 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5107 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5108 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5109 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5110 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5111 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5112 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5113 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5114 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5115 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5116 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5117 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5118 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5119 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5120 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5121 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5122 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5123 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5124 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5125 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5126 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5127 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5128 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5129 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5130 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5131 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5132 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5133 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5134 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5135 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5136 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5137 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5138 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5139 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5140 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5141 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5142 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5143 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5144 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5145 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5146 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5147 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5148 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5149 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5150 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5151 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5152 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5153 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5154 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5155 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5156 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5157
AnnaBridge 171:3a7713b1edbc 5158 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5159 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5160 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5161 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5162 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5163 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5164 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5165 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5166 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5167 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5168 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5169 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5170 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5171 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5172 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5173 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5174 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5175 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5176 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5177 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5178 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5179 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5180 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5181 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5182 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5183 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5184 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5185 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5186 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5187 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5188 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5189 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5190 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5191 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5192 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5193 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5194 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5195 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5196 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5197 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5198 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5199 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5200 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5201 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5202 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5203 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5204 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5205 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5206 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5207 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5208 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5209 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5210 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5211 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5212 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5213 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5214 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5215 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5216 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5217 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5218 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5219 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5220 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5221 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5222 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5223 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5224 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5225 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5226 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5227 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5228 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5229 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5230 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5231 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5232 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5233 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5234 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5235 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5236 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5237 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5238 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5239 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5240 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5241 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5242 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5243 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5244 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5245 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5246 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5247 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5248 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5249 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5250 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5251 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5252 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5253 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5254 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5255
AnnaBridge 171:3a7713b1edbc 5256 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5257 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5258 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5259 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5260 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5261 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5262 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5263 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5264 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5265 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5266 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5267 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5268 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5269 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5270 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5271 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5272 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5273 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5274 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5275 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5276 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5277 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5278 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5279 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5280 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5281 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5282 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5283 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5284 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5285 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5286 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5287 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5288 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5289 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5290 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5291 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5292 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5293 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5294 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5295 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5296 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5297 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5298 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5299 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5300 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5301 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5302 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5303 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5304 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5305 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5306 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5307 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5308 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5309 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5310 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5311 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5312 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5313 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5314 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5315 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5316 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5317 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5318 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5319 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5320 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5321 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5322 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5323 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5324 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5325 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5326 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5327 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5328 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5329 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5330 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5331 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5332 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5333 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5334 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5335 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5336 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5337 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5338 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5339 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5340 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5341 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5342 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5343 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5344 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5345 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5346 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5347 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5348 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5349 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5350 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5351 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5352 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5353
AnnaBridge 171:3a7713b1edbc 5354 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5355 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5356 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5357 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5358 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5359 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5360 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5361 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5362 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5363 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5364 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5365 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5366 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5367 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5368 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5369 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5370 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5371 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5372 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5373 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5374 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5375 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5376 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5377 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5378 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5379 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5380 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5381 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5382 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5383 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5384 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5385 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5386 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5387 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5388 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5389 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5390 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5391 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5392 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5393 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5394 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5395 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5396 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5397 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5398 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5399 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5400 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5401 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5402 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5403 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5404 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5405 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5406 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5407 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5408 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5409 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5410 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5411 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5412 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5413 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5414 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5415 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5416 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5417 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5418 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5419 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5420 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5421 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5422 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5423 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5424 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5425 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5426 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5427 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5428 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5429 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5430 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5431 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5432 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5433 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5434 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5435 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5436 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5437 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5438 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5439 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5440 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5441 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5442 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5443 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5444 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5445 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5446 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5447 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5448 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5449 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5450 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5451
AnnaBridge 171:3a7713b1edbc 5452 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5453 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5454 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5455 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5456 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5457 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5458 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5459 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5460 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5461 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5462 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5463 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5464 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5465 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5466 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5467 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5468 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5469 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5470 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5471 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5472 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5473 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5474 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5475 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5476 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5477 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5478 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5479 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5480 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5481 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5482 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5483 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5484 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5485 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5486 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5487 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5488 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5489 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5490 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5491 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5492 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5493 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5494 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5495 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5496 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5497 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5498 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5499 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5500 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5501 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5502 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5503 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5504 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5505 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5506 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5507 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5508 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5509 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5510 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5511 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5512 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5513 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5514 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5515 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5516 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5517 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5518 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5519 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5520 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5521 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5522 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5523 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5524 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5525 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5526 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5527 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5528 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5529 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5530 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5531 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5532 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5533 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5534 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5535 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5536 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5537 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5538 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5539 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5540 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5541 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5542 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5543 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5544 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5545 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5546 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5547 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5548 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5549
AnnaBridge 171:3a7713b1edbc 5550 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5551 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5552 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5553 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5554 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5555 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5556 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5557 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5558 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5559 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5560 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5561 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5562 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5563 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5564 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5565 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5566 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5567 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5568 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5569 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5570 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5571 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5572 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5573 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5574 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5575 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5576 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5577 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5578 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5579 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5580 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5581 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5582 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5583 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5584 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5585 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5586 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5587 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5588 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5589 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5590 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5591 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5592 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5593 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5594 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5595 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5596 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5597 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5598 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5599 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5600 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5601 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5602 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5603 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5604 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5605 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5606 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5607 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5608 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5609 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5610 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5611 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5612 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5613 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5614 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5615 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5616 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5617 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5618 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5619 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5620 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5621 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5622 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5623 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5624 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5625 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5626 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5627 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5628 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5629 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5630 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5631 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5632 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5633 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5634 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5635 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5636 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5637 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5638 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5639 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5640 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5641 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5642 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5643 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5644 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5645 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5646 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5647
AnnaBridge 171:3a7713b1edbc 5648 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5649 /* */
AnnaBridge 171:3a7713b1edbc 5650 /* CRC calculation unit */
AnnaBridge 171:3a7713b1edbc 5651 /* */
AnnaBridge 171:3a7713b1edbc 5652 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5653 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 171:3a7713b1edbc 5654 #define CRC_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5655 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5656 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 171:3a7713b1edbc 5657
AnnaBridge 171:3a7713b1edbc 5658 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 171:3a7713b1edbc 5659 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5660 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5661 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 171:3a7713b1edbc 5662
AnnaBridge 171:3a7713b1edbc 5663 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 5664 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5665 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5666 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
AnnaBridge 171:3a7713b1edbc 5667 #define CRC_CR_POLYSIZE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5668 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 5669 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
AnnaBridge 171:3a7713b1edbc 5670 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5671 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5672 #define CRC_CR_REV_IN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5673 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 5674 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
AnnaBridge 171:3a7713b1edbc 5675 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5676 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5677 #define CRC_CR_REV_OUT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5678 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5679 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 171:3a7713b1edbc 5680
AnnaBridge 171:3a7713b1edbc 5681 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 171:3a7713b1edbc 5682 #define CRC_INIT_INIT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5683 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5684 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
AnnaBridge 171:3a7713b1edbc 5685
AnnaBridge 171:3a7713b1edbc 5686 /******************* Bit definition for CRC_POL register ********************/
AnnaBridge 171:3a7713b1edbc 5687 #define CRC_POL_POL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5688 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5689 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
AnnaBridge 171:3a7713b1edbc 5690
AnnaBridge 171:3a7713b1edbc 5691 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5692 /* */
AnnaBridge 171:3a7713b1edbc 5693 /* CRS Clock Recovery System */
AnnaBridge 171:3a7713b1edbc 5694 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5695
AnnaBridge 171:3a7713b1edbc 5696 /******************* Bit definition for CRS_CR register *********************/
AnnaBridge 171:3a7713b1edbc 5697 #define CRS_CR_SYNCOKIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5698 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5699 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
AnnaBridge 171:3a7713b1edbc 5700 #define CRS_CR_SYNCWARNIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5701 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5702 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
AnnaBridge 171:3a7713b1edbc 5703 #define CRS_CR_ERRIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5704 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5705 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
AnnaBridge 171:3a7713b1edbc 5706 #define CRS_CR_ESYNCIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5707 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5708 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
AnnaBridge 171:3a7713b1edbc 5709 #define CRS_CR_CEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5710 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5711 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
AnnaBridge 171:3a7713b1edbc 5712 #define CRS_CR_AUTOTRIMEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5713 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5714 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
AnnaBridge 171:3a7713b1edbc 5715 #define CRS_CR_SWSYNC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5716 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5717 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
AnnaBridge 171:3a7713b1edbc 5718 #define CRS_CR_TRIM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5719 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
AnnaBridge 171:3a7713b1edbc 5720 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
AnnaBridge 171:3a7713b1edbc 5721
AnnaBridge 171:3a7713b1edbc 5722 /******************* Bit definition for CRS_CFGR register *********************/
AnnaBridge 171:3a7713b1edbc 5723 #define CRS_CFGR_RELOAD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5724 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5725 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
AnnaBridge 171:3a7713b1edbc 5726 #define CRS_CFGR_FELIM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5727 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 5728 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
AnnaBridge 171:3a7713b1edbc 5729
AnnaBridge 171:3a7713b1edbc 5730 #define CRS_CFGR_SYNCDIV_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5731 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 5732 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
AnnaBridge 171:3a7713b1edbc 5733 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5734 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5735 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5736
AnnaBridge 171:3a7713b1edbc 5737 #define CRS_CFGR_SYNCSRC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5738 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 5739 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
AnnaBridge 171:3a7713b1edbc 5740 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5741 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5742
AnnaBridge 171:3a7713b1edbc 5743 #define CRS_CFGR_SYNCPOL_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5744 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5745 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
AnnaBridge 171:3a7713b1edbc 5746
AnnaBridge 171:3a7713b1edbc 5747 /******************* Bit definition for CRS_ISR register *********************/
AnnaBridge 171:3a7713b1edbc 5748 #define CRS_ISR_SYNCOKF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5749 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5750 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
AnnaBridge 171:3a7713b1edbc 5751 #define CRS_ISR_SYNCWARNF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5752 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5753 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
AnnaBridge 171:3a7713b1edbc 5754 #define CRS_ISR_ERRF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5755 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5756 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
AnnaBridge 171:3a7713b1edbc 5757 #define CRS_ISR_ESYNCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5758 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5759 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
AnnaBridge 171:3a7713b1edbc 5760 #define CRS_ISR_SYNCERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5761 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5762 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
AnnaBridge 171:3a7713b1edbc 5763 #define CRS_ISR_SYNCMISS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5764 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5765 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
AnnaBridge 171:3a7713b1edbc 5766 #define CRS_ISR_TRIMOVF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5767 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5768 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
AnnaBridge 171:3a7713b1edbc 5769 #define CRS_ISR_FEDIR_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5770 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5771 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
AnnaBridge 171:3a7713b1edbc 5772 #define CRS_ISR_FECAP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5773 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 5774 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
AnnaBridge 171:3a7713b1edbc 5775
AnnaBridge 171:3a7713b1edbc 5776 /******************* Bit definition for CRS_ICR register *********************/
AnnaBridge 171:3a7713b1edbc 5777 #define CRS_ICR_SYNCOKC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5778 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5779 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
AnnaBridge 171:3a7713b1edbc 5780 #define CRS_ICR_SYNCWARNC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5781 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5782 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
AnnaBridge 171:3a7713b1edbc 5783 #define CRS_ICR_ERRC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5784 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5785 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
AnnaBridge 171:3a7713b1edbc 5786 #define CRS_ICR_ESYNCC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5787 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5788 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
AnnaBridge 171:3a7713b1edbc 5789
AnnaBridge 171:3a7713b1edbc 5790 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5791 /* */
AnnaBridge 171:3a7713b1edbc 5792 /* Digital to Analog Converter */
AnnaBridge 171:3a7713b1edbc 5793 /* */
AnnaBridge 171:3a7713b1edbc 5794 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5795 /*
AnnaBridge 171:3a7713b1edbc 5796 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
AnnaBridge 171:3a7713b1edbc 5797 */
AnnaBridge 171:3a7713b1edbc 5798 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
AnnaBridge 171:3a7713b1edbc 5799
AnnaBridge 171:3a7713b1edbc 5800 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 5801 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5802 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5803 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 171:3a7713b1edbc 5804 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5805 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5806 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 171:3a7713b1edbc 5807
AnnaBridge 171:3a7713b1edbc 5808 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5809 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 5810 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 5811 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5812 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5813 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5814
AnnaBridge 171:3a7713b1edbc 5815 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5816 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 5817 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 5818 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5819 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5820
AnnaBridge 171:3a7713b1edbc 5821 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5822 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5823 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 5824 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5825 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5826 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5827 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5828
AnnaBridge 171:3a7713b1edbc 5829 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5830 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5831 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 171:3a7713b1edbc 5832 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5833 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5834 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
AnnaBridge 171:3a7713b1edbc 5835 #define DAC_CR_CEN1_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5836 #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5837 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
AnnaBridge 171:3a7713b1edbc 5838
AnnaBridge 171:3a7713b1edbc 5839 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5840 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5841 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 171:3a7713b1edbc 5842 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5843 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5844 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 171:3a7713b1edbc 5845
AnnaBridge 171:3a7713b1edbc 5846 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5847 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 171:3a7713b1edbc 5848 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 5849 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5850 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5851 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5852
AnnaBridge 171:3a7713b1edbc 5853 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5854 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 5855 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 5856 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5857 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5858
AnnaBridge 171:3a7713b1edbc 5859 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5860 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5861 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 5862 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5863 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5864 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5865 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5866
AnnaBridge 171:3a7713b1edbc 5867 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5868 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5869 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 171:3a7713b1edbc 5870 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5871 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5872 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
AnnaBridge 171:3a7713b1edbc 5873 #define DAC_CR_CEN2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5874 #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5875 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
AnnaBridge 171:3a7713b1edbc 5876
AnnaBridge 171:3a7713b1edbc 5877 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 171:3a7713b1edbc 5878 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5879 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5880 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 171:3a7713b1edbc 5881 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5882 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5883 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 171:3a7713b1edbc 5884
AnnaBridge 171:3a7713b1edbc 5885 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 5886 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5887 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5888 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5889
AnnaBridge 171:3a7713b1edbc 5890 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 171:3a7713b1edbc 5891 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5892 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5893 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5894
AnnaBridge 171:3a7713b1edbc 5895 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 171:3a7713b1edbc 5896 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5897 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5898 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5899
AnnaBridge 171:3a7713b1edbc 5900 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5901 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5902 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5903 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5904
AnnaBridge 171:3a7713b1edbc 5905 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 171:3a7713b1edbc 5906 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5907 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5908 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5909
AnnaBridge 171:3a7713b1edbc 5910 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5911 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5912 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5913 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5914
AnnaBridge 171:3a7713b1edbc 5915 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 171:3a7713b1edbc 5916 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5917 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5918 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5919 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5920 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 5921 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5922
AnnaBridge 171:3a7713b1edbc 5923 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 171:3a7713b1edbc 5924 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5925 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5926 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5927 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5928 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 171:3a7713b1edbc 5929 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5930
AnnaBridge 171:3a7713b1edbc 5931 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 171:3a7713b1edbc 5932 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5933 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5934 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5935 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5936 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 5937 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5938
AnnaBridge 171:3a7713b1edbc 5939 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 171:3a7713b1edbc 5940 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5941 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5942 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 171:3a7713b1edbc 5943
AnnaBridge 171:3a7713b1edbc 5944 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 171:3a7713b1edbc 5945 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5946 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5947 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 171:3a7713b1edbc 5948
AnnaBridge 171:3a7713b1edbc 5949 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 5950 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5951 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5952 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 5953 #define DAC_SR_CAL_FLAG1_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5954 #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5955 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
AnnaBridge 171:3a7713b1edbc 5956 #define DAC_SR_BWST1_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5957 #define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5958 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
AnnaBridge 171:3a7713b1edbc 5959
AnnaBridge 171:3a7713b1edbc 5960 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5961 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5962 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 5963 #define DAC_SR_CAL_FLAG2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5964 #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5965 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
AnnaBridge 171:3a7713b1edbc 5966 #define DAC_SR_BWST2_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5967 #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5968 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
AnnaBridge 171:3a7713b1edbc 5969
AnnaBridge 171:3a7713b1edbc 5970 /******************* Bit definition for DAC_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 5971 #define DAC_CCR_OTRIM1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5972 #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 5973 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
AnnaBridge 171:3a7713b1edbc 5974 #define DAC_CCR_OTRIM2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5975 #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 5976 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
AnnaBridge 171:3a7713b1edbc 5977
AnnaBridge 171:3a7713b1edbc 5978 /******************* Bit definition for DAC_MCR register *******************/
AnnaBridge 171:3a7713b1edbc 5979 #define DAC_MCR_MODE1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5980 #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 5981 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
AnnaBridge 171:3a7713b1edbc 5982 #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5983 #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5984 #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5985
AnnaBridge 171:3a7713b1edbc 5986 #define DAC_MCR_MODE2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5987 #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 5988 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
AnnaBridge 171:3a7713b1edbc 5989 #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5990 #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5991 #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5992
AnnaBridge 171:3a7713b1edbc 5993 /****************** Bit definition for DAC_SHSR1 register ******************/
AnnaBridge 171:3a7713b1edbc 5994 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5995 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 5996 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
AnnaBridge 171:3a7713b1edbc 5997
AnnaBridge 171:3a7713b1edbc 5998 /****************** Bit definition for DAC_SHSR2 register ******************/
AnnaBridge 171:3a7713b1edbc 5999 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6000 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 6001 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
AnnaBridge 171:3a7713b1edbc 6002
AnnaBridge 171:3a7713b1edbc 6003 /****************** Bit definition for DAC_SHHR register ******************/
AnnaBridge 171:3a7713b1edbc 6004 #define DAC_SHHR_THOLD1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6005 #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 6006 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
AnnaBridge 171:3a7713b1edbc 6007 #define DAC_SHHR_THOLD2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6008 #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
AnnaBridge 171:3a7713b1edbc 6009 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
AnnaBridge 171:3a7713b1edbc 6010
AnnaBridge 171:3a7713b1edbc 6011 /****************** Bit definition for DAC_SHRR register ******************/
AnnaBridge 171:3a7713b1edbc 6012 #define DAC_SHRR_TREFRESH1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6013 #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6014 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
AnnaBridge 171:3a7713b1edbc 6015 #define DAC_SHRR_TREFRESH2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6016 #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 6017 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
AnnaBridge 171:3a7713b1edbc 6018
AnnaBridge 171:3a7713b1edbc 6019 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6020 /* */
AnnaBridge 171:3a7713b1edbc 6021 /* DMA Controller (DMA) */
AnnaBridge 171:3a7713b1edbc 6022 /* */
AnnaBridge 171:3a7713b1edbc 6023 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6024
AnnaBridge 171:3a7713b1edbc 6025 /******************* Bit definition for DMA_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 6026 #define DMA_ISR_GIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6027 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6028 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6029 #define DMA_ISR_TCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6030 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6031 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6032 #define DMA_ISR_HTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6033 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6034 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6035 #define DMA_ISR_TEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6036 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6037 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6038 #define DMA_ISR_GIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6039 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6040 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6041 #define DMA_ISR_TCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6042 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6043 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6044 #define DMA_ISR_HTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6045 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6046 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6047 #define DMA_ISR_TEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6048 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6049 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6050 #define DMA_ISR_GIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6051 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6052 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6053 #define DMA_ISR_TCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6054 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6055 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6056 #define DMA_ISR_HTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6057 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6058 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6059 #define DMA_ISR_TEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6060 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6061 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6062 #define DMA_ISR_GIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6063 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6064 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6065 #define DMA_ISR_TCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6066 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6067 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6068 #define DMA_ISR_HTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6069 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6070 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6071 #define DMA_ISR_TEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6072 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6073 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6074 #define DMA_ISR_GIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6075 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6076 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6077 #define DMA_ISR_TCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6078 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6079 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6080 #define DMA_ISR_HTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6081 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6082 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6083 #define DMA_ISR_TEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6084 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6085 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6086 #define DMA_ISR_GIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6087 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6088 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6089 #define DMA_ISR_TCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6090 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6091 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6092 #define DMA_ISR_HTIF6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6093 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6094 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6095 #define DMA_ISR_TEIF6_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6096 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6097 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6098 #define DMA_ISR_GIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6099 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6100 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6101 #define DMA_ISR_TCIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6102 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6103 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6104 #define DMA_ISR_HTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6105 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6106 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6107 #define DMA_ISR_TEIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6108 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6109 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6110
AnnaBridge 171:3a7713b1edbc 6111 /******************* Bit definition for DMA_IFCR register *******************/
AnnaBridge 171:3a7713b1edbc 6112 #define DMA_IFCR_CGIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6113 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6114 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
AnnaBridge 171:3a7713b1edbc 6115 #define DMA_IFCR_CTCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6116 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6117 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6118 #define DMA_IFCR_CHTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6119 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6120 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6121 #define DMA_IFCR_CTEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6122 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6123 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6124 #define DMA_IFCR_CGIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6125 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6126 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6127 #define DMA_IFCR_CTCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6128 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6129 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6130 #define DMA_IFCR_CHTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6131 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6132 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6133 #define DMA_IFCR_CTEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6134 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6135 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6136 #define DMA_IFCR_CGIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6137 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6138 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6139 #define DMA_IFCR_CTCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6140 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6141 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6142 #define DMA_IFCR_CHTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6143 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6144 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6145 #define DMA_IFCR_CTEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6146 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6147 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6148 #define DMA_IFCR_CGIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6149 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6150 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6151 #define DMA_IFCR_CTCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6152 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6153 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6154 #define DMA_IFCR_CHTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6155 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6156 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6157 #define DMA_IFCR_CTEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6158 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6159 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6160 #define DMA_IFCR_CGIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6161 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6162 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6163 #define DMA_IFCR_CTCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6164 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6165 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6166 #define DMA_IFCR_CHTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6167 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6168 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6169 #define DMA_IFCR_CTEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6170 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6171 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6172 #define DMA_IFCR_CGIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6173 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6174 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6175 #define DMA_IFCR_CTCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6176 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6177 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6178 #define DMA_IFCR_CHTIF6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6179 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6180 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6181 #define DMA_IFCR_CTEIF6_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6182 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6183 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6184 #define DMA_IFCR_CGIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6185 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6186 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6187 #define DMA_IFCR_CTCIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6188 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6189 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6190 #define DMA_IFCR_CHTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6191 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6192 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6193 #define DMA_IFCR_CTEIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6194 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6195 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6196
AnnaBridge 171:3a7713b1edbc 6197 /******************* Bit definition for DMA_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 6198 #define DMA_CCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6199 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6200 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
AnnaBridge 171:3a7713b1edbc 6201 #define DMA_CCR_TCIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6202 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6203 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 6204 #define DMA_CCR_HTIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6205 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6206 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
AnnaBridge 171:3a7713b1edbc 6207 #define DMA_CCR_TEIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6208 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6209 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 171:3a7713b1edbc 6210 #define DMA_CCR_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6211 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6212 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 171:3a7713b1edbc 6213 #define DMA_CCR_CIRC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6214 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6215 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 171:3a7713b1edbc 6216 #define DMA_CCR_PINC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6217 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6218 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 171:3a7713b1edbc 6219 #define DMA_CCR_MINC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6220 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6221 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 171:3a7713b1edbc 6222
AnnaBridge 171:3a7713b1edbc 6223 #define DMA_CCR_PSIZE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6224 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6225 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
AnnaBridge 171:3a7713b1edbc 6226 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6227 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6228
AnnaBridge 171:3a7713b1edbc 6229 #define DMA_CCR_MSIZE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6230 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 6231 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
AnnaBridge 171:3a7713b1edbc 6232 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6233 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6234
AnnaBridge 171:3a7713b1edbc 6235 #define DMA_CCR_PL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6236 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 6237 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
AnnaBridge 171:3a7713b1edbc 6238 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6239 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6240
AnnaBridge 171:3a7713b1edbc 6241 #define DMA_CCR_MEM2MEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6242 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6243 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
AnnaBridge 171:3a7713b1edbc 6244
AnnaBridge 171:3a7713b1edbc 6245 /****************** Bit definition for DMA_CNDTR register *******************/
AnnaBridge 171:3a7713b1edbc 6246 #define DMA_CNDTR_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6247 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6248 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 6249
AnnaBridge 171:3a7713b1edbc 6250 /****************** Bit definition for DMA_CPAR register ********************/
AnnaBridge 171:3a7713b1edbc 6251 #define DMA_CPAR_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6252 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6253 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 6254
AnnaBridge 171:3a7713b1edbc 6255 /****************** Bit definition for DMA_CMAR register ********************/
AnnaBridge 171:3a7713b1edbc 6256 #define DMA_CMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6257 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6258 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6259
AnnaBridge 171:3a7713b1edbc 6260
AnnaBridge 171:3a7713b1edbc 6261 /******************* Bit definition for DMA_CSELR register *******************/
AnnaBridge 171:3a7713b1edbc 6262 #define DMA_CSELR_C1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6263 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 6264 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
AnnaBridge 171:3a7713b1edbc 6265 #define DMA_CSELR_C2S_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6266 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6267 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
AnnaBridge 171:3a7713b1edbc 6268 #define DMA_CSELR_C3S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6269 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 6270 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
AnnaBridge 171:3a7713b1edbc 6271 #define DMA_CSELR_C4S_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6272 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6273 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
AnnaBridge 171:3a7713b1edbc 6274 #define DMA_CSELR_C5S_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6275 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 6276 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
AnnaBridge 171:3a7713b1edbc 6277 #define DMA_CSELR_C6S_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6278 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 6279 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
AnnaBridge 171:3a7713b1edbc 6280 #define DMA_CSELR_C7S_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6281 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 6282 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
AnnaBridge 171:3a7713b1edbc 6283
AnnaBridge 171:3a7713b1edbc 6284 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6285 /* */
AnnaBridge 171:3a7713b1edbc 6286 /* External Interrupt/Event Controller */
AnnaBridge 171:3a7713b1edbc 6287 /* */
AnnaBridge 171:3a7713b1edbc 6288 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6289 /******************* Bit definition for EXTI_IMR1 register ******************/
AnnaBridge 171:3a7713b1edbc 6290 #define EXTI_IMR1_IM0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6291 #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6292 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 6293 #define EXTI_IMR1_IM1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6294 #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6295 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 6296 #define EXTI_IMR1_IM2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6297 #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6298 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 6299 #define EXTI_IMR1_IM3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6300 #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6301 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 6302 #define EXTI_IMR1_IM4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6303 #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6304 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 6305 #define EXTI_IMR1_IM5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6306 #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6307 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 6308 #define EXTI_IMR1_IM6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6309 #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6310 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 6311 #define EXTI_IMR1_IM7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6312 #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6313 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 6314 #define EXTI_IMR1_IM8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6315 #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6316 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 6317 #define EXTI_IMR1_IM9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6318 #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6319 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 6320 #define EXTI_IMR1_IM10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6321 #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6322 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 6323 #define EXTI_IMR1_IM11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6324 #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6325 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 6326 #define EXTI_IMR1_IM12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6327 #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6328 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 6329 #define EXTI_IMR1_IM13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6330 #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6331 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 6332 #define EXTI_IMR1_IM14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6333 #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6334 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 6335 #define EXTI_IMR1_IM15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6336 #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6337 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 6338 #define EXTI_IMR1_IM16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6339 #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6340 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 6341 #define EXTI_IMR1_IM17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6342 #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6343 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 6344 #define EXTI_IMR1_IM18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6345 #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6346 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 6347 #define EXTI_IMR1_IM19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6348 #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6349 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 6350 #define EXTI_IMR1_IM20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6351 #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6352 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 6353 #define EXTI_IMR1_IM21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6354 #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6355 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 6356 #define EXTI_IMR1_IM22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6357 #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6358 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 6359 #define EXTI_IMR1_IM23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6360 #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6361 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 6362 #define EXTI_IMR1_IM24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6363 #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6364 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
AnnaBridge 171:3a7713b1edbc 6365 #define EXTI_IMR1_IM25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6366 #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6367 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
AnnaBridge 171:3a7713b1edbc 6368 #define EXTI_IMR1_IM26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6369 #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6370 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
AnnaBridge 171:3a7713b1edbc 6371 #define EXTI_IMR1_IM27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6372 #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6373 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
AnnaBridge 171:3a7713b1edbc 6374 #define EXTI_IMR1_IM28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 6375 #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6376 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
AnnaBridge 171:3a7713b1edbc 6377 #define EXTI_IMR1_IM31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 6378 #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6379 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
AnnaBridge 171:3a7713b1edbc 6380 #define EXTI_IMR1_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6381 #define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */
AnnaBridge 171:3a7713b1edbc 6382 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 171:3a7713b1edbc 6383
AnnaBridge 171:3a7713b1edbc 6384 /******************* Bit definition for EXTI_EMR1 register ******************/
AnnaBridge 171:3a7713b1edbc 6385 #define EXTI_EMR1_EM0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6386 #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6387 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 6388 #define EXTI_EMR1_EM1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6389 #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6390 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 6391 #define EXTI_EMR1_EM2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6392 #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6393 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 6394 #define EXTI_EMR1_EM3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6395 #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6396 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 6397 #define EXTI_EMR1_EM4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6398 #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6399 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 6400 #define EXTI_EMR1_EM5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6401 #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6402 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 6403 #define EXTI_EMR1_EM6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6404 #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6405 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 6406 #define EXTI_EMR1_EM7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6407 #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6408 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 6409 #define EXTI_EMR1_EM8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6410 #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6411 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 6412 #define EXTI_EMR1_EM9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6413 #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6414 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 6415 #define EXTI_EMR1_EM10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6416 #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6417 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 6418 #define EXTI_EMR1_EM11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6419 #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6420 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 6421 #define EXTI_EMR1_EM12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6422 #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6423 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 6424 #define EXTI_EMR1_EM13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6425 #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6426 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 6427 #define EXTI_EMR1_EM14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6428 #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6429 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 6430 #define EXTI_EMR1_EM15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6431 #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6432 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 6433 #define EXTI_EMR1_EM16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6434 #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6435 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 6436 #define EXTI_EMR1_EM17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6437 #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6438 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 6439 #define EXTI_EMR1_EM18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6440 #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6441 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 6442 #define EXTI_EMR1_EM19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6443 #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6444 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 6445 #define EXTI_EMR1_EM20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6446 #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6447 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 6448 #define EXTI_EMR1_EM21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6449 #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6450 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 6451 #define EXTI_EMR1_EM22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6452 #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6453 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 6454 #define EXTI_EMR1_EM23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6455 #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6456 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 6457 #define EXTI_EMR1_EM24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6458 #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6459 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
AnnaBridge 171:3a7713b1edbc 6460 #define EXTI_EMR1_EM25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6461 #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6462 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
AnnaBridge 171:3a7713b1edbc 6463 #define EXTI_EMR1_EM26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6464 #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6465 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
AnnaBridge 171:3a7713b1edbc 6466 #define EXTI_EMR1_EM27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6467 #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6468 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
AnnaBridge 171:3a7713b1edbc 6469 #define EXTI_EMR1_EM28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 6470 #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6471 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
AnnaBridge 171:3a7713b1edbc 6472 #define EXTI_EMR1_EM31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 6473 #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6474 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
AnnaBridge 171:3a7713b1edbc 6475
AnnaBridge 171:3a7713b1edbc 6476 /****************** Bit definition for EXTI_RTSR1 register ******************/
AnnaBridge 171:3a7713b1edbc 6477 #define EXTI_RTSR1_RT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6478 #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6479 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 6480 #define EXTI_RTSR1_RT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6481 #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6482 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 6483 #define EXTI_RTSR1_RT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6484 #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6485 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 6486 #define EXTI_RTSR1_RT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6487 #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6488 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 6489 #define EXTI_RTSR1_RT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6490 #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6491 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 6492 #define EXTI_RTSR1_RT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6493 #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6494 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 6495 #define EXTI_RTSR1_RT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6496 #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6497 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 6498 #define EXTI_RTSR1_RT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6499 #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6500 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 6501 #define EXTI_RTSR1_RT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6502 #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6503 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 6504 #define EXTI_RTSR1_RT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6505 #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6506 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 6507 #define EXTI_RTSR1_RT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6508 #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6509 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 6510 #define EXTI_RTSR1_RT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6511 #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6512 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 6513 #define EXTI_RTSR1_RT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6514 #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6515 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 6516 #define EXTI_RTSR1_RT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6517 #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6518 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 6519 #define EXTI_RTSR1_RT14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6520 #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6521 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 6522 #define EXTI_RTSR1_RT15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6523 #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6524 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 6525 #define EXTI_RTSR1_RT16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6526 #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6527 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 6528 #define EXTI_RTSR1_RT18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6529 #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6530 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 6531 #define EXTI_RTSR1_RT19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6532 #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6533 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 6534 #define EXTI_RTSR1_RT20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6535 #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6536 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 6537 #define EXTI_RTSR1_RT21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6538 #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6539 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 6540 #define EXTI_RTSR1_RT22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6541 #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6542 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 6543
AnnaBridge 171:3a7713b1edbc 6544 /****************** Bit definition for EXTI_FTSR1 register ******************/
AnnaBridge 171:3a7713b1edbc 6545 #define EXTI_FTSR1_FT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6546 #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6547 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 6548 #define EXTI_FTSR1_FT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6549 #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6550 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 6551 #define EXTI_FTSR1_FT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6552 #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6553 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 6554 #define EXTI_FTSR1_FT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6555 #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6556 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 6557 #define EXTI_FTSR1_FT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6558 #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6559 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 6560 #define EXTI_FTSR1_FT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6561 #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6562 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 6563 #define EXTI_FTSR1_FT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6564 #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6565 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 6566 #define EXTI_FTSR1_FT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6567 #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6568 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 6569 #define EXTI_FTSR1_FT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6570 #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6571 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 6572 #define EXTI_FTSR1_FT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6573 #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6574 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 6575 #define EXTI_FTSR1_FT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6576 #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6577 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 6578 #define EXTI_FTSR1_FT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6579 #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6580 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 6581 #define EXTI_FTSR1_FT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6582 #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6583 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 6584 #define EXTI_FTSR1_FT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6585 #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6586 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 6587 #define EXTI_FTSR1_FT14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6588 #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6589 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 6590 #define EXTI_FTSR1_FT15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6591 #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6592 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 6593 #define EXTI_FTSR1_FT16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6594 #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6595 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 6596 #define EXTI_FTSR1_FT18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6597 #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6598 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 6599 #define EXTI_FTSR1_FT19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6600 #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6601 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 6602 #define EXTI_FTSR1_FT20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6603 #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6604 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 6605 #define EXTI_FTSR1_FT21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6606 #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6607 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 6608 #define EXTI_FTSR1_FT22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6609 #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6610 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 6611
AnnaBridge 171:3a7713b1edbc 6612 /****************** Bit definition for EXTI_SWIER1 register *****************/
AnnaBridge 171:3a7713b1edbc 6613 #define EXTI_SWIER1_SWI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6614 #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6615 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 171:3a7713b1edbc 6616 #define EXTI_SWIER1_SWI1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6617 #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6618 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 171:3a7713b1edbc 6619 #define EXTI_SWIER1_SWI2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6620 #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6621 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 171:3a7713b1edbc 6622 #define EXTI_SWIER1_SWI3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6623 #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6624 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 171:3a7713b1edbc 6625 #define EXTI_SWIER1_SWI4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6626 #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6627 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 171:3a7713b1edbc 6628 #define EXTI_SWIER1_SWI5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6629 #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6630 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 171:3a7713b1edbc 6631 #define EXTI_SWIER1_SWI6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6632 #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6633 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 171:3a7713b1edbc 6634 #define EXTI_SWIER1_SWI7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6635 #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6636 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 171:3a7713b1edbc 6637 #define EXTI_SWIER1_SWI8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6638 #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6639 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 171:3a7713b1edbc 6640 #define EXTI_SWIER1_SWI9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6641 #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6642 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 171:3a7713b1edbc 6643 #define EXTI_SWIER1_SWI10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6644 #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6645 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 171:3a7713b1edbc 6646 #define EXTI_SWIER1_SWI11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6647 #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6648 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 171:3a7713b1edbc 6649 #define EXTI_SWIER1_SWI12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6650 #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6651 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 171:3a7713b1edbc 6652 #define EXTI_SWIER1_SWI13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6653 #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6654 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 171:3a7713b1edbc 6655 #define EXTI_SWIER1_SWI14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6656 #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6657 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 171:3a7713b1edbc 6658 #define EXTI_SWIER1_SWI15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6659 #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6660 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 171:3a7713b1edbc 6661 #define EXTI_SWIER1_SWI16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6662 #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6663 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 171:3a7713b1edbc 6664 #define EXTI_SWIER1_SWI18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6665 #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6666 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 171:3a7713b1edbc 6667 #define EXTI_SWIER1_SWI19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6668 #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6669 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 171:3a7713b1edbc 6670 #define EXTI_SWIER1_SWI20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6671 #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6672 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 171:3a7713b1edbc 6673 #define EXTI_SWIER1_SWI21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6674 #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6675 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 171:3a7713b1edbc 6676 #define EXTI_SWIER1_SWI22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6677 #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6678 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 171:3a7713b1edbc 6679
AnnaBridge 171:3a7713b1edbc 6680 /******************* Bit definition for EXTI_PR1 register *******************/
AnnaBridge 171:3a7713b1edbc 6681 #define EXTI_PR1_PIF0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6682 #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6683 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
AnnaBridge 171:3a7713b1edbc 6684 #define EXTI_PR1_PIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6685 #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6686 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
AnnaBridge 171:3a7713b1edbc 6687 #define EXTI_PR1_PIF2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6688 #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6689 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
AnnaBridge 171:3a7713b1edbc 6690 #define EXTI_PR1_PIF3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6691 #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6692 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
AnnaBridge 171:3a7713b1edbc 6693 #define EXTI_PR1_PIF4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6694 #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6695 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
AnnaBridge 171:3a7713b1edbc 6696 #define EXTI_PR1_PIF5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6697 #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6698 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
AnnaBridge 171:3a7713b1edbc 6699 #define EXTI_PR1_PIF6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6700 #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6701 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
AnnaBridge 171:3a7713b1edbc 6702 #define EXTI_PR1_PIF7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6703 #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6704 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
AnnaBridge 171:3a7713b1edbc 6705 #define EXTI_PR1_PIF8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6706 #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6707 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
AnnaBridge 171:3a7713b1edbc 6708 #define EXTI_PR1_PIF9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6709 #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6710 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
AnnaBridge 171:3a7713b1edbc 6711 #define EXTI_PR1_PIF10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6712 #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6713 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
AnnaBridge 171:3a7713b1edbc 6714 #define EXTI_PR1_PIF11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6715 #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6716 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
AnnaBridge 171:3a7713b1edbc 6717 #define EXTI_PR1_PIF12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6718 #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6719 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
AnnaBridge 171:3a7713b1edbc 6720 #define EXTI_PR1_PIF13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6721 #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6722 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
AnnaBridge 171:3a7713b1edbc 6723 #define EXTI_PR1_PIF14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6724 #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6725 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
AnnaBridge 171:3a7713b1edbc 6726 #define EXTI_PR1_PIF15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6727 #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6728 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
AnnaBridge 171:3a7713b1edbc 6729 #define EXTI_PR1_PIF16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6730 #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6731 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
AnnaBridge 171:3a7713b1edbc 6732 #define EXTI_PR1_PIF18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6733 #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6734 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
AnnaBridge 171:3a7713b1edbc 6735 #define EXTI_PR1_PIF19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6736 #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6737 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
AnnaBridge 171:3a7713b1edbc 6738 #define EXTI_PR1_PIF20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6739 #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6740 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
AnnaBridge 171:3a7713b1edbc 6741 #define EXTI_PR1_PIF21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6742 #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6743 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
AnnaBridge 171:3a7713b1edbc 6744 #define EXTI_PR1_PIF22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6745 #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6746 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
AnnaBridge 171:3a7713b1edbc 6747
AnnaBridge 171:3a7713b1edbc 6748 /******************* Bit definition for EXTI_IMR2 register ******************/
AnnaBridge 171:3a7713b1edbc 6749 #define EXTI_IMR2_IM32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6750 #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6751 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
AnnaBridge 171:3a7713b1edbc 6752 #define EXTI_IMR2_IM33_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6753 #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6754 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
AnnaBridge 171:3a7713b1edbc 6755 #define EXTI_IMR2_IM34_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6756 #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6757 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
AnnaBridge 171:3a7713b1edbc 6758 #define EXTI_IMR2_IM35_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6759 #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6760 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
AnnaBridge 171:3a7713b1edbc 6761 #define EXTI_IMR2_IM37_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6762 #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6763 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
AnnaBridge 171:3a7713b1edbc 6764 #define EXTI_IMR2_IM38_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6765 #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6766 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
AnnaBridge 171:3a7713b1edbc 6767 #define EXTI_IMR2_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6768 #define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
AnnaBridge 171:3a7713b1edbc 6769 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
AnnaBridge 171:3a7713b1edbc 6770
AnnaBridge 171:3a7713b1edbc 6771 /******************* Bit definition for EXTI_EMR2 register ******************/
AnnaBridge 171:3a7713b1edbc 6772 #define EXTI_EMR2_EM32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6773 #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6774 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
AnnaBridge 171:3a7713b1edbc 6775 #define EXTI_EMR2_EM33_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6776 #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6777 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
AnnaBridge 171:3a7713b1edbc 6778 #define EXTI_EMR2_EM34_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6779 #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6780 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
AnnaBridge 171:3a7713b1edbc 6781 #define EXTI_EMR2_EM35_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6782 #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6783 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
AnnaBridge 171:3a7713b1edbc 6784 #define EXTI_EMR2_EM37_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6785 #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6786 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
AnnaBridge 171:3a7713b1edbc 6787 #define EXTI_EMR2_EM38_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6788 #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6789 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
AnnaBridge 171:3a7713b1edbc 6790 #define EXTI_EMR2_EM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6791 #define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
AnnaBridge 171:3a7713b1edbc 6792 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
AnnaBridge 171:3a7713b1edbc 6793
AnnaBridge 171:3a7713b1edbc 6794 /****************** Bit definition for EXTI_RTSR2 register ******************/
AnnaBridge 171:3a7713b1edbc 6795 #define EXTI_RTSR2_RT35_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6796 #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6797 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
AnnaBridge 171:3a7713b1edbc 6798 #define EXTI_RTSR2_RT37_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6799 #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6800 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
AnnaBridge 171:3a7713b1edbc 6801 #define EXTI_RTSR2_RT38_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6802 #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6803 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
AnnaBridge 171:3a7713b1edbc 6804
AnnaBridge 171:3a7713b1edbc 6805 /****************** Bit definition for EXTI_FTSR2 register ******************/
AnnaBridge 171:3a7713b1edbc 6806 #define EXTI_FTSR2_FT35_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6807 #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6808 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
AnnaBridge 171:3a7713b1edbc 6809 #define EXTI_FTSR2_FT37_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6810 #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6811 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
AnnaBridge 171:3a7713b1edbc 6812 #define EXTI_FTSR2_FT38_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6813 #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6814 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
AnnaBridge 171:3a7713b1edbc 6815
AnnaBridge 171:3a7713b1edbc 6816 /****************** Bit definition for EXTI_SWIER2 register *****************/
AnnaBridge 171:3a7713b1edbc 6817 #define EXTI_SWIER2_SWI35_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6818 #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6819 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
AnnaBridge 171:3a7713b1edbc 6820 #define EXTI_SWIER2_SWI37_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6821 #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6822 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
AnnaBridge 171:3a7713b1edbc 6823 #define EXTI_SWIER2_SWI38_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6824 #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6825 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
AnnaBridge 171:3a7713b1edbc 6826
AnnaBridge 171:3a7713b1edbc 6827 /******************* Bit definition for EXTI_PR2 register *******************/
AnnaBridge 171:3a7713b1edbc 6828 #define EXTI_PR2_PIF35_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6829 #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6830 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
AnnaBridge 171:3a7713b1edbc 6831 #define EXTI_PR2_PIF37_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6832 #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6833 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
AnnaBridge 171:3a7713b1edbc 6834 #define EXTI_PR2_PIF38_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6835 #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6836 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
AnnaBridge 171:3a7713b1edbc 6837
AnnaBridge 171:3a7713b1edbc 6838
AnnaBridge 171:3a7713b1edbc 6839 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6840 /* */
AnnaBridge 171:3a7713b1edbc 6841 /* FLASH */
AnnaBridge 171:3a7713b1edbc 6842 /* */
AnnaBridge 171:3a7713b1edbc 6843 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6844 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 171:3a7713b1edbc 6845 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6846 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 6847 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 171:3a7713b1edbc 6848 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
AnnaBridge 171:3a7713b1edbc 6849 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
AnnaBridge 171:3a7713b1edbc 6850 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
AnnaBridge 171:3a7713b1edbc 6851 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
AnnaBridge 171:3a7713b1edbc 6852 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
AnnaBridge 171:3a7713b1edbc 6853 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6854 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6855 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 171:3a7713b1edbc 6856 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6857 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6858 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 171:3a7713b1edbc 6859 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6860 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6861 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 171:3a7713b1edbc 6862 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6863 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6864 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 171:3a7713b1edbc 6865 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6866 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6867 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 171:3a7713b1edbc 6868 #define FLASH_ACR_RUN_PD_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6869 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6870 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
AnnaBridge 171:3a7713b1edbc 6871 #define FLASH_ACR_SLEEP_PD_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6872 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6873 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
AnnaBridge 171:3a7713b1edbc 6874
AnnaBridge 171:3a7713b1edbc 6875 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 171:3a7713b1edbc 6876 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6877 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6878 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 171:3a7713b1edbc 6879 #define FLASH_SR_OPERR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6880 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6881 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
AnnaBridge 171:3a7713b1edbc 6882 #define FLASH_SR_PROGERR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6883 #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6884 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
AnnaBridge 171:3a7713b1edbc 6885 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6886 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6887 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 171:3a7713b1edbc 6888 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6889 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6890 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 171:3a7713b1edbc 6891 #define FLASH_SR_SIZERR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6892 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6893 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
AnnaBridge 171:3a7713b1edbc 6894 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6895 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6896 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 171:3a7713b1edbc 6897 #define FLASH_SR_MISERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6898 #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6899 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
AnnaBridge 171:3a7713b1edbc 6900 #define FLASH_SR_FASTERR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6901 #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6902 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
AnnaBridge 171:3a7713b1edbc 6903 #define FLASH_SR_RDERR_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6904 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6905 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 171:3a7713b1edbc 6906 #define FLASH_SR_OPTVERR_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6907 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6908 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
AnnaBridge 171:3a7713b1edbc 6909 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6910 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6911 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 171:3a7713b1edbc 6912 #define FLASH_SR_PEMPTY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6913 #define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6914 #define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
AnnaBridge 171:3a7713b1edbc 6915
AnnaBridge 171:3a7713b1edbc 6916 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 171:3a7713b1edbc 6917 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6918 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6919 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 171:3a7713b1edbc 6920 #define FLASH_CR_PER_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6921 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6922 #define FLASH_CR_PER FLASH_CR_PER_Msk
AnnaBridge 171:3a7713b1edbc 6923 #define FLASH_CR_MER1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6924 #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6925 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
AnnaBridge 171:3a7713b1edbc 6926 #define FLASH_CR_PNB_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6927 #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
AnnaBridge 171:3a7713b1edbc 6928 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
AnnaBridge 171:3a7713b1edbc 6929 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6930 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6931 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 171:3a7713b1edbc 6932 #define FLASH_CR_OPTSTRT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6933 #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6934 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
AnnaBridge 171:3a7713b1edbc 6935 #define FLASH_CR_FSTPG_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6936 #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6937 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
AnnaBridge 171:3a7713b1edbc 6938 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6939 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6940 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 171:3a7713b1edbc 6941 #define FLASH_CR_ERRIE_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6942 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6943 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
AnnaBridge 171:3a7713b1edbc 6944 #define FLASH_CR_RDERRIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6945 #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6946 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
AnnaBridge 171:3a7713b1edbc 6947 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6948 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6949 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
AnnaBridge 171:3a7713b1edbc 6950 #define FLASH_CR_OPTLOCK_Pos (30U)
AnnaBridge 171:3a7713b1edbc 6951 #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6952 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
AnnaBridge 171:3a7713b1edbc 6953 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 6954 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6955 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 171:3a7713b1edbc 6956
AnnaBridge 171:3a7713b1edbc 6957 /******************* Bits definition for FLASH_ECCR register ***************/
AnnaBridge 171:3a7713b1edbc 6958 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6959 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 6960 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
AnnaBridge 171:3a7713b1edbc 6961 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6962 #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6963 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
AnnaBridge 171:3a7713b1edbc 6964 #define FLASH_ECCR_ECCIE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6965 #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6966 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
AnnaBridge 171:3a7713b1edbc 6967 #define FLASH_ECCR_ECCC_Pos (30U)
AnnaBridge 171:3a7713b1edbc 6968 #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6969 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
AnnaBridge 171:3a7713b1edbc 6970 #define FLASH_ECCR_ECCD_Pos (31U)
AnnaBridge 171:3a7713b1edbc 6971 #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6972 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
AnnaBridge 171:3a7713b1edbc 6973
AnnaBridge 171:3a7713b1edbc 6974 /******************* Bits definition for FLASH_OPTR register ***************/
AnnaBridge 171:3a7713b1edbc 6975 #define FLASH_OPTR_RDP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6976 #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6977 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
AnnaBridge 171:3a7713b1edbc 6978 #define FLASH_OPTR_BOR_LEV_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6979 #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 6980 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
AnnaBridge 171:3a7713b1edbc 6981 #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
AnnaBridge 171:3a7713b1edbc 6982 #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6983 #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6984 #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6985 #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6986 #define FLASH_OPTR_nRST_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6987 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6988 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6989 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6990 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6991 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
AnnaBridge 171:3a7713b1edbc 6992 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6993 #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6994 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
AnnaBridge 171:3a7713b1edbc 6995 #define FLASH_OPTR_IWDG_SW_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6996 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6997 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
AnnaBridge 171:3a7713b1edbc 6998 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6999 #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7000 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7001 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7002 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7003 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
AnnaBridge 171:3a7713b1edbc 7004 #define FLASH_OPTR_WWDG_SW_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7005 #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7006 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
AnnaBridge 171:3a7713b1edbc 7007 #define FLASH_OPTR_nBOOT1_Pos (23U)
AnnaBridge 171:3a7713b1edbc 7008 #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7009 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
AnnaBridge 171:3a7713b1edbc 7010 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7011 #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7012 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
AnnaBridge 171:3a7713b1edbc 7013 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 7014 #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7015 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
AnnaBridge 171:3a7713b1edbc 7016 #define FLASH_OPTR_nSWBOOT0_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7017 #define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7018 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
AnnaBridge 171:3a7713b1edbc 7019 #define FLASH_OPTR_nBOOT0_Pos (27U)
AnnaBridge 171:3a7713b1edbc 7020 #define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7021 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
AnnaBridge 171:3a7713b1edbc 7022
AnnaBridge 171:3a7713b1edbc 7023 /****************** Bits definition for FLASH_PCROP1SR register **********/
AnnaBridge 171:3a7713b1edbc 7024 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7025 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7026 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
AnnaBridge 171:3a7713b1edbc 7027
AnnaBridge 171:3a7713b1edbc 7028 /****************** Bits definition for FLASH_PCROP1ER register ***********/
AnnaBridge 171:3a7713b1edbc 7029 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7030 #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7031 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
AnnaBridge 171:3a7713b1edbc 7032 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
AnnaBridge 171:3a7713b1edbc 7033 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7034 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
AnnaBridge 171:3a7713b1edbc 7035
AnnaBridge 171:3a7713b1edbc 7036 /****************** Bits definition for FLASH_WRP1AR register ***************/
AnnaBridge 171:3a7713b1edbc 7037 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7038 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 7039 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
AnnaBridge 171:3a7713b1edbc 7040 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7041 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 7042 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
AnnaBridge 171:3a7713b1edbc 7043
AnnaBridge 171:3a7713b1edbc 7044 /****************** Bits definition for FLASH_WRPB1R register ***************/
AnnaBridge 171:3a7713b1edbc 7045 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7046 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 7047 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
AnnaBridge 171:3a7713b1edbc 7048 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7049 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 7050 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
AnnaBridge 171:3a7713b1edbc 7051
AnnaBridge 171:3a7713b1edbc 7052
AnnaBridge 171:3a7713b1edbc 7053
AnnaBridge 171:3a7713b1edbc 7054
AnnaBridge 171:3a7713b1edbc 7055 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7056 /* */
AnnaBridge 171:3a7713b1edbc 7057 /* General Purpose IOs (GPIO) */
AnnaBridge 171:3a7713b1edbc 7058 /* */
AnnaBridge 171:3a7713b1edbc 7059 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7060 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 171:3a7713b1edbc 7061 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7062 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7063 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 171:3a7713b1edbc 7064 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7065 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7066 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7067 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7068 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 171:3a7713b1edbc 7069 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7070 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7071 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7072 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7073 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 171:3a7713b1edbc 7074 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7075 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7076 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7077 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7078 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 171:3a7713b1edbc 7079 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7080 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7081 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7082 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7083 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 171:3a7713b1edbc 7084 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7085 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7086 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7087 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 7088 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 171:3a7713b1edbc 7089 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7090 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7091 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7092 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7093 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 171:3a7713b1edbc 7094 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7095 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7096 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7097 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 7098 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 171:3a7713b1edbc 7099 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7100 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7101 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7102 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 7103 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 171:3a7713b1edbc 7104 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7105 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7106 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7107 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 7108 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 171:3a7713b1edbc 7109 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7110 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7111 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7112 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 7113 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 171:3a7713b1edbc 7114 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7115 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7116 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7117 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 7118 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 171:3a7713b1edbc 7119 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7120 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7121 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7122 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 7123 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 171:3a7713b1edbc 7124 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7125 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7126 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7127 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 7128 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 171:3a7713b1edbc 7129 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7130 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7131 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7132 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7133 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 171:3a7713b1edbc 7134 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7135 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7136 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7137 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 7138 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 171:3a7713b1edbc 7139 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7140 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7141
AnnaBridge 171:3a7713b1edbc 7142 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7143 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
AnnaBridge 171:3a7713b1edbc 7144 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
AnnaBridge 171:3a7713b1edbc 7145 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
AnnaBridge 171:3a7713b1edbc 7146 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
AnnaBridge 171:3a7713b1edbc 7147 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
AnnaBridge 171:3a7713b1edbc 7148 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
AnnaBridge 171:3a7713b1edbc 7149 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
AnnaBridge 171:3a7713b1edbc 7150 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
AnnaBridge 171:3a7713b1edbc 7151 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
AnnaBridge 171:3a7713b1edbc 7152 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
AnnaBridge 171:3a7713b1edbc 7153 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
AnnaBridge 171:3a7713b1edbc 7154 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
AnnaBridge 171:3a7713b1edbc 7155 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
AnnaBridge 171:3a7713b1edbc 7156 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
AnnaBridge 171:3a7713b1edbc 7157 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
AnnaBridge 171:3a7713b1edbc 7158 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
AnnaBridge 171:3a7713b1edbc 7159 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
AnnaBridge 171:3a7713b1edbc 7160 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
AnnaBridge 171:3a7713b1edbc 7161 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
AnnaBridge 171:3a7713b1edbc 7162 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
AnnaBridge 171:3a7713b1edbc 7163 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
AnnaBridge 171:3a7713b1edbc 7164 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
AnnaBridge 171:3a7713b1edbc 7165 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
AnnaBridge 171:3a7713b1edbc 7166 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
AnnaBridge 171:3a7713b1edbc 7167 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
AnnaBridge 171:3a7713b1edbc 7168 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
AnnaBridge 171:3a7713b1edbc 7169 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
AnnaBridge 171:3a7713b1edbc 7170 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
AnnaBridge 171:3a7713b1edbc 7171 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
AnnaBridge 171:3a7713b1edbc 7172 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
AnnaBridge 171:3a7713b1edbc 7173 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
AnnaBridge 171:3a7713b1edbc 7174 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
AnnaBridge 171:3a7713b1edbc 7175 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
AnnaBridge 171:3a7713b1edbc 7176 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
AnnaBridge 171:3a7713b1edbc 7177 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
AnnaBridge 171:3a7713b1edbc 7178 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
AnnaBridge 171:3a7713b1edbc 7179 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
AnnaBridge 171:3a7713b1edbc 7180 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
AnnaBridge 171:3a7713b1edbc 7181 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
AnnaBridge 171:3a7713b1edbc 7182 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
AnnaBridge 171:3a7713b1edbc 7183 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
AnnaBridge 171:3a7713b1edbc 7184 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
AnnaBridge 171:3a7713b1edbc 7185 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
AnnaBridge 171:3a7713b1edbc 7186 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
AnnaBridge 171:3a7713b1edbc 7187 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
AnnaBridge 171:3a7713b1edbc 7188 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
AnnaBridge 171:3a7713b1edbc 7189 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
AnnaBridge 171:3a7713b1edbc 7190 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
AnnaBridge 171:3a7713b1edbc 7191
AnnaBridge 171:3a7713b1edbc 7192 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 171:3a7713b1edbc 7193 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7194 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7195 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 171:3a7713b1edbc 7196 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7197 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7198 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 171:3a7713b1edbc 7199 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7200 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7201 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 171:3a7713b1edbc 7202 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7203 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7204 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 171:3a7713b1edbc 7205 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7206 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7207 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 171:3a7713b1edbc 7208 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7209 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7210 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 171:3a7713b1edbc 7211 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7212 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7213 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 171:3a7713b1edbc 7214 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7215 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7216 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 171:3a7713b1edbc 7217 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7218 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7219 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 171:3a7713b1edbc 7220 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7221 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7222 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 171:3a7713b1edbc 7223 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7224 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7225 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 171:3a7713b1edbc 7226 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7227 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7228 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 171:3a7713b1edbc 7229 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7230 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7231 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 171:3a7713b1edbc 7232 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7233 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7234 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 171:3a7713b1edbc 7235 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7236 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7237 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 171:3a7713b1edbc 7238 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7239 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7240 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 171:3a7713b1edbc 7241
AnnaBridge 171:3a7713b1edbc 7242 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7243 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 171:3a7713b1edbc 7244 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 171:3a7713b1edbc 7245 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 171:3a7713b1edbc 7246 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 171:3a7713b1edbc 7247 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 171:3a7713b1edbc 7248 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 171:3a7713b1edbc 7249 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 171:3a7713b1edbc 7250 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 171:3a7713b1edbc 7251 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 171:3a7713b1edbc 7252 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 171:3a7713b1edbc 7253 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 171:3a7713b1edbc 7254 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 171:3a7713b1edbc 7255 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 171:3a7713b1edbc 7256 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 171:3a7713b1edbc 7257 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 171:3a7713b1edbc 7258 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
AnnaBridge 171:3a7713b1edbc 7259
AnnaBridge 171:3a7713b1edbc 7260 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 171:3a7713b1edbc 7261 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7262 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7263 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 171:3a7713b1edbc 7264 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7265 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7266 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7267 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7268 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 171:3a7713b1edbc 7269 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7270 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7271 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7272 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7273 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 171:3a7713b1edbc 7274 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7275 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7276 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7277 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7278 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 171:3a7713b1edbc 7279 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7280 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7281 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7282 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7283 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 171:3a7713b1edbc 7284 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7285 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7286 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7287 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 7288 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 171:3a7713b1edbc 7289 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7290 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7291 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7292 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7293 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 171:3a7713b1edbc 7294 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7295 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7296 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7297 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 7298 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 171:3a7713b1edbc 7299 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7300 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7301 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7302 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 7303 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 171:3a7713b1edbc 7304 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7305 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7306 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7307 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 7308 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 171:3a7713b1edbc 7309 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7310 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7311 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7312 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 7313 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 171:3a7713b1edbc 7314 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7315 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7316 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7317 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 7318 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 171:3a7713b1edbc 7319 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7320 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7321 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7322 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 7323 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 171:3a7713b1edbc 7324 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7325 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7326 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7327 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 7328 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 171:3a7713b1edbc 7329 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7330 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7331 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7332 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7333 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 171:3a7713b1edbc 7334 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7335 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7336 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7337 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 7338 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 171:3a7713b1edbc 7339 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7340 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7341
AnnaBridge 171:3a7713b1edbc 7342 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7343 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 171:3a7713b1edbc 7344 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 171:3a7713b1edbc 7345 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 171:3a7713b1edbc 7346 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 171:3a7713b1edbc 7347 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 171:3a7713b1edbc 7348 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 171:3a7713b1edbc 7349 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 171:3a7713b1edbc 7350 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 171:3a7713b1edbc 7351 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 171:3a7713b1edbc 7352 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 171:3a7713b1edbc 7353 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 171:3a7713b1edbc 7354 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 171:3a7713b1edbc 7355 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 171:3a7713b1edbc 7356 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 171:3a7713b1edbc 7357 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 171:3a7713b1edbc 7358 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 171:3a7713b1edbc 7359 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 171:3a7713b1edbc 7360 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 171:3a7713b1edbc 7361 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 171:3a7713b1edbc 7362 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 171:3a7713b1edbc 7363 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 171:3a7713b1edbc 7364 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 171:3a7713b1edbc 7365 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 171:3a7713b1edbc 7366 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 171:3a7713b1edbc 7367 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 171:3a7713b1edbc 7368 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 171:3a7713b1edbc 7369 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 171:3a7713b1edbc 7370 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 171:3a7713b1edbc 7371 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 171:3a7713b1edbc 7372 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 171:3a7713b1edbc 7373 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 171:3a7713b1edbc 7374 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 171:3a7713b1edbc 7375 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 171:3a7713b1edbc 7376 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 171:3a7713b1edbc 7377 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 171:3a7713b1edbc 7378 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 171:3a7713b1edbc 7379 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 171:3a7713b1edbc 7380 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 171:3a7713b1edbc 7381 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 171:3a7713b1edbc 7382 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 171:3a7713b1edbc 7383 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 171:3a7713b1edbc 7384 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 171:3a7713b1edbc 7385 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 171:3a7713b1edbc 7386 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 171:3a7713b1edbc 7387 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 171:3a7713b1edbc 7388 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 171:3a7713b1edbc 7389 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 171:3a7713b1edbc 7390 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
AnnaBridge 171:3a7713b1edbc 7391
AnnaBridge 171:3a7713b1edbc 7392 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 171:3a7713b1edbc 7393 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7394 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7395 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 171:3a7713b1edbc 7396 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7397 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7398 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7399 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7400 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 171:3a7713b1edbc 7401 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7402 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7403 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7404 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7405 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 171:3a7713b1edbc 7406 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7407 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7408 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7409 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7410 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 171:3a7713b1edbc 7411 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7412 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7413 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7414 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7415 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 171:3a7713b1edbc 7416 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7417 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7418 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7419 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 7420 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 171:3a7713b1edbc 7421 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7422 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7423 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7424 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7425 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 171:3a7713b1edbc 7426 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7427 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7428 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7429 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 7430 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 171:3a7713b1edbc 7431 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7432 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7433 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7434 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 7435 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 171:3a7713b1edbc 7436 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7437 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7438 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7439 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 7440 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 171:3a7713b1edbc 7441 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7442 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7443 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7444 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 7445 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 171:3a7713b1edbc 7446 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7447 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7448 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7449 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 7450 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 171:3a7713b1edbc 7451 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7452 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7453 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7454 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 7455 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 171:3a7713b1edbc 7456 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7457 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7458 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7459 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 7460 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 171:3a7713b1edbc 7461 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7462 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7463 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7464 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7465 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 171:3a7713b1edbc 7466 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7467 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7468 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7469 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 7470 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 171:3a7713b1edbc 7471 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7472 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7473
AnnaBridge 171:3a7713b1edbc 7474 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7475 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 171:3a7713b1edbc 7476 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 171:3a7713b1edbc 7477 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 171:3a7713b1edbc 7478 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 171:3a7713b1edbc 7479 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 171:3a7713b1edbc 7480 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 171:3a7713b1edbc 7481 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 171:3a7713b1edbc 7482 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 171:3a7713b1edbc 7483 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 171:3a7713b1edbc 7484 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 171:3a7713b1edbc 7485 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 171:3a7713b1edbc 7486 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 171:3a7713b1edbc 7487 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 171:3a7713b1edbc 7488 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 171:3a7713b1edbc 7489 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 171:3a7713b1edbc 7490 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 171:3a7713b1edbc 7491 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 171:3a7713b1edbc 7492 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 171:3a7713b1edbc 7493 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 171:3a7713b1edbc 7494 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 171:3a7713b1edbc 7495 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 171:3a7713b1edbc 7496 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 171:3a7713b1edbc 7497 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 171:3a7713b1edbc 7498 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 171:3a7713b1edbc 7499 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 171:3a7713b1edbc 7500 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 171:3a7713b1edbc 7501 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 171:3a7713b1edbc 7502 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 171:3a7713b1edbc 7503 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 171:3a7713b1edbc 7504 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 171:3a7713b1edbc 7505 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 171:3a7713b1edbc 7506 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 171:3a7713b1edbc 7507 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 171:3a7713b1edbc 7508 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 171:3a7713b1edbc 7509 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 171:3a7713b1edbc 7510 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 171:3a7713b1edbc 7511 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 171:3a7713b1edbc 7512 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 171:3a7713b1edbc 7513 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 171:3a7713b1edbc 7514 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 171:3a7713b1edbc 7515 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 171:3a7713b1edbc 7516 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 171:3a7713b1edbc 7517 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 171:3a7713b1edbc 7518 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 171:3a7713b1edbc 7519 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 171:3a7713b1edbc 7520 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 171:3a7713b1edbc 7521 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 171:3a7713b1edbc 7522 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
AnnaBridge 171:3a7713b1edbc 7523
AnnaBridge 171:3a7713b1edbc 7524 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 171:3a7713b1edbc 7525 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7526 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7527 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 171:3a7713b1edbc 7528 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7529 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7530 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 171:3a7713b1edbc 7531 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7532 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7533 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 171:3a7713b1edbc 7534 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7535 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7536 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 171:3a7713b1edbc 7537 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7538 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7539 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 171:3a7713b1edbc 7540 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7541 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7542 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 171:3a7713b1edbc 7543 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7544 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7545 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 171:3a7713b1edbc 7546 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7547 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7548 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 171:3a7713b1edbc 7549 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7550 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7551 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 171:3a7713b1edbc 7552 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7553 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7554 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 171:3a7713b1edbc 7555 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7556 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7557 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 171:3a7713b1edbc 7558 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7559 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7560 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 171:3a7713b1edbc 7561 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7562 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7563 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 171:3a7713b1edbc 7564 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7565 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7566 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 171:3a7713b1edbc 7567 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7568 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7569 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 171:3a7713b1edbc 7570 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7571 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7572 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 171:3a7713b1edbc 7573
AnnaBridge 171:3a7713b1edbc 7574 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7575 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 171:3a7713b1edbc 7576 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 171:3a7713b1edbc 7577 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 171:3a7713b1edbc 7578 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 171:3a7713b1edbc 7579 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 171:3a7713b1edbc 7580 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 171:3a7713b1edbc 7581 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 171:3a7713b1edbc 7582 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 171:3a7713b1edbc 7583 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 171:3a7713b1edbc 7584 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 171:3a7713b1edbc 7585 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 171:3a7713b1edbc 7586 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 171:3a7713b1edbc 7587 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 171:3a7713b1edbc 7588 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 171:3a7713b1edbc 7589 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 171:3a7713b1edbc 7590 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
AnnaBridge 171:3a7713b1edbc 7591
AnnaBridge 171:3a7713b1edbc 7592 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 7593 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
AnnaBridge 171:3a7713b1edbc 7594 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
AnnaBridge 171:3a7713b1edbc 7595 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
AnnaBridge 171:3a7713b1edbc 7596 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
AnnaBridge 171:3a7713b1edbc 7597 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
AnnaBridge 171:3a7713b1edbc 7598 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
AnnaBridge 171:3a7713b1edbc 7599 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
AnnaBridge 171:3a7713b1edbc 7600 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
AnnaBridge 171:3a7713b1edbc 7601 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
AnnaBridge 171:3a7713b1edbc 7602 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
AnnaBridge 171:3a7713b1edbc 7603 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
AnnaBridge 171:3a7713b1edbc 7604 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
AnnaBridge 171:3a7713b1edbc 7605 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
AnnaBridge 171:3a7713b1edbc 7606 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
AnnaBridge 171:3a7713b1edbc 7607 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
AnnaBridge 171:3a7713b1edbc 7608 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
AnnaBridge 171:3a7713b1edbc 7609
AnnaBridge 171:3a7713b1edbc 7610 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 171:3a7713b1edbc 7611 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7612 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7613 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 171:3a7713b1edbc 7614 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7615 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7616 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 171:3a7713b1edbc 7617 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7618 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7619 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 171:3a7713b1edbc 7620 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7621 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7622 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 171:3a7713b1edbc 7623 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7624 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7625 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 171:3a7713b1edbc 7626 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7627 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7628 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 171:3a7713b1edbc 7629 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7630 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7631 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 171:3a7713b1edbc 7632 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7633 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7634 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 171:3a7713b1edbc 7635 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7636 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7637 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 171:3a7713b1edbc 7638 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7639 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7640 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 171:3a7713b1edbc 7641 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7642 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7643 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 171:3a7713b1edbc 7644 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7645 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7646 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 171:3a7713b1edbc 7647 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7648 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7649 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 171:3a7713b1edbc 7650 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7651 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7652 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 171:3a7713b1edbc 7653 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7654 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7655 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 171:3a7713b1edbc 7656 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7657 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7658 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 171:3a7713b1edbc 7659
AnnaBridge 171:3a7713b1edbc 7660 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7661 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 171:3a7713b1edbc 7662 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 171:3a7713b1edbc 7663 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 171:3a7713b1edbc 7664 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 171:3a7713b1edbc 7665 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 171:3a7713b1edbc 7666 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 171:3a7713b1edbc 7667 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 171:3a7713b1edbc 7668 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 171:3a7713b1edbc 7669 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 171:3a7713b1edbc 7670 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 171:3a7713b1edbc 7671 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 171:3a7713b1edbc 7672 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 171:3a7713b1edbc 7673 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 171:3a7713b1edbc 7674 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 171:3a7713b1edbc 7675 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 171:3a7713b1edbc 7676 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
AnnaBridge 171:3a7713b1edbc 7677
AnnaBridge 171:3a7713b1edbc 7678 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 7679 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
AnnaBridge 171:3a7713b1edbc 7680 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
AnnaBridge 171:3a7713b1edbc 7681 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
AnnaBridge 171:3a7713b1edbc 7682 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
AnnaBridge 171:3a7713b1edbc 7683 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
AnnaBridge 171:3a7713b1edbc 7684 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
AnnaBridge 171:3a7713b1edbc 7685 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
AnnaBridge 171:3a7713b1edbc 7686 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
AnnaBridge 171:3a7713b1edbc 7687 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
AnnaBridge 171:3a7713b1edbc 7688 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
AnnaBridge 171:3a7713b1edbc 7689 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
AnnaBridge 171:3a7713b1edbc 7690 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
AnnaBridge 171:3a7713b1edbc 7691 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
AnnaBridge 171:3a7713b1edbc 7692 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
AnnaBridge 171:3a7713b1edbc 7693 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
AnnaBridge 171:3a7713b1edbc 7694 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
AnnaBridge 171:3a7713b1edbc 7695
AnnaBridge 171:3a7713b1edbc 7696 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 171:3a7713b1edbc 7697 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7698 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7699 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 171:3a7713b1edbc 7700 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7701 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7702 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 171:3a7713b1edbc 7703 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7704 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7705 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 171:3a7713b1edbc 7706 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7707 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7708 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 171:3a7713b1edbc 7709 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7710 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7711 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 171:3a7713b1edbc 7712 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7713 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7714 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 171:3a7713b1edbc 7715 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7716 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7717 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 171:3a7713b1edbc 7718 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7719 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7720 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 171:3a7713b1edbc 7721 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7722 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7723 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 171:3a7713b1edbc 7724 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7725 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7726 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 171:3a7713b1edbc 7727 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7728 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7729 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 171:3a7713b1edbc 7730 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7731 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7732 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 171:3a7713b1edbc 7733 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7734 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7735 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 171:3a7713b1edbc 7736 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7737 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7738 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 171:3a7713b1edbc 7739 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7740 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7741 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 171:3a7713b1edbc 7742 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7743 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7744 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 171:3a7713b1edbc 7745 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7746 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7747 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 171:3a7713b1edbc 7748 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7749 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7750 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 171:3a7713b1edbc 7751 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7752 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7753 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 171:3a7713b1edbc 7754 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7755 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7756 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 171:3a7713b1edbc 7757 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7758 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7759 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 171:3a7713b1edbc 7760 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 171:3a7713b1edbc 7761 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7762 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 171:3a7713b1edbc 7763 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7764 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7765 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 171:3a7713b1edbc 7766 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 171:3a7713b1edbc 7767 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7768 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 171:3a7713b1edbc 7769 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7770 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7771 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 171:3a7713b1edbc 7772 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 171:3a7713b1edbc 7773 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7774 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 171:3a7713b1edbc 7775 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7776 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7777 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 171:3a7713b1edbc 7778 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 171:3a7713b1edbc 7779 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7780 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 171:3a7713b1edbc 7781 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7782 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7783 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 171:3a7713b1edbc 7784 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 171:3a7713b1edbc 7785 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7786 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 171:3a7713b1edbc 7787 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7788 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7789 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 171:3a7713b1edbc 7790 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 171:3a7713b1edbc 7791 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7792 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 171:3a7713b1edbc 7793
AnnaBridge 171:3a7713b1edbc 7794 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7795 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 171:3a7713b1edbc 7796 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 171:3a7713b1edbc 7797 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 171:3a7713b1edbc 7798 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 171:3a7713b1edbc 7799 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 171:3a7713b1edbc 7800 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 171:3a7713b1edbc 7801 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 171:3a7713b1edbc 7802 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 171:3a7713b1edbc 7803 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 171:3a7713b1edbc 7804 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 171:3a7713b1edbc 7805 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 171:3a7713b1edbc 7806 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 171:3a7713b1edbc 7807 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 171:3a7713b1edbc 7808 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 171:3a7713b1edbc 7809 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 171:3a7713b1edbc 7810 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 171:3a7713b1edbc 7811 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 171:3a7713b1edbc 7812 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 171:3a7713b1edbc 7813 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 171:3a7713b1edbc 7814 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 171:3a7713b1edbc 7815 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 171:3a7713b1edbc 7816 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 171:3a7713b1edbc 7817 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 171:3a7713b1edbc 7818 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 171:3a7713b1edbc 7819 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 171:3a7713b1edbc 7820 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 171:3a7713b1edbc 7821 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 171:3a7713b1edbc 7822 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 171:3a7713b1edbc 7823 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 171:3a7713b1edbc 7824 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 171:3a7713b1edbc 7825 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 171:3a7713b1edbc 7826 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
AnnaBridge 171:3a7713b1edbc 7827
AnnaBridge 171:3a7713b1edbc 7828 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 171:3a7713b1edbc 7829 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7830 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7831 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 171:3a7713b1edbc 7832 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7833 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7834 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 171:3a7713b1edbc 7835 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7836 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7837 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 171:3a7713b1edbc 7838 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7839 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7840 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 171:3a7713b1edbc 7841 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7842 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7843 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 171:3a7713b1edbc 7844 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7845 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7846 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 171:3a7713b1edbc 7847 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7848 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7849 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 171:3a7713b1edbc 7850 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7851 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7852 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 171:3a7713b1edbc 7853 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7854 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7855 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 171:3a7713b1edbc 7856 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7857 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7858 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 171:3a7713b1edbc 7859 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7860 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7861 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 171:3a7713b1edbc 7862 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7863 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7864 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 171:3a7713b1edbc 7865 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7866 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7867 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 171:3a7713b1edbc 7868 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7869 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7870 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 171:3a7713b1edbc 7871 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7872 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7873 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 171:3a7713b1edbc 7874 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7875 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7876 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 171:3a7713b1edbc 7877 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7878 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7879 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 171:3a7713b1edbc 7880
AnnaBridge 171:3a7713b1edbc 7881 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 171:3a7713b1edbc 7882 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7883 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7884 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 171:3a7713b1edbc 7885 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7886 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7887 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7888 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7889 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7890 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7891 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 171:3a7713b1edbc 7892 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7893 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7894 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7895 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7896 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7897 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 7898 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 171:3a7713b1edbc 7899 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7900 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7901 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7902 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7903 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7904 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 7905 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 171:3a7713b1edbc 7906 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7907 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7908 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7909 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7910 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7911 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7912 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 171:3a7713b1edbc 7913 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7914 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7915 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7916 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7917 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7918 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 7919 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 171:3a7713b1edbc 7920 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7921 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7922 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7923 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7924 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7925 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 7926 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 171:3a7713b1edbc 7927 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7928 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7929 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7930 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7931 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7932 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 7933 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 171:3a7713b1edbc 7934 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7935 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7936 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7937 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7938
AnnaBridge 171:3a7713b1edbc 7939 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7940 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 171:3a7713b1edbc 7941 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 171:3a7713b1edbc 7942 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 171:3a7713b1edbc 7943 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 171:3a7713b1edbc 7944 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 171:3a7713b1edbc 7945 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 171:3a7713b1edbc 7946 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 171:3a7713b1edbc 7947 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 171:3a7713b1edbc 7948
AnnaBridge 171:3a7713b1edbc 7949 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 171:3a7713b1edbc 7950 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7951 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7952 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 171:3a7713b1edbc 7953 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7954 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7955 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7956 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7957 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7958 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7959 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 171:3a7713b1edbc 7960 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7961 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7962 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7963 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7964 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7965 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 7966 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 171:3a7713b1edbc 7967 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7968 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7969 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7970 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7971 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7972 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 7973 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 171:3a7713b1edbc 7974 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7975 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7976 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7977 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7978 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7979 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7980 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 171:3a7713b1edbc 7981 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7982 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7983 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7984 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7985 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7986 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 7987 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 171:3a7713b1edbc 7988 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7989 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7990 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7991 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7992 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7993 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 7994 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 171:3a7713b1edbc 7995 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7996 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7997 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7998 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7999 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8000 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8001 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 171:3a7713b1edbc 8002 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8003 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8004 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8005 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8006
AnnaBridge 171:3a7713b1edbc 8007 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8008 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 171:3a7713b1edbc 8009 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 171:3a7713b1edbc 8010 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 171:3a7713b1edbc 8011 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 171:3a7713b1edbc 8012 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 171:3a7713b1edbc 8013 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 171:3a7713b1edbc 8014 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 171:3a7713b1edbc 8015 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 171:3a7713b1edbc 8016
AnnaBridge 171:3a7713b1edbc 8017 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 171:3a7713b1edbc 8018 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8019 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8020 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 171:3a7713b1edbc 8021 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8022 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8023 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 171:3a7713b1edbc 8024 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8025 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8026 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 171:3a7713b1edbc 8027 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8028 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8029 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 171:3a7713b1edbc 8030 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8031 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8032 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 171:3a7713b1edbc 8033 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8034 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8035 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 171:3a7713b1edbc 8036 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8037 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8038 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 171:3a7713b1edbc 8039 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8040 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8041 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 171:3a7713b1edbc 8042 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8043 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8044 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 171:3a7713b1edbc 8045 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8046 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8047 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 171:3a7713b1edbc 8048 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8049 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8050 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 171:3a7713b1edbc 8051 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8052 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8053 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 171:3a7713b1edbc 8054 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8055 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8056 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 171:3a7713b1edbc 8057 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8058 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8059 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 171:3a7713b1edbc 8060 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8061 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8062 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 171:3a7713b1edbc 8063 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8064 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8065 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 171:3a7713b1edbc 8066
AnnaBridge 171:3a7713b1edbc 8067 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8068 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
AnnaBridge 171:3a7713b1edbc 8069 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
AnnaBridge 171:3a7713b1edbc 8070 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
AnnaBridge 171:3a7713b1edbc 8071 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
AnnaBridge 171:3a7713b1edbc 8072 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
AnnaBridge 171:3a7713b1edbc 8073 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
AnnaBridge 171:3a7713b1edbc 8074 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
AnnaBridge 171:3a7713b1edbc 8075 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
AnnaBridge 171:3a7713b1edbc 8076 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
AnnaBridge 171:3a7713b1edbc 8077 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
AnnaBridge 171:3a7713b1edbc 8078 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
AnnaBridge 171:3a7713b1edbc 8079 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
AnnaBridge 171:3a7713b1edbc 8080 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
AnnaBridge 171:3a7713b1edbc 8081 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
AnnaBridge 171:3a7713b1edbc 8082 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
AnnaBridge 171:3a7713b1edbc 8083 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
AnnaBridge 171:3a7713b1edbc 8084
AnnaBridge 171:3a7713b1edbc 8085
AnnaBridge 171:3a7713b1edbc 8086
AnnaBridge 171:3a7713b1edbc 8087 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8088 /* */
AnnaBridge 171:3a7713b1edbc 8089 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 171:3a7713b1edbc 8090 /* */
AnnaBridge 171:3a7713b1edbc 8091 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8092 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 8093 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8094 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8095 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 171:3a7713b1edbc 8096 #define I2C_CR1_TXIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8097 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8098 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 171:3a7713b1edbc 8099 #define I2C_CR1_RXIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8100 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8101 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 171:3a7713b1edbc 8102 #define I2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8103 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8104 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 171:3a7713b1edbc 8105 #define I2C_CR1_NACKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8106 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8107 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 171:3a7713b1edbc 8108 #define I2C_CR1_STOPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8109 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8110 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 8111 #define I2C_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8112 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8113 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 8114 #define I2C_CR1_ERRIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8115 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8116 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 171:3a7713b1edbc 8117 #define I2C_CR1_DNF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8118 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8119 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
AnnaBridge 171:3a7713b1edbc 8120 #define I2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8121 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8122 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 171:3a7713b1edbc 8123 #define I2C_CR1_SWRST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8124 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8125 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
AnnaBridge 171:3a7713b1edbc 8126 #define I2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8127 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8128 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 171:3a7713b1edbc 8129 #define I2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8130 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8131 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 171:3a7713b1edbc 8132 #define I2C_CR1_SBC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8133 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8134 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 171:3a7713b1edbc 8135 #define I2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8136 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8137 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 171:3a7713b1edbc 8138 #define I2C_CR1_WUPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8139 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8140 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
AnnaBridge 171:3a7713b1edbc 8141 #define I2C_CR1_GCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8142 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8143 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 171:3a7713b1edbc 8144 #define I2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8145 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8146 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 171:3a7713b1edbc 8147 #define I2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8148 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8149 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 171:3a7713b1edbc 8150 #define I2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8151 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8152 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 171:3a7713b1edbc 8153 #define I2C_CR1_PECEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8154 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8155 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 171:3a7713b1edbc 8156
AnnaBridge 171:3a7713b1edbc 8157 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 8158 #define I2C_CR2_SADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8159 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8160 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 171:3a7713b1edbc 8161 #define I2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8162 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8163 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 171:3a7713b1edbc 8164 #define I2C_CR2_ADD10_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8165 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8166 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 171:3a7713b1edbc 8167 #define I2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8168 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8169 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 171:3a7713b1edbc 8170 #define I2C_CR2_START_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8171 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8172 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
AnnaBridge 171:3a7713b1edbc 8173 #define I2C_CR2_STOP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8174 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8175 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 171:3a7713b1edbc 8176 #define I2C_CR2_NACK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8177 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8178 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 171:3a7713b1edbc 8179 #define I2C_CR2_NBYTES_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8180 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 8181 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 171:3a7713b1edbc 8182 #define I2C_CR2_RELOAD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8183 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8184 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 171:3a7713b1edbc 8185 #define I2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8186 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8187 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 171:3a7713b1edbc 8188 #define I2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8189 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8190 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 171:3a7713b1edbc 8191
AnnaBridge 171:3a7713b1edbc 8192 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 171:3a7713b1edbc 8193 #define I2C_OAR1_OA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8194 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8195 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 171:3a7713b1edbc 8196 #define I2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8197 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8198 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 171:3a7713b1edbc 8199 #define I2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8200 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8201 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 171:3a7713b1edbc 8202
AnnaBridge 171:3a7713b1edbc 8203 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 171:3a7713b1edbc 8204 #define I2C_OAR2_OA2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8205 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 8206 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 171:3a7713b1edbc 8207 #define I2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8208 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 8209 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 171:3a7713b1edbc 8210 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
AnnaBridge 171:3a7713b1edbc 8211 #define I2C_OAR2_OA2MASK01_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8212 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8213 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 171:3a7713b1edbc 8214 #define I2C_OAR2_OA2MASK02_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8215 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8216 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 171:3a7713b1edbc 8217 #define I2C_OAR2_OA2MASK03_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8218 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 8219 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 171:3a7713b1edbc 8220 #define I2C_OAR2_OA2MASK04_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8221 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8222 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 171:3a7713b1edbc 8223 #define I2C_OAR2_OA2MASK05_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8224 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
AnnaBridge 171:3a7713b1edbc 8225 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 171:3a7713b1edbc 8226 #define I2C_OAR2_OA2MASK06_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8227 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 8228 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 171:3a7713b1edbc 8229 #define I2C_OAR2_OA2MASK07_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8230 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 8231 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 171:3a7713b1edbc 8232 #define I2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8233 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8234 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 171:3a7713b1edbc 8235
AnnaBridge 171:3a7713b1edbc 8236 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 171:3a7713b1edbc 8237 #define I2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8238 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8239 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 171:3a7713b1edbc 8240 #define I2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8241 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 8242 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 171:3a7713b1edbc 8243 #define I2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8244 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8245 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 171:3a7713b1edbc 8246 #define I2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8247 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8248 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 171:3a7713b1edbc 8249 #define I2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8250 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8251 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 171:3a7713b1edbc 8252
AnnaBridge 171:3a7713b1edbc 8253 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 171:3a7713b1edbc 8254 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8255 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 8256 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 171:3a7713b1edbc 8257 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8258 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8259 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 171:3a7713b1edbc 8260 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8261 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8262 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 171:3a7713b1edbc 8263 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8264 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 8265 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
AnnaBridge 171:3a7713b1edbc 8266 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 8267 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8268 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 171:3a7713b1edbc 8269
AnnaBridge 171:3a7713b1edbc 8270 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 171:3a7713b1edbc 8271 #define I2C_ISR_TXE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8272 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8273 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 171:3a7713b1edbc 8274 #define I2C_ISR_TXIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8275 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8276 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 171:3a7713b1edbc 8277 #define I2C_ISR_RXNE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8278 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8279 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 171:3a7713b1edbc 8280 #define I2C_ISR_ADDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8281 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8282 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
AnnaBridge 171:3a7713b1edbc 8283 #define I2C_ISR_NACKF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8284 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8285 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 171:3a7713b1edbc 8286 #define I2C_ISR_STOPF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8287 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8288 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 171:3a7713b1edbc 8289 #define I2C_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8290 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8291 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 171:3a7713b1edbc 8292 #define I2C_ISR_TCR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8293 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8294 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 171:3a7713b1edbc 8295 #define I2C_ISR_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8296 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8297 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 171:3a7713b1edbc 8298 #define I2C_ISR_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8299 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8300 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 171:3a7713b1edbc 8301 #define I2C_ISR_OVR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8302 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8303 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 8304 #define I2C_ISR_PECERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8305 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8306 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 171:3a7713b1edbc 8307 #define I2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8308 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8309 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 171:3a7713b1edbc 8310 #define I2C_ISR_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8311 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8312 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 171:3a7713b1edbc 8313 #define I2C_ISR_BUSY_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8314 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8315 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 171:3a7713b1edbc 8316 #define I2C_ISR_DIR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8317 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8318 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 171:3a7713b1edbc 8319 #define I2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8320 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 8321 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 171:3a7713b1edbc 8322
AnnaBridge 171:3a7713b1edbc 8323 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 171:3a7713b1edbc 8324 #define I2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8325 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8326 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 171:3a7713b1edbc 8327 #define I2C_ICR_NACKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8328 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8329 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 171:3a7713b1edbc 8330 #define I2C_ICR_STOPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8331 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8332 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 171:3a7713b1edbc 8333 #define I2C_ICR_BERRCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8334 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8335 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 171:3a7713b1edbc 8336 #define I2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8337 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8338 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 171:3a7713b1edbc 8339 #define I2C_ICR_OVRCF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8340 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8341 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 171:3a7713b1edbc 8342 #define I2C_ICR_PECCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8343 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8344 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 171:3a7713b1edbc 8345 #define I2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8346 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8347 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 171:3a7713b1edbc 8348 #define I2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8349 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8350 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 171:3a7713b1edbc 8351
AnnaBridge 171:3a7713b1edbc 8352 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 171:3a7713b1edbc 8353 #define I2C_PECR_PEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8354 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8355 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 171:3a7713b1edbc 8356
AnnaBridge 171:3a7713b1edbc 8357 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 171:3a7713b1edbc 8358 #define I2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8359 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8360 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 171:3a7713b1edbc 8361
AnnaBridge 171:3a7713b1edbc 8362 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 171:3a7713b1edbc 8363 #define I2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8364 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8365 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 171:3a7713b1edbc 8366
AnnaBridge 171:3a7713b1edbc 8367 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8368 /* */
AnnaBridge 171:3a7713b1edbc 8369 /* Independent WATCHDOG */
AnnaBridge 171:3a7713b1edbc 8370 /* */
AnnaBridge 171:3a7713b1edbc 8371 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8372 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 8373 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8374 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 8375 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 171:3a7713b1edbc 8376
AnnaBridge 171:3a7713b1edbc 8377 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 171:3a7713b1edbc 8378 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8379 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 8380 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 171:3a7713b1edbc 8381 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8382 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8383 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8384
AnnaBridge 171:3a7713b1edbc 8385 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 171:3a7713b1edbc 8386 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8387 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 8388 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 171:3a7713b1edbc 8389
AnnaBridge 171:3a7713b1edbc 8390 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 8391 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8392 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8393 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 171:3a7713b1edbc 8394 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8395 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8396 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 171:3a7713b1edbc 8397 #define IWDG_SR_WVU_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8398 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8399 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
AnnaBridge 171:3a7713b1edbc 8400
AnnaBridge 171:3a7713b1edbc 8401 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 8402 #define IWDG_WINR_WIN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8403 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 8404 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
AnnaBridge 171:3a7713b1edbc 8405
AnnaBridge 171:3a7713b1edbc 8406 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8407 /* */
AnnaBridge 171:3a7713b1edbc 8408 /* Firewall */
AnnaBridge 171:3a7713b1edbc 8409 /* */
AnnaBridge 171:3a7713b1edbc 8410 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8411
AnnaBridge 171:3a7713b1edbc 8412 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
AnnaBridge 171:3a7713b1edbc 8413 #define FW_CSSA_ADD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8414 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
AnnaBridge 171:3a7713b1edbc 8415 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
AnnaBridge 171:3a7713b1edbc 8416 #define FW_CSL_LENG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8417 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
AnnaBridge 171:3a7713b1edbc 8418 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
AnnaBridge 171:3a7713b1edbc 8419 #define FW_NVDSSA_ADD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8420 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
AnnaBridge 171:3a7713b1edbc 8421 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
AnnaBridge 171:3a7713b1edbc 8422 #define FW_NVDSL_LENG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8423 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
AnnaBridge 171:3a7713b1edbc 8424 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
AnnaBridge 171:3a7713b1edbc 8425 #define FW_VDSSA_ADD_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8426 #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
AnnaBridge 171:3a7713b1edbc 8427 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
AnnaBridge 171:3a7713b1edbc 8428 #define FW_VDSL_LENG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8429 #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
AnnaBridge 171:3a7713b1edbc 8430 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
AnnaBridge 171:3a7713b1edbc 8431
AnnaBridge 171:3a7713b1edbc 8432 /**************************Bit definition for CR register *********************/
AnnaBridge 171:3a7713b1edbc 8433 #define FW_CR_FPA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8434 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8435 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
AnnaBridge 171:3a7713b1edbc 8436 #define FW_CR_VDS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8437 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8438 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
AnnaBridge 171:3a7713b1edbc 8439 #define FW_CR_VDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8440 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8441 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
AnnaBridge 171:3a7713b1edbc 8442
AnnaBridge 171:3a7713b1edbc 8443 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8444 /* */
AnnaBridge 171:3a7713b1edbc 8445 /* Power Control */
AnnaBridge 171:3a7713b1edbc 8446 /* */
AnnaBridge 171:3a7713b1edbc 8447 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8448
AnnaBridge 171:3a7713b1edbc 8449 /******************** Bit definition for PWR_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 8450
AnnaBridge 171:3a7713b1edbc 8451 #define PWR_CR1_LPR_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8452 #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8453 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
AnnaBridge 171:3a7713b1edbc 8454 #define PWR_CR1_VOS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8455 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 8456 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 171:3a7713b1edbc 8457 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8458 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8459 #define PWR_CR1_DBP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8460 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8461 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
AnnaBridge 171:3a7713b1edbc 8462 #define PWR_CR1_LPMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8463 #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 8464 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
AnnaBridge 171:3a7713b1edbc 8465 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
AnnaBridge 171:3a7713b1edbc 8466 #define PWR_CR1_LPMS_STOP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8467 #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8468 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
AnnaBridge 171:3a7713b1edbc 8469 #define PWR_CR1_LPMS_STOP2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8470 #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8471 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
AnnaBridge 171:3a7713b1edbc 8472 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8473 #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8474 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
AnnaBridge 171:3a7713b1edbc 8475 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8476 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8477 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
AnnaBridge 171:3a7713b1edbc 8478
AnnaBridge 171:3a7713b1edbc 8479
AnnaBridge 171:3a7713b1edbc 8480 /******************** Bit definition for PWR_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 8481 #define PWR_CR2_USV_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8482 #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8483 #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
AnnaBridge 171:3a7713b1edbc 8484 /*!< PVME Peripheral Voltage Monitor Enable */
AnnaBridge 171:3a7713b1edbc 8485 #define PWR_CR2_PVME_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8486 #define PWR_CR2_PVME_Msk (0x3U << PWR_CR2_PVME_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 8487 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
AnnaBridge 171:3a7713b1edbc 8488 #define PWR_CR2_PVME4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8489 #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8490 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
AnnaBridge 171:3a7713b1edbc 8491 #define PWR_CR2_PVME3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8492 #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8493 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
AnnaBridge 171:3a7713b1edbc 8494 /*!< PVD level configuration */
AnnaBridge 171:3a7713b1edbc 8495 #define PWR_CR2_PLS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8496 #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
AnnaBridge 171:3a7713b1edbc 8497 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
AnnaBridge 171:3a7713b1edbc 8498 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
AnnaBridge 171:3a7713b1edbc 8499 #define PWR_CR2_PLS_LEV1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8500 #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8501 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
AnnaBridge 171:3a7713b1edbc 8502 #define PWR_CR2_PLS_LEV2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8503 #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8504 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
AnnaBridge 171:3a7713b1edbc 8505 #define PWR_CR2_PLS_LEV3_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8506 #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 8507 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
AnnaBridge 171:3a7713b1edbc 8508 #define PWR_CR2_PLS_LEV4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8509 #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8510 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
AnnaBridge 171:3a7713b1edbc 8511 #define PWR_CR2_PLS_LEV5_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8512 #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
AnnaBridge 171:3a7713b1edbc 8513 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
AnnaBridge 171:3a7713b1edbc 8514 #define PWR_CR2_PLS_LEV6_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8515 #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8516 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
AnnaBridge 171:3a7713b1edbc 8517 #define PWR_CR2_PLS_LEV7_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8518 #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
AnnaBridge 171:3a7713b1edbc 8519 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
AnnaBridge 171:3a7713b1edbc 8520 #define PWR_CR2_PVDE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8521 #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8522 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 171:3a7713b1edbc 8523
AnnaBridge 171:3a7713b1edbc 8524 /******************** Bit definition for PWR_CR3 register ********************/
AnnaBridge 171:3a7713b1edbc 8525 #define PWR_CR3_EIWUL_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8526 #define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8527 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
AnnaBridge 171:3a7713b1edbc 8528 #define PWR_CR3_APC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8529 #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8530 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
AnnaBridge 171:3a7713b1edbc 8531 #define PWR_CR3_RRS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8532 #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8533 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
AnnaBridge 171:3a7713b1edbc 8534 #define PWR_CR3_EWUP5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8535 #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8536 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
AnnaBridge 171:3a7713b1edbc 8537 #define PWR_CR3_EWUP4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8538 #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8539 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
AnnaBridge 171:3a7713b1edbc 8540 #define PWR_CR3_EWUP3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8541 #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8542 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
AnnaBridge 171:3a7713b1edbc 8543 #define PWR_CR3_EWUP2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8544 #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8545 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
AnnaBridge 171:3a7713b1edbc 8546 #define PWR_CR3_EWUP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8547 #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8548 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
AnnaBridge 171:3a7713b1edbc 8549 #define PWR_CR3_EWUP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8550 #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 8551 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
AnnaBridge 171:3a7713b1edbc 8552
AnnaBridge 171:3a7713b1edbc 8553 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8554 #define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
AnnaBridge 171:3a7713b1edbc 8555 #define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
AnnaBridge 171:3a7713b1edbc 8556 #define PWR_CR3_EIWF PWR_CR3_EIWUL
AnnaBridge 171:3a7713b1edbc 8557
AnnaBridge 171:3a7713b1edbc 8558
AnnaBridge 171:3a7713b1edbc 8559 /******************** Bit definition for PWR_CR4 register ********************/
AnnaBridge 171:3a7713b1edbc 8560 #define PWR_CR4_VBRS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8561 #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8562 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
AnnaBridge 171:3a7713b1edbc 8563 #define PWR_CR4_VBE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8564 #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8565 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
AnnaBridge 171:3a7713b1edbc 8566 #define PWR_CR4_WP5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8567 #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8568 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
AnnaBridge 171:3a7713b1edbc 8569 #define PWR_CR4_WP4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8570 #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8571 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
AnnaBridge 171:3a7713b1edbc 8572 #define PWR_CR4_WP3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8573 #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8574 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
AnnaBridge 171:3a7713b1edbc 8575 #define PWR_CR4_WP2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8576 #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8577 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
AnnaBridge 171:3a7713b1edbc 8578 #define PWR_CR4_WP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8579 #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8580 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
AnnaBridge 171:3a7713b1edbc 8581
AnnaBridge 171:3a7713b1edbc 8582 /******************** Bit definition for PWR_SR1 register ********************/
AnnaBridge 171:3a7713b1edbc 8583 #define PWR_SR1_WUFI_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8584 #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8585 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
AnnaBridge 171:3a7713b1edbc 8586 #define PWR_SR1_SBF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8587 #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8588 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
AnnaBridge 171:3a7713b1edbc 8589 #define PWR_SR1_WUF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8590 #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 8591 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
AnnaBridge 171:3a7713b1edbc 8592 #define PWR_SR1_WUF5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8593 #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8594 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
AnnaBridge 171:3a7713b1edbc 8595 #define PWR_SR1_WUF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8596 #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8597 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
AnnaBridge 171:3a7713b1edbc 8598 #define PWR_SR1_WUF3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8599 #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8600 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
AnnaBridge 171:3a7713b1edbc 8601 #define PWR_SR1_WUF2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8602 #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8603 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
AnnaBridge 171:3a7713b1edbc 8604 #define PWR_SR1_WUF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8605 #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8606 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
AnnaBridge 171:3a7713b1edbc 8607
AnnaBridge 171:3a7713b1edbc 8608 /******************** Bit definition for PWR_SR2 register ********************/
AnnaBridge 171:3a7713b1edbc 8609 #define PWR_SR2_PVMO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8610 #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8611 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
AnnaBridge 171:3a7713b1edbc 8612 #define PWR_SR2_PVMO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8613 #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8614 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
AnnaBridge 171:3a7713b1edbc 8615 #define PWR_SR2_PVDO_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8616 #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8617 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
AnnaBridge 171:3a7713b1edbc 8618 #define PWR_SR2_VOSF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8619 #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8620 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
AnnaBridge 171:3a7713b1edbc 8621 #define PWR_SR2_REGLPF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8622 #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8623 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
AnnaBridge 171:3a7713b1edbc 8624 #define PWR_SR2_REGLPS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8625 #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8626 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
AnnaBridge 171:3a7713b1edbc 8627
AnnaBridge 171:3a7713b1edbc 8628 /******************** Bit definition for PWR_SCR register ********************/
AnnaBridge 171:3a7713b1edbc 8629 #define PWR_SCR_CSBF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8630 #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8631 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
AnnaBridge 171:3a7713b1edbc 8632 #define PWR_SCR_CWUF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8633 #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 8634 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
AnnaBridge 171:3a7713b1edbc 8635 #define PWR_SCR_CWUF5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8636 #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8637 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
AnnaBridge 171:3a7713b1edbc 8638 #define PWR_SCR_CWUF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8639 #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8640 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
AnnaBridge 171:3a7713b1edbc 8641 #define PWR_SCR_CWUF3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8642 #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8643 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
AnnaBridge 171:3a7713b1edbc 8644 #define PWR_SCR_CWUF2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8645 #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8646 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
AnnaBridge 171:3a7713b1edbc 8647 #define PWR_SCR_CWUF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8648 #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8649 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
AnnaBridge 171:3a7713b1edbc 8650
AnnaBridge 171:3a7713b1edbc 8651 /******************** Bit definition for PWR_PUCRA register ********************/
AnnaBridge 171:3a7713b1edbc 8652 #define PWR_PUCRA_PA15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8653 #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8654 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8655 #define PWR_PUCRA_PA13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8656 #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8657 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8658 #define PWR_PUCRA_PA12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8659 #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8660 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8661 #define PWR_PUCRA_PA11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8662 #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8663 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8664 #define PWR_PUCRA_PA10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8665 #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8666 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8667 #define PWR_PUCRA_PA9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8668 #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8669 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8670 #define PWR_PUCRA_PA8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8671 #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8672 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8673 #define PWR_PUCRA_PA7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8674 #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8675 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8676 #define PWR_PUCRA_PA6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8677 #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8678 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8679 #define PWR_PUCRA_PA5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8680 #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8681 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8682 #define PWR_PUCRA_PA4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8683 #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8684 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8685 #define PWR_PUCRA_PA3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8686 #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8687 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8688 #define PWR_PUCRA_PA2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8689 #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8690 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8691 #define PWR_PUCRA_PA1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8692 #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8693 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8694 #define PWR_PUCRA_PA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8695 #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8696 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8697
AnnaBridge 171:3a7713b1edbc 8698 /******************** Bit definition for PWR_PDCRA register ********************/
AnnaBridge 171:3a7713b1edbc 8699 #define PWR_PDCRA_PA14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8700 #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8701 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8702 #define PWR_PDCRA_PA12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8703 #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8704 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8705 #define PWR_PDCRA_PA11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8706 #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8707 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8708 #define PWR_PDCRA_PA10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8709 #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8710 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8711 #define PWR_PDCRA_PA9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8712 #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8713 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8714 #define PWR_PDCRA_PA8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8715 #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8716 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8717 #define PWR_PDCRA_PA7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8718 #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8719 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8720 #define PWR_PDCRA_PA6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8721 #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8722 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8723 #define PWR_PDCRA_PA5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8724 #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8725 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8726 #define PWR_PDCRA_PA4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8727 #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8728 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8729 #define PWR_PDCRA_PA3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8730 #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8731 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8732 #define PWR_PDCRA_PA2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8733 #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8734 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8735 #define PWR_PDCRA_PA1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8736 #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8737 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8738 #define PWR_PDCRA_PA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8739 #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8740 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8741
AnnaBridge 171:3a7713b1edbc 8742 /******************** Bit definition for PWR_PUCRB register ********************/
AnnaBridge 171:3a7713b1edbc 8743 #define PWR_PUCRB_PB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8744 #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8745 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8746 #define PWR_PUCRB_PB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8747 #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8748 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8749 #define PWR_PUCRB_PB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8750 #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8751 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8752 #define PWR_PUCRB_PB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8753 #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8754 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8755 #define PWR_PUCRB_PB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8756 #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8757 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8758 #define PWR_PUCRB_PB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8759 #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8760 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8761 #define PWR_PUCRB_PB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8762 #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8763 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8764
AnnaBridge 171:3a7713b1edbc 8765 /******************** Bit definition for PWR_PDCRB register ********************/
AnnaBridge 171:3a7713b1edbc 8766 #define PWR_PDCRB_PB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8767 #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8768 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8769 #define PWR_PDCRB_PB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8770 #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8771 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8772 #define PWR_PDCRB_PB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8773 #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8774 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8775 #define PWR_PDCRB_PB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8776 #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8777 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8778 #define PWR_PDCRB_PB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8779 #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8780 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8781 #define PWR_PDCRB_PB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8782 #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8783 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8784
AnnaBridge 171:3a7713b1edbc 8785 /******************** Bit definition for PWR_PUCRC register ********************/
AnnaBridge 171:3a7713b1edbc 8786 #define PWR_PUCRC_PC15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8787 #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8788 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8789 #define PWR_PUCRC_PC14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8790 #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8791 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8792
AnnaBridge 171:3a7713b1edbc 8793 /******************** Bit definition for PWR_PDCRC register ********************/
AnnaBridge 171:3a7713b1edbc 8794 #define PWR_PDCRC_PC15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8795 #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8796 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8797 #define PWR_PDCRC_PC14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8798 #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8799 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8800
AnnaBridge 171:3a7713b1edbc 8801
AnnaBridge 171:3a7713b1edbc 8802
AnnaBridge 171:3a7713b1edbc 8803
AnnaBridge 171:3a7713b1edbc 8804 /******************** Bit definition for PWR_PUCRH register ********************/
AnnaBridge 171:3a7713b1edbc 8805 #define PWR_PUCRH_PH3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8806 #define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8807 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */
AnnaBridge 171:3a7713b1edbc 8808
AnnaBridge 171:3a7713b1edbc 8809 /******************** Bit definition for PWR_PDCRH register ********************/
AnnaBridge 171:3a7713b1edbc 8810 #define PWR_PDCRH_PH3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8811 #define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8812 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
AnnaBridge 171:3a7713b1edbc 8813
AnnaBridge 171:3a7713b1edbc 8814
AnnaBridge 171:3a7713b1edbc 8815 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8816 /* */
AnnaBridge 171:3a7713b1edbc 8817 /* Reset and Clock Control */
AnnaBridge 171:3a7713b1edbc 8818 /* */
AnnaBridge 171:3a7713b1edbc 8819 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8820 /*
AnnaBridge 171:3a7713b1edbc 8821 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
AnnaBridge 171:3a7713b1edbc 8822 */
AnnaBridge 171:3a7713b1edbc 8823 #define RCC_HSI48_SUPPORT
AnnaBridge 171:3a7713b1edbc 8824 #define RCC_PLLP_DIV_2_31_SUPPORT
AnnaBridge 171:3a7713b1edbc 8825 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
AnnaBridge 171:3a7713b1edbc 8826
AnnaBridge 171:3a7713b1edbc 8827 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 8828 #define RCC_CR_MSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8829 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8830 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
AnnaBridge 171:3a7713b1edbc 8831 #define RCC_CR_MSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8832 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8833 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
AnnaBridge 171:3a7713b1edbc 8834 #define RCC_CR_MSIPLLEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8835 #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8836 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
AnnaBridge 171:3a7713b1edbc 8837 #define RCC_CR_MSIRGSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8838 #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8839 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
AnnaBridge 171:3a7713b1edbc 8840
AnnaBridge 171:3a7713b1edbc 8841 /*!< MSIRANGE configuration : 12 frequency ranges available */
AnnaBridge 171:3a7713b1edbc 8842 #define RCC_CR_MSIRANGE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8843 #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8844 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
AnnaBridge 171:3a7713b1edbc 8845 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
AnnaBridge 171:3a7713b1edbc 8846 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8847 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8848 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 8849 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8850 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
AnnaBridge 171:3a7713b1edbc 8851 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 8852 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 8853 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8854 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
AnnaBridge 171:3a7713b1edbc 8855 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
AnnaBridge 171:3a7713b1edbc 8856 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
AnnaBridge 171:3a7713b1edbc 8857
AnnaBridge 171:3a7713b1edbc 8858 #define RCC_CR_HSION_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8859 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8860 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
AnnaBridge 171:3a7713b1edbc 8861 #define RCC_CR_HSIKERON_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8862 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8863 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
AnnaBridge 171:3a7713b1edbc 8864 #define RCC_CR_HSIRDY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8865 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8866 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
AnnaBridge 171:3a7713b1edbc 8867 #define RCC_CR_HSIASFS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8868 #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8869 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
AnnaBridge 171:3a7713b1edbc 8870
AnnaBridge 171:3a7713b1edbc 8871 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8872 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8873 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
AnnaBridge 171:3a7713b1edbc 8874 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8875 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8876 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
AnnaBridge 171:3a7713b1edbc 8877 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8878 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8879 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
AnnaBridge 171:3a7713b1edbc 8880 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8881 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8882 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
AnnaBridge 171:3a7713b1edbc 8883
AnnaBridge 171:3a7713b1edbc 8884 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8885 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8886 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
AnnaBridge 171:3a7713b1edbc 8887 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8888 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8889 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
AnnaBridge 171:3a7713b1edbc 8890 #define RCC_CR_PLLSAI1ON_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8891 #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8892 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
AnnaBridge 171:3a7713b1edbc 8893 #define RCC_CR_PLLSAI1RDY_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8894 #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8895 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
AnnaBridge 171:3a7713b1edbc 8896
AnnaBridge 171:3a7713b1edbc 8897 /******************** Bit definition for RCC_ICSCR register ***************/
AnnaBridge 171:3a7713b1edbc 8898 /*!< MSICAL configuration */
AnnaBridge 171:3a7713b1edbc 8899 #define RCC_ICSCR_MSICAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8900 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8901 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
AnnaBridge 171:3a7713b1edbc 8902 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8903 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8904 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8905 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8906 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8907 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8908 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8909 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8910
AnnaBridge 171:3a7713b1edbc 8911 /*!< MSITRIM configuration */
AnnaBridge 171:3a7713b1edbc 8912 #define RCC_ICSCR_MSITRIM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8913 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 8914 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
AnnaBridge 171:3a7713b1edbc 8915 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8916 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8917 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8918 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8919 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8920 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8921 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8922 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8923
AnnaBridge 171:3a7713b1edbc 8924 /*!< HSICAL configuration */
AnnaBridge 171:3a7713b1edbc 8925 #define RCC_ICSCR_HSICAL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8926 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 8927 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
AnnaBridge 171:3a7713b1edbc 8928 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8929 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8930 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8931 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8932 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8933 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8934 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8935 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8936
AnnaBridge 171:3a7713b1edbc 8937 /*!< HSITRIM configuration */
AnnaBridge 171:3a7713b1edbc 8938 #define RCC_ICSCR_HSITRIM_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8939 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 8940 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
AnnaBridge 171:3a7713b1edbc 8941 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8942 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8943 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8944 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8945 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8946
AnnaBridge 171:3a7713b1edbc 8947 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 8948 /*!< SW configuration */
AnnaBridge 171:3a7713b1edbc 8949 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8950 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8951 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 171:3a7713b1edbc 8952 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8953 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8954
AnnaBridge 171:3a7713b1edbc 8955 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
AnnaBridge 171:3a7713b1edbc 8956 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
AnnaBridge 171:3a7713b1edbc 8957 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
AnnaBridge 171:3a7713b1edbc 8958 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
AnnaBridge 171:3a7713b1edbc 8959
AnnaBridge 171:3a7713b1edbc 8960 /*!< SWS configuration */
AnnaBridge 171:3a7713b1edbc 8961 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8962 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8963 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 171:3a7713b1edbc 8964 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8965 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8966
AnnaBridge 171:3a7713b1edbc 8967 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 8968 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 8969 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 8970 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 8971
AnnaBridge 171:3a7713b1edbc 8972 /*!< HPRE configuration */
AnnaBridge 171:3a7713b1edbc 8973 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8974 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8975 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 171:3a7713b1edbc 8976 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8977 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8978 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8979 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8980
AnnaBridge 171:3a7713b1edbc 8981 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 8982 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 8983 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 8984 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 8985 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 8986 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 8987 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 8988 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 8989 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 8990
AnnaBridge 171:3a7713b1edbc 8991 /*!< PPRE1 configuration */
AnnaBridge 171:3a7713b1edbc 8992 #define RCC_CFGR_PPRE1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8993 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 8994 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
AnnaBridge 171:3a7713b1edbc 8995 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8996 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8997 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8998
AnnaBridge 171:3a7713b1edbc 8999 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 9000 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 9001 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 9002 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 9003 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 9004
AnnaBridge 171:3a7713b1edbc 9005 /*!< PPRE2 configuration */
AnnaBridge 171:3a7713b1edbc 9006 #define RCC_CFGR_PPRE2_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9007 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
AnnaBridge 171:3a7713b1edbc 9008 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 171:3a7713b1edbc 9009 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9010 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9011 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9012
AnnaBridge 171:3a7713b1edbc 9013 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 9014 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 9015 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 9016 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 9017 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 9018
AnnaBridge 171:3a7713b1edbc 9019 #define RCC_CFGR_STOPWUCK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9020 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9021 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
AnnaBridge 171:3a7713b1edbc 9022
AnnaBridge 171:3a7713b1edbc 9023 /*!< MCOSEL configuration */
AnnaBridge 171:3a7713b1edbc 9024 #define RCC_CFGR_MCOSEL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9025 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 9026 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
AnnaBridge 171:3a7713b1edbc 9027 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9028 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9029 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9030 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9031
AnnaBridge 171:3a7713b1edbc 9032 #define RCC_CFGR_MCOPRE_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9033 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 9034 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
AnnaBridge 171:3a7713b1edbc 9035 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9036 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9037 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9038
AnnaBridge 171:3a7713b1edbc 9039 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
AnnaBridge 171:3a7713b1edbc 9040 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
AnnaBridge 171:3a7713b1edbc 9041 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
AnnaBridge 171:3a7713b1edbc 9042 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
AnnaBridge 171:3a7713b1edbc 9043 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
AnnaBridge 171:3a7713b1edbc 9044
AnnaBridge 171:3a7713b1edbc 9045 /* Legacy aliases */
AnnaBridge 171:3a7713b1edbc 9046 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
AnnaBridge 171:3a7713b1edbc 9047 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
AnnaBridge 171:3a7713b1edbc 9048 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
AnnaBridge 171:3a7713b1edbc 9049 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
AnnaBridge 171:3a7713b1edbc 9050 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
AnnaBridge 171:3a7713b1edbc 9051 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
AnnaBridge 171:3a7713b1edbc 9052
AnnaBridge 171:3a7713b1edbc 9053 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 171:3a7713b1edbc 9054 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9055 #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 9056 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 171:3a7713b1edbc 9057
AnnaBridge 171:3a7713b1edbc 9058 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9059 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9060 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
AnnaBridge 171:3a7713b1edbc 9061 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9062 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9063 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
AnnaBridge 171:3a7713b1edbc 9064 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9065 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 9066 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
AnnaBridge 171:3a7713b1edbc 9067
AnnaBridge 171:3a7713b1edbc 9068 #define RCC_PLLCFGR_PLLM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9069 #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 9070 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 171:3a7713b1edbc 9071 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9072 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9073 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9074
AnnaBridge 171:3a7713b1edbc 9075 #define RCC_PLLCFGR_PLLN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9076 #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
AnnaBridge 171:3a7713b1edbc 9077 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 171:3a7713b1edbc 9078 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9079 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9080 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9081 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9082 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9083 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9084 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9085
AnnaBridge 171:3a7713b1edbc 9086 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9087 #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9088 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
AnnaBridge 171:3a7713b1edbc 9089 #define RCC_PLLCFGR_PLLP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9090 #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9091 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 171:3a7713b1edbc 9092 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9093 #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9094 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
AnnaBridge 171:3a7713b1edbc 9095
AnnaBridge 171:3a7713b1edbc 9096 #define RCC_PLLCFGR_PLLQ_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9097 #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 9098 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 171:3a7713b1edbc 9099 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9100 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9101
AnnaBridge 171:3a7713b1edbc 9102 #define RCC_PLLCFGR_PLLREN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9103 #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9104 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
AnnaBridge 171:3a7713b1edbc 9105 #define RCC_PLLCFGR_PLLR_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9106 #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 9107 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
AnnaBridge 171:3a7713b1edbc 9108 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9109 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9110
AnnaBridge 171:3a7713b1edbc 9111 #define RCC_PLLCFGR_PLLPDIV_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9112 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
AnnaBridge 171:3a7713b1edbc 9113 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
AnnaBridge 171:3a7713b1edbc 9114 #define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9115 #define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9116 #define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9117 #define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9118 #define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9119
AnnaBridge 171:3a7713b1edbc 9120 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
AnnaBridge 171:3a7713b1edbc 9121 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9122 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
AnnaBridge 171:3a7713b1edbc 9123 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
AnnaBridge 171:3a7713b1edbc 9124 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9125 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9126 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9127 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9128 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9129 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9130 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9131
AnnaBridge 171:3a7713b1edbc 9132 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9133 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9134 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
AnnaBridge 171:3a7713b1edbc 9135 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9136 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9137 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
AnnaBridge 171:3a7713b1edbc 9138
AnnaBridge 171:3a7713b1edbc 9139 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9140 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9141 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
AnnaBridge 171:3a7713b1edbc 9142 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9143 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 9144 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
AnnaBridge 171:3a7713b1edbc 9145 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9146 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9147
AnnaBridge 171:3a7713b1edbc 9148 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9149 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9150 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
AnnaBridge 171:3a7713b1edbc 9151 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9152 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 9153 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
AnnaBridge 171:3a7713b1edbc 9154 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9155 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9156
AnnaBridge 171:3a7713b1edbc 9157 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9158 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
AnnaBridge 171:3a7713b1edbc 9159 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
AnnaBridge 171:3a7713b1edbc 9160 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9161 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9162 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9163 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9164 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9165
AnnaBridge 171:3a7713b1edbc 9166 /******************** Bit definition for RCC_CIER register ******************/
AnnaBridge 171:3a7713b1edbc 9167 #define RCC_CIER_LSIRDYIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9168 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9169 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9170 #define RCC_CIER_LSERDYIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9171 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9172 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9173 #define RCC_CIER_MSIRDYIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9174 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9175 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9176 #define RCC_CIER_HSIRDYIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9177 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9178 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9179 #define RCC_CIER_HSERDYIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9180 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9181 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9182 #define RCC_CIER_PLLRDYIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9183 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9184 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9185 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9186 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9187 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9188 #define RCC_CIER_LSECSSIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9189 #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9190 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
AnnaBridge 171:3a7713b1edbc 9191 #define RCC_CIER_HSI48RDYIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9192 #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9193 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
AnnaBridge 171:3a7713b1edbc 9194
AnnaBridge 171:3a7713b1edbc 9195 /******************** Bit definition for RCC_CIFR register ******************/
AnnaBridge 171:3a7713b1edbc 9196 #define RCC_CIFR_LSIRDYF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9197 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9198 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 9199 #define RCC_CIFR_LSERDYF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9200 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9201 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
AnnaBridge 171:3a7713b1edbc 9202 #define RCC_CIFR_MSIRDYF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9203 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9204 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 9205 #define RCC_CIFR_HSIRDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9206 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9207 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 9208 #define RCC_CIFR_HSERDYF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9209 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9210 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
AnnaBridge 171:3a7713b1edbc 9211 #define RCC_CIFR_PLLRDYF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9212 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9213 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
AnnaBridge 171:3a7713b1edbc 9214 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9215 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9216 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
AnnaBridge 171:3a7713b1edbc 9217 #define RCC_CIFR_CSSF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9218 #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9219 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
AnnaBridge 171:3a7713b1edbc 9220 #define RCC_CIFR_LSECSSF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9221 #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9222 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
AnnaBridge 171:3a7713b1edbc 9223 #define RCC_CIFR_HSI48RDYF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9224 #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9225 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
AnnaBridge 171:3a7713b1edbc 9226
AnnaBridge 171:3a7713b1edbc 9227 /******************** Bit definition for RCC_CICR register ******************/
AnnaBridge 171:3a7713b1edbc 9228 #define RCC_CICR_LSIRDYC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9229 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9230 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 9231 #define RCC_CICR_LSERDYC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9232 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9233 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
AnnaBridge 171:3a7713b1edbc 9234 #define RCC_CICR_MSIRDYC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9235 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9236 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 9237 #define RCC_CICR_HSIRDYC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9238 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9239 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 9240 #define RCC_CICR_HSERDYC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9241 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9242 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
AnnaBridge 171:3a7713b1edbc 9243 #define RCC_CICR_PLLRDYC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9244 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9245 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
AnnaBridge 171:3a7713b1edbc 9246 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9247 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9248 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
AnnaBridge 171:3a7713b1edbc 9249 #define RCC_CICR_CSSC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9250 #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9251 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
AnnaBridge 171:3a7713b1edbc 9252 #define RCC_CICR_LSECSSC_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9253 #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9254 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
AnnaBridge 171:3a7713b1edbc 9255 #define RCC_CICR_HSI48RDYC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9256 #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9257 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
AnnaBridge 171:3a7713b1edbc 9258
AnnaBridge 171:3a7713b1edbc 9259 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 171:3a7713b1edbc 9260 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9261 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9262 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 171:3a7713b1edbc 9263 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9264 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9265 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 171:3a7713b1edbc 9266 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9267 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9268 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
AnnaBridge 171:3a7713b1edbc 9269 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9270 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9271 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 171:3a7713b1edbc 9272 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9273 #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9274 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
AnnaBridge 171:3a7713b1edbc 9275
AnnaBridge 171:3a7713b1edbc 9276 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 171:3a7713b1edbc 9277 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9278 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9279 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
AnnaBridge 171:3a7713b1edbc 9280 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9281 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9282 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
AnnaBridge 171:3a7713b1edbc 9283 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9284 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9285 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
AnnaBridge 171:3a7713b1edbc 9286 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9287 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9288 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
AnnaBridge 171:3a7713b1edbc 9289 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9290 #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9291 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
AnnaBridge 171:3a7713b1edbc 9292 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9293 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9294 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 171:3a7713b1edbc 9295
AnnaBridge 171:3a7713b1edbc 9296 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 171:3a7713b1edbc 9297 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9298 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9299 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
AnnaBridge 171:3a7713b1edbc 9300
AnnaBridge 171:3a7713b1edbc 9301 /******************** Bit definition for RCC_APB1RSTR1 register **************/
AnnaBridge 171:3a7713b1edbc 9302 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9303 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9304 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
AnnaBridge 171:3a7713b1edbc 9305 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9306 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9307 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
AnnaBridge 171:3a7713b1edbc 9308 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9309 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9310 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
AnnaBridge 171:3a7713b1edbc 9311 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9312 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9313 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
AnnaBridge 171:3a7713b1edbc 9314 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9315 #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9316 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
AnnaBridge 171:3a7713b1edbc 9317 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9318 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9319 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
AnnaBridge 171:3a7713b1edbc 9320 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9321 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9322 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
AnnaBridge 171:3a7713b1edbc 9323 #define RCC_APB1RSTR1_CRSRST_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9324 #define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9325 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
AnnaBridge 171:3a7713b1edbc 9326 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9327 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9328 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
AnnaBridge 171:3a7713b1edbc 9329 #define RCC_APB1RSTR1_USBFSRST_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9330 #define RCC_APB1RSTR1_USBFSRST_Msk (0x1U << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9331 #define RCC_APB1RSTR1_USBFSRST RCC_APB1RSTR1_USBFSRST_Msk
AnnaBridge 171:3a7713b1edbc 9332 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9333 #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9334 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
AnnaBridge 171:3a7713b1edbc 9335 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9336 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9337 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
AnnaBridge 171:3a7713b1edbc 9338 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9339 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9340 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
AnnaBridge 171:3a7713b1edbc 9341 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9342 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9343 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
AnnaBridge 171:3a7713b1edbc 9344
AnnaBridge 171:3a7713b1edbc 9345 /******************** Bit definition for RCC_APB1RSTR2 register **************/
AnnaBridge 171:3a7713b1edbc 9346 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9347 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9348 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
AnnaBridge 171:3a7713b1edbc 9349 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9350 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9351 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
AnnaBridge 171:3a7713b1edbc 9352 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9353 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9354 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
AnnaBridge 171:3a7713b1edbc 9355
AnnaBridge 171:3a7713b1edbc 9356 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 171:3a7713b1edbc 9357 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9358 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9359 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 171:3a7713b1edbc 9360 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9361 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9362 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 171:3a7713b1edbc 9363 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9364 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9365 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 171:3a7713b1edbc 9366 #define RCC_APB2RSTR_USART1RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9367 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9368 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 171:3a7713b1edbc 9369 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9370 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9371 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
AnnaBridge 171:3a7713b1edbc 9372 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9373 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9374 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
AnnaBridge 171:3a7713b1edbc 9375 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9376 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9377 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
AnnaBridge 171:3a7713b1edbc 9378
AnnaBridge 171:3a7713b1edbc 9379 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 171:3a7713b1edbc 9380 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9381 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9382 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 171:3a7713b1edbc 9383 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9384 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9385 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 171:3a7713b1edbc 9386 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9387 #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9388 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
AnnaBridge 171:3a7713b1edbc 9389 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9390 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9391 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 171:3a7713b1edbc 9392 #define RCC_AHB1ENR_TSCEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9393 #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9394 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
AnnaBridge 171:3a7713b1edbc 9395
AnnaBridge 171:3a7713b1edbc 9396 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 171:3a7713b1edbc 9397 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9398 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9399 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
AnnaBridge 171:3a7713b1edbc 9400 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9401 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9402 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
AnnaBridge 171:3a7713b1edbc 9403 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9404 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9405 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
AnnaBridge 171:3a7713b1edbc 9406 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9407 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9408 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
AnnaBridge 171:3a7713b1edbc 9409 #define RCC_AHB2ENR_ADCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9410 #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9411 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
AnnaBridge 171:3a7713b1edbc 9412 #define RCC_AHB2ENR_RNGEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9413 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9414 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 171:3a7713b1edbc 9415
AnnaBridge 171:3a7713b1edbc 9416 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 171:3a7713b1edbc 9417 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9418 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9419 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
AnnaBridge 171:3a7713b1edbc 9420
AnnaBridge 171:3a7713b1edbc 9421 /******************** Bit definition for RCC_APB1ENR1 register ***************/
AnnaBridge 171:3a7713b1edbc 9422 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9423 #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9424 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
AnnaBridge 171:3a7713b1edbc 9425 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9426 #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9427 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
AnnaBridge 171:3a7713b1edbc 9428 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9429 #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9430 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
AnnaBridge 171:3a7713b1edbc 9431 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9432 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9433 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
AnnaBridge 171:3a7713b1edbc 9434 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9435 #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9436 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
AnnaBridge 171:3a7713b1edbc 9437 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9438 #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9439 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
AnnaBridge 171:3a7713b1edbc 9440 #define RCC_APB1ENR1_USART2EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9441 #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9442 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
AnnaBridge 171:3a7713b1edbc 9443 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9444 #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9445 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
AnnaBridge 171:3a7713b1edbc 9446 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9447 #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9448 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
AnnaBridge 171:3a7713b1edbc 9449 #define RCC_APB1ENR1_CRSEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9450 #define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9451 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
AnnaBridge 171:3a7713b1edbc 9452 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9453 #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9454 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
AnnaBridge 171:3a7713b1edbc 9455 #define RCC_APB1ENR1_USBFSEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9456 #define RCC_APB1ENR1_USBFSEN_Msk (0x1U << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9457 #define RCC_APB1ENR1_USBFSEN RCC_APB1ENR1_USBFSEN_Msk
AnnaBridge 171:3a7713b1edbc 9458 #define RCC_APB1ENR1_PWREN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9459 #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9460 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
AnnaBridge 171:3a7713b1edbc 9461 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9462 #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9463 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
AnnaBridge 171:3a7713b1edbc 9464 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9465 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9466 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
AnnaBridge 171:3a7713b1edbc 9467 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9468 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9469 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
AnnaBridge 171:3a7713b1edbc 9470
AnnaBridge 171:3a7713b1edbc 9471 /******************** Bit definition for RCC_APB1RSTR2 register **************/
AnnaBridge 171:3a7713b1edbc 9472 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9473 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9474 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
AnnaBridge 171:3a7713b1edbc 9475 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9476 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9477 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
AnnaBridge 171:3a7713b1edbc 9478 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9479 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9480 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
AnnaBridge 171:3a7713b1edbc 9481
AnnaBridge 171:3a7713b1edbc 9482 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 171:3a7713b1edbc 9483 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9484 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9485 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 171:3a7713b1edbc 9486 #define RCC_APB2ENR_FWEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9487 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9488 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
AnnaBridge 171:3a7713b1edbc 9489 #define RCC_APB2ENR_TIM1EN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9490 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9491 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 171:3a7713b1edbc 9492 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9493 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9494 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 171:3a7713b1edbc 9495 #define RCC_APB2ENR_USART1EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9496 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9497 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 171:3a7713b1edbc 9498 #define RCC_APB2ENR_TIM15EN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9499 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9500 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
AnnaBridge 171:3a7713b1edbc 9501 #define RCC_APB2ENR_TIM16EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9502 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9503 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
AnnaBridge 171:3a7713b1edbc 9504 #define RCC_APB2ENR_SAI1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9505 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9506 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
AnnaBridge 171:3a7713b1edbc 9507
AnnaBridge 171:3a7713b1edbc 9508 /******************** Bit definition for RCC_AHB1SMENR register ***************/
AnnaBridge 171:3a7713b1edbc 9509 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9510 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9511 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9512 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9513 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9514 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9515 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9516 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9517 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9518 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9519 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9520 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9521 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9522 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9523 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9524 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9525 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9526 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9527
AnnaBridge 171:3a7713b1edbc 9528 /******************** Bit definition for RCC_AHB2SMENR register *************/
AnnaBridge 171:3a7713b1edbc 9529 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9530 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9531 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
AnnaBridge 171:3a7713b1edbc 9532 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9533 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9534 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9535 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9536 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9537 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9538 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9539 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9540 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9541 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9542 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9543 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9544 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9545 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9546 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9547 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9548 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9549 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9550
AnnaBridge 171:3a7713b1edbc 9551 /******************** Bit definition for RCC_AHB3SMENR register *************/
AnnaBridge 171:3a7713b1edbc 9552 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9553 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9554 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
AnnaBridge 171:3a7713b1edbc 9555
AnnaBridge 171:3a7713b1edbc 9556 /******************** Bit definition for RCC_APB1SMENR1 register *************/
AnnaBridge 171:3a7713b1edbc 9557 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9558 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9559 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9560 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9561 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9562 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9563 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9564 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9565 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9566 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9567 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9568 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9569 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9570 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9571 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9572 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9573 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9574 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9575 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9576 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9577 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9578 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9579 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9580 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9581 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9582 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9583 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9584 #define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9585 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9586 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9587 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9588 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9589 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9590 #define RCC_APB1SMENR1_USBFSSMEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9591 #define RCC_APB1SMENR1_USBFSSMEN_Msk (0x1U << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9592 #define RCC_APB1SMENR1_USBFSSMEN RCC_APB1SMENR1_USBFSSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9593 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9594 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9595 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9596 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9597 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9598 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9599 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9600 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9601 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9602 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9603 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9604 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9605
AnnaBridge 171:3a7713b1edbc 9606 /******************** Bit definition for RCC_APB1SMENR2 register *************/
AnnaBridge 171:3a7713b1edbc 9607 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9608 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9609 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9610 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9611 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9612 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9613 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9614 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9615 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9616
AnnaBridge 171:3a7713b1edbc 9617 /******************** Bit definition for RCC_APB2SMENR register *************/
AnnaBridge 171:3a7713b1edbc 9618 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9619 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9620 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
AnnaBridge 171:3a7713b1edbc 9621 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9622 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9623 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9624 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9625 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9626 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9627 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9628 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9629 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9630 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9631 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9632 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9633 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9634 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9635 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9636 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9637 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9638 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
AnnaBridge 171:3a7713b1edbc 9639
AnnaBridge 171:3a7713b1edbc 9640 /******************** Bit definition for RCC_CCIPR register ******************/
AnnaBridge 171:3a7713b1edbc 9641 #define RCC_CCIPR_USART1SEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9642 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 9643 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
AnnaBridge 171:3a7713b1edbc 9644 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9645 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9646
AnnaBridge 171:3a7713b1edbc 9647 #define RCC_CCIPR_USART2SEL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9648 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 9649 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
AnnaBridge 171:3a7713b1edbc 9650 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9651 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9652
AnnaBridge 171:3a7713b1edbc 9653 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9654 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 9655 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
AnnaBridge 171:3a7713b1edbc 9656 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9657 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9658
AnnaBridge 171:3a7713b1edbc 9659 #define RCC_CCIPR_I2C1SEL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9660 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 9661 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
AnnaBridge 171:3a7713b1edbc 9662 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9663 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9664
AnnaBridge 171:3a7713b1edbc 9665 #define RCC_CCIPR_I2C3SEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9666 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 9667 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
AnnaBridge 171:3a7713b1edbc 9668 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9669 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9670
AnnaBridge 171:3a7713b1edbc 9671 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9672 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 9673 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
AnnaBridge 171:3a7713b1edbc 9674 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9675 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9676
AnnaBridge 171:3a7713b1edbc 9677 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9678 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 9679 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
AnnaBridge 171:3a7713b1edbc 9680 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9681 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9682
AnnaBridge 171:3a7713b1edbc 9683 #define RCC_CCIPR_SAI1SEL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9684 #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 9685 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
AnnaBridge 171:3a7713b1edbc 9686 #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9687 #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9688
AnnaBridge 171:3a7713b1edbc 9689 #define RCC_CCIPR_CLK48SEL_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9690 #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 9691 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
AnnaBridge 171:3a7713b1edbc 9692 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9693 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9694
AnnaBridge 171:3a7713b1edbc 9695 #define RCC_CCIPR_ADCSEL_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9696 #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 9697 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
AnnaBridge 171:3a7713b1edbc 9698 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9699 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9700
AnnaBridge 171:3a7713b1edbc 9701 #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9702 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9703 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
AnnaBridge 171:3a7713b1edbc 9704
AnnaBridge 171:3a7713b1edbc 9705 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 171:3a7713b1edbc 9706 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9707 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9708 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 171:3a7713b1edbc 9709 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9710 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9711 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 171:3a7713b1edbc 9712 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9713 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9714 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 171:3a7713b1edbc 9715
AnnaBridge 171:3a7713b1edbc 9716 #define RCC_BDCR_LSEDRV_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9717 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 9718 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
AnnaBridge 171:3a7713b1edbc 9719 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9720 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9721
AnnaBridge 171:3a7713b1edbc 9722 #define RCC_BDCR_LSECSSON_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9723 #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9724 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
AnnaBridge 171:3a7713b1edbc 9725 #define RCC_BDCR_LSECSSD_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9726 #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9727 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
AnnaBridge 171:3a7713b1edbc 9728
AnnaBridge 171:3a7713b1edbc 9729 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9730 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 9731 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 171:3a7713b1edbc 9732 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9733 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9734
AnnaBridge 171:3a7713b1edbc 9735 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9736 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9737 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 171:3a7713b1edbc 9738 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9739 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9740 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 171:3a7713b1edbc 9741 #define RCC_BDCR_LSCOEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9742 #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9743 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
AnnaBridge 171:3a7713b1edbc 9744 #define RCC_BDCR_LSCOSEL_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9745 #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9746 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
AnnaBridge 171:3a7713b1edbc 9747
AnnaBridge 171:3a7713b1edbc 9748 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 9749 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9750 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9751 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 171:3a7713b1edbc 9752 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9753 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9754 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 171:3a7713b1edbc 9755
AnnaBridge 171:3a7713b1edbc 9756 #define RCC_CSR_MSISRANGE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9757 #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 9758 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
AnnaBridge 171:3a7713b1edbc 9759 #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9760 #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
AnnaBridge 171:3a7713b1edbc 9761 #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 9762 #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 9763
AnnaBridge 171:3a7713b1edbc 9764 #define RCC_CSR_RMVF_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9765 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9766 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 171:3a7713b1edbc 9767 #define RCC_CSR_FWRSTF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9768 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9769 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9770 #define RCC_CSR_OBLRSTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9771 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9772 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9773 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9774 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9775 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9776 #define RCC_CSR_BORRSTF_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9777 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9778 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9779 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9780 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9781 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9782 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9783 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9784 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9785 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9786 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9787 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9788 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9789 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9790 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 171:3a7713b1edbc 9791
AnnaBridge 171:3a7713b1edbc 9792 /******************** Bit definition for RCC_CRRCR register *****************/
AnnaBridge 171:3a7713b1edbc 9793 #define RCC_CRRCR_HSI48ON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9794 #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9795 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
AnnaBridge 171:3a7713b1edbc 9796 #define RCC_CRRCR_HSI48RDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9797 #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9798 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
AnnaBridge 171:3a7713b1edbc 9799
AnnaBridge 171:3a7713b1edbc 9800 /*!< HSI48CAL configuration */
AnnaBridge 171:3a7713b1edbc 9801 #define RCC_CRRCR_HSI48CAL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9802 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
AnnaBridge 171:3a7713b1edbc 9803 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
AnnaBridge 171:3a7713b1edbc 9804 #define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9805 #define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9806 #define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9807 #define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9808 #define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9809 #define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9810 #define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9811 #define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9812 #define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9813
AnnaBridge 171:3a7713b1edbc 9814 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9815 /* */
AnnaBridge 171:3a7713b1edbc 9816 /* RNG */
AnnaBridge 171:3a7713b1edbc 9817 /* */
AnnaBridge 171:3a7713b1edbc 9818 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9819 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 171:3a7713b1edbc 9820 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9821 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9822 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 171:3a7713b1edbc 9823 #define RNG_CR_IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9824 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9825 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 171:3a7713b1edbc 9826
AnnaBridge 171:3a7713b1edbc 9827 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 171:3a7713b1edbc 9828 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9829 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9830 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 171:3a7713b1edbc 9831 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9832 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9833 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 171:3a7713b1edbc 9834 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9835 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9836 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 171:3a7713b1edbc 9837 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9838 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9839 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 171:3a7713b1edbc 9840 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9841 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9842 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 171:3a7713b1edbc 9843
AnnaBridge 171:3a7713b1edbc 9844 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9845 /* */
AnnaBridge 171:3a7713b1edbc 9846 /* Real-Time Clock (RTC) */
AnnaBridge 171:3a7713b1edbc 9847 /* */
AnnaBridge 171:3a7713b1edbc 9848 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9849 /*
AnnaBridge 171:3a7713b1edbc 9850 * @brief Specific device feature definitions
AnnaBridge 171:3a7713b1edbc 9851 */
AnnaBridge 171:3a7713b1edbc 9852 #define RTC_TAMPER2_SUPPORT
AnnaBridge 171:3a7713b1edbc 9853 #define RTC_WAKEUP_SUPPORT
AnnaBridge 171:3a7713b1edbc 9854 #define RTC_BACKUP_SUPPORT
AnnaBridge 171:3a7713b1edbc 9855
AnnaBridge 171:3a7713b1edbc 9856 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 171:3a7713b1edbc 9857 #define RTC_TR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9858 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9859 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 171:3a7713b1edbc 9860 #define RTC_TR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9861 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 9862 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 171:3a7713b1edbc 9863 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9864 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9865 #define RTC_TR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9866 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 9867 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 171:3a7713b1edbc 9868 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9869 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9870 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9871 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9872 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9873 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 9874 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 9875 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9876 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9877 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9878 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9879 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 9880 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 9881 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9882 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9883 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9884 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9885 #define RTC_TR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9886 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 9887 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 171:3a7713b1edbc 9888 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9889 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9890 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9891 #define RTC_TR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9892 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 9893 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 171:3a7713b1edbc 9894 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9895 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9896 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9897 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9898
AnnaBridge 171:3a7713b1edbc 9899 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 171:3a7713b1edbc 9900 #define RTC_DR_YT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9901 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 9902 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 171:3a7713b1edbc 9903 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9904 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9905 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9906 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9907 #define RTC_DR_YU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9908 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 9909 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 171:3a7713b1edbc 9910 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9911 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9912 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9913 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9914 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9915 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 9916 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 9917 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9918 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9919 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9920 #define RTC_DR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9921 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9922 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 171:3a7713b1edbc 9923 #define RTC_DR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9924 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 9925 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 171:3a7713b1edbc 9926 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9927 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9928 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9929 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9930 #define RTC_DR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9931 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 9932 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 171:3a7713b1edbc 9933 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9934 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9935 #define RTC_DR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9936 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 9937 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 171:3a7713b1edbc 9938 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9939 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9940 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9941 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9942
AnnaBridge 171:3a7713b1edbc 9943 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 9944 #define RTC_CR_ITSE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9945 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9946 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
AnnaBridge 171:3a7713b1edbc 9947 #define RTC_CR_COE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9948 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9949 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 171:3a7713b1edbc 9950 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9951 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 9952 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 171:3a7713b1edbc 9953 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9954 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9955 #define RTC_CR_POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9956 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9957 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 171:3a7713b1edbc 9958 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9959 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9960 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 171:3a7713b1edbc 9961 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9962 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9963 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 9964 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9965 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9966 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 171:3a7713b1edbc 9967 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9968 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9969 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 171:3a7713b1edbc 9970 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9971 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9972 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 171:3a7713b1edbc 9973 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9974 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9975 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 171:3a7713b1edbc 9976 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9977 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9978 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 171:3a7713b1edbc 9979 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9980 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9981 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 171:3a7713b1edbc 9982 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9983 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9984 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 171:3a7713b1edbc 9985 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9986 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9987 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 171:3a7713b1edbc 9988 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9989 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9990 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 171:3a7713b1edbc 9991 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9992 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9993 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 171:3a7713b1edbc 9994 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9995 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9996 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 171:3a7713b1edbc 9997 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9998 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9999 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 171:3a7713b1edbc 10000 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10001 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10002 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 171:3a7713b1edbc 10003 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10004 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10005 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 171:3a7713b1edbc 10006 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10007 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 10008 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 171:3a7713b1edbc 10009 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10010 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10011 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10012
AnnaBridge 171:3a7713b1edbc 10013 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 10014 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
AnnaBridge 171:3a7713b1edbc 10015 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 10016 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 171:3a7713b1edbc 10017
AnnaBridge 171:3a7713b1edbc 10018 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 10019 #define RTC_ISR_ITSF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10020 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10021 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
AnnaBridge 171:3a7713b1edbc 10022 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10023 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10024 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 171:3a7713b1edbc 10025 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10026 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10027 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 171:3a7713b1edbc 10028 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10029 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10030 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 171:3a7713b1edbc 10031 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10032 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10033 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 171:3a7713b1edbc 10034 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10035 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10036 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 171:3a7713b1edbc 10037 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10038 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10039 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 171:3a7713b1edbc 10040 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10041 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10042 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 171:3a7713b1edbc 10043 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10044 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10045 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 171:3a7713b1edbc 10046 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10047 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10048 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 171:3a7713b1edbc 10049 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10050 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10051 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 171:3a7713b1edbc 10052 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10053 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10054 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 171:3a7713b1edbc 10055 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10056 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10057 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 171:3a7713b1edbc 10058 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10059 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10060 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 171:3a7713b1edbc 10061 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10062 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10063 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 171:3a7713b1edbc 10064 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10065 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10066 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 171:3a7713b1edbc 10067
AnnaBridge 171:3a7713b1edbc 10068 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 171:3a7713b1edbc 10069 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10070 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 10071 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 171:3a7713b1edbc 10072 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10073 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 10074 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 171:3a7713b1edbc 10075
AnnaBridge 171:3a7713b1edbc 10076 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 171:3a7713b1edbc 10077 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10078 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10079 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 171:3a7713b1edbc 10080
AnnaBridge 171:3a7713b1edbc 10081 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 171:3a7713b1edbc 10082 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10083 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10084 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 10085 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10086 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10087 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 10088 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10089 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 10090 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 171:3a7713b1edbc 10091 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10092 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10093 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10094 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 10095 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 171:3a7713b1edbc 10096 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10097 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10098 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10099 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10100 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10101 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10102 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 10103 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10104 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10105 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 171:3a7713b1edbc 10106 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10107 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 10108 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 171:3a7713b1edbc 10109 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10110 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10111 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10112 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 10113 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 171:3a7713b1edbc 10114 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10115 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10116 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10117 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10118 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10119 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10120 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 10121 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10122 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 10123 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 10124 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10125 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10126 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10127 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10128 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10129 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 10130 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10131 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10132 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10133 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10134 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10135 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10136 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 10137 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10138 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 10139 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 171:3a7713b1edbc 10140 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10141 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10142 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10143 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10144 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 10145 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 171:3a7713b1edbc 10146 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10147 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10148 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10149 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10150
AnnaBridge 171:3a7713b1edbc 10151 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 171:3a7713b1edbc 10152 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10153 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10154 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 10155 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10156 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10157 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 10158 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10159 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 10160 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 171:3a7713b1edbc 10161 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10162 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10163 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10164 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 10165 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 171:3a7713b1edbc 10166 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10167 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10168 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10169 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10170 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10171 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10172 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 10173 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10174 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10175 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 171:3a7713b1edbc 10176 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10177 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 10178 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 171:3a7713b1edbc 10179 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10180 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10181 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10182 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 10183 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 171:3a7713b1edbc 10184 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10185 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10186 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10187 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10188 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10189 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10190 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 10191 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10192 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 10193 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 10194 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10195 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10196 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10197 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10198 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10199 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 10200 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10201 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10202 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10203 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10204 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10205 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10206 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 10207 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10208 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 10209 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 171:3a7713b1edbc 10210 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10211 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10212 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10213 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10214 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 10215 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 171:3a7713b1edbc 10216 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10217 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10218 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10219 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10220
AnnaBridge 171:3a7713b1edbc 10221 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 171:3a7713b1edbc 10222 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10223 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 10224 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 171:3a7713b1edbc 10225
AnnaBridge 171:3a7713b1edbc 10226 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 171:3a7713b1edbc 10227 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10228 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10229 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 10230
AnnaBridge 171:3a7713b1edbc 10231 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 171:3a7713b1edbc 10232 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10233 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 10234 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 171:3a7713b1edbc 10235 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10236 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10237 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 171:3a7713b1edbc 10238
AnnaBridge 171:3a7713b1edbc 10239 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 171:3a7713b1edbc 10240 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10241 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10242 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 171:3a7713b1edbc 10243 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10244 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 10245 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 171:3a7713b1edbc 10246 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10247 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10248 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10249 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 10250 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 171:3a7713b1edbc 10251 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10252 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10253 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10254 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10255 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10256 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 10257 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 10258 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10259 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10260 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10261 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10262 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10263 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 10264 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10265 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10266 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10267 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10268 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10269 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 10270 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 171:3a7713b1edbc 10271 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10272 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10273 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10274 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10275 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 10276 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 171:3a7713b1edbc 10277 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10278 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10279 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10280 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10281
AnnaBridge 171:3a7713b1edbc 10282 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 171:3a7713b1edbc 10283 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10284 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 10285 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 10286 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10287 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10288 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10289 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10290 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10291 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 171:3a7713b1edbc 10292 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10293 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10294 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 171:3a7713b1edbc 10295 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10296 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10297 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10298 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10299 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10300 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 10301 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 171:3a7713b1edbc 10302 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10303 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10304 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10305 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 10306 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 171:3a7713b1edbc 10307 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10308 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10309 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10310 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10311
AnnaBridge 171:3a7713b1edbc 10312 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 171:3a7713b1edbc 10313 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10314 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10315 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 10316
AnnaBridge 171:3a7713b1edbc 10317 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 171:3a7713b1edbc 10318 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10319 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10320 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 171:3a7713b1edbc 10321 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10322 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10323 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 171:3a7713b1edbc 10324 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10325 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10326 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 171:3a7713b1edbc 10327 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10328 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 10329 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 171:3a7713b1edbc 10330 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10331 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10332 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10333 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10334 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10335 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10336 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10337 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10338 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10339
AnnaBridge 171:3a7713b1edbc 10340 /******************** Bits definition for RTC_TAMPCR register ***************/
AnnaBridge 171:3a7713b1edbc 10341 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10342 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10343 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
AnnaBridge 171:3a7713b1edbc 10344 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10345 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10346 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
AnnaBridge 171:3a7713b1edbc 10347 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10348 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10349 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
AnnaBridge 171:3a7713b1edbc 10350 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10351 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10352 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
AnnaBridge 171:3a7713b1edbc 10353 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10354 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 10355 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
AnnaBridge 171:3a7713b1edbc 10356 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10357 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10358 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10359 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 10360 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
AnnaBridge 171:3a7713b1edbc 10361 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10362 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10363 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10364 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 10365 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
AnnaBridge 171:3a7713b1edbc 10366 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10367 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10368 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10369 #define RTC_TAMPCR_TAMPTS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10370 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10371 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
AnnaBridge 171:3a7713b1edbc 10372 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10373 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10374 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
AnnaBridge 171:3a7713b1edbc 10375 #define RTC_TAMPCR_TAMP2E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10376 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10377 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
AnnaBridge 171:3a7713b1edbc 10378 #define RTC_TAMPCR_TAMPIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10379 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10380 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
AnnaBridge 171:3a7713b1edbc 10381
AnnaBridge 171:3a7713b1edbc 10382 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 171:3a7713b1edbc 10383 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10384 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 10385 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 10386 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10387 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10388 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10389 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10390 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10391 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 10392 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 10393
AnnaBridge 171:3a7713b1edbc 10394 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 171:3a7713b1edbc 10395 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10396 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 10397 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 10398 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10399 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10400 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10401 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10402 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10403 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 10404 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 10405
AnnaBridge 171:3a7713b1edbc 10406 /******************** Bits definition for RTC_0R register *******************/
AnnaBridge 171:3a7713b1edbc 10407 #define RTC_OR_OUT_RMP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10408 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10409 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
AnnaBridge 171:3a7713b1edbc 10410 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10411 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10412 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
AnnaBridge 171:3a7713b1edbc 10413
AnnaBridge 171:3a7713b1edbc 10414
AnnaBridge 171:3a7713b1edbc 10415 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 171:3a7713b1edbc 10416 #define RTC_BKP0R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10417 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10418 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 171:3a7713b1edbc 10419
AnnaBridge 171:3a7713b1edbc 10420 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 171:3a7713b1edbc 10421 #define RTC_BKP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10422 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10423 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 171:3a7713b1edbc 10424
AnnaBridge 171:3a7713b1edbc 10425 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 171:3a7713b1edbc 10426 #define RTC_BKP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10427 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10428 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 171:3a7713b1edbc 10429
AnnaBridge 171:3a7713b1edbc 10430 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 171:3a7713b1edbc 10431 #define RTC_BKP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10432 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10433 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 171:3a7713b1edbc 10434
AnnaBridge 171:3a7713b1edbc 10435 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 171:3a7713b1edbc 10436 #define RTC_BKP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10437 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10438 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 171:3a7713b1edbc 10439
AnnaBridge 171:3a7713b1edbc 10440 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 171:3a7713b1edbc 10441 #define RTC_BKP5R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10442 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10443 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 171:3a7713b1edbc 10444
AnnaBridge 171:3a7713b1edbc 10445 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 171:3a7713b1edbc 10446 #define RTC_BKP6R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10447 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10448 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 171:3a7713b1edbc 10449
AnnaBridge 171:3a7713b1edbc 10450 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 171:3a7713b1edbc 10451 #define RTC_BKP7R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10452 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10453 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 171:3a7713b1edbc 10454
AnnaBridge 171:3a7713b1edbc 10455 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 171:3a7713b1edbc 10456 #define RTC_BKP8R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10457 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10458 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 171:3a7713b1edbc 10459
AnnaBridge 171:3a7713b1edbc 10460 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 171:3a7713b1edbc 10461 #define RTC_BKP9R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10462 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10463 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 171:3a7713b1edbc 10464
AnnaBridge 171:3a7713b1edbc 10465 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 171:3a7713b1edbc 10466 #define RTC_BKP10R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10467 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10468 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 171:3a7713b1edbc 10469
AnnaBridge 171:3a7713b1edbc 10470 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 171:3a7713b1edbc 10471 #define RTC_BKP11R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10472 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10473 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 171:3a7713b1edbc 10474
AnnaBridge 171:3a7713b1edbc 10475 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 171:3a7713b1edbc 10476 #define RTC_BKP12R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10477 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10478 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 171:3a7713b1edbc 10479
AnnaBridge 171:3a7713b1edbc 10480 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 171:3a7713b1edbc 10481 #define RTC_BKP13R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10482 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10483 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 171:3a7713b1edbc 10484
AnnaBridge 171:3a7713b1edbc 10485 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 171:3a7713b1edbc 10486 #define RTC_BKP14R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10487 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10488 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 171:3a7713b1edbc 10489
AnnaBridge 171:3a7713b1edbc 10490 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 171:3a7713b1edbc 10491 #define RTC_BKP15R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10492 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10493 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 171:3a7713b1edbc 10494
AnnaBridge 171:3a7713b1edbc 10495 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 171:3a7713b1edbc 10496 #define RTC_BKP16R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10497 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10498 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 171:3a7713b1edbc 10499
AnnaBridge 171:3a7713b1edbc 10500 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 171:3a7713b1edbc 10501 #define RTC_BKP17R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10502 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10503 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 171:3a7713b1edbc 10504
AnnaBridge 171:3a7713b1edbc 10505 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 171:3a7713b1edbc 10506 #define RTC_BKP18R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10507 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10508 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 171:3a7713b1edbc 10509
AnnaBridge 171:3a7713b1edbc 10510 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 171:3a7713b1edbc 10511 #define RTC_BKP19R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10512 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10513 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 171:3a7713b1edbc 10514
AnnaBridge 171:3a7713b1edbc 10515 /******************** Bits definition for RTC_BKP20R register ***************/
AnnaBridge 171:3a7713b1edbc 10516 #define RTC_BKP20R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10517 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10518 #define RTC_BKP20R RTC_BKP20R_Msk
AnnaBridge 171:3a7713b1edbc 10519
AnnaBridge 171:3a7713b1edbc 10520 /******************** Bits definition for RTC_BKP21R register ***************/
AnnaBridge 171:3a7713b1edbc 10521 #define RTC_BKP21R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10522 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10523 #define RTC_BKP21R RTC_BKP21R_Msk
AnnaBridge 171:3a7713b1edbc 10524
AnnaBridge 171:3a7713b1edbc 10525 /******************** Bits definition for RTC_BKP22R register ***************/
AnnaBridge 171:3a7713b1edbc 10526 #define RTC_BKP22R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10527 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10528 #define RTC_BKP22R RTC_BKP22R_Msk
AnnaBridge 171:3a7713b1edbc 10529
AnnaBridge 171:3a7713b1edbc 10530 /******************** Bits definition for RTC_BKP23R register ***************/
AnnaBridge 171:3a7713b1edbc 10531 #define RTC_BKP23R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10532 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10533 #define RTC_BKP23R RTC_BKP23R_Msk
AnnaBridge 171:3a7713b1edbc 10534
AnnaBridge 171:3a7713b1edbc 10535 /******************** Bits definition for RTC_BKP24R register ***************/
AnnaBridge 171:3a7713b1edbc 10536 #define RTC_BKP24R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10537 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10538 #define RTC_BKP24R RTC_BKP24R_Msk
AnnaBridge 171:3a7713b1edbc 10539
AnnaBridge 171:3a7713b1edbc 10540 /******************** Bits definition for RTC_BKP25R register ***************/
AnnaBridge 171:3a7713b1edbc 10541 #define RTC_BKP25R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10542 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10543 #define RTC_BKP25R RTC_BKP25R_Msk
AnnaBridge 171:3a7713b1edbc 10544
AnnaBridge 171:3a7713b1edbc 10545 /******************** Bits definition for RTC_BKP26R register ***************/
AnnaBridge 171:3a7713b1edbc 10546 #define RTC_BKP26R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10547 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10548 #define RTC_BKP26R RTC_BKP26R_Msk
AnnaBridge 171:3a7713b1edbc 10549
AnnaBridge 171:3a7713b1edbc 10550 /******************** Bits definition for RTC_BKP27R register ***************/
AnnaBridge 171:3a7713b1edbc 10551 #define RTC_BKP27R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10552 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10553 #define RTC_BKP27R RTC_BKP27R_Msk
AnnaBridge 171:3a7713b1edbc 10554
AnnaBridge 171:3a7713b1edbc 10555 /******************** Bits definition for RTC_BKP28R register ***************/
AnnaBridge 171:3a7713b1edbc 10556 #define RTC_BKP28R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10557 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10558 #define RTC_BKP28R RTC_BKP28R_Msk
AnnaBridge 171:3a7713b1edbc 10559
AnnaBridge 171:3a7713b1edbc 10560 /******************** Bits definition for RTC_BKP29R register ***************/
AnnaBridge 171:3a7713b1edbc 10561 #define RTC_BKP29R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10562 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10563 #define RTC_BKP29R RTC_BKP29R_Msk
AnnaBridge 171:3a7713b1edbc 10564
AnnaBridge 171:3a7713b1edbc 10565 /******************** Bits definition for RTC_BKP30R register ***************/
AnnaBridge 171:3a7713b1edbc 10566 #define RTC_BKP30R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10567 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10568 #define RTC_BKP30R RTC_BKP30R_Msk
AnnaBridge 171:3a7713b1edbc 10569
AnnaBridge 171:3a7713b1edbc 10570 /******************** Bits definition for RTC_BKP31R register ***************/
AnnaBridge 171:3a7713b1edbc 10571 #define RTC_BKP31R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10572 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10573 #define RTC_BKP31R RTC_BKP31R_Msk
AnnaBridge 171:3a7713b1edbc 10574
AnnaBridge 171:3a7713b1edbc 10575 /******************** Number of backup registers ******************************/
AnnaBridge 171:3a7713b1edbc 10576 #define RTC_BKP_NUMBER 32U
AnnaBridge 171:3a7713b1edbc 10577
AnnaBridge 171:3a7713b1edbc 10578 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10579 /* */
AnnaBridge 171:3a7713b1edbc 10580 /* Serial Audio Interface */
AnnaBridge 171:3a7713b1edbc 10581 /* */
AnnaBridge 171:3a7713b1edbc 10582 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10583 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 171:3a7713b1edbc 10584 #define SAI_GCR_SYNCIN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10585 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 10586 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 171:3a7713b1edbc 10587 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10588 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10589
AnnaBridge 171:3a7713b1edbc 10590 #define SAI_GCR_SYNCOUT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10591 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 10592 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 171:3a7713b1edbc 10593 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10594 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10595
AnnaBridge 171:3a7713b1edbc 10596 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 10597 #define SAI_xCR1_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10598 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 10599 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 171:3a7713b1edbc 10600 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10601 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10602
AnnaBridge 171:3a7713b1edbc 10603 #define SAI_xCR1_PRTCFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10604 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 10605 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 171:3a7713b1edbc 10606 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10607 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10608
AnnaBridge 171:3a7713b1edbc 10609 #define SAI_xCR1_DS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10610 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 10611 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
AnnaBridge 171:3a7713b1edbc 10612 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10613 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10614 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10615
AnnaBridge 171:3a7713b1edbc 10616 #define SAI_xCR1_LSBFIRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10617 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10618 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
AnnaBridge 171:3a7713b1edbc 10619 #define SAI_xCR1_CKSTR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10620 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10621 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
AnnaBridge 171:3a7713b1edbc 10622
AnnaBridge 171:3a7713b1edbc 10623 #define SAI_xCR1_SYNCEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10624 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 10625 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 171:3a7713b1edbc 10626 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10627 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10628
AnnaBridge 171:3a7713b1edbc 10629 #define SAI_xCR1_MONO_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10630 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10631 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
AnnaBridge 171:3a7713b1edbc 10632 #define SAI_xCR1_OUTDRIV_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10633 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10634 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
AnnaBridge 171:3a7713b1edbc 10635 #define SAI_xCR1_SAIEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10636 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10637 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
AnnaBridge 171:3a7713b1edbc 10638 #define SAI_xCR1_DMAEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10639 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10640 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
AnnaBridge 171:3a7713b1edbc 10641 #define SAI_xCR1_NODIV_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10642 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10643 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
AnnaBridge 171:3a7713b1edbc 10644
AnnaBridge 171:3a7713b1edbc 10645 #define SAI_xCR1_MCKDIV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10646 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 10647 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
AnnaBridge 171:3a7713b1edbc 10648 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 10649 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 10650 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 10651 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 10652
AnnaBridge 171:3a7713b1edbc 10653 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 10654 #define SAI_xCR2_FTH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10655 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 10656 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 171:3a7713b1edbc 10657 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10658 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10659 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10660
AnnaBridge 171:3a7713b1edbc 10661 #define SAI_xCR2_FFLUSH_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10662 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10663 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
AnnaBridge 171:3a7713b1edbc 10664 #define SAI_xCR2_TRIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10665 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10666 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
AnnaBridge 171:3a7713b1edbc 10667 #define SAI_xCR2_MUTE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10668 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10669 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
AnnaBridge 171:3a7713b1edbc 10670 #define SAI_xCR2_MUTEVAL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10671 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10672 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
AnnaBridge 171:3a7713b1edbc 10673
AnnaBridge 171:3a7713b1edbc 10674
AnnaBridge 171:3a7713b1edbc 10675 #define SAI_xCR2_MUTECNT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10676 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
AnnaBridge 171:3a7713b1edbc 10677 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 171:3a7713b1edbc 10678 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10679 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10680 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10681 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10682 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10683 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10684
AnnaBridge 171:3a7713b1edbc 10685 #define SAI_xCR2_CPL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10686 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10687 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
AnnaBridge 171:3a7713b1edbc 10688 #define SAI_xCR2_COMP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10689 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 10690 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
AnnaBridge 171:3a7713b1edbc 10691 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10692 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10693
AnnaBridge 171:3a7713b1edbc 10694
AnnaBridge 171:3a7713b1edbc 10695 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 171:3a7713b1edbc 10696 #define SAI_xFRCR_FRL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10697 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 10698 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
AnnaBridge 171:3a7713b1edbc 10699 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10700 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10701 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10702 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10703 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10704 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10705 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10706 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10707
AnnaBridge 171:3a7713b1edbc 10708 #define SAI_xFRCR_FSALL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10709 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
AnnaBridge 171:3a7713b1edbc 10710 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
AnnaBridge 171:3a7713b1edbc 10711 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10712 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10713 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10714 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10715 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10716 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10717 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10718
AnnaBridge 171:3a7713b1edbc 10719 #define SAI_xFRCR_FSDEF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10720 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10721 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
AnnaBridge 171:3a7713b1edbc 10722 #define SAI_xFRCR_FSPOL_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10723 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10724 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
AnnaBridge 171:3a7713b1edbc 10725 #define SAI_xFRCR_FSOFF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10726 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10727 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
AnnaBridge 171:3a7713b1edbc 10728
AnnaBridge 171:3a7713b1edbc 10729 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 171:3a7713b1edbc 10730 #define SAI_xSLOTR_FBOFF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10731 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 10732 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
AnnaBridge 171:3a7713b1edbc 10733 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10734 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10735 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10736 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10737 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10738
AnnaBridge 171:3a7713b1edbc 10739 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10740 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 10741 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 171:3a7713b1edbc 10742 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10743 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10744
AnnaBridge 171:3a7713b1edbc 10745 #define SAI_xSLOTR_NBSLOT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10746 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10747 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 171:3a7713b1edbc 10748 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10749 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10750 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10751 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10752
AnnaBridge 171:3a7713b1edbc 10753 #define SAI_xSLOTR_SLOTEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10754 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 10755 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
AnnaBridge 171:3a7713b1edbc 10756
AnnaBridge 171:3a7713b1edbc 10757 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 171:3a7713b1edbc 10758 #define SAI_xIMR_OVRUDRIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10759 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10760 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 10761 #define SAI_xIMR_MUTEDETIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10762 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10763 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 10764 #define SAI_xIMR_WCKCFGIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10765 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10766 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 171:3a7713b1edbc 10767 #define SAI_xIMR_FREQIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10768 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10769 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
AnnaBridge 171:3a7713b1edbc 10770 #define SAI_xIMR_CNRDYIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10771 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10772 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
AnnaBridge 171:3a7713b1edbc 10773 #define SAI_xIMR_AFSDETIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10774 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10775 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 10776 #define SAI_xIMR_LFSDETIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10777 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10778 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 10779
AnnaBridge 171:3a7713b1edbc 10780 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 171:3a7713b1edbc 10781 #define SAI_xSR_OVRUDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10782 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10783 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
AnnaBridge 171:3a7713b1edbc 10784 #define SAI_xSR_MUTEDET_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10785 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10786 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
AnnaBridge 171:3a7713b1edbc 10787 #define SAI_xSR_WCKCFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10788 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10789 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
AnnaBridge 171:3a7713b1edbc 10790 #define SAI_xSR_FREQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10791 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10792 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
AnnaBridge 171:3a7713b1edbc 10793 #define SAI_xSR_CNRDY_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10794 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10795 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
AnnaBridge 171:3a7713b1edbc 10796 #define SAI_xSR_AFSDET_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10797 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10798 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 10799 #define SAI_xSR_LFSDET_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10800 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10801 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 10802
AnnaBridge 171:3a7713b1edbc 10803 #define SAI_xSR_FLVL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10804 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 10805 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 171:3a7713b1edbc 10806 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10807 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10808 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10809
AnnaBridge 171:3a7713b1edbc 10810 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 171:3a7713b1edbc 10811 #define SAI_xCLRFR_COVRUDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10812 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10813 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
AnnaBridge 171:3a7713b1edbc 10814 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10815 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10816 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
AnnaBridge 171:3a7713b1edbc 10817 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10818 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10819 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
AnnaBridge 171:3a7713b1edbc 10820 #define SAI_xCLRFR_CFREQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10821 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10822 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
AnnaBridge 171:3a7713b1edbc 10823 #define SAI_xCLRFR_CCNRDY_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10824 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10825 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
AnnaBridge 171:3a7713b1edbc 10826 #define SAI_xCLRFR_CAFSDET_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10827 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10828 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 10829 #define SAI_xCLRFR_CLFSDET_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10830 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10831 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 10832
AnnaBridge 171:3a7713b1edbc 10833 /****************** Bit definition for SAI_xDR register ******************/
AnnaBridge 171:3a7713b1edbc 10834 #define SAI_xDR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10835 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10836 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
AnnaBridge 171:3a7713b1edbc 10837
AnnaBridge 171:3a7713b1edbc 10838 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10839 /* */
AnnaBridge 171:3a7713b1edbc 10840 /* Serial Peripheral Interface (SPI) */
AnnaBridge 171:3a7713b1edbc 10841 /* */
AnnaBridge 171:3a7713b1edbc 10842 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10843 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 10844 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10845 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10846 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 171:3a7713b1edbc 10847 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10848 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10849 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 171:3a7713b1edbc 10850 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10851 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10852 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 171:3a7713b1edbc 10853
AnnaBridge 171:3a7713b1edbc 10854 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10855 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 10856 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 171:3a7713b1edbc 10857 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10858 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10859 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10860
AnnaBridge 171:3a7713b1edbc 10861 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10862 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10863 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 171:3a7713b1edbc 10864 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10865 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10866 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 171:3a7713b1edbc 10867 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10868 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10869 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 171:3a7713b1edbc 10870 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10871 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10872 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 171:3a7713b1edbc 10873 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10874 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10875 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 171:3a7713b1edbc 10876 #define SPI_CR1_CRCL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10877 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10878 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
AnnaBridge 171:3a7713b1edbc 10879 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10880 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10881 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 171:3a7713b1edbc 10882 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10883 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10884 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 171:3a7713b1edbc 10885 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10886 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10887 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 171:3a7713b1edbc 10888 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10889 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10890 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
AnnaBridge 171:3a7713b1edbc 10891
AnnaBridge 171:3a7713b1edbc 10892 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 10893 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10894 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10895 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 10896 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10897 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10898 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 10899 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10900 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10901 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
AnnaBridge 171:3a7713b1edbc 10902 #define SPI_CR2_NSSP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10903 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10904 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
AnnaBridge 171:3a7713b1edbc 10905 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10906 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10907 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
AnnaBridge 171:3a7713b1edbc 10908 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10909 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10910 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 10911 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10912 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10913 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 10914 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10915 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10916 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 10917 #define SPI_CR2_DS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10918 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10919 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
AnnaBridge 171:3a7713b1edbc 10920 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10921 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10922 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10923 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10924 #define SPI_CR2_FRXTH_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10925 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10926 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
AnnaBridge 171:3a7713b1edbc 10927 #define SPI_CR2_LDMARX_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10928 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10929 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
AnnaBridge 171:3a7713b1edbc 10930 #define SPI_CR2_LDMATX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10931 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10932 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
AnnaBridge 171:3a7713b1edbc 10933
AnnaBridge 171:3a7713b1edbc 10934 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 171:3a7713b1edbc 10935 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10936 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10937 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
AnnaBridge 171:3a7713b1edbc 10938 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10939 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10940 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
AnnaBridge 171:3a7713b1edbc 10941 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10942 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10943 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
AnnaBridge 171:3a7713b1edbc 10944 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10945 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10946 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
AnnaBridge 171:3a7713b1edbc 10947 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10948 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10949 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
AnnaBridge 171:3a7713b1edbc 10950 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10951 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10952 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
AnnaBridge 171:3a7713b1edbc 10953 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10954 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10955 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 10956 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10957 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10958 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 10959 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10960 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10961 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
AnnaBridge 171:3a7713b1edbc 10962 #define SPI_SR_FRLVL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10963 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 10964 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
AnnaBridge 171:3a7713b1edbc 10965 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10966 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10967 #define SPI_SR_FTLVL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10968 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 10969 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
AnnaBridge 171:3a7713b1edbc 10970 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10971 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10972
AnnaBridge 171:3a7713b1edbc 10973 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 171:3a7713b1edbc 10974 #define SPI_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10975 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10976 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
AnnaBridge 171:3a7713b1edbc 10977
AnnaBridge 171:3a7713b1edbc 10978 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 171:3a7713b1edbc 10979 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10980 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10981 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
AnnaBridge 171:3a7713b1edbc 10982
AnnaBridge 171:3a7713b1edbc 10983 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 10984 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10985 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10986 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
AnnaBridge 171:3a7713b1edbc 10987
AnnaBridge 171:3a7713b1edbc 10988 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 10989 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10990 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10991 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
AnnaBridge 171:3a7713b1edbc 10992
AnnaBridge 171:3a7713b1edbc 10993 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10994 /* */
AnnaBridge 171:3a7713b1edbc 10995 /* QUADSPI */
AnnaBridge 171:3a7713b1edbc 10996 /* */
AnnaBridge 171:3a7713b1edbc 10997 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10998 /***************** Bit definition for QUADSPI_CR register *******************/
AnnaBridge 171:3a7713b1edbc 10999 #define QUADSPI_CR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11000 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11001 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
AnnaBridge 171:3a7713b1edbc 11002 #define QUADSPI_CR_ABORT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11003 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11004 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
AnnaBridge 171:3a7713b1edbc 11005 #define QUADSPI_CR_DMAEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11006 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11007 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
AnnaBridge 171:3a7713b1edbc 11008 #define QUADSPI_CR_TCEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11009 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11010 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
AnnaBridge 171:3a7713b1edbc 11011 #define QUADSPI_CR_SSHIFT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11012 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11013 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
AnnaBridge 171:3a7713b1edbc 11014 #define QUADSPI_CR_DFM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11015 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11016 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
AnnaBridge 171:3a7713b1edbc 11017 #define QUADSPI_CR_FSEL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11018 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11019 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
AnnaBridge 171:3a7713b1edbc 11020 #define QUADSPI_CR_FTHRES_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11021 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11022 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
AnnaBridge 171:3a7713b1edbc 11023 #define QUADSPI_CR_TEIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11024 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11025 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11026 #define QUADSPI_CR_TCIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11027 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11028 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11029 #define QUADSPI_CR_FTIE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11030 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11031 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11032 #define QUADSPI_CR_SMIE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11033 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11034 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11035 #define QUADSPI_CR_TOIE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11036 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11037 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11038 #define QUADSPI_CR_APMS_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11039 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11040 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
AnnaBridge 171:3a7713b1edbc 11041 #define QUADSPI_CR_PMM_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11042 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11043 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
AnnaBridge 171:3a7713b1edbc 11044 #define QUADSPI_CR_PRESCALER_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11045 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 11046 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
AnnaBridge 171:3a7713b1edbc 11047
AnnaBridge 171:3a7713b1edbc 11048 /***************** Bit definition for QUADSPI_DCR register ******************/
AnnaBridge 171:3a7713b1edbc 11049 #define QUADSPI_DCR_CKMODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11050 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11051 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
AnnaBridge 171:3a7713b1edbc 11052 #define QUADSPI_DCR_CSHT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11053 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11054 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
AnnaBridge 171:3a7713b1edbc 11055 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11056 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11057 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11058 #define QUADSPI_DCR_FSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11059 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 11060 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
AnnaBridge 171:3a7713b1edbc 11061
AnnaBridge 171:3a7713b1edbc 11062 /****************** Bit definition for QUADSPI_SR register *******************/
AnnaBridge 171:3a7713b1edbc 11063 #define QUADSPI_SR_TEF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11064 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11065 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
AnnaBridge 171:3a7713b1edbc 11066 #define QUADSPI_SR_TCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11067 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11068 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
AnnaBridge 171:3a7713b1edbc 11069 #define QUADSPI_SR_FTF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11070 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11071 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 171:3a7713b1edbc 11072 #define QUADSPI_SR_SMF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11073 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11074 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
AnnaBridge 171:3a7713b1edbc 11075 #define QUADSPI_SR_TOF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11076 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11077 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
AnnaBridge 171:3a7713b1edbc 11078 #define QUADSPI_SR_BUSY_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11079 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11080 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
AnnaBridge 171:3a7713b1edbc 11081 #define QUADSPI_SR_FLEVEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11082 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 11083 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 171:3a7713b1edbc 11084
AnnaBridge 171:3a7713b1edbc 11085 /****************** Bit definition for QUADSPI_FCR register ******************/
AnnaBridge 171:3a7713b1edbc 11086 #define QUADSPI_FCR_CTEF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11087 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11088 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
AnnaBridge 171:3a7713b1edbc 11089 #define QUADSPI_FCR_CTCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11090 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11091 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
AnnaBridge 171:3a7713b1edbc 11092 #define QUADSPI_FCR_CSMF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11093 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11094 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
AnnaBridge 171:3a7713b1edbc 11095 #define QUADSPI_FCR_CTOF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11096 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11097 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
AnnaBridge 171:3a7713b1edbc 11098
AnnaBridge 171:3a7713b1edbc 11099 /****************** Bit definition for QUADSPI_DLR register ******************/
AnnaBridge 171:3a7713b1edbc 11100 #define QUADSPI_DLR_DL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11101 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11102 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
AnnaBridge 171:3a7713b1edbc 11103
AnnaBridge 171:3a7713b1edbc 11104 /****************** Bit definition for QUADSPI_CCR register ******************/
AnnaBridge 171:3a7713b1edbc 11105 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11106 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 11107 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
AnnaBridge 171:3a7713b1edbc 11108 #define QUADSPI_CCR_IMODE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11109 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 11110 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
AnnaBridge 171:3a7713b1edbc 11111 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11112 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11113 #define QUADSPI_CCR_ADMODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11114 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 11115 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
AnnaBridge 171:3a7713b1edbc 11116 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11117 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11118 #define QUADSPI_CCR_ADSIZE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11119 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 11120 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
AnnaBridge 171:3a7713b1edbc 11121 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11122 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11123 #define QUADSPI_CCR_ABMODE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11124 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 11125 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
AnnaBridge 171:3a7713b1edbc 11126 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11127 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11128 #define QUADSPI_CCR_ABSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11129 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 11130 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
AnnaBridge 171:3a7713b1edbc 11131 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11132 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11133 #define QUADSPI_CCR_DCYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11134 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 11135 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
AnnaBridge 171:3a7713b1edbc 11136 #define QUADSPI_CCR_DMODE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11137 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 11138 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
AnnaBridge 171:3a7713b1edbc 11139 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11140 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11141 #define QUADSPI_CCR_FMODE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 11142 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 11143 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
AnnaBridge 171:3a7713b1edbc 11144 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11145 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11146 #define QUADSPI_CCR_SIOO_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11147 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11148 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
AnnaBridge 171:3a7713b1edbc 11149 #define QUADSPI_CCR_DHHC_Pos (30U)
AnnaBridge 171:3a7713b1edbc 11150 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 11151 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
AnnaBridge 171:3a7713b1edbc 11152 #define QUADSPI_CCR_DDRM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11153 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11154 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
AnnaBridge 171:3a7713b1edbc 11155
AnnaBridge 171:3a7713b1edbc 11156 /****************** Bit definition for QUADSPI_AR register *******************/
AnnaBridge 171:3a7713b1edbc 11157 #define QUADSPI_AR_ADDRESS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11158 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11159 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
AnnaBridge 171:3a7713b1edbc 11160
AnnaBridge 171:3a7713b1edbc 11161 /****************** Bit definition for QUADSPI_ABR register ******************/
AnnaBridge 171:3a7713b1edbc 11162 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11163 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11164 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
AnnaBridge 171:3a7713b1edbc 11165
AnnaBridge 171:3a7713b1edbc 11166 /****************** Bit definition for QUADSPI_DR register *******************/
AnnaBridge 171:3a7713b1edbc 11167 #define QUADSPI_DR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11168 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11169 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
AnnaBridge 171:3a7713b1edbc 11170
AnnaBridge 171:3a7713b1edbc 11171 /****************** Bit definition for QUADSPI_PSMKR register ****************/
AnnaBridge 171:3a7713b1edbc 11172 #define QUADSPI_PSMKR_MASK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11173 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11174 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
AnnaBridge 171:3a7713b1edbc 11175
AnnaBridge 171:3a7713b1edbc 11176 /****************** Bit definition for QUADSPI_PSMAR register ****************/
AnnaBridge 171:3a7713b1edbc 11177 #define QUADSPI_PSMAR_MATCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11178 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11179 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
AnnaBridge 171:3a7713b1edbc 11180
AnnaBridge 171:3a7713b1edbc 11181 /****************** Bit definition for QUADSPI_PIR register *****************/
AnnaBridge 171:3a7713b1edbc 11182 #define QUADSPI_PIR_INTERVAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11183 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 11184 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
AnnaBridge 171:3a7713b1edbc 11185
AnnaBridge 171:3a7713b1edbc 11186 /****************** Bit definition for QUADSPI_LPTR register *****************/
AnnaBridge 171:3a7713b1edbc 11187 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11188 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 11189 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
AnnaBridge 171:3a7713b1edbc 11190
AnnaBridge 171:3a7713b1edbc 11191 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11192 /* */
AnnaBridge 171:3a7713b1edbc 11193 /* SYSCFG */
AnnaBridge 171:3a7713b1edbc 11194 /* */
AnnaBridge 171:3a7713b1edbc 11195 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11196 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 171:3a7713b1edbc 11197 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11198 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11199 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 171:3a7713b1edbc 11200 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11201 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11202 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11203
AnnaBridge 171:3a7713b1edbc 11204 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
AnnaBridge 171:3a7713b1edbc 11205 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11206 #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11207 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
AnnaBridge 171:3a7713b1edbc 11208 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11209 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11210 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
AnnaBridge 171:3a7713b1edbc 11211 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11212 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11213 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 11214 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11215 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11216 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 11217 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11218 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11219 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 11220 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11221 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11222 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 11223 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
AnnaBridge 171:3a7713b1edbc 11224 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
AnnaBridge 171:3a7713b1edbc 11225 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
AnnaBridge 171:3a7713b1edbc 11226 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
AnnaBridge 171:3a7713b1edbc 11227 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
AnnaBridge 171:3a7713b1edbc 11228 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
AnnaBridge 171:3a7713b1edbc 11229
AnnaBridge 171:3a7713b1edbc 11230 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 171:3a7713b1edbc 11231 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11232 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11233 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 171:3a7713b1edbc 11234 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11235 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11236 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 171:3a7713b1edbc 11237 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11238 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11239 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 171:3a7713b1edbc 11240 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11241 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11242 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 171:3a7713b1edbc 11243
AnnaBridge 171:3a7713b1edbc 11244 /**
AnnaBridge 171:3a7713b1edbc 11245 * @brief EXTI0 configuration
AnnaBridge 171:3a7713b1edbc 11246 */
AnnaBridge 171:3a7713b1edbc 11247 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
AnnaBridge 171:3a7713b1edbc 11248 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
AnnaBridge 171:3a7713b1edbc 11249 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
AnnaBridge 171:3a7713b1edbc 11250
AnnaBridge 171:3a7713b1edbc 11251 /**
AnnaBridge 171:3a7713b1edbc 11252 * @brief EXTI1 configuration
AnnaBridge 171:3a7713b1edbc 11253 */
AnnaBridge 171:3a7713b1edbc 11254 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
AnnaBridge 171:3a7713b1edbc 11255 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
AnnaBridge 171:3a7713b1edbc 11256 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
AnnaBridge 171:3a7713b1edbc 11257
AnnaBridge 171:3a7713b1edbc 11258 /**
AnnaBridge 171:3a7713b1edbc 11259 * @brief EXTI2 configuration
AnnaBridge 171:3a7713b1edbc 11260 */
AnnaBridge 171:3a7713b1edbc 11261 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
AnnaBridge 171:3a7713b1edbc 11262
AnnaBridge 171:3a7713b1edbc 11263 /**
AnnaBridge 171:3a7713b1edbc 11264 * @brief EXTI3 configuration
AnnaBridge 171:3a7713b1edbc 11265 */
AnnaBridge 171:3a7713b1edbc 11266 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
AnnaBridge 171:3a7713b1edbc 11267 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
AnnaBridge 171:3a7713b1edbc 11268 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
AnnaBridge 171:3a7713b1edbc 11269
AnnaBridge 171:3a7713b1edbc 11270 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 171:3a7713b1edbc 11271 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11272 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11273 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 171:3a7713b1edbc 11274 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11275 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11276 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 171:3a7713b1edbc 11277 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11278 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11279 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 171:3a7713b1edbc 11280 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11281 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11282 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 171:3a7713b1edbc 11283 /**
AnnaBridge 171:3a7713b1edbc 11284 * @brief EXTI4 configuration
AnnaBridge 171:3a7713b1edbc 11285 */
AnnaBridge 171:3a7713b1edbc 11286 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
AnnaBridge 171:3a7713b1edbc 11287 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
AnnaBridge 171:3a7713b1edbc 11288
AnnaBridge 171:3a7713b1edbc 11289 /**
AnnaBridge 171:3a7713b1edbc 11290 * @brief EXTI5 configuration
AnnaBridge 171:3a7713b1edbc 11291 */
AnnaBridge 171:3a7713b1edbc 11292 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
AnnaBridge 171:3a7713b1edbc 11293 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
AnnaBridge 171:3a7713b1edbc 11294
AnnaBridge 171:3a7713b1edbc 11295 /**
AnnaBridge 171:3a7713b1edbc 11296 * @brief EXTI6 configuration
AnnaBridge 171:3a7713b1edbc 11297 */
AnnaBridge 171:3a7713b1edbc 11298 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
AnnaBridge 171:3a7713b1edbc 11299 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
AnnaBridge 171:3a7713b1edbc 11300
AnnaBridge 171:3a7713b1edbc 11301 /**
AnnaBridge 171:3a7713b1edbc 11302 * @brief EXTI7 configuration
AnnaBridge 171:3a7713b1edbc 11303 */
AnnaBridge 171:3a7713b1edbc 11304 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
AnnaBridge 171:3a7713b1edbc 11305 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
AnnaBridge 171:3a7713b1edbc 11306
AnnaBridge 171:3a7713b1edbc 11307 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 171:3a7713b1edbc 11308 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11309 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11310 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 171:3a7713b1edbc 11311 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11312 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11313 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 171:3a7713b1edbc 11314 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11315 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11316 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 171:3a7713b1edbc 11317 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11318 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11319 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 171:3a7713b1edbc 11320
AnnaBridge 171:3a7713b1edbc 11321 /**
AnnaBridge 171:3a7713b1edbc 11322 * @brief EXTI8 configuration
AnnaBridge 171:3a7713b1edbc 11323 */
AnnaBridge 171:3a7713b1edbc 11324 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
AnnaBridge 171:3a7713b1edbc 11325
AnnaBridge 171:3a7713b1edbc 11326 /**
AnnaBridge 171:3a7713b1edbc 11327 * @brief EXTI9 configuration
AnnaBridge 171:3a7713b1edbc 11328 */
AnnaBridge 171:3a7713b1edbc 11329 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
AnnaBridge 171:3a7713b1edbc 11330
AnnaBridge 171:3a7713b1edbc 11331 /**
AnnaBridge 171:3a7713b1edbc 11332 * @brief EXTI10 configuration
AnnaBridge 171:3a7713b1edbc 11333 */
AnnaBridge 171:3a7713b1edbc 11334 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
AnnaBridge 171:3a7713b1edbc 11335
AnnaBridge 171:3a7713b1edbc 11336 /**
AnnaBridge 171:3a7713b1edbc 11337 * @brief EXTI11 configuration
AnnaBridge 171:3a7713b1edbc 11338 */
AnnaBridge 171:3a7713b1edbc 11339 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
AnnaBridge 171:3a7713b1edbc 11340
AnnaBridge 171:3a7713b1edbc 11341 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 171:3a7713b1edbc 11342 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11343 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11344 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 171:3a7713b1edbc 11345 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11346 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11347 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 171:3a7713b1edbc 11348 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11349 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11350 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 171:3a7713b1edbc 11351 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11352 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11353 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 171:3a7713b1edbc 11354
AnnaBridge 171:3a7713b1edbc 11355 /**
AnnaBridge 171:3a7713b1edbc 11356 * @brief EXTI12 configuration
AnnaBridge 171:3a7713b1edbc 11357 */
AnnaBridge 171:3a7713b1edbc 11358 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
AnnaBridge 171:3a7713b1edbc 11359
AnnaBridge 171:3a7713b1edbc 11360 /**
AnnaBridge 171:3a7713b1edbc 11361 * @brief EXTI13 configuration
AnnaBridge 171:3a7713b1edbc 11362 */
AnnaBridge 171:3a7713b1edbc 11363 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
AnnaBridge 171:3a7713b1edbc 11364
AnnaBridge 171:3a7713b1edbc 11365 /**
AnnaBridge 171:3a7713b1edbc 11366 * @brief EXTI14 configuration
AnnaBridge 171:3a7713b1edbc 11367 */
AnnaBridge 171:3a7713b1edbc 11368 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
AnnaBridge 171:3a7713b1edbc 11369 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
AnnaBridge 171:3a7713b1edbc 11370
AnnaBridge 171:3a7713b1edbc 11371 /**
AnnaBridge 171:3a7713b1edbc 11372 * @brief EXTI15 configuration
AnnaBridge 171:3a7713b1edbc 11373 */
AnnaBridge 171:3a7713b1edbc 11374 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
AnnaBridge 171:3a7713b1edbc 11375 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
AnnaBridge 171:3a7713b1edbc 11376
AnnaBridge 171:3a7713b1edbc 11377 /****************** Bit definition for SYSCFG_SCSR register ****************/
AnnaBridge 171:3a7713b1edbc 11378 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11379 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11380 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
AnnaBridge 171:3a7713b1edbc 11381 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11382 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11383 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
AnnaBridge 171:3a7713b1edbc 11384
AnnaBridge 171:3a7713b1edbc 11385 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
AnnaBridge 171:3a7713b1edbc 11386 #define SYSCFG_CFGR2_CLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11387 #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11388 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
AnnaBridge 171:3a7713b1edbc 11389 #define SYSCFG_CFGR2_SPL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11390 #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11391 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
AnnaBridge 171:3a7713b1edbc 11392 #define SYSCFG_CFGR2_PVDL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11393 #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11394 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
AnnaBridge 171:3a7713b1edbc 11395 #define SYSCFG_CFGR2_ECCL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11396 #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11397 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
AnnaBridge 171:3a7713b1edbc 11398 #define SYSCFG_CFGR2_SPF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11399 #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11400 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
AnnaBridge 171:3a7713b1edbc 11401
AnnaBridge 171:3a7713b1edbc 11402 /****************** Bit definition for SYSCFG_SWPR register ****************/
AnnaBridge 171:3a7713b1edbc 11403 #define SYSCFG_SWPR_PAGE0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11404 #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11405 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
AnnaBridge 171:3a7713b1edbc 11406 #define SYSCFG_SWPR_PAGE1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11407 #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11408 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
AnnaBridge 171:3a7713b1edbc 11409 #define SYSCFG_SWPR_PAGE2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11410 #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11411 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
AnnaBridge 171:3a7713b1edbc 11412 #define SYSCFG_SWPR_PAGE3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11413 #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11414 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
AnnaBridge 171:3a7713b1edbc 11415 #define SYSCFG_SWPR_PAGE4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11416 #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11417 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
AnnaBridge 171:3a7713b1edbc 11418 #define SYSCFG_SWPR_PAGE5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11419 #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11420 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
AnnaBridge 171:3a7713b1edbc 11421 #define SYSCFG_SWPR_PAGE6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11422 #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11423 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
AnnaBridge 171:3a7713b1edbc 11424 #define SYSCFG_SWPR_PAGE7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11425 #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11426 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
AnnaBridge 171:3a7713b1edbc 11427 #define SYSCFG_SWPR_PAGE8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11428 #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11429 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
AnnaBridge 171:3a7713b1edbc 11430 #define SYSCFG_SWPR_PAGE9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11431 #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11432 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
AnnaBridge 171:3a7713b1edbc 11433 #define SYSCFG_SWPR_PAGE10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11434 #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11435 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
AnnaBridge 171:3a7713b1edbc 11436 #define SYSCFG_SWPR_PAGE11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11437 #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11438 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
AnnaBridge 171:3a7713b1edbc 11439 #define SYSCFG_SWPR_PAGE12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11440 #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11441 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
AnnaBridge 171:3a7713b1edbc 11442 #define SYSCFG_SWPR_PAGE13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11443 #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11444 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
AnnaBridge 171:3a7713b1edbc 11445 #define SYSCFG_SWPR_PAGE14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11446 #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11447 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
AnnaBridge 171:3a7713b1edbc 11448 #define SYSCFG_SWPR_PAGE15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11449 #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11450 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
AnnaBridge 171:3a7713b1edbc 11451
AnnaBridge 171:3a7713b1edbc 11452 /****************** Bit definition for SYSCFG_SKR register ****************/
AnnaBridge 171:3a7713b1edbc 11453 #define SYSCFG_SKR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11454 #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 11455 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
AnnaBridge 171:3a7713b1edbc 11456
AnnaBridge 171:3a7713b1edbc 11457
AnnaBridge 171:3a7713b1edbc 11458
AnnaBridge 171:3a7713b1edbc 11459
AnnaBridge 171:3a7713b1edbc 11460 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11461 /* */
AnnaBridge 171:3a7713b1edbc 11462 /* TIM */
AnnaBridge 171:3a7713b1edbc 11463 /* */
AnnaBridge 171:3a7713b1edbc 11464 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11465 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 11466 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11467 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11468 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 171:3a7713b1edbc 11469 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11470 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11471 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 171:3a7713b1edbc 11472 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11473 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11474 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 171:3a7713b1edbc 11475 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11476 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11477 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 171:3a7713b1edbc 11478 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11479 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11480 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 171:3a7713b1edbc 11481
AnnaBridge 171:3a7713b1edbc 11482 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11483 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 11484 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 171:3a7713b1edbc 11485 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11486 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11487
AnnaBridge 171:3a7713b1edbc 11488 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11489 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11490 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 171:3a7713b1edbc 11491
AnnaBridge 171:3a7713b1edbc 11492 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11493 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 11494 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 171:3a7713b1edbc 11495 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11496 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11497
AnnaBridge 171:3a7713b1edbc 11498 #define TIM_CR1_UIFREMAP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11499 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11500 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
AnnaBridge 171:3a7713b1edbc 11501
AnnaBridge 171:3a7713b1edbc 11502 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 11503 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11504 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11505 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 171:3a7713b1edbc 11506 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11507 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11508 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 171:3a7713b1edbc 11509 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11510 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11511 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 171:3a7713b1edbc 11512
AnnaBridge 171:3a7713b1edbc 11513 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11514 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11515 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 11516 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11517 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11518 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11519
AnnaBridge 171:3a7713b1edbc 11520 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11521 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11522 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 171:3a7713b1edbc 11523 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11524 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11525 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 171:3a7713b1edbc 11526 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11527 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11528 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 171:3a7713b1edbc 11529 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11530 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11531 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 171:3a7713b1edbc 11532 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11533 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11534 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 171:3a7713b1edbc 11535 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11536 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11537 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 171:3a7713b1edbc 11538 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11539 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11540 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 171:3a7713b1edbc 11541 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11542 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11543 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 11544 #define TIM_CR2_OIS5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11545 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11546 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
AnnaBridge 171:3a7713b1edbc 11547 #define TIM_CR2_OIS6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11548 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11549 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
AnnaBridge 171:3a7713b1edbc 11550
AnnaBridge 171:3a7713b1edbc 11551 #define TIM_CR2_MMS2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11552 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 11553 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 11554 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11555 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11556 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11557 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11558
AnnaBridge 171:3a7713b1edbc 11559 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 171:3a7713b1edbc 11560 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11561 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
AnnaBridge 171:3a7713b1edbc 11562 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 171:3a7713b1edbc 11563 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11564 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11565 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11566 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11567
AnnaBridge 171:3a7713b1edbc 11568 #define TIM_SMCR_OCCS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11569 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11570 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
AnnaBridge 171:3a7713b1edbc 11571
AnnaBridge 171:3a7713b1edbc 11572 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11573 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11574 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 171:3a7713b1edbc 11575 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11576 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11577 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11578
AnnaBridge 171:3a7713b1edbc 11579 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11580 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11581 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 171:3a7713b1edbc 11582
AnnaBridge 171:3a7713b1edbc 11583 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11584 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11585 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 171:3a7713b1edbc 11586 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11587 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11588 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11589 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11590
AnnaBridge 171:3a7713b1edbc 11591 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11592 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 11593 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 171:3a7713b1edbc 11594 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11595 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11596
AnnaBridge 171:3a7713b1edbc 11597 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11598 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11599 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 171:3a7713b1edbc 11600 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11601 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11602 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 171:3a7713b1edbc 11603
AnnaBridge 171:3a7713b1edbc 11604 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 171:3a7713b1edbc 11605 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11606 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11607 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 171:3a7713b1edbc 11608 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11609 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11610 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 11611 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11612 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11613 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 11614 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11615 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11616 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 11617 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11618 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11619 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 11620 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11621 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11622 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 171:3a7713b1edbc 11623 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11624 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11625 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 171:3a7713b1edbc 11626 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11627 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11628 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 171:3a7713b1edbc 11629 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11630 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11631 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 171:3a7713b1edbc 11632 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11633 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11634 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 171:3a7713b1edbc 11635 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11636 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11637 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 171:3a7713b1edbc 11638 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11639 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11640 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 171:3a7713b1edbc 11641 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11642 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11643 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 171:3a7713b1edbc 11644 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11645 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11646 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 171:3a7713b1edbc 11647 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11648 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11649 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 171:3a7713b1edbc 11650
AnnaBridge 171:3a7713b1edbc 11651 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 171:3a7713b1edbc 11652 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11653 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11654 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11655 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11656 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11657 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11658 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11659 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11660 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11661 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11662 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11663 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11664 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11665 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11666 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11667 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11668 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11669 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11670 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11671 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11672 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11673 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11674 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11675 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11676 #define TIM_SR_B2IF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11677 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11678 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11679 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11680 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11681 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 11682 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11683 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11684 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 11685 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11686 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11687 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 11688 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11689 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11690 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 11691 #define TIM_SR_SBIF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11692 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11693 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11694 #define TIM_SR_CC5IF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11695 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11696 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11697 #define TIM_SR_CC6IF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11698 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11699 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 11700
AnnaBridge 171:3a7713b1edbc 11701
AnnaBridge 171:3a7713b1edbc 11702 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 171:3a7713b1edbc 11703 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11704 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11705 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 171:3a7713b1edbc 11706 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11707 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11708 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 171:3a7713b1edbc 11709 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11710 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11711 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 171:3a7713b1edbc 11712 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11713 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11714 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 171:3a7713b1edbc 11715 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11716 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11717 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 171:3a7713b1edbc 11718 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11719 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11720 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 171:3a7713b1edbc 11721 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11722 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11723 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 171:3a7713b1edbc 11724 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11725 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11726 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 171:3a7713b1edbc 11727 #define TIM_EGR_B2G_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11728 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11729 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
AnnaBridge 171:3a7713b1edbc 11730
AnnaBridge 171:3a7713b1edbc 11731
AnnaBridge 171:3a7713b1edbc 11732 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 171:3a7713b1edbc 11733 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11734 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11735 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 171:3a7713b1edbc 11736 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11737 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11738
AnnaBridge 171:3a7713b1edbc 11739 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11740 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11741 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 171:3a7713b1edbc 11742 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11743 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11744 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 171:3a7713b1edbc 11745
AnnaBridge 171:3a7713b1edbc 11746 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11747 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 11748 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 171:3a7713b1edbc 11749 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11750 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11751 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11752 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11753
AnnaBridge 171:3a7713b1edbc 11754 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11755 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11756 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
AnnaBridge 171:3a7713b1edbc 11757
AnnaBridge 171:3a7713b1edbc 11758 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11759 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 11760 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 171:3a7713b1edbc 11761 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11762 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11763
AnnaBridge 171:3a7713b1edbc 11764 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11765 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11766 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 171:3a7713b1edbc 11767 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11768 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11769 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 171:3a7713b1edbc 11770
AnnaBridge 171:3a7713b1edbc 11771 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11772 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 11773 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 171:3a7713b1edbc 11774 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11775 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11776 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11777 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11778
AnnaBridge 171:3a7713b1edbc 11779 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11780 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11781 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 171:3a7713b1edbc 11782
AnnaBridge 171:3a7713b1edbc 11783 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 11784 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11785 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 11786 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 171:3a7713b1edbc 11787 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11788 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11789
AnnaBridge 171:3a7713b1edbc 11790 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11791 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 11792 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 171:3a7713b1edbc 11793 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11794 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11795 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11796 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11797
AnnaBridge 171:3a7713b1edbc 11798 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11799 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 11800 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 171:3a7713b1edbc 11801 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11802 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11803
AnnaBridge 171:3a7713b1edbc 11804 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11805 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 11806 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 171:3a7713b1edbc 11807 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11808 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11809 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11810 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11811
AnnaBridge 171:3a7713b1edbc 11812 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 171:3a7713b1edbc 11813 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11814 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11815 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 171:3a7713b1edbc 11816 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11817 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11818
AnnaBridge 171:3a7713b1edbc 11819 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11820 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11821 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 171:3a7713b1edbc 11822 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11823 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11824 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 171:3a7713b1edbc 11825
AnnaBridge 171:3a7713b1edbc 11826 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11827 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 11828 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 171:3a7713b1edbc 11829 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11830 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11831 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11832 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11833
AnnaBridge 171:3a7713b1edbc 11834 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11835 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11836 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 171:3a7713b1edbc 11837
AnnaBridge 171:3a7713b1edbc 11838 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11839 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 11840 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 171:3a7713b1edbc 11841 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11842 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11843
AnnaBridge 171:3a7713b1edbc 11844 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11845 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11846 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 11847 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11848 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11849 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 11850
AnnaBridge 171:3a7713b1edbc 11851 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11852 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 11853 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 11854 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11855 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11856 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11857 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11858
AnnaBridge 171:3a7713b1edbc 11859 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11860 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11861 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 11862
AnnaBridge 171:3a7713b1edbc 11863 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 11864 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11865 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 11866 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 171:3a7713b1edbc 11867 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11868 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11869
AnnaBridge 171:3a7713b1edbc 11870 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11871 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 11872 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 171:3a7713b1edbc 11873 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11874 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11875 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11876 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11877
AnnaBridge 171:3a7713b1edbc 11878 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11879 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 11880 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 171:3a7713b1edbc 11881 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11882 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11883
AnnaBridge 171:3a7713b1edbc 11884 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11885 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 11886 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 171:3a7713b1edbc 11887 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11888 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11889 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11890 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11891
AnnaBridge 171:3a7713b1edbc 11892 /****************** Bit definition for TIM_CCMR3 register *******************/
AnnaBridge 171:3a7713b1edbc 11893 #define TIM_CCMR3_OC5FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11894 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11895 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
AnnaBridge 171:3a7713b1edbc 11896 #define TIM_CCMR3_OC5PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11897 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11898 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
AnnaBridge 171:3a7713b1edbc 11899
AnnaBridge 171:3a7713b1edbc 11900 #define TIM_CCMR3_OC5M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11901 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 11902 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
AnnaBridge 171:3a7713b1edbc 11903 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11904 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11905 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11906 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11907
AnnaBridge 171:3a7713b1edbc 11908 #define TIM_CCMR3_OC5CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11909 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11910 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
AnnaBridge 171:3a7713b1edbc 11911
AnnaBridge 171:3a7713b1edbc 11912 #define TIM_CCMR3_OC6FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11913 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11914 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
AnnaBridge 171:3a7713b1edbc 11915 #define TIM_CCMR3_OC6PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11916 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11917 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
AnnaBridge 171:3a7713b1edbc 11918
AnnaBridge 171:3a7713b1edbc 11919 #define TIM_CCMR3_OC6M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11920 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 11921 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
AnnaBridge 171:3a7713b1edbc 11922 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11923 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11924 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11925 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11926
AnnaBridge 171:3a7713b1edbc 11927 #define TIM_CCMR3_OC6CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11928 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11929 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
AnnaBridge 171:3a7713b1edbc 11930
AnnaBridge 171:3a7713b1edbc 11931 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 171:3a7713b1edbc 11932 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11933 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11934 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 171:3a7713b1edbc 11935 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11936 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11937 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 171:3a7713b1edbc 11938 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11939 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11940 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 11941 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11942 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11943 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 11944 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11945 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11946 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 171:3a7713b1edbc 11947 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11948 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11949 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 171:3a7713b1edbc 11950 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11951 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11952 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 11953 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11954 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11955 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 11956 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11957 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11958 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 171:3a7713b1edbc 11959 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11960 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11961 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 171:3a7713b1edbc 11962 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11963 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11964 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 11965 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11966 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11967 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 11968 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11969 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11970 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 171:3a7713b1edbc 11971 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11972 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11973 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 171:3a7713b1edbc 11974 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11975 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11976 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 11977 #define TIM_CCER_CC5E_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11978 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11979 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
AnnaBridge 171:3a7713b1edbc 11980 #define TIM_CCER_CC5P_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11981 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11982 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
AnnaBridge 171:3a7713b1edbc 11983 #define TIM_CCER_CC6E_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11984 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11985 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
AnnaBridge 171:3a7713b1edbc 11986 #define TIM_CCER_CC6P_Pos (21U)
AnnaBridge 171:3a7713b1edbc 11987 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11988 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
AnnaBridge 171:3a7713b1edbc 11989
AnnaBridge 171:3a7713b1edbc 11990 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 171:3a7713b1edbc 11991 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11992 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11993 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 11994 #define TIM_CNT_UIFCPY_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11995 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11996 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
AnnaBridge 171:3a7713b1edbc 11997
AnnaBridge 171:3a7713b1edbc 11998 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 171:3a7713b1edbc 11999 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12000 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12001 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 171:3a7713b1edbc 12002
AnnaBridge 171:3a7713b1edbc 12003 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 171:3a7713b1edbc 12004 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12005 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12006 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
AnnaBridge 171:3a7713b1edbc 12007
AnnaBridge 171:3a7713b1edbc 12008 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 171:3a7713b1edbc 12009 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12010 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12011 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 171:3a7713b1edbc 12012
AnnaBridge 171:3a7713b1edbc 12013 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 12014 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12015 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12016 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 171:3a7713b1edbc 12017
AnnaBridge 171:3a7713b1edbc 12018 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 12019 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12020 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12021 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 171:3a7713b1edbc 12022
AnnaBridge 171:3a7713b1edbc 12023 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 171:3a7713b1edbc 12024 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12025 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12026 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 171:3a7713b1edbc 12027
AnnaBridge 171:3a7713b1edbc 12028 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 171:3a7713b1edbc 12029 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12030 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12031 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 171:3a7713b1edbc 12032
AnnaBridge 171:3a7713b1edbc 12033 /******************* Bit definition for TIM_CCR5 register *******************/
AnnaBridge 171:3a7713b1edbc 12034 #define TIM_CCR5_CCR5_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12035 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12036 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
AnnaBridge 171:3a7713b1edbc 12037 #define TIM_CCR5_GC5C1_Pos (29U)
AnnaBridge 171:3a7713b1edbc 12038 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 12039 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
AnnaBridge 171:3a7713b1edbc 12040 #define TIM_CCR5_GC5C2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 12041 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 12042 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
AnnaBridge 171:3a7713b1edbc 12043 #define TIM_CCR5_GC5C3_Pos (31U)
AnnaBridge 171:3a7713b1edbc 12044 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12045 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
AnnaBridge 171:3a7713b1edbc 12046
AnnaBridge 171:3a7713b1edbc 12047 /******************* Bit definition for TIM_CCR6 register *******************/
AnnaBridge 171:3a7713b1edbc 12048 #define TIM_CCR6_CCR6_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12049 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12050 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
AnnaBridge 171:3a7713b1edbc 12051
AnnaBridge 171:3a7713b1edbc 12052 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 171:3a7713b1edbc 12053 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12054 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 12055 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 171:3a7713b1edbc 12056 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12057 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12058 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12059 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12060 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12061 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12062 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12063 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12064
AnnaBridge 171:3a7713b1edbc 12065 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12066 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 12067 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 171:3a7713b1edbc 12068 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12069 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12070
AnnaBridge 171:3a7713b1edbc 12071 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12072 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12073 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 171:3a7713b1edbc 12074 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12075 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12076 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 171:3a7713b1edbc 12077 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12078 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12079 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
AnnaBridge 171:3a7713b1edbc 12080 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12081 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12082 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
AnnaBridge 171:3a7713b1edbc 12083 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12084 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12085 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 171:3a7713b1edbc 12086 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12087 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12088 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 171:3a7713b1edbc 12089
AnnaBridge 171:3a7713b1edbc 12090 #define TIM_BDTR_BKF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12091 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 12092 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
AnnaBridge 171:3a7713b1edbc 12093 #define TIM_BDTR_BK2F_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12094 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 12095 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
AnnaBridge 171:3a7713b1edbc 12096
AnnaBridge 171:3a7713b1edbc 12097 #define TIM_BDTR_BK2E_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12098 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12099 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
AnnaBridge 171:3a7713b1edbc 12100 #define TIM_BDTR_BK2P_Pos (25U)
AnnaBridge 171:3a7713b1edbc 12101 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12102 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
AnnaBridge 171:3a7713b1edbc 12103
AnnaBridge 171:3a7713b1edbc 12104 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 171:3a7713b1edbc 12105 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12106 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 12107 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 171:3a7713b1edbc 12108 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12109 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12110 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12111 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12112 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12113
AnnaBridge 171:3a7713b1edbc 12114 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12115 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 12116 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 171:3a7713b1edbc 12117 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12118 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12119 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12120 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12121 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12122
AnnaBridge 171:3a7713b1edbc 12123 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 171:3a7713b1edbc 12124 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12125 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12126 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 171:3a7713b1edbc 12127
AnnaBridge 171:3a7713b1edbc 12128 /******************* Bit definition for TIM1_OR1 register *******************/
AnnaBridge 171:3a7713b1edbc 12129 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12130 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 12131 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
AnnaBridge 171:3a7713b1edbc 12132 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12133 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12134
AnnaBridge 171:3a7713b1edbc 12135 #define TIM1_OR1_TI1_RMP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12136 #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12137 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
AnnaBridge 171:3a7713b1edbc 12138
AnnaBridge 171:3a7713b1edbc 12139 /******************* Bit definition for TIM1_OR2 register *******************/
AnnaBridge 171:3a7713b1edbc 12140 #define TIM1_OR2_BKINE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12141 #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12142 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
AnnaBridge 171:3a7713b1edbc 12143 #define TIM1_OR2_BKCMP1E_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12144 #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12145 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
AnnaBridge 171:3a7713b1edbc 12146 #define TIM1_OR2_BKCMP2E_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12147 #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12148 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
AnnaBridge 171:3a7713b1edbc 12149 #define TIM1_OR2_BKINP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12150 #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12151 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
AnnaBridge 171:3a7713b1edbc 12152 #define TIM1_OR2_BKCMP1P_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12153 #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12154 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
AnnaBridge 171:3a7713b1edbc 12155 #define TIM1_OR2_BKCMP2P_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12156 #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12157 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
AnnaBridge 171:3a7713b1edbc 12158
AnnaBridge 171:3a7713b1edbc 12159 #define TIM1_OR2_ETRSEL_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12160 #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
AnnaBridge 171:3a7713b1edbc 12161 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
AnnaBridge 171:3a7713b1edbc 12162 #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12163 #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12164 #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12165
AnnaBridge 171:3a7713b1edbc 12166 /******************* Bit definition for TIM1_OR3 register *******************/
AnnaBridge 171:3a7713b1edbc 12167 #define TIM1_OR3_BK2INE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12168 #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12169 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
AnnaBridge 171:3a7713b1edbc 12170 #define TIM1_OR3_BK2CMP1E_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12171 #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12172 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
AnnaBridge 171:3a7713b1edbc 12173 #define TIM1_OR3_BK2CMP2E_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12174 #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12175 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
AnnaBridge 171:3a7713b1edbc 12176 #define TIM1_OR3_BK2INP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12177 #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12178 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
AnnaBridge 171:3a7713b1edbc 12179 #define TIM1_OR3_BK2CMP1P_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12180 #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12181 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
AnnaBridge 171:3a7713b1edbc 12182 #define TIM1_OR3_BK2CMP2P_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12183 #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12184 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
AnnaBridge 171:3a7713b1edbc 12185
AnnaBridge 171:3a7713b1edbc 12186
AnnaBridge 171:3a7713b1edbc 12187 /******************* Bit definition for TIM2_OR1 register *******************/
AnnaBridge 171:3a7713b1edbc 12188 #define TIM2_OR1_ITR1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12189 #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12190 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
AnnaBridge 171:3a7713b1edbc 12191 #define TIM2_OR1_ETR1_RMP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12192 #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12193 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
AnnaBridge 171:3a7713b1edbc 12194
AnnaBridge 171:3a7713b1edbc 12195 #define TIM2_OR1_TI4_RMP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12196 #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 12197 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
AnnaBridge 171:3a7713b1edbc 12198 #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12199 #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12200
AnnaBridge 171:3a7713b1edbc 12201 /******************* Bit definition for TIM2_OR2 register *******************/
AnnaBridge 171:3a7713b1edbc 12202 #define TIM2_OR2_ETRSEL_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12203 #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
AnnaBridge 171:3a7713b1edbc 12204 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
AnnaBridge 171:3a7713b1edbc 12205 #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12206 #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12207 #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12208
AnnaBridge 171:3a7713b1edbc 12209
AnnaBridge 171:3a7713b1edbc 12210 /******************* Bit definition for TIM15_OR1 register ******************/
AnnaBridge 171:3a7713b1edbc 12211 #define TIM15_OR1_TI1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12212 #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12213 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
AnnaBridge 171:3a7713b1edbc 12214
AnnaBridge 171:3a7713b1edbc 12215 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12216 #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 12217 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
AnnaBridge 171:3a7713b1edbc 12218 #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12219 #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12220
AnnaBridge 171:3a7713b1edbc 12221 /******************* Bit definition for TIM15_OR2 register ******************/
AnnaBridge 171:3a7713b1edbc 12222 #define TIM15_OR2_BKINE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12223 #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12224 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
AnnaBridge 171:3a7713b1edbc 12225 #define TIM15_OR2_BKCMP1E_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12226 #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12227 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
AnnaBridge 171:3a7713b1edbc 12228 #define TIM15_OR2_BKCMP2E_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12229 #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12230 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
AnnaBridge 171:3a7713b1edbc 12231 #define TIM15_OR2_BKINP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12232 #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12233 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
AnnaBridge 171:3a7713b1edbc 12234 #define TIM15_OR2_BKCMP1P_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12235 #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12236 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
AnnaBridge 171:3a7713b1edbc 12237 #define TIM15_OR2_BKCMP2P_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12238 #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12239 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
AnnaBridge 171:3a7713b1edbc 12240
AnnaBridge 171:3a7713b1edbc 12241 /******************* Bit definition for TIM16_OR1 register ******************/
AnnaBridge 171:3a7713b1edbc 12242 #define TIM16_OR1_TI1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12243 #define TIM16_OR1_TI1_RMP_Msk (0x7U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 12244 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
AnnaBridge 171:3a7713b1edbc 12245 #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12246 #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12247 #define TIM16_OR1_TI1_RMP_2 (0x4U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12248
AnnaBridge 171:3a7713b1edbc 12249 /******************* Bit definition for TIM16_OR2 register ******************/
AnnaBridge 171:3a7713b1edbc 12250 #define TIM16_OR2_BKINE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12251 #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12252 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
AnnaBridge 171:3a7713b1edbc 12253 #define TIM16_OR2_BKCMP1E_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12254 #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12255 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
AnnaBridge 171:3a7713b1edbc 12256 #define TIM16_OR2_BKCMP2E_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12257 #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12258 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
AnnaBridge 171:3a7713b1edbc 12259 #define TIM16_OR2_BKINP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12260 #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12261 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
AnnaBridge 171:3a7713b1edbc 12262 #define TIM16_OR2_BKCMP1P_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12263 #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12264 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
AnnaBridge 171:3a7713b1edbc 12265 #define TIM16_OR2_BKCMP2P_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12266 #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12267 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
AnnaBridge 171:3a7713b1edbc 12268
AnnaBridge 171:3a7713b1edbc 12269
AnnaBridge 171:3a7713b1edbc 12270 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12271 /* */
AnnaBridge 171:3a7713b1edbc 12272 /* Low Power Timer (LPTTIM) */
AnnaBridge 171:3a7713b1edbc 12273 /* */
AnnaBridge 171:3a7713b1edbc 12274 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12275 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 171:3a7713b1edbc 12276 #define LPTIM_ISR_CMPM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12277 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12278 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
AnnaBridge 171:3a7713b1edbc 12279 #define LPTIM_ISR_ARRM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12280 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12281 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
AnnaBridge 171:3a7713b1edbc 12282 #define LPTIM_ISR_EXTTRIG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12283 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12284 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
AnnaBridge 171:3a7713b1edbc 12285 #define LPTIM_ISR_CMPOK_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12286 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12287 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
AnnaBridge 171:3a7713b1edbc 12288 #define LPTIM_ISR_ARROK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12289 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12290 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
AnnaBridge 171:3a7713b1edbc 12291 #define LPTIM_ISR_UP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12292 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12293 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
AnnaBridge 171:3a7713b1edbc 12294 #define LPTIM_ISR_DOWN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12295 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12296 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
AnnaBridge 171:3a7713b1edbc 12297
AnnaBridge 171:3a7713b1edbc 12298 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 171:3a7713b1edbc 12299 #define LPTIM_ICR_CMPMCF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12300 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12301 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
AnnaBridge 171:3a7713b1edbc 12302 #define LPTIM_ICR_ARRMCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12303 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12304 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
AnnaBridge 171:3a7713b1edbc 12305 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12306 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12307 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
AnnaBridge 171:3a7713b1edbc 12308 #define LPTIM_ICR_CMPOKCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12309 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12310 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
AnnaBridge 171:3a7713b1edbc 12311 #define LPTIM_ICR_ARROKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12312 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12313 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
AnnaBridge 171:3a7713b1edbc 12314 #define LPTIM_ICR_UPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12315 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12316 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
AnnaBridge 171:3a7713b1edbc 12317 #define LPTIM_ICR_DOWNCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12318 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12319 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
AnnaBridge 171:3a7713b1edbc 12320
AnnaBridge 171:3a7713b1edbc 12321 /****************** Bit definition for LPTIM_IER register ********************/
AnnaBridge 171:3a7713b1edbc 12322 #define LPTIM_IER_CMPMIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12323 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12324 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12325 #define LPTIM_IER_ARRMIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12326 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12327 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12328 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12329 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12330 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12331 #define LPTIM_IER_CMPOKIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12332 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12333 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12334 #define LPTIM_IER_ARROKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12335 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12336 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12337 #define LPTIM_IER_UPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12338 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12339 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12340 #define LPTIM_IER_DOWNIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12341 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12342 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12343
AnnaBridge 171:3a7713b1edbc 12344 /****************** Bit definition for LPTIM_CFGR register *******************/
AnnaBridge 171:3a7713b1edbc 12345 #define LPTIM_CFGR_CKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12346 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12347 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
AnnaBridge 171:3a7713b1edbc 12348
AnnaBridge 171:3a7713b1edbc 12349 #define LPTIM_CFGR_CKPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12350 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 12351 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 171:3a7713b1edbc 12352 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12353 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12354
AnnaBridge 171:3a7713b1edbc 12355 #define LPTIM_CFGR_CKFLT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12356 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 12357 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 171:3a7713b1edbc 12358 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12359 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12360
AnnaBridge 171:3a7713b1edbc 12361 #define LPTIM_CFGR_TRGFLT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12362 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 12363 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 171:3a7713b1edbc 12364 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12365 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12366
AnnaBridge 171:3a7713b1edbc 12367 #define LPTIM_CFGR_PRESC_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12368 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 12369 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 171:3a7713b1edbc 12370 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12371 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12372 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12373
AnnaBridge 171:3a7713b1edbc 12374 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12375 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 12376 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 171:3a7713b1edbc 12377 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12378 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12379 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12380
AnnaBridge 171:3a7713b1edbc 12381 #define LPTIM_CFGR_TRIGEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12382 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 12383 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 171:3a7713b1edbc 12384 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12385 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12386
AnnaBridge 171:3a7713b1edbc 12387 #define LPTIM_CFGR_TIMOUT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12388 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12389 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
AnnaBridge 171:3a7713b1edbc 12390 #define LPTIM_CFGR_WAVE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12391 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12392 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
AnnaBridge 171:3a7713b1edbc 12393 #define LPTIM_CFGR_WAVPOL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12394 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12395 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
AnnaBridge 171:3a7713b1edbc 12396 #define LPTIM_CFGR_PRELOAD_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12397 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12398 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
AnnaBridge 171:3a7713b1edbc 12399 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12400 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12401 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
AnnaBridge 171:3a7713b1edbc 12402 #define LPTIM_CFGR_ENC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12403 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12404 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
AnnaBridge 171:3a7713b1edbc 12405
AnnaBridge 171:3a7713b1edbc 12406 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 171:3a7713b1edbc 12407 #define LPTIM_CR_ENABLE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12408 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12409 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
AnnaBridge 171:3a7713b1edbc 12410 #define LPTIM_CR_SNGSTRT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12411 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12412 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
AnnaBridge 171:3a7713b1edbc 12413 #define LPTIM_CR_CNTSTRT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12414 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12415 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
AnnaBridge 171:3a7713b1edbc 12416
AnnaBridge 171:3a7713b1edbc 12417 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 171:3a7713b1edbc 12418 #define LPTIM_CMP_CMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12419 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12420 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
AnnaBridge 171:3a7713b1edbc 12421
AnnaBridge 171:3a7713b1edbc 12422 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 171:3a7713b1edbc 12423 #define LPTIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12424 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12425 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
AnnaBridge 171:3a7713b1edbc 12426
AnnaBridge 171:3a7713b1edbc 12427 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 171:3a7713b1edbc 12428 #define LPTIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12429 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12430 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
AnnaBridge 171:3a7713b1edbc 12431
AnnaBridge 171:3a7713b1edbc 12432 /****************** Bit definition for LPTIM_OR register ********************/
AnnaBridge 171:3a7713b1edbc 12433 #define LPTIM_OR_OR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12434 #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 12435 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
AnnaBridge 171:3a7713b1edbc 12436 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12437 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12438
AnnaBridge 171:3a7713b1edbc 12439 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12440 /* */
AnnaBridge 171:3a7713b1edbc 12441 /* Analog Comparators (COMP) */
AnnaBridge 171:3a7713b1edbc 12442 /* */
AnnaBridge 171:3a7713b1edbc 12443 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12444 /********************** Bit definition for COMP_CSR register ****************/
AnnaBridge 171:3a7713b1edbc 12445 #define COMP_CSR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12446 #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12447 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
AnnaBridge 171:3a7713b1edbc 12448
AnnaBridge 171:3a7713b1edbc 12449 #define COMP_CSR_PWRMODE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12450 #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 12451 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
AnnaBridge 171:3a7713b1edbc 12452 #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12453 #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12454
AnnaBridge 171:3a7713b1edbc 12455 #define COMP_CSR_INMSEL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12456 #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 12457 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
AnnaBridge 171:3a7713b1edbc 12458 #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12459 #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12460 #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12461
AnnaBridge 171:3a7713b1edbc 12462 #define COMP_CSR_INPSEL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12463 #define COMP_CSR_INPSEL_Msk (0x3U << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 12464 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
AnnaBridge 171:3a7713b1edbc 12465 #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12466 #define COMP_CSR_INPSEL_1 (0x2U << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12467
AnnaBridge 171:3a7713b1edbc 12468 #define COMP_CSR_WINMODE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12469 #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12470 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
AnnaBridge 171:3a7713b1edbc 12471
AnnaBridge 171:3a7713b1edbc 12472 #define COMP_CSR_POLARITY_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12473 #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12474 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
AnnaBridge 171:3a7713b1edbc 12475
AnnaBridge 171:3a7713b1edbc 12476 #define COMP_CSR_HYST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12477 #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 12478 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
AnnaBridge 171:3a7713b1edbc 12479 #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12480 #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12481
AnnaBridge 171:3a7713b1edbc 12482 #define COMP_CSR_BLANKING_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12483 #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 12484 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
AnnaBridge 171:3a7713b1edbc 12485 #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12486 #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12487 #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12488
AnnaBridge 171:3a7713b1edbc 12489 #define COMP_CSR_BRGEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12490 #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12491 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
AnnaBridge 171:3a7713b1edbc 12492 #define COMP_CSR_SCALEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12493 #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12494 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
AnnaBridge 171:3a7713b1edbc 12495
AnnaBridge 171:3a7713b1edbc 12496 #define COMP_CSR_INMESEL_Pos (25U)
AnnaBridge 171:3a7713b1edbc 12497 #define COMP_CSR_INMESEL_Msk (0x3U << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 12498 #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */
AnnaBridge 171:3a7713b1edbc 12499 #define COMP_CSR_INMESEL_0 (0x1U << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12500 #define COMP_CSR_INMESEL_1 (0x2U << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12501
AnnaBridge 171:3a7713b1edbc 12502 #define COMP_CSR_VALUE_Pos (30U)
AnnaBridge 171:3a7713b1edbc 12503 #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 12504 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
AnnaBridge 171:3a7713b1edbc 12505
AnnaBridge 171:3a7713b1edbc 12506 #define COMP_CSR_LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 12507 #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12508 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
AnnaBridge 171:3a7713b1edbc 12509
AnnaBridge 171:3a7713b1edbc 12510 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12511 /* */
AnnaBridge 171:3a7713b1edbc 12512 /* Operational Amplifier (OPAMP) */
AnnaBridge 171:3a7713b1edbc 12513 /* */
AnnaBridge 171:3a7713b1edbc 12514 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12515 /********************* Bit definition for OPAMPx_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 12516 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12517 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12518 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
AnnaBridge 171:3a7713b1edbc 12519 #define OPAMP_CSR_OPALPM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12520 #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12521 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
AnnaBridge 171:3a7713b1edbc 12522
AnnaBridge 171:3a7713b1edbc 12523 #define OPAMP_CSR_OPAMODE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12524 #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 12525 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
AnnaBridge 171:3a7713b1edbc 12526 #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12527 #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12528
AnnaBridge 171:3a7713b1edbc 12529 #define OPAMP_CSR_PGGAIN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12530 #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12531 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
AnnaBridge 171:3a7713b1edbc 12532 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12533 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12534
AnnaBridge 171:3a7713b1edbc 12535 #define OPAMP_CSR_VMSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12536 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 12537 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 171:3a7713b1edbc 12538 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12539 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12540
AnnaBridge 171:3a7713b1edbc 12541 #define OPAMP_CSR_VPSEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12542 #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12543 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
AnnaBridge 171:3a7713b1edbc 12544 #define OPAMP_CSR_CALON_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12545 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12546 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 171:3a7713b1edbc 12547 #define OPAMP_CSR_CALSEL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12548 #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12549 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 171:3a7713b1edbc 12550 #define OPAMP_CSR_USERTRIM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12551 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12552 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 171:3a7713b1edbc 12553 #define OPAMP_CSR_CALOUT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12554 #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12555 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
AnnaBridge 171:3a7713b1edbc 12556
AnnaBridge 171:3a7713b1edbc 12557 /********************* Bit definition for OPAMP1_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 12558 #define OPAMP1_CSR_OPAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12559 #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12560 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
AnnaBridge 171:3a7713b1edbc 12561 #define OPAMP1_CSR_OPALPM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12562 #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12563 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
AnnaBridge 171:3a7713b1edbc 12564
AnnaBridge 171:3a7713b1edbc 12565 #define OPAMP1_CSR_OPAMODE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12566 #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 12567 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
AnnaBridge 171:3a7713b1edbc 12568 #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12569 #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12570
AnnaBridge 171:3a7713b1edbc 12571 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12572 #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12573 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
AnnaBridge 171:3a7713b1edbc 12574 #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12575 #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12576
AnnaBridge 171:3a7713b1edbc 12577 #define OPAMP1_CSR_VMSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12578 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 12579 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 171:3a7713b1edbc 12580 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12581 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12582
AnnaBridge 171:3a7713b1edbc 12583 #define OPAMP1_CSR_VPSEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12584 #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12585 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
AnnaBridge 171:3a7713b1edbc 12586 #define OPAMP1_CSR_CALON_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12587 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12588 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 171:3a7713b1edbc 12589 #define OPAMP1_CSR_CALSEL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12590 #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12591 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 171:3a7713b1edbc 12592 #define OPAMP1_CSR_USERTRIM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12593 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12594 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 171:3a7713b1edbc 12595 #define OPAMP1_CSR_CALOUT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12596 #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12597 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
AnnaBridge 171:3a7713b1edbc 12598
AnnaBridge 171:3a7713b1edbc 12599 #define OPAMP1_CSR_OPARANGE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 12600 #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12601 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
AnnaBridge 171:3a7713b1edbc 12602
AnnaBridge 171:3a7713b1edbc 12603 /******************* Bit definition for OPAMP_OTR register ******************/
AnnaBridge 171:3a7713b1edbc 12604 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12605 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 12606 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12607 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12608 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 12609 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12610
AnnaBridge 171:3a7713b1edbc 12611 /******************* Bit definition for OPAMP1_OTR register ******************/
AnnaBridge 171:3a7713b1edbc 12612 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12613 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 12614 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12615 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12616 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 12617 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12618
AnnaBridge 171:3a7713b1edbc 12619 /******************* Bit definition for OPAMP_LPOTR register ****************/
AnnaBridge 171:3a7713b1edbc 12620 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12621 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 12622 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12623 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12624 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 12625 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12626
AnnaBridge 171:3a7713b1edbc 12627 /******************* Bit definition for OPAMP1_LPOTR register ****************/
AnnaBridge 171:3a7713b1edbc 12628 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12629 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 12630 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12631 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12632 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 12633 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 171:3a7713b1edbc 12634
AnnaBridge 171:3a7713b1edbc 12635 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12636 /* */
AnnaBridge 171:3a7713b1edbc 12637 /* Touch Sensing Controller (TSC) */
AnnaBridge 171:3a7713b1edbc 12638 /* */
AnnaBridge 171:3a7713b1edbc 12639 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12640 /******************* Bit definition for TSC_CR register *********************/
AnnaBridge 171:3a7713b1edbc 12641 #define TSC_CR_TSCE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12642 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12643 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
AnnaBridge 171:3a7713b1edbc 12644 #define TSC_CR_START_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12645 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12646 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
AnnaBridge 171:3a7713b1edbc 12647 #define TSC_CR_AM_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12648 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12649 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
AnnaBridge 171:3a7713b1edbc 12650 #define TSC_CR_SYNCPOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12651 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12652 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
AnnaBridge 171:3a7713b1edbc 12653 #define TSC_CR_IODEF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12654 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12655 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
AnnaBridge 171:3a7713b1edbc 12656
AnnaBridge 171:3a7713b1edbc 12657 #define TSC_CR_MCV_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12658 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 12659 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
AnnaBridge 171:3a7713b1edbc 12660 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12661 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12662 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12663
AnnaBridge 171:3a7713b1edbc 12664 #define TSC_CR_PGPSC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12665 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 12666 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
AnnaBridge 171:3a7713b1edbc 12667 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12668 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12669 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12670
AnnaBridge 171:3a7713b1edbc 12671 #define TSC_CR_SSPSC_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12672 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12673 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
AnnaBridge 171:3a7713b1edbc 12674 #define TSC_CR_SSE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12675 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12676 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
AnnaBridge 171:3a7713b1edbc 12677
AnnaBridge 171:3a7713b1edbc 12678 #define TSC_CR_SSD_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12679 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 12680 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
AnnaBridge 171:3a7713b1edbc 12681 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12682 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12683 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12684 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12685 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12686 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12687 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12688
AnnaBridge 171:3a7713b1edbc 12689 #define TSC_CR_CTPL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12690 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 12691 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
AnnaBridge 171:3a7713b1edbc 12692 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12693 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12694 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12695 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12696
AnnaBridge 171:3a7713b1edbc 12697 #define TSC_CR_CTPH_Pos (28U)
AnnaBridge 171:3a7713b1edbc 12698 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 12699 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
AnnaBridge 171:3a7713b1edbc 12700 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 12701 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 12702 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 12703 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12704
AnnaBridge 171:3a7713b1edbc 12705 /******************* Bit definition for TSC_IER register ********************/
AnnaBridge 171:3a7713b1edbc 12706 #define TSC_IER_EOAIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12707 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12708 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
AnnaBridge 171:3a7713b1edbc 12709 #define TSC_IER_MCEIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12710 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12711 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
AnnaBridge 171:3a7713b1edbc 12712
AnnaBridge 171:3a7713b1edbc 12713 /******************* Bit definition for TSC_ICR register ********************/
AnnaBridge 171:3a7713b1edbc 12714 #define TSC_ICR_EOAIC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12715 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12716 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
AnnaBridge 171:3a7713b1edbc 12717 #define TSC_ICR_MCEIC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12718 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12719 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
AnnaBridge 171:3a7713b1edbc 12720
AnnaBridge 171:3a7713b1edbc 12721 /******************* Bit definition for TSC_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 12722 #define TSC_ISR_EOAF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12723 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12724 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
AnnaBridge 171:3a7713b1edbc 12725 #define TSC_ISR_MCEF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12726 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12727 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
AnnaBridge 171:3a7713b1edbc 12728
AnnaBridge 171:3a7713b1edbc 12729 /******************* Bit definition for TSC_IOHCR register ******************/
AnnaBridge 171:3a7713b1edbc 12730 #define TSC_IOHCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12731 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12732 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12733 #define TSC_IOHCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12734 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12735 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12736 #define TSC_IOHCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12737 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12738 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12739 #define TSC_IOHCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12740 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12741 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12742 #define TSC_IOHCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12743 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12744 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12745 #define TSC_IOHCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12746 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12747 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12748 #define TSC_IOHCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12749 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12750 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12751 #define TSC_IOHCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12752 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12753 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12754 #define TSC_IOHCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12755 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12756 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12757 #define TSC_IOHCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12758 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12759 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12760 #define TSC_IOHCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12761 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12762 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12763 #define TSC_IOHCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12764 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12765 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12766 #define TSC_IOHCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12767 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12768 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12769 #define TSC_IOHCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12770 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12771 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12772 #define TSC_IOHCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12773 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12774 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12775 #define TSC_IOHCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12776 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12777 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12778 #define TSC_IOHCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12779 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12780 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12781 #define TSC_IOHCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12782 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12783 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12784 #define TSC_IOHCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12785 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12786 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12787 #define TSC_IOHCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12788 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12789 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12790 #define TSC_IOHCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12791 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12792 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12793 #define TSC_IOHCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12794 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12795 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12796 #define TSC_IOHCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12797 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12798 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12799 #define TSC_IOHCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12800 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12801 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12802 #define TSC_IOHCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12803 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12804 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12805 #define TSC_IOHCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 12806 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12807 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12808 #define TSC_IOHCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 12809 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12810 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12811 #define TSC_IOHCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 12812 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12813 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 12814
AnnaBridge 171:3a7713b1edbc 12815 /******************* Bit definition for TSC_IOASCR register *****************/
AnnaBridge 171:3a7713b1edbc 12816 #define TSC_IOASCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12817 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12818 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12819 #define TSC_IOASCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12820 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12821 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12822 #define TSC_IOASCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12823 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12824 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12825 #define TSC_IOASCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12826 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12827 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12828 #define TSC_IOASCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12829 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12830 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12831 #define TSC_IOASCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12832 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12833 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12834 #define TSC_IOASCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12835 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12836 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12837 #define TSC_IOASCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12838 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12839 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12840 #define TSC_IOASCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12841 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12842 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12843 #define TSC_IOASCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12844 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12845 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12846 #define TSC_IOASCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12847 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12848 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12849 #define TSC_IOASCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12850 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12851 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12852 #define TSC_IOASCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12853 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12854 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12855 #define TSC_IOASCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12856 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12857 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12858 #define TSC_IOASCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12859 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12860 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12861 #define TSC_IOASCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12862 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12863 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12864 #define TSC_IOASCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12865 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12866 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12867 #define TSC_IOASCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12868 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12869 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12870 #define TSC_IOASCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12871 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12872 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12873 #define TSC_IOASCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12874 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12875 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12876 #define TSC_IOASCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12877 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12878 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12879 #define TSC_IOASCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12880 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12881 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12882 #define TSC_IOASCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12883 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12884 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12885 #define TSC_IOASCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12886 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12887 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12888 #define TSC_IOASCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12889 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12890 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12891 #define TSC_IOASCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 12892 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12893 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12894 #define TSC_IOASCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 12895 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12896 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12897 #define TSC_IOASCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 12898 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12899 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 12900
AnnaBridge 171:3a7713b1edbc 12901 /******************* Bit definition for TSC_IOSCR register ******************/
AnnaBridge 171:3a7713b1edbc 12902 #define TSC_IOSCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12903 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12904 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12905 #define TSC_IOSCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12906 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12907 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12908 #define TSC_IOSCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12909 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12910 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12911 #define TSC_IOSCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12912 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12913 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12914 #define TSC_IOSCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12915 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12916 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12917 #define TSC_IOSCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12918 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12919 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12920 #define TSC_IOSCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12921 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12922 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12923 #define TSC_IOSCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12924 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12925 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12926 #define TSC_IOSCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12927 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12928 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12929 #define TSC_IOSCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12930 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12931 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12932 #define TSC_IOSCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12933 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12934 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12935 #define TSC_IOSCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12936 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12937 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12938 #define TSC_IOSCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12939 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12940 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12941 #define TSC_IOSCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12942 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12943 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12944 #define TSC_IOSCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12945 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12946 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12947 #define TSC_IOSCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12948 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12949 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12950 #define TSC_IOSCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12951 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12952 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12953 #define TSC_IOSCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12954 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12955 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12956 #define TSC_IOSCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12957 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12958 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12959 #define TSC_IOSCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12960 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12961 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12962 #define TSC_IOSCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12963 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12964 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12965 #define TSC_IOSCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12966 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12967 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12968 #define TSC_IOSCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12969 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12970 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12971 #define TSC_IOSCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12972 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12973 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12974 #define TSC_IOSCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12975 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12976 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 12977 #define TSC_IOSCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 12978 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12979 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 12980 #define TSC_IOSCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 12981 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12982 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 12983 #define TSC_IOSCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 12984 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12985 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 12986
AnnaBridge 171:3a7713b1edbc 12987 /******************* Bit definition for TSC_IOCCR register ******************/
AnnaBridge 171:3a7713b1edbc 12988 #define TSC_IOCCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12989 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12990 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 12991 #define TSC_IOCCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12992 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12993 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 12994 #define TSC_IOCCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12995 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12996 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 12997 #define TSC_IOCCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12998 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12999 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13000 #define TSC_IOCCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13001 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13002 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 13003 #define TSC_IOCCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13004 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13005 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 13006 #define TSC_IOCCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13007 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13008 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 13009 #define TSC_IOCCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13010 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13011 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13012 #define TSC_IOCCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13013 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13014 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 13015 #define TSC_IOCCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13016 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13017 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 13018 #define TSC_IOCCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13019 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13020 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 13021 #define TSC_IOCCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13022 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13023 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13024 #define TSC_IOCCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13025 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13026 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 13027 #define TSC_IOCCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13028 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13029 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 13030 #define TSC_IOCCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13031 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13032 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 13033 #define TSC_IOCCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13034 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13035 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13036 #define TSC_IOCCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13037 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13038 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 13039 #define TSC_IOCCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13040 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13041 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 13042 #define TSC_IOCCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13043 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13044 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 13045 #define TSC_IOCCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13046 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13047 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13048 #define TSC_IOCCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13049 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13050 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 13051 #define TSC_IOCCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13052 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13053 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 13054 #define TSC_IOCCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 13055 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13056 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 13057 #define TSC_IOCCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 13058 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13059 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13060 #define TSC_IOCCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13061 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13062 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 13063 #define TSC_IOCCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13064 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13065 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 13066 #define TSC_IOCCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 13067 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 13068 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 13069 #define TSC_IOCCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 13070 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 13071 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 13072
AnnaBridge 171:3a7713b1edbc 13073 /******************* Bit definition for TSC_IOGCSR register *****************/
AnnaBridge 171:3a7713b1edbc 13074 #define TSC_IOGCSR_G1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13075 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13076 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
AnnaBridge 171:3a7713b1edbc 13077 #define TSC_IOGCSR_G2E_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13078 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13079 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
AnnaBridge 171:3a7713b1edbc 13080 #define TSC_IOGCSR_G3E_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13081 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13082 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
AnnaBridge 171:3a7713b1edbc 13083 #define TSC_IOGCSR_G4E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13084 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13085 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
AnnaBridge 171:3a7713b1edbc 13086 #define TSC_IOGCSR_G5E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13087 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13088 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
AnnaBridge 171:3a7713b1edbc 13089 #define TSC_IOGCSR_G6E_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13090 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13091 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
AnnaBridge 171:3a7713b1edbc 13092 #define TSC_IOGCSR_G7E_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13093 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13094 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
AnnaBridge 171:3a7713b1edbc 13095 #define TSC_IOGCSR_G1S_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13096 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13097 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
AnnaBridge 171:3a7713b1edbc 13098 #define TSC_IOGCSR_G2S_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13099 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13100 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
AnnaBridge 171:3a7713b1edbc 13101 #define TSC_IOGCSR_G3S_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13102 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13103 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
AnnaBridge 171:3a7713b1edbc 13104 #define TSC_IOGCSR_G4S_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13105 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13106 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
AnnaBridge 171:3a7713b1edbc 13107 #define TSC_IOGCSR_G5S_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13108 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13109 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
AnnaBridge 171:3a7713b1edbc 13110 #define TSC_IOGCSR_G6S_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13111 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13112 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
AnnaBridge 171:3a7713b1edbc 13113 #define TSC_IOGCSR_G7S_Pos (22U)
AnnaBridge 171:3a7713b1edbc 13114 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13115 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
AnnaBridge 171:3a7713b1edbc 13116
AnnaBridge 171:3a7713b1edbc 13117 /******************* Bit definition for TSC_IOGXCR register *****************/
AnnaBridge 171:3a7713b1edbc 13118 #define TSC_IOGXCR_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13119 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 13120 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
AnnaBridge 171:3a7713b1edbc 13121
AnnaBridge 171:3a7713b1edbc 13122 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13123 /* */
AnnaBridge 171:3a7713b1edbc 13124 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 171:3a7713b1edbc 13125 /* */
AnnaBridge 171:3a7713b1edbc 13126 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13127
AnnaBridge 171:3a7713b1edbc 13128 /*
AnnaBridge 171:3a7713b1edbc 13129 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
AnnaBridge 171:3a7713b1edbc 13130 */
AnnaBridge 171:3a7713b1edbc 13131 #define USART_TCBGT_SUPPORT
AnnaBridge 171:3a7713b1edbc 13132
AnnaBridge 171:3a7713b1edbc 13133 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 13134 #define USART_CR1_UE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13135 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13136 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 171:3a7713b1edbc 13137 #define USART_CR1_UESM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13138 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13139 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
AnnaBridge 171:3a7713b1edbc 13140 #define USART_CR1_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13141 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13142 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 171:3a7713b1edbc 13143 #define USART_CR1_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13144 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13145 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 13146 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13147 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13148 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13149 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13150 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13151 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13152 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13153 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13154 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13155 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13156 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13157 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13158 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13159 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13160 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13161 #define USART_CR1_PS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13162 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13163 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 171:3a7713b1edbc 13164 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13165 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13166 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 171:3a7713b1edbc 13167 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13168 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13169 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
AnnaBridge 171:3a7713b1edbc 13170 #define USART_CR1_M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13171 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
AnnaBridge 171:3a7713b1edbc 13172 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
AnnaBridge 171:3a7713b1edbc 13173 #define USART_CR1_M0_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13174 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13175 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
AnnaBridge 171:3a7713b1edbc 13176 #define USART_CR1_MME_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13177 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13178 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
AnnaBridge 171:3a7713b1edbc 13179 #define USART_CR1_CMIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13180 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13181 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
AnnaBridge 171:3a7713b1edbc 13182 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13183 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13184 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 171:3a7713b1edbc 13185 #define USART_CR1_DEDT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13186 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 13187 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 171:3a7713b1edbc 13188 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13189 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13190 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13191 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13192 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13193 #define USART_CR1_DEAT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13194 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
AnnaBridge 171:3a7713b1edbc 13195 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 171:3a7713b1edbc 13196 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13197 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13198 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13199 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13200 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13201 #define USART_CR1_RTOIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 13202 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 13203 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
AnnaBridge 171:3a7713b1edbc 13204 #define USART_CR1_EOBIE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 13205 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 13206 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
AnnaBridge 171:3a7713b1edbc 13207 #define USART_CR1_M1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 13208 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 13209 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
AnnaBridge 171:3a7713b1edbc 13210
AnnaBridge 171:3a7713b1edbc 13211 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 13212 #define USART_CR2_ADDM7_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13213 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13214 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 171:3a7713b1edbc 13215 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13216 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13217 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 171:3a7713b1edbc 13218 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13219 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13220 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13221 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13222 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13223 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 171:3a7713b1edbc 13224 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13225 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13226 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 13227 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13228 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13229 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 13230 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13231 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13232 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 171:3a7713b1edbc 13233 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13234 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 13235 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 171:3a7713b1edbc 13236 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13237 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13238 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13239 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13240 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 171:3a7713b1edbc 13241 #define USART_CR2_SWAP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13242 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13243 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
AnnaBridge 171:3a7713b1edbc 13244 #define USART_CR2_RXINV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13245 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13246 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 13247 #define USART_CR2_TXINV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13248 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13249 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 13250 #define USART_CR2_DATAINV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13251 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13252 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
AnnaBridge 171:3a7713b1edbc 13253 #define USART_CR2_MSBFIRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13254 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13255 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
AnnaBridge 171:3a7713b1edbc 13256 #define USART_CR2_ABREN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13257 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13258 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
AnnaBridge 171:3a7713b1edbc 13259 #define USART_CR2_ABRMODE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13260 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 13261 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 171:3a7713b1edbc 13262 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13263 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13264 #define USART_CR2_RTOEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 13265 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13266 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
AnnaBridge 171:3a7713b1edbc 13267 #define USART_CR2_ADD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13268 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 13269 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 171:3a7713b1edbc 13270
AnnaBridge 171:3a7713b1edbc 13271 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 171:3a7713b1edbc 13272 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13273 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13274 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13275 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13276 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13277 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 171:3a7713b1edbc 13278 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13279 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13280 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 171:3a7713b1edbc 13281 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13282 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13283 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 171:3a7713b1edbc 13284 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13285 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13286 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
AnnaBridge 171:3a7713b1edbc 13287 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13288 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13289 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
AnnaBridge 171:3a7713b1edbc 13290 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13291 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13292 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 171:3a7713b1edbc 13293 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13294 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13295 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 171:3a7713b1edbc 13296 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13297 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13298 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 171:3a7713b1edbc 13299 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13300 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13301 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 171:3a7713b1edbc 13302 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13303 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13304 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13305 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13306 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13307 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 171:3a7713b1edbc 13308 #define USART_CR3_OVRDIS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13309 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13310 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
AnnaBridge 171:3a7713b1edbc 13311 #define USART_CR3_DDRE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13312 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13313 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
AnnaBridge 171:3a7713b1edbc 13314 #define USART_CR3_DEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13315 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13316 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
AnnaBridge 171:3a7713b1edbc 13317 #define USART_CR3_DEP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13318 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13319 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
AnnaBridge 171:3a7713b1edbc 13320 #define USART_CR3_SCARCNT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13321 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 13322 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 171:3a7713b1edbc 13323 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13324 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13325 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13326 #define USART_CR3_WUS_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13327 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 13328 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
AnnaBridge 171:3a7713b1edbc 13329 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13330 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13331 #define USART_CR3_WUFIE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 13332 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13333 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13334 /* MBED */
AnnaBridge 171:3a7713b1edbc 13335 #define USART_CR3_UCESM_Pos (23U)
AnnaBridge 171:3a7713b1edbc 13336 #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13337 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
AnnaBridge 171:3a7713b1edbc 13338 /* MBED */
AnnaBridge 171:3a7713b1edbc 13339 #define USART_CR3_TCBGTIE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13340 #define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13341 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13342
AnnaBridge 171:3a7713b1edbc 13343 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 171:3a7713b1edbc 13344 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13345 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 13346 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 171:3a7713b1edbc 13347 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13348 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 13349 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 171:3a7713b1edbc 13350
AnnaBridge 171:3a7713b1edbc 13351 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 171:3a7713b1edbc 13352 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13353 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 13354 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 171:3a7713b1edbc 13355 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13356 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 13357 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 171:3a7713b1edbc 13358
AnnaBridge 171:3a7713b1edbc 13359 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 171:3a7713b1edbc 13360 #define USART_RTOR_RTO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13361 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 13362 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
AnnaBridge 171:3a7713b1edbc 13363 #define USART_RTOR_BLEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13364 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 13365 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
AnnaBridge 171:3a7713b1edbc 13366
AnnaBridge 171:3a7713b1edbc 13367 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 171:3a7713b1edbc 13368 #define USART_RQR_ABRRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13369 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13370 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
AnnaBridge 171:3a7713b1edbc 13371 #define USART_RQR_SBKRQ_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13372 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13373 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
AnnaBridge 171:3a7713b1edbc 13374 #define USART_RQR_MMRQ_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13375 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13376 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
AnnaBridge 171:3a7713b1edbc 13377 #define USART_RQR_RXFRQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13378 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13379 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
AnnaBridge 171:3a7713b1edbc 13380 #define USART_RQR_TXFRQ_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13381 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13382 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
AnnaBridge 171:3a7713b1edbc 13383
AnnaBridge 171:3a7713b1edbc 13384 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 13385 #define USART_ISR_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13386 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13387 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
AnnaBridge 171:3a7713b1edbc 13388 #define USART_ISR_FE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13389 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13390 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
AnnaBridge 171:3a7713b1edbc 13391 #define USART_ISR_NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13392 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13393 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
AnnaBridge 171:3a7713b1edbc 13394 #define USART_ISR_ORE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13395 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13396 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
AnnaBridge 171:3a7713b1edbc 13397 #define USART_ISR_IDLE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13398 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13399 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 171:3a7713b1edbc 13400 #define USART_ISR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13401 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13402 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
AnnaBridge 171:3a7713b1edbc 13403 #define USART_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13404 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13405 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
AnnaBridge 171:3a7713b1edbc 13406 #define USART_ISR_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13407 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13408 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
AnnaBridge 171:3a7713b1edbc 13409 #define USART_ISR_LBDF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13410 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13411 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
AnnaBridge 171:3a7713b1edbc 13412 #define USART_ISR_CTSIF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13413 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13414 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
AnnaBridge 171:3a7713b1edbc 13415 #define USART_ISR_CTS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13416 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13417 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
AnnaBridge 171:3a7713b1edbc 13418 #define USART_ISR_RTOF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13419 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13420 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
AnnaBridge 171:3a7713b1edbc 13421 #define USART_ISR_EOBF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13422 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13423 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
AnnaBridge 171:3a7713b1edbc 13424 #define USART_ISR_ABRE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13425 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13426 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
AnnaBridge 171:3a7713b1edbc 13427 #define USART_ISR_ABRF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13428 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13429 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
AnnaBridge 171:3a7713b1edbc 13430 #define USART_ISR_BUSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13431 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13432 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
AnnaBridge 171:3a7713b1edbc 13433 #define USART_ISR_CMF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13434 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13435 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
AnnaBridge 171:3a7713b1edbc 13436 #define USART_ISR_SBKF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13437 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13438 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
AnnaBridge 171:3a7713b1edbc 13439 #define USART_ISR_RWU_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13440 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13441 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 171:3a7713b1edbc 13442 #define USART_ISR_WUF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13443 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13444 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
AnnaBridge 171:3a7713b1edbc 13445 #define USART_ISR_TEACK_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13446 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13447 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 13448 #define USART_ISR_REACK_Pos (22U)
AnnaBridge 171:3a7713b1edbc 13449 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13450 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 13451 #define USART_ISR_TCBGT_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13452 #define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13453 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
AnnaBridge 171:3a7713b1edbc 13454
AnnaBridge 171:3a7713b1edbc 13455 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 171:3a7713b1edbc 13456 #define USART_ICR_PECF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13457 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13458 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 13459 #define USART_ICR_FECF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13460 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13461 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 13462 #define USART_ICR_NECF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13463 #define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13464 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 13465 #define USART_ICR_ORECF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13466 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13467 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 13468 #define USART_ICR_IDLECF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13469 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13470 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 13471 #define USART_ICR_TCCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13472 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13473 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
AnnaBridge 171:3a7713b1edbc 13474 #define USART_ICR_TCBGTCF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13475 #define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13476 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
AnnaBridge 171:3a7713b1edbc 13477 #define USART_ICR_LBDCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13478 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13479 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
AnnaBridge 171:3a7713b1edbc 13480 #define USART_ICR_CTSCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13481 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13482 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
AnnaBridge 171:3a7713b1edbc 13483 #define USART_ICR_RTOCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13484 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13485 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
AnnaBridge 171:3a7713b1edbc 13486 #define USART_ICR_EOBCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13487 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13488 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
AnnaBridge 171:3a7713b1edbc 13489 #define USART_ICR_CMCF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13490 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13491 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
AnnaBridge 171:3a7713b1edbc 13492 #define USART_ICR_WUCF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13493 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13494 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
AnnaBridge 171:3a7713b1edbc 13495
AnnaBridge 171:3a7713b1edbc 13496 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 13497 #define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
AnnaBridge 171:3a7713b1edbc 13498 #define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
AnnaBridge 171:3a7713b1edbc 13499 #define USART_ICR_NCF USART_ICR_NECF
AnnaBridge 171:3a7713b1edbc 13500
AnnaBridge 171:3a7713b1edbc 13501 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 171:3a7713b1edbc 13502 #define USART_RDR_RDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13503 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 13504 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 171:3a7713b1edbc 13505
AnnaBridge 171:3a7713b1edbc 13506 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 171:3a7713b1edbc 13507 #define USART_TDR_TDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13508 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 13509 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 171:3a7713b1edbc 13510
AnnaBridge 171:3a7713b1edbc 13511 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13512 /* */
AnnaBridge 171:3a7713b1edbc 13513 /* Single Wire Protocol Master Interface (SWPMI) */
AnnaBridge 171:3a7713b1edbc 13514 /* */
AnnaBridge 171:3a7713b1edbc 13515 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13516
AnnaBridge 171:3a7713b1edbc 13517 /******************* Bit definition for SWPMI_CR register ********************/
AnnaBridge 171:3a7713b1edbc 13518 #define SWPMI_CR_RXDMA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13519 #define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13520 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
AnnaBridge 171:3a7713b1edbc 13521 #define SWPMI_CR_TXDMA_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13522 #define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13523 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
AnnaBridge 171:3a7713b1edbc 13524 #define SWPMI_CR_RXMODE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13525 #define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13526 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
AnnaBridge 171:3a7713b1edbc 13527 #define SWPMI_CR_TXMODE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13528 #define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13529 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
AnnaBridge 171:3a7713b1edbc 13530 #define SWPMI_CR_LPBK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13531 #define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13532 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
AnnaBridge 171:3a7713b1edbc 13533 #define SWPMI_CR_SWPACT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13534 #define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13535 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
AnnaBridge 171:3a7713b1edbc 13536 #define SWPMI_CR_DEACT_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13537 #define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13538 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
AnnaBridge 171:3a7713b1edbc 13539
AnnaBridge 171:3a7713b1edbc 13540 /******************* Bit definition for SWPMI_BRR register ********************/
AnnaBridge 171:3a7713b1edbc 13541 #define SWPMI_BRR_BR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13542 #define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 13543 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
AnnaBridge 171:3a7713b1edbc 13544
AnnaBridge 171:3a7713b1edbc 13545 /******************* Bit definition for SWPMI_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 13546 #define SWPMI_ISR_RXBFF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13547 #define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13548 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
AnnaBridge 171:3a7713b1edbc 13549 #define SWPMI_ISR_TXBEF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13550 #define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13551 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
AnnaBridge 171:3a7713b1edbc 13552 #define SWPMI_ISR_RXBERF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13553 #define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13554 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
AnnaBridge 171:3a7713b1edbc 13555 #define SWPMI_ISR_RXOVRF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13556 #define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13557 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
AnnaBridge 171:3a7713b1edbc 13558 #define SWPMI_ISR_TXUNRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13559 #define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13560 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
AnnaBridge 171:3a7713b1edbc 13561 #define SWPMI_ISR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13562 #define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13563 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
AnnaBridge 171:3a7713b1edbc 13564 #define SWPMI_ISR_TXE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13565 #define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13566 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
AnnaBridge 171:3a7713b1edbc 13567 #define SWPMI_ISR_TCF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13568 #define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13569 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
AnnaBridge 171:3a7713b1edbc 13570 #define SWPMI_ISR_SRF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13571 #define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13572 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
AnnaBridge 171:3a7713b1edbc 13573 #define SWPMI_ISR_SUSP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13574 #define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13575 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
AnnaBridge 171:3a7713b1edbc 13576 #define SWPMI_ISR_DEACTF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13577 #define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13578 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
AnnaBridge 171:3a7713b1edbc 13579
AnnaBridge 171:3a7713b1edbc 13580 /******************* Bit definition for SWPMI_ICR register ********************/
AnnaBridge 171:3a7713b1edbc 13581 #define SWPMI_ICR_CRXBFF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13582 #define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13583 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
AnnaBridge 171:3a7713b1edbc 13584 #define SWPMI_ICR_CTXBEF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13585 #define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13586 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
AnnaBridge 171:3a7713b1edbc 13587 #define SWPMI_ICR_CRXBERF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13588 #define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13589 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
AnnaBridge 171:3a7713b1edbc 13590 #define SWPMI_ICR_CRXOVRF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13591 #define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13592 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
AnnaBridge 171:3a7713b1edbc 13593 #define SWPMI_ICR_CTXUNRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13594 #define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13595 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
AnnaBridge 171:3a7713b1edbc 13596 #define SWPMI_ICR_CTCF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13597 #define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13598 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
AnnaBridge 171:3a7713b1edbc 13599 #define SWPMI_ICR_CSRF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13600 #define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13601 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
AnnaBridge 171:3a7713b1edbc 13602
AnnaBridge 171:3a7713b1edbc 13603 /******************* Bit definition for SWPMI_IER register ********************/
AnnaBridge 171:3a7713b1edbc 13604 #define SWPMI_IER_SRIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13605 #define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13606 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
AnnaBridge 171:3a7713b1edbc 13607 #define SWPMI_IER_TCIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13608 #define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13609 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 13610 #define SWPMI_IER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13611 #define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13612 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
AnnaBridge 171:3a7713b1edbc 13613 #define SWPMI_IER_RIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13614 #define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13615 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
AnnaBridge 171:3a7713b1edbc 13616 #define SWPMI_IER_TXUNRIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13617 #define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13618 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
AnnaBridge 171:3a7713b1edbc 13619 #define SWPMI_IER_RXOVRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13620 #define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13621 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
AnnaBridge 171:3a7713b1edbc 13622 #define SWPMI_IER_RXBERIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13623 #define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13624 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
AnnaBridge 171:3a7713b1edbc 13625 #define SWPMI_IER_TXBEIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13626 #define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13627 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
AnnaBridge 171:3a7713b1edbc 13628 #define SWPMI_IER_RXBFIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13629 #define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13630 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
AnnaBridge 171:3a7713b1edbc 13631
AnnaBridge 171:3a7713b1edbc 13632 /******************* Bit definition for SWPMI_RFL register ********************/
AnnaBridge 171:3a7713b1edbc 13633 #define SWPMI_RFL_RFL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13634 #define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 13635 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
AnnaBridge 171:3a7713b1edbc 13636 #define SWPMI_RFL_RFL_0_1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13637 #define SWPMI_RFL_RFL_0_1_Msk (0x3U << SWPMI_RFL_RFL_0_1_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13638 #define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
AnnaBridge 171:3a7713b1edbc 13639
AnnaBridge 171:3a7713b1edbc 13640 /******************* Bit definition for SWPMI_TDR register ********************/
AnnaBridge 171:3a7713b1edbc 13641 #define SWPMI_TDR_TD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13642 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13643 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
AnnaBridge 171:3a7713b1edbc 13644
AnnaBridge 171:3a7713b1edbc 13645 /******************* Bit definition for SWPMI_RDR register ********************/
AnnaBridge 171:3a7713b1edbc 13646 #define SWPMI_RDR_RD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13647 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13648 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
AnnaBridge 171:3a7713b1edbc 13649
AnnaBridge 171:3a7713b1edbc 13650 /******************* Bit definition for SWPMI_OR register ********************/
AnnaBridge 171:3a7713b1edbc 13651 #define SWPMI_OR_TBYP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13652 #define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13653 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
AnnaBridge 171:3a7713b1edbc 13654 #define SWPMI_OR_CLASS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13655 #define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13656 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
AnnaBridge 171:3a7713b1edbc 13657
AnnaBridge 171:3a7713b1edbc 13658
AnnaBridge 171:3a7713b1edbc 13659 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13660 /* */
AnnaBridge 171:3a7713b1edbc 13661 /* Window WATCHDOG */
AnnaBridge 171:3a7713b1edbc 13662 /* */
AnnaBridge 171:3a7713b1edbc 13663 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13664 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 171:3a7713b1edbc 13665 #define WWDG_CR_T_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13666 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 13667 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 171:3a7713b1edbc 13668 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13669 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13670 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13671 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13672 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13673 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13674 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13675
AnnaBridge 171:3a7713b1edbc 13676 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13677 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13678 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 171:3a7713b1edbc 13679
AnnaBridge 171:3a7713b1edbc 13680 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 171:3a7713b1edbc 13681 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13682 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 13683 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 171:3a7713b1edbc 13684 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13685 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13686 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13687 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13688 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13689 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13690 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13691
AnnaBridge 171:3a7713b1edbc 13692 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13693 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 13694 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 171:3a7713b1edbc 13695 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13696 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13697
AnnaBridge 171:3a7713b1edbc 13698 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13699 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13700 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 13701
AnnaBridge 171:3a7713b1edbc 13702 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 13703 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13704 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13705 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13706
AnnaBridge 171:3a7713b1edbc 13707
AnnaBridge 171:3a7713b1edbc 13708 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13709 /* */
AnnaBridge 171:3a7713b1edbc 13710 /* Debug MCU */
AnnaBridge 171:3a7713b1edbc 13711 /* */
AnnaBridge 171:3a7713b1edbc 13712 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13713 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 171:3a7713b1edbc 13714 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13715 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 13716 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 171:3a7713b1edbc 13717 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13718 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 13719 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 171:3a7713b1edbc 13720
AnnaBridge 171:3a7713b1edbc 13721 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 171:3a7713b1edbc 13722 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13723 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13724 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 171:3a7713b1edbc 13725 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13726 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13727 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13728 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13729 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13730 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 171:3a7713b1edbc 13731 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13732 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13733 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 171:3a7713b1edbc 13734
AnnaBridge 171:3a7713b1edbc 13735 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13736 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 13737 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 171:3a7713b1edbc 13738 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13739 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13740
AnnaBridge 171:3a7713b1edbc 13741 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
AnnaBridge 171:3a7713b1edbc 13742 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13743 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13744 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13745 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13746 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13747 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13748 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13749 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13750 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13751 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13752 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13753 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13754 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13755 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13756 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13757 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13758 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13759 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13760 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13761 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13762 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13763 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
AnnaBridge 171:3a7713b1edbc 13764 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13765 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13766 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13767 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13768 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13769 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13770 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13771 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13772
AnnaBridge 171:3a7713b1edbc 13773 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
AnnaBridge 171:3a7713b1edbc 13774 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13775 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13776 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13777
AnnaBridge 171:3a7713b1edbc 13778 /******************** Bit definition for DBGMCU_APB2FZ register ************/
AnnaBridge 171:3a7713b1edbc 13779 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13780 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13781 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13782 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13783 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13784 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13785 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13786 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13787 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
AnnaBridge 171:3a7713b1edbc 13788
AnnaBridge 171:3a7713b1edbc 13789 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13790 /* */
AnnaBridge 171:3a7713b1edbc 13791 /* USB Device FS Endpoint registers */
AnnaBridge 171:3a7713b1edbc 13792 /* */
AnnaBridge 171:3a7713b1edbc 13793 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13794 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
AnnaBridge 171:3a7713b1edbc 13795 #define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
AnnaBridge 171:3a7713b1edbc 13796 #define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
AnnaBridge 171:3a7713b1edbc 13797 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
AnnaBridge 171:3a7713b1edbc 13798 #define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
AnnaBridge 171:3a7713b1edbc 13799 #define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
AnnaBridge 171:3a7713b1edbc 13800 #define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
AnnaBridge 171:3a7713b1edbc 13801 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
AnnaBridge 171:3a7713b1edbc 13802
AnnaBridge 171:3a7713b1edbc 13803 /* bit positions */
AnnaBridge 171:3a7713b1edbc 13804 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
AnnaBridge 171:3a7713b1edbc 13805 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
AnnaBridge 171:3a7713b1edbc 13806 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
AnnaBridge 171:3a7713b1edbc 13807 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
AnnaBridge 171:3a7713b1edbc 13808 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
AnnaBridge 171:3a7713b1edbc 13809 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
AnnaBridge 171:3a7713b1edbc 13810 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
AnnaBridge 171:3a7713b1edbc 13811 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
AnnaBridge 171:3a7713b1edbc 13812 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
AnnaBridge 171:3a7713b1edbc 13813 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
AnnaBridge 171:3a7713b1edbc 13814
AnnaBridge 171:3a7713b1edbc 13815 /* EndPoint REGister MASK (no toggle fields) */
AnnaBridge 171:3a7713b1edbc 13816 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
AnnaBridge 171:3a7713b1edbc 13817 /*!< EP_TYPE[1:0] EndPoint TYPE */
AnnaBridge 171:3a7713b1edbc 13818 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
AnnaBridge 171:3a7713b1edbc 13819 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
AnnaBridge 171:3a7713b1edbc 13820 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
AnnaBridge 171:3a7713b1edbc 13821 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
AnnaBridge 171:3a7713b1edbc 13822 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
AnnaBridge 171:3a7713b1edbc 13823 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
AnnaBridge 171:3a7713b1edbc 13824
AnnaBridge 171:3a7713b1edbc 13825 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
AnnaBridge 171:3a7713b1edbc 13826 /*!< STAT_TX[1:0] STATus for TX transfer */
AnnaBridge 171:3a7713b1edbc 13827 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
AnnaBridge 171:3a7713b1edbc 13828 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
AnnaBridge 171:3a7713b1edbc 13829 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
AnnaBridge 171:3a7713b1edbc 13830 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
AnnaBridge 171:3a7713b1edbc 13831 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
AnnaBridge 171:3a7713b1edbc 13832 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
AnnaBridge 171:3a7713b1edbc 13833 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
AnnaBridge 171:3a7713b1edbc 13834 /*!< STAT_RX[1:0] STATus for RX transfer */
AnnaBridge 171:3a7713b1edbc 13835 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
AnnaBridge 171:3a7713b1edbc 13836 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
AnnaBridge 171:3a7713b1edbc 13837 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
AnnaBridge 171:3a7713b1edbc 13838 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
AnnaBridge 171:3a7713b1edbc 13839 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
AnnaBridge 171:3a7713b1edbc 13840 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
AnnaBridge 171:3a7713b1edbc 13841 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
AnnaBridge 171:3a7713b1edbc 13842
AnnaBridge 171:3a7713b1edbc 13843 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13844 /* */
AnnaBridge 171:3a7713b1edbc 13845 /* USB Device FS General registers */
AnnaBridge 171:3a7713b1edbc 13846 /* */
AnnaBridge 171:3a7713b1edbc 13847 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13848 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
AnnaBridge 171:3a7713b1edbc 13849 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
AnnaBridge 171:3a7713b1edbc 13850 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
AnnaBridge 171:3a7713b1edbc 13851 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
AnnaBridge 171:3a7713b1edbc 13852 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
AnnaBridge 171:3a7713b1edbc 13853 #define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
AnnaBridge 171:3a7713b1edbc 13854 #define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
AnnaBridge 171:3a7713b1edbc 13855
AnnaBridge 171:3a7713b1edbc 13856 /****************** Bits definition for USB_CNTR register *******************/
AnnaBridge 171:3a7713b1edbc 13857 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
AnnaBridge 171:3a7713b1edbc 13858 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
AnnaBridge 171:3a7713b1edbc 13859 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
AnnaBridge 171:3a7713b1edbc 13860 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
AnnaBridge 171:3a7713b1edbc 13861 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
AnnaBridge 171:3a7713b1edbc 13862 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
AnnaBridge 171:3a7713b1edbc 13863 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
AnnaBridge 171:3a7713b1edbc 13864 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
AnnaBridge 171:3a7713b1edbc 13865 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
AnnaBridge 171:3a7713b1edbc 13866 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
AnnaBridge 171:3a7713b1edbc 13867 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
AnnaBridge 171:3a7713b1edbc 13868 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
AnnaBridge 171:3a7713b1edbc 13869 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
AnnaBridge 171:3a7713b1edbc 13870 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
AnnaBridge 171:3a7713b1edbc 13871 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
AnnaBridge 171:3a7713b1edbc 13872
AnnaBridge 171:3a7713b1edbc 13873 /****************** Bits definition for USB_ISTR register *******************/
AnnaBridge 171:3a7713b1edbc 13874 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
AnnaBridge 171:3a7713b1edbc 13875 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
AnnaBridge 171:3a7713b1edbc 13876 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
AnnaBridge 171:3a7713b1edbc 13877 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13878 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13879 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13880 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13881 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13882 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13883 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13884 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
AnnaBridge 171:3a7713b1edbc 13885
AnnaBridge 171:3a7713b1edbc 13886 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
AnnaBridge 171:3a7713b1edbc 13887 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
AnnaBridge 171:3a7713b1edbc 13888 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
AnnaBridge 171:3a7713b1edbc 13889 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
AnnaBridge 171:3a7713b1edbc 13890 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
AnnaBridge 171:3a7713b1edbc 13891 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
AnnaBridge 171:3a7713b1edbc 13892 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
AnnaBridge 171:3a7713b1edbc 13893 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
AnnaBridge 171:3a7713b1edbc 13894 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
AnnaBridge 171:3a7713b1edbc 13895
AnnaBridge 171:3a7713b1edbc 13896 /****************** Bits definition for USB_FNR register ********************/
AnnaBridge 171:3a7713b1edbc 13897 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
AnnaBridge 171:3a7713b1edbc 13898 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
AnnaBridge 171:3a7713b1edbc 13899 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
AnnaBridge 171:3a7713b1edbc 13900 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
AnnaBridge 171:3a7713b1edbc 13901 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
AnnaBridge 171:3a7713b1edbc 13902
AnnaBridge 171:3a7713b1edbc 13903 /****************** Bits definition for USB_DADDR register ****************/
AnnaBridge 171:3a7713b1edbc 13904 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
AnnaBridge 171:3a7713b1edbc 13905 #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 13906 #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 13907 #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 13908 #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 13909 #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 13910 #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
AnnaBridge 171:3a7713b1edbc 13911 #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
AnnaBridge 171:3a7713b1edbc 13912
AnnaBridge 171:3a7713b1edbc 13913 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
AnnaBridge 171:3a7713b1edbc 13914
AnnaBridge 171:3a7713b1edbc 13915 /****************** Bit definition for USB_BTABLE register ******************/
AnnaBridge 171:3a7713b1edbc 13916 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
AnnaBridge 171:3a7713b1edbc 13917
AnnaBridge 171:3a7713b1edbc 13918 /****************** Bits definition for USB_BCDR register *******************/
AnnaBridge 171:3a7713b1edbc 13919 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
AnnaBridge 171:3a7713b1edbc 13920 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
AnnaBridge 171:3a7713b1edbc 13921 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
AnnaBridge 171:3a7713b1edbc 13922 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
AnnaBridge 171:3a7713b1edbc 13923 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
AnnaBridge 171:3a7713b1edbc 13924 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
AnnaBridge 171:3a7713b1edbc 13925 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
AnnaBridge 171:3a7713b1edbc 13926 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
AnnaBridge 171:3a7713b1edbc 13927 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
AnnaBridge 171:3a7713b1edbc 13928
AnnaBridge 171:3a7713b1edbc 13929 /******************* Bit definition for LPMCSR register *********************/
AnnaBridge 171:3a7713b1edbc 13930 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
AnnaBridge 171:3a7713b1edbc 13931 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
AnnaBridge 171:3a7713b1edbc 13932 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
AnnaBridge 171:3a7713b1edbc 13933 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
AnnaBridge 171:3a7713b1edbc 13934
AnnaBridge 171:3a7713b1edbc 13935 /*!< Buffer descriptor table */
AnnaBridge 171:3a7713b1edbc 13936 /***************** Bit definition for USB_ADDR0_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13937 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13938 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13939 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
AnnaBridge 171:3a7713b1edbc 13940
AnnaBridge 171:3a7713b1edbc 13941 /***************** Bit definition for USB_ADDR1_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13942 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13943 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13944 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
AnnaBridge 171:3a7713b1edbc 13945
AnnaBridge 171:3a7713b1edbc 13946 /***************** Bit definition for USB_ADDR2_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13947 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13948 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13949 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
AnnaBridge 171:3a7713b1edbc 13950
AnnaBridge 171:3a7713b1edbc 13951 /***************** Bit definition for USB_ADDR3_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13952 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13953 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13954 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
AnnaBridge 171:3a7713b1edbc 13955
AnnaBridge 171:3a7713b1edbc 13956 /***************** Bit definition for USB_ADDR4_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13957 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13958 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13959 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
AnnaBridge 171:3a7713b1edbc 13960
AnnaBridge 171:3a7713b1edbc 13961 /***************** Bit definition for USB_ADDR5_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13962 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13963 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13964 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
AnnaBridge 171:3a7713b1edbc 13965
AnnaBridge 171:3a7713b1edbc 13966 /***************** Bit definition for USB_ADDR6_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13967 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13968 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13969 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
AnnaBridge 171:3a7713b1edbc 13970
AnnaBridge 171:3a7713b1edbc 13971 /***************** Bit definition for USB_ADDR7_TX register *****************/
AnnaBridge 171:3a7713b1edbc 13972 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13973 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 13974 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
AnnaBridge 171:3a7713b1edbc 13975
AnnaBridge 171:3a7713b1edbc 13976 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 13977
AnnaBridge 171:3a7713b1edbc 13978 /***************** Bit definition for USB_COUNT0_TX register ****************/
AnnaBridge 171:3a7713b1edbc 13979 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13980 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 13981 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
AnnaBridge 171:3a7713b1edbc 13982
AnnaBridge 171:3a7713b1edbc 13983 /***************** Bit definition for USB_COUNT1_TX register ****************/
AnnaBridge 171:3a7713b1edbc 13984 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13985 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 13986 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
AnnaBridge 171:3a7713b1edbc 13987
AnnaBridge 171:3a7713b1edbc 13988 /***************** Bit definition for USB_COUNT2_TX register ****************/
AnnaBridge 171:3a7713b1edbc 13989 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13990 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 13991 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
AnnaBridge 171:3a7713b1edbc 13992
AnnaBridge 171:3a7713b1edbc 13993 /***************** Bit definition for USB_COUNT3_TX register ****************/
AnnaBridge 171:3a7713b1edbc 13994 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13995 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 13996 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
AnnaBridge 171:3a7713b1edbc 13997
AnnaBridge 171:3a7713b1edbc 13998 /***************** Bit definition for USB_COUNT4_TX register ****************/
AnnaBridge 171:3a7713b1edbc 13999 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14000 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14001 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
AnnaBridge 171:3a7713b1edbc 14002
AnnaBridge 171:3a7713b1edbc 14003 /***************** Bit definition for USB_COUNT5_TX register ****************/
AnnaBridge 171:3a7713b1edbc 14004 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14005 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14006 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
AnnaBridge 171:3a7713b1edbc 14007
AnnaBridge 171:3a7713b1edbc 14008 /***************** Bit definition for USB_COUNT6_TX register ****************/
AnnaBridge 171:3a7713b1edbc 14009 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14010 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14011 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
AnnaBridge 171:3a7713b1edbc 14012
AnnaBridge 171:3a7713b1edbc 14013 /***************** Bit definition for USB_COUNT7_TX register ****************/
AnnaBridge 171:3a7713b1edbc 14014 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14015 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14016 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
AnnaBridge 171:3a7713b1edbc 14017
AnnaBridge 171:3a7713b1edbc 14018 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 14019
AnnaBridge 171:3a7713b1edbc 14020 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14021 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
AnnaBridge 171:3a7713b1edbc 14022
AnnaBridge 171:3a7713b1edbc 14023 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14024 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
AnnaBridge 171:3a7713b1edbc 14025
AnnaBridge 171:3a7713b1edbc 14026 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14027 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
AnnaBridge 171:3a7713b1edbc 14028
AnnaBridge 171:3a7713b1edbc 14029 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14030 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
AnnaBridge 171:3a7713b1edbc 14031
AnnaBridge 171:3a7713b1edbc 14032 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14033 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
AnnaBridge 171:3a7713b1edbc 14034
AnnaBridge 171:3a7713b1edbc 14035 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14036 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
AnnaBridge 171:3a7713b1edbc 14037
AnnaBridge 171:3a7713b1edbc 14038 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14039 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
AnnaBridge 171:3a7713b1edbc 14040
AnnaBridge 171:3a7713b1edbc 14041 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14042 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
AnnaBridge 171:3a7713b1edbc 14043
AnnaBridge 171:3a7713b1edbc 14044 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14045 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
AnnaBridge 171:3a7713b1edbc 14046
AnnaBridge 171:3a7713b1edbc 14047 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14048 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
AnnaBridge 171:3a7713b1edbc 14049
AnnaBridge 171:3a7713b1edbc 14050 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14051 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
AnnaBridge 171:3a7713b1edbc 14052
AnnaBridge 171:3a7713b1edbc 14053 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14054 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
AnnaBridge 171:3a7713b1edbc 14055
AnnaBridge 171:3a7713b1edbc 14056 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14057 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
AnnaBridge 171:3a7713b1edbc 14058
AnnaBridge 171:3a7713b1edbc 14059 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14060 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
AnnaBridge 171:3a7713b1edbc 14061
AnnaBridge 171:3a7713b1edbc 14062 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14063 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
AnnaBridge 171:3a7713b1edbc 14064
AnnaBridge 171:3a7713b1edbc 14065 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14066 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
AnnaBridge 171:3a7713b1edbc 14067
AnnaBridge 171:3a7713b1edbc 14068 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 14069
AnnaBridge 171:3a7713b1edbc 14070 /***************** Bit definition for USB_ADDR0_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14071 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14072 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14073 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
AnnaBridge 171:3a7713b1edbc 14074
AnnaBridge 171:3a7713b1edbc 14075 /***************** Bit definition for USB_ADDR1_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14076 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14077 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14078 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
AnnaBridge 171:3a7713b1edbc 14079
AnnaBridge 171:3a7713b1edbc 14080 /***************** Bit definition for USB_ADDR2_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14081 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14082 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14083 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
AnnaBridge 171:3a7713b1edbc 14084
AnnaBridge 171:3a7713b1edbc 14085 /***************** Bit definition for USB_ADDR3_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14086 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14087 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14088 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
AnnaBridge 171:3a7713b1edbc 14089
AnnaBridge 171:3a7713b1edbc 14090 /***************** Bit definition for USB_ADDR4_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14091 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14092 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14093 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
AnnaBridge 171:3a7713b1edbc 14094
AnnaBridge 171:3a7713b1edbc 14095 /***************** Bit definition for USB_ADDR5_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14096 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14097 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14098 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
AnnaBridge 171:3a7713b1edbc 14099
AnnaBridge 171:3a7713b1edbc 14100 /***************** Bit definition for USB_ADDR6_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14101 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14102 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14103 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
AnnaBridge 171:3a7713b1edbc 14104
AnnaBridge 171:3a7713b1edbc 14105 /***************** Bit definition for USB_ADDR7_RX register *****************/
AnnaBridge 171:3a7713b1edbc 14106 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14107 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 14108 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
AnnaBridge 171:3a7713b1edbc 14109
AnnaBridge 171:3a7713b1edbc 14110 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 14111
AnnaBridge 171:3a7713b1edbc 14112 /***************** Bit definition for USB_COUNT0_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14113 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14114 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14115 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14116
AnnaBridge 171:3a7713b1edbc 14117 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14118 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14119 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14120 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14121 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14122 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14123 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14124 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14125
AnnaBridge 171:3a7713b1edbc 14126 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14127 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14128 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14129
AnnaBridge 171:3a7713b1edbc 14130 /***************** Bit definition for USB_COUNT1_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14131 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14132 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14133 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14134
AnnaBridge 171:3a7713b1edbc 14135 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14136 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14137 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14138 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14139 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14140 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14141 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14142 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14143
AnnaBridge 171:3a7713b1edbc 14144 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14145 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14146 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14147
AnnaBridge 171:3a7713b1edbc 14148 /***************** Bit definition for USB_COUNT2_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14149 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14150 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14151 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14152
AnnaBridge 171:3a7713b1edbc 14153 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14154 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14155 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14156 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14157 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14158 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14159 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14160 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14161
AnnaBridge 171:3a7713b1edbc 14162 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14163 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14164 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14165
AnnaBridge 171:3a7713b1edbc 14166 /***************** Bit definition for USB_COUNT3_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14167 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14168 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14169 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14170
AnnaBridge 171:3a7713b1edbc 14171 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14172 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14173 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14174 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14175 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14176 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14177 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14178 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14179
AnnaBridge 171:3a7713b1edbc 14180 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14181 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14182 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14183
AnnaBridge 171:3a7713b1edbc 14184 /***************** Bit definition for USB_COUNT4_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14185 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14186 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14187 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14188
AnnaBridge 171:3a7713b1edbc 14189 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14190 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14191 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14192 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14193 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14194 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14195 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14196 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14197
AnnaBridge 171:3a7713b1edbc 14198 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14199 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14200 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14201
AnnaBridge 171:3a7713b1edbc 14202 /***************** Bit definition for USB_COUNT5_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14203 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14204 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14205 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14206
AnnaBridge 171:3a7713b1edbc 14207 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14208 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14209 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14210 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14211 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14212 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14213 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14214 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14215
AnnaBridge 171:3a7713b1edbc 14216 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14217 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14218 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14219
AnnaBridge 171:3a7713b1edbc 14220 /***************** Bit definition for USB_COUNT6_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14221 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14222 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14223 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14224
AnnaBridge 171:3a7713b1edbc 14225 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14226 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14227 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14228 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14229 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14230 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14231 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14232 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14233
AnnaBridge 171:3a7713b1edbc 14234 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14235 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14236 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14237
AnnaBridge 171:3a7713b1edbc 14238 /***************** Bit definition for USB_COUNT7_RX register ****************/
AnnaBridge 171:3a7713b1edbc 14239 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14240 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 14241 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 14242
AnnaBridge 171:3a7713b1edbc 14243 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14244 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 14245 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 14246 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14247 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14248 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14249 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14250 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14251
AnnaBridge 171:3a7713b1edbc 14252 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14253 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14254 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 14255
AnnaBridge 171:3a7713b1edbc 14256 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 14257
AnnaBridge 171:3a7713b1edbc 14258 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14259 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14260
AnnaBridge 171:3a7713b1edbc 14261 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14262 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14263 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14264 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14265 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14266 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14267
AnnaBridge 171:3a7713b1edbc 14268 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14269
AnnaBridge 171:3a7713b1edbc 14270 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14271 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14272
AnnaBridge 171:3a7713b1edbc 14273 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14274 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14275 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14276 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14277 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14278 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14279
AnnaBridge 171:3a7713b1edbc 14280 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14281
AnnaBridge 171:3a7713b1edbc 14282 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14283 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14284
AnnaBridge 171:3a7713b1edbc 14285 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14286 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14287 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14288 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14289 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14290 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14291
AnnaBridge 171:3a7713b1edbc 14292 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14293
AnnaBridge 171:3a7713b1edbc 14294 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14295 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14296
AnnaBridge 171:3a7713b1edbc 14297 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14298 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14299 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14300 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14301 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14302 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14303
AnnaBridge 171:3a7713b1edbc 14304 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14305
AnnaBridge 171:3a7713b1edbc 14306 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14307 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14308
AnnaBridge 171:3a7713b1edbc 14309 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14310 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14311 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14312 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14313 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14314 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14315
AnnaBridge 171:3a7713b1edbc 14316 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14317
AnnaBridge 171:3a7713b1edbc 14318 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14319 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14320
AnnaBridge 171:3a7713b1edbc 14321 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14322 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14323 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14324 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14325 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14326 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14327
AnnaBridge 171:3a7713b1edbc 14328 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14329
AnnaBridge 171:3a7713b1edbc 14330 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14331 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14332
AnnaBridge 171:3a7713b1edbc 14333 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14334 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14335 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14336 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14337 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14338 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14339
AnnaBridge 171:3a7713b1edbc 14340 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14341
AnnaBridge 171:3a7713b1edbc 14342 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14343 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14344
AnnaBridge 171:3a7713b1edbc 14345 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14346 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14347 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14348 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14349 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14350 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14351
AnnaBridge 171:3a7713b1edbc 14352 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14353
AnnaBridge 171:3a7713b1edbc 14354 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14355 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14356
AnnaBridge 171:3a7713b1edbc 14357 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14358 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14359 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14360 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14361 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14362 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14363
AnnaBridge 171:3a7713b1edbc 14364 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14365
AnnaBridge 171:3a7713b1edbc 14366 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14367 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14368
AnnaBridge 171:3a7713b1edbc 14369 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14370 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14371 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14372 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14373 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14374 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14375
AnnaBridge 171:3a7713b1edbc 14376 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14377
AnnaBridge 171:3a7713b1edbc 14378 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14379 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14380
AnnaBridge 171:3a7713b1edbc 14381 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14382 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14383 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14384 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14385 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14386 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14387
AnnaBridge 171:3a7713b1edbc 14388 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14389
AnnaBridge 171:3a7713b1edbc 14390 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14391 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14392
AnnaBridge 171:3a7713b1edbc 14393 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14394 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14395 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14396 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14397 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14398 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14399
AnnaBridge 171:3a7713b1edbc 14400 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14401
AnnaBridge 171:3a7713b1edbc 14402 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 14403 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14404
AnnaBridge 171:3a7713b1edbc 14405 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14406 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14407 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14408 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14409 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14410 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14411
AnnaBridge 171:3a7713b1edbc 14412 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14413
AnnaBridge 171:3a7713b1edbc 14414 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 14415 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14416
AnnaBridge 171:3a7713b1edbc 14417 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14418 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14419 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14420 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14421 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14422 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14423
AnnaBridge 171:3a7713b1edbc 14424 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14425
AnnaBridge 171:3a7713b1edbc 14426 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
AnnaBridge 171:3a7713b1edbc 14427 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 14428
AnnaBridge 171:3a7713b1edbc 14429 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 14430 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14431 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14432 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14433 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14434 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14435
AnnaBridge 171:3a7713b1edbc 14436 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 14437
AnnaBridge 171:3a7713b1edbc 14438 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
AnnaBridge 171:3a7713b1edbc 14439 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 14440
AnnaBridge 171:3a7713b1edbc 14441 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 14442 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 14443 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 14444 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 14445 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 14446 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 14447
AnnaBridge 171:3a7713b1edbc 14448 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 14449
AnnaBridge 171:3a7713b1edbc 14450
AnnaBridge 171:3a7713b1edbc 14451 /**
AnnaBridge 171:3a7713b1edbc 14452 * @}
AnnaBridge 171:3a7713b1edbc 14453 */
AnnaBridge 171:3a7713b1edbc 14454
AnnaBridge 171:3a7713b1edbc 14455 /**
AnnaBridge 171:3a7713b1edbc 14456 * @}
AnnaBridge 171:3a7713b1edbc 14457 */
AnnaBridge 171:3a7713b1edbc 14458
AnnaBridge 171:3a7713b1edbc 14459 /** @addtogroup Exported_macros
AnnaBridge 171:3a7713b1edbc 14460 * @{
AnnaBridge 171:3a7713b1edbc 14461 */
AnnaBridge 171:3a7713b1edbc 14462
AnnaBridge 171:3a7713b1edbc 14463 /******************************* ADC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14464 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 171:3a7713b1edbc 14465
AnnaBridge 171:3a7713b1edbc 14466 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
AnnaBridge 171:3a7713b1edbc 14467
AnnaBridge 171:3a7713b1edbc 14468 /******************************** CAN Instances ******************************/
AnnaBridge 171:3a7713b1edbc 14469 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
AnnaBridge 171:3a7713b1edbc 14470
AnnaBridge 171:3a7713b1edbc 14471 /******************************** COMP Instances ******************************/
AnnaBridge 171:3a7713b1edbc 14472 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
AnnaBridge 171:3a7713b1edbc 14473 ((INSTANCE) == COMP2))
AnnaBridge 171:3a7713b1edbc 14474
AnnaBridge 171:3a7713b1edbc 14475 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
AnnaBridge 171:3a7713b1edbc 14476
AnnaBridge 171:3a7713b1edbc 14477 /******************** COMP Instances with window mode capability **************/
AnnaBridge 171:3a7713b1edbc 14478 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
AnnaBridge 171:3a7713b1edbc 14479
AnnaBridge 171:3a7713b1edbc 14480 /******************************* CRC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14481 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 171:3a7713b1edbc 14482
AnnaBridge 171:3a7713b1edbc 14483 /******************************* DAC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14484 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
AnnaBridge 171:3a7713b1edbc 14485
AnnaBridge 171:3a7713b1edbc 14486 /******************************** DMA Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14487 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
AnnaBridge 171:3a7713b1edbc 14488 ((INSTANCE) == DMA1_Channel2) || \
AnnaBridge 171:3a7713b1edbc 14489 ((INSTANCE) == DMA1_Channel3) || \
AnnaBridge 171:3a7713b1edbc 14490 ((INSTANCE) == DMA1_Channel4) || \
AnnaBridge 171:3a7713b1edbc 14491 ((INSTANCE) == DMA1_Channel5) || \
AnnaBridge 171:3a7713b1edbc 14492 ((INSTANCE) == DMA1_Channel6) || \
AnnaBridge 171:3a7713b1edbc 14493 ((INSTANCE) == DMA1_Channel7) || \
AnnaBridge 171:3a7713b1edbc 14494 ((INSTANCE) == DMA2_Channel1) || \
AnnaBridge 171:3a7713b1edbc 14495 ((INSTANCE) == DMA2_Channel2) || \
AnnaBridge 171:3a7713b1edbc 14496 ((INSTANCE) == DMA2_Channel3) || \
AnnaBridge 171:3a7713b1edbc 14497 ((INSTANCE) == DMA2_Channel4) || \
AnnaBridge 171:3a7713b1edbc 14498 ((INSTANCE) == DMA2_Channel5) || \
AnnaBridge 171:3a7713b1edbc 14499 ((INSTANCE) == DMA2_Channel6) || \
AnnaBridge 171:3a7713b1edbc 14500 ((INSTANCE) == DMA2_Channel7))
AnnaBridge 171:3a7713b1edbc 14501
AnnaBridge 171:3a7713b1edbc 14502 /******************************* GPIO Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14503 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 14504 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 14505 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 14506 ((INSTANCE) == GPIOH))
AnnaBridge 171:3a7713b1edbc 14507
AnnaBridge 171:3a7713b1edbc 14508 /******************************* GPIO AF Instances ****************************/
AnnaBridge 171:3a7713b1edbc 14509 /* On L4, all GPIO Bank support AF */
AnnaBridge 171:3a7713b1edbc 14510 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 14511
AnnaBridge 171:3a7713b1edbc 14512 /**************************** GPIO Lock Instances *****************************/
AnnaBridge 171:3a7713b1edbc 14513 /* On L4, all GPIO Bank support the Lock mechanism */
AnnaBridge 171:3a7713b1edbc 14514 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 14515
AnnaBridge 171:3a7713b1edbc 14516 /******************************** I2C Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14517 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 171:3a7713b1edbc 14518 ((INSTANCE) == I2C3))
AnnaBridge 171:3a7713b1edbc 14519
AnnaBridge 171:3a7713b1edbc 14520 /****************** I2C Instances : wakeup capability from stop modes *********/
AnnaBridge 171:3a7713b1edbc 14521 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 14522
AnnaBridge 171:3a7713b1edbc 14523 /****************************** OPAMP Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14524 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
AnnaBridge 171:3a7713b1edbc 14525
AnnaBridge 171:3a7713b1edbc 14526 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
AnnaBridge 171:3a7713b1edbc 14527
AnnaBridge 171:3a7713b1edbc 14528 /******************************* QSPI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14529 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
AnnaBridge 171:3a7713b1edbc 14530
AnnaBridge 171:3a7713b1edbc 14531 /******************************* RNG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14532 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 171:3a7713b1edbc 14533
AnnaBridge 171:3a7713b1edbc 14534 /****************************** RTC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14535 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 171:3a7713b1edbc 14536
AnnaBridge 171:3a7713b1edbc 14537 /******************************** SAI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14538 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
AnnaBridge 171:3a7713b1edbc 14539 ((INSTANCE) == SAI1_Block_B))
AnnaBridge 171:3a7713b1edbc 14540
AnnaBridge 171:3a7713b1edbc 14541 /****************************** SMBUS Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14542 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 171:3a7713b1edbc 14543 ((INSTANCE) == I2C3))
AnnaBridge 171:3a7713b1edbc 14544
AnnaBridge 171:3a7713b1edbc 14545 /******************************** SPI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14546 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 14547 ((INSTANCE) == SPI3))
AnnaBridge 171:3a7713b1edbc 14548
AnnaBridge 171:3a7713b1edbc 14549 /******************************** SWPMI Instances *****************************/
AnnaBridge 171:3a7713b1edbc 14550 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
AnnaBridge 171:3a7713b1edbc 14551
AnnaBridge 171:3a7713b1edbc 14552 /****************** LPTIM Instances : All supported instances *****************/
AnnaBridge 171:3a7713b1edbc 14553 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
AnnaBridge 171:3a7713b1edbc 14554 ((INSTANCE) == LPTIM2))
AnnaBridge 171:3a7713b1edbc 14555
AnnaBridge 171:3a7713b1edbc 14556 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 171:3a7713b1edbc 14557 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14558 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14559 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14560 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14561 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14562 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14563
AnnaBridge 171:3a7713b1edbc 14564 /****************** TIM Instances : supporting 32 bits counter ****************/
AnnaBridge 171:3a7713b1edbc 14565 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
AnnaBridge 171:3a7713b1edbc 14566
AnnaBridge 171:3a7713b1edbc 14567 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 171:3a7713b1edbc 14568 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14569 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14570 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14571
AnnaBridge 171:3a7713b1edbc 14572 /************** TIM Instances : supporting Break source selection *************/
AnnaBridge 171:3a7713b1edbc 14573 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14574 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14575 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14576
AnnaBridge 171:3a7713b1edbc 14577 /****************** TIM Instances : supporting 2 break inputs *****************/
AnnaBridge 171:3a7713b1edbc 14578 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14579
AnnaBridge 171:3a7713b1edbc 14580 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 171:3a7713b1edbc 14581 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14582 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14583 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14584 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14585
AnnaBridge 171:3a7713b1edbc 14586 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 14587 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14588 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14589 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14590
AnnaBridge 171:3a7713b1edbc 14591 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 14592 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14593 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14594
AnnaBridge 171:3a7713b1edbc 14595 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 14596 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14597 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14598
AnnaBridge 171:3a7713b1edbc 14599 /****************** TIM Instances : at least 5 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14600 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14601
AnnaBridge 171:3a7713b1edbc 14602 /****************** TIM Instances : at least 6 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14603 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14604
AnnaBridge 171:3a7713b1edbc 14605 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
AnnaBridge 171:3a7713b1edbc 14606 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14607 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14608 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14609
AnnaBridge 171:3a7713b1edbc 14610 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
AnnaBridge 171:3a7713b1edbc 14611 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14612 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14613 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14614 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14615 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14616 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14617
AnnaBridge 171:3a7713b1edbc 14618 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
AnnaBridge 171:3a7713b1edbc 14619 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14620 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14621 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14622 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14623
AnnaBridge 171:3a7713b1edbc 14624 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 171:3a7713b1edbc 14625 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14626 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14627 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14628 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14629
AnnaBridge 171:3a7713b1edbc 14630 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 171:3a7713b1edbc 14631 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 14632 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 14633 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14634 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14635 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 14636 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 14637 ((CHANNEL) == TIM_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 14638 ((CHANNEL) == TIM_CHANNEL_6))) \
AnnaBridge 171:3a7713b1edbc 14639 || \
AnnaBridge 171:3a7713b1edbc 14640 (((INSTANCE) == TIM2) && \
AnnaBridge 171:3a7713b1edbc 14641 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14642 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14643 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 14644 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 14645 || \
AnnaBridge 171:3a7713b1edbc 14646 (((INSTANCE) == TIM15) && \
AnnaBridge 171:3a7713b1edbc 14647 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14648 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 14649 || \
AnnaBridge 171:3a7713b1edbc 14650 (((INSTANCE) == TIM16) && \
AnnaBridge 171:3a7713b1edbc 14651 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 14652
AnnaBridge 171:3a7713b1edbc 14653 /****************** TIM Instances : supporting complementary output(s) ********/
AnnaBridge 171:3a7713b1edbc 14654 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 14655 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 14656 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14657 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14658 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 171:3a7713b1edbc 14659 || \
AnnaBridge 171:3a7713b1edbc 14660 (((INSTANCE) == TIM15) && \
AnnaBridge 171:3a7713b1edbc 14661 ((CHANNEL) == TIM_CHANNEL_1)) \
AnnaBridge 171:3a7713b1edbc 14662 || \
AnnaBridge 171:3a7713b1edbc 14663 (((INSTANCE) == TIM16) && \
AnnaBridge 171:3a7713b1edbc 14664 ((CHANNEL) == TIM_CHANNEL_1)))
AnnaBridge 171:3a7713b1edbc 14665
AnnaBridge 171:3a7713b1edbc 14666 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 171:3a7713b1edbc 14667 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14668 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14669 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14670 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14671
AnnaBridge 171:3a7713b1edbc 14672 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 171:3a7713b1edbc 14673 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14674 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14675 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14676
AnnaBridge 171:3a7713b1edbc 14677 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 171:3a7713b1edbc 14678 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14679 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14680
AnnaBridge 171:3a7713b1edbc 14681 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
AnnaBridge 171:3a7713b1edbc 14682 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14683 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14684 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14685
AnnaBridge 171:3a7713b1edbc 14686 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
AnnaBridge 171:3a7713b1edbc 14687 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14688 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14689 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14690
AnnaBridge 171:3a7713b1edbc 14691 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
AnnaBridge 171:3a7713b1edbc 14692 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14693
AnnaBridge 171:3a7713b1edbc 14694 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 171:3a7713b1edbc 14695 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14696 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14697 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14698
AnnaBridge 171:3a7713b1edbc 14699 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 171:3a7713b1edbc 14700 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14701 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14702
AnnaBridge 171:3a7713b1edbc 14703 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 171:3a7713b1edbc 14704 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14705 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14706
AnnaBridge 171:3a7713b1edbc 14707 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 171:3a7713b1edbc 14708 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14709 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14710
AnnaBridge 171:3a7713b1edbc 14711 /**************** TIM Instances : external trigger input available ************/
AnnaBridge 171:3a7713b1edbc 14712 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14713 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14714
AnnaBridge 171:3a7713b1edbc 14715 /************* TIM Instances : supporting ETR source selection ***************/
AnnaBridge 171:3a7713b1edbc 14716 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14717 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14718
AnnaBridge 171:3a7713b1edbc 14719 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 171:3a7713b1edbc 14720 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14721 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14722 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14723 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14724 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14725
AnnaBridge 171:3a7713b1edbc 14726 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 171:3a7713b1edbc 14727 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14728 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14729 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14730
AnnaBridge 171:3a7713b1edbc 14731 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 171:3a7713b1edbc 14732 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14733 ((INSTANCE) == TIM2))
AnnaBridge 171:3a7713b1edbc 14734
AnnaBridge 171:3a7713b1edbc 14735 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 171:3a7713b1edbc 14736 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14737 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14738 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14739 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14740
AnnaBridge 171:3a7713b1edbc 14741 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 171:3a7713b1edbc 14742 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14743 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14744 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 14745
AnnaBridge 171:3a7713b1edbc 14746 /****************** TIM Instances : supporting synchronization ****************/
AnnaBridge 171:3a7713b1edbc 14747 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 14748
AnnaBridge 171:3a7713b1edbc 14749 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
AnnaBridge 171:3a7713b1edbc 14750 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14751
AnnaBridge 171:3a7713b1edbc 14752 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 171:3a7713b1edbc 14753 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14754 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14755 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14756
AnnaBridge 171:3a7713b1edbc 14757 /****************** TIM Instances : Advanced timer instances *******************/
AnnaBridge 171:3a7713b1edbc 14758 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14759
AnnaBridge 171:3a7713b1edbc 14760 /****************************** TSC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14761 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
AnnaBridge 171:3a7713b1edbc 14762
AnnaBridge 171:3a7713b1edbc 14763 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 14764 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14765 ((INSTANCE) == USART2))
AnnaBridge 171:3a7713b1edbc 14766
AnnaBridge 171:3a7713b1edbc 14767 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 14768 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14769 ((INSTANCE) == USART2))
AnnaBridge 171:3a7713b1edbc 14770
AnnaBridge 171:3a7713b1edbc 14771 /****************** UART Instances : Auto Baud Rate detection ****************/
AnnaBridge 171:3a7713b1edbc 14772 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14773 ((INSTANCE) == USART2))
AnnaBridge 171:3a7713b1edbc 14774
AnnaBridge 171:3a7713b1edbc 14775 /****************** UART Instances : Driver Enable *****************/
AnnaBridge 171:3a7713b1edbc 14776 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14777 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 14778 ((INSTANCE) == LPUART1))
AnnaBridge 171:3a7713b1edbc 14779
AnnaBridge 171:3a7713b1edbc 14780 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 171:3a7713b1edbc 14781 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14782 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 14783 ((INSTANCE) == LPUART1))
AnnaBridge 171:3a7713b1edbc 14784
AnnaBridge 171:3a7713b1edbc 14785 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 171:3a7713b1edbc 14786 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14787 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 14788 ((INSTANCE) == LPUART1))
AnnaBridge 171:3a7713b1edbc 14789
AnnaBridge 171:3a7713b1edbc 14790 /******************** UART Instances : LIN mode **********************/
AnnaBridge 171:3a7713b1edbc 14791 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14792 ((INSTANCE) == USART2))
AnnaBridge 171:3a7713b1edbc 14793
AnnaBridge 171:3a7713b1edbc 14794 /******************** UART Instances : Wake-up from Stop mode **********************/
AnnaBridge 171:3a7713b1edbc 14795 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14796 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 14797 ((INSTANCE) == LPUART1))
AnnaBridge 171:3a7713b1edbc 14798
AnnaBridge 171:3a7713b1edbc 14799 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 171:3a7713b1edbc 14800 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14801 ((INSTANCE) == USART2))
AnnaBridge 171:3a7713b1edbc 14802
AnnaBridge 171:3a7713b1edbc 14803 /********************* USART Instances : Smard card mode ***********************/
AnnaBridge 171:3a7713b1edbc 14804 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 14805 ((INSTANCE) == USART2))
AnnaBridge 171:3a7713b1edbc 14806
AnnaBridge 171:3a7713b1edbc 14807 /******************** LPUART Instance *****************************************/
AnnaBridge 171:3a7713b1edbc 14808 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
AnnaBridge 171:3a7713b1edbc 14809
AnnaBridge 171:3a7713b1edbc 14810 /****************************** IWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14811 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 171:3a7713b1edbc 14812
AnnaBridge 171:3a7713b1edbc 14813 /****************************** WWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14814 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 171:3a7713b1edbc 14815
AnnaBridge 171:3a7713b1edbc 14816 /******************************* USB Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14817 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
AnnaBridge 171:3a7713b1edbc 14818
AnnaBridge 171:3a7713b1edbc 14819 /**
AnnaBridge 171:3a7713b1edbc 14820 * @}
AnnaBridge 171:3a7713b1edbc 14821 */
AnnaBridge 171:3a7713b1edbc 14822
AnnaBridge 171:3a7713b1edbc 14823
AnnaBridge 171:3a7713b1edbc 14824 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14825 /* For a painless codes migration between the STM32L4xx device product */
AnnaBridge 171:3a7713b1edbc 14826 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 171:3a7713b1edbc 14827 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 171:3a7713b1edbc 14828 /* No need to update developed interrupt code when moving across */
AnnaBridge 171:3a7713b1edbc 14829 /* product lines within the same STM32L4 Family */
AnnaBridge 171:3a7713b1edbc 14830 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14831
AnnaBridge 171:3a7713b1edbc 14832 /* Aliases for __IRQn */
AnnaBridge 171:3a7713b1edbc 14833 #define ADC1_2_IRQn ADC1_IRQn
AnnaBridge 171:3a7713b1edbc 14834 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
AnnaBridge 171:3a7713b1edbc 14835 #define HASH_RNG_IRQn RNG_IRQn
AnnaBridge 171:3a7713b1edbc 14836 #define HASH_CRS_IRQn CRS_IRQn
AnnaBridge 171:3a7713b1edbc 14837 #define USB_FS_IRQn USB_IRQn
AnnaBridge 171:3a7713b1edbc 14838
AnnaBridge 171:3a7713b1edbc 14839 /* Aliases for __IRQHandler */
AnnaBridge 171:3a7713b1edbc 14840 #define ADC1_2_IRQHandler ADC1_IRQHandler
AnnaBridge 171:3a7713b1edbc 14841 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
AnnaBridge 171:3a7713b1edbc 14842 #define HASH_RNG_IRQHandler RNG_IRQHandler
AnnaBridge 171:3a7713b1edbc 14843 #define HASH_CRS_IRQHandler CRS_IRQHandler
AnnaBridge 171:3a7713b1edbc 14844 #define USB_FS_IRQHandler USB_IRQHandler
AnnaBridge 171:3a7713b1edbc 14845
AnnaBridge 171:3a7713b1edbc 14846 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 14847 }
AnnaBridge 171:3a7713b1edbc 14848 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 14849
AnnaBridge 171:3a7713b1edbc 14850 #endif /* __STM32L432xx_H */
AnnaBridge 171:3a7713b1edbc 14851
AnnaBridge 171:3a7713b1edbc 14852 /**
AnnaBridge 171:3a7713b1edbc 14853 * @}
AnnaBridge 171:3a7713b1edbc 14854 */
AnnaBridge 171:3a7713b1edbc 14855
AnnaBridge 171:3a7713b1edbc 14856 /**
AnnaBridge 171:3a7713b1edbc 14857 * @}
AnnaBridge 171:3a7713b1edbc 14858 */
AnnaBridge 171:3a7713b1edbc 14859
AnnaBridge 171:3a7713b1edbc 14860 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/