mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_ll_tim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_ll_tim.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of TIM LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32L1xx_LL_TIM_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32L1xx_LL_TIM_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32l1xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32L1xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM6) \|\| defined (TIM7)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup TIM_LL TIM
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	171:3a7713b1edbc	63	{
AnnaBridge	171:3a7713b1edbc	64	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	171:3a7713b1edbc	65	0x00U, /* 1: NA */
AnnaBridge	171:3a7713b1edbc	66	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	171:3a7713b1edbc	67	0x00U, /* 3: NA */
AnnaBridge	171:3a7713b1edbc	68	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	171:3a7713b1edbc	69	0x00U, /* 5: NA */
AnnaBridge	171:3a7713b1edbc	70	0x04U /* 6: TIMx_CH4 */
AnnaBridge	171:3a7713b1edbc	71	};
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	171:3a7713b1edbc	74	{
AnnaBridge	171:3a7713b1edbc	75	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	171:3a7713b1edbc	76	0U, /* 1: - NA */
AnnaBridge	171:3a7713b1edbc	77	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	171:3a7713b1edbc	78	0U, /* 3: - NA */
AnnaBridge	171:3a7713b1edbc	79	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	171:3a7713b1edbc	80	0U, /* 5: - NA */
AnnaBridge	171:3a7713b1edbc	81	8U /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	171:3a7713b1edbc	82	};
AnnaBridge	171:3a7713b1edbc	83
AnnaBridge	171:3a7713b1edbc	84	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	171:3a7713b1edbc	85	{
AnnaBridge	171:3a7713b1edbc	86	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	171:3a7713b1edbc	87	0U, /* 1: - NA */
AnnaBridge	171:3a7713b1edbc	88	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	171:3a7713b1edbc	89	0U, /* 3: - NA */
AnnaBridge	171:3a7713b1edbc	90	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	171:3a7713b1edbc	91	0U, /* 5: - NA */
AnnaBridge	171:3a7713b1edbc	92	8U /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	171:3a7713b1edbc	93	};
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	171:3a7713b1edbc	96	{
AnnaBridge	171:3a7713b1edbc	97	0U, /* 0: CC1P */
AnnaBridge	171:3a7713b1edbc	98	0U, /* 1: NA */
AnnaBridge	171:3a7713b1edbc	99	4U, /* 2: CC2P */
AnnaBridge	171:3a7713b1edbc	100	0U, /* 3: NA */
AnnaBridge	171:3a7713b1edbc	101	8U, /* 4: CC3P */
AnnaBridge	171:3a7713b1edbc	102	0U, /* 5: NA */
AnnaBridge	171:3a7713b1edbc	103	12U /* 6: CC4P */
AnnaBridge	171:3a7713b1edbc	104	};
AnnaBridge	171:3a7713b1edbc	105
AnnaBridge	171:3a7713b1edbc	106	/**
AnnaBridge	171:3a7713b1edbc	107	* @}
AnnaBridge	171:3a7713b1edbc	108	*/
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	112	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	171:3a7713b1edbc	113	* @{
AnnaBridge	171:3a7713b1edbc	114	*/
AnnaBridge	171:3a7713b1edbc	115
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117	#define TIMx_OR_RMP_SHIFT 16U
AnnaBridge	171:3a7713b1edbc	118	#define TIMx_OR_RMP_MASK 0x0000FFFFU
AnnaBridge	171:3a7713b1edbc	119	#define TIM_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM_OR_ETR_RMP \| TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
AnnaBridge	171:3a7713b1edbc	120	#define TIM9_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
AnnaBridge	171:3a7713b1edbc	121	#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	171:3a7713b1edbc	122	#define TIM3_OR_RMP_MASK (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126	/**
AnnaBridge	171:3a7713b1edbc	127	* @}
AnnaBridge	171:3a7713b1edbc	128	*/
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	131	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	171:3a7713b1edbc	132	* @{
AnnaBridge	171:3a7713b1edbc	133	*/
AnnaBridge	171:3a7713b1edbc	134	/** @brief Convert channel id into channel index.
AnnaBridge	171:3a7713b1edbc	135	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	136	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	137	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	138	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	139	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	140	* @retval none
AnnaBridge	171:3a7713b1edbc	141	*/
AnnaBridge	171:3a7713b1edbc	142	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	143	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	171:3a7713b1edbc	144	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	171:3a7713b1edbc	145	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	/**
AnnaBridge	171:3a7713b1edbc	148	* @}
AnnaBridge	171:3a7713b1edbc	149	*/
AnnaBridge	171:3a7713b1edbc	150
AnnaBridge	171:3a7713b1edbc	151
AnnaBridge	171:3a7713b1edbc	152	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	153	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	154	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	171:3a7713b1edbc	155	* @{
AnnaBridge	171:3a7713b1edbc	156	*/
AnnaBridge	171:3a7713b1edbc	157
AnnaBridge	171:3a7713b1edbc	158	/**
AnnaBridge	171:3a7713b1edbc	159	* @brief TIM Time Base configuration structure definition.
AnnaBridge	171:3a7713b1edbc	160	*/
AnnaBridge	171:3a7713b1edbc	161	typedef struct
AnnaBridge	171:3a7713b1edbc	162	{
AnnaBridge	171:3a7713b1edbc	163	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	171:3a7713b1edbc	164	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	171:3a7713b1edbc	165
AnnaBridge	171:3a7713b1edbc	166	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	167
AnnaBridge	171:3a7713b1edbc	168	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	171:3a7713b1edbc	169	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	171:3a7713b1edbc	170
AnnaBridge	171:3a7713b1edbc	171	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	171:3a7713b1edbc	172
AnnaBridge	171:3a7713b1edbc	173	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	171:3a7713b1edbc	174	Auto-Reload Register at the next update event.
AnnaBridge	171:3a7713b1edbc	175	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	171:3a7713b1edbc	176	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	177
AnnaBridge	171:3a7713b1edbc	178	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	171:3a7713b1edbc	179
AnnaBridge	171:3a7713b1edbc	180	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	171:3a7713b1edbc	181	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	171:3a7713b1edbc	184	} LL_TIM_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	185
AnnaBridge	171:3a7713b1edbc	186	/**
AnnaBridge	171:3a7713b1edbc	187	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	171:3a7713b1edbc	188	*/
AnnaBridge	171:3a7713b1edbc	189	typedef struct
AnnaBridge	171:3a7713b1edbc	190	{
AnnaBridge	171:3a7713b1edbc	191	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	171:3a7713b1edbc	192	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	171:3a7713b1edbc	193
AnnaBridge	171:3a7713b1edbc	194	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	171:3a7713b1edbc	195
AnnaBridge	171:3a7713b1edbc	196	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	171:3a7713b1edbc	197	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	171:3a7713b1edbc	198
AnnaBridge	171:3a7713b1edbc	199	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	171:3a7713b1edbc	200
AnnaBridge	171:3a7713b1edbc	201	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	171:3a7713b1edbc	202	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	171:3a7713b1edbc	203
AnnaBridge	171:3a7713b1edbc	204	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	171:3a7713b1edbc	205
AnnaBridge	171:3a7713b1edbc	206	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	171:3a7713b1edbc	207	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	171:3a7713b1edbc	208
AnnaBridge	171:3a7713b1edbc	209	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	210
AnnaBridge	171:3a7713b1edbc	211
AnnaBridge	171:3a7713b1edbc	212	} LL_TIM_OC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	213
AnnaBridge	171:3a7713b1edbc	214	/**
AnnaBridge	171:3a7713b1edbc	215	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	171:3a7713b1edbc	216	*/
AnnaBridge	171:3a7713b1edbc	217
AnnaBridge	171:3a7713b1edbc	218	typedef struct
AnnaBridge	171:3a7713b1edbc	219	{
AnnaBridge	171:3a7713b1edbc	220
AnnaBridge	171:3a7713b1edbc	221	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	222	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	223
AnnaBridge	171:3a7713b1edbc	224	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	171:3a7713b1edbc	227	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	171:3a7713b1edbc	228
AnnaBridge	171:3a7713b1edbc	229	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	171:3a7713b1edbc	230
AnnaBridge	171:3a7713b1edbc	231	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	171:3a7713b1edbc	232	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	233
AnnaBridge	171:3a7713b1edbc	234	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	235
AnnaBridge	171:3a7713b1edbc	236	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	171:3a7713b1edbc	237	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	240	} LL_TIM_IC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242
AnnaBridge	171:3a7713b1edbc	243	/**
AnnaBridge	171:3a7713b1edbc	244	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	171:3a7713b1edbc	245	*/
AnnaBridge	171:3a7713b1edbc	246	typedef struct
AnnaBridge	171:3a7713b1edbc	247	{
AnnaBridge	171:3a7713b1edbc	248	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	171:3a7713b1edbc	249	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	171:3a7713b1edbc	250
AnnaBridge	171:3a7713b1edbc	251	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	171:3a7713b1edbc	252
AnnaBridge	171:3a7713b1edbc	253	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	171:3a7713b1edbc	254	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	257
AnnaBridge	171:3a7713b1edbc	258	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	171:3a7713b1edbc	259	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	171:3a7713b1edbc	260
AnnaBridge	171:3a7713b1edbc	261	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	171:3a7713b1edbc	262
AnnaBridge	171:3a7713b1edbc	263	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	171:3a7713b1edbc	264	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	265
AnnaBridge	171:3a7713b1edbc	266	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	171:3a7713b1edbc	269	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	270
AnnaBridge	171:3a7713b1edbc	271	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	171:3a7713b1edbc	274	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	275
AnnaBridge	171:3a7713b1edbc	276	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	277
AnnaBridge	171:3a7713b1edbc	278	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	171:3a7713b1edbc	279	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	171:3a7713b1edbc	280
AnnaBridge	171:3a7713b1edbc	281	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	171:3a7713b1edbc	282
AnnaBridge	171:3a7713b1edbc	283	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	171:3a7713b1edbc	284	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	285
AnnaBridge	171:3a7713b1edbc	286	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	287
AnnaBridge	171:3a7713b1edbc	288	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	171:3a7713b1edbc	289	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	290
AnnaBridge	171:3a7713b1edbc	291	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	292
AnnaBridge	171:3a7713b1edbc	293	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	294
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	/**
AnnaBridge	171:3a7713b1edbc	297	* @}
AnnaBridge	171:3a7713b1edbc	298	*/
AnnaBridge	171:3a7713b1edbc	299	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	302	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	171:3a7713b1edbc	303	* @{
AnnaBridge	171:3a7713b1edbc	304	*/
AnnaBridge	171:3a7713b1edbc	305
AnnaBridge	171:3a7713b1edbc	306	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	171:3a7713b1edbc	307	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	171:3a7713b1edbc	308	* @{
AnnaBridge	171:3a7713b1edbc	309	*/
AnnaBridge	171:3a7713b1edbc	310	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	171:3a7713b1edbc	311	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	171:3a7713b1edbc	312	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	171:3a7713b1edbc	313	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	171:3a7713b1edbc	314	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	171:3a7713b1edbc	315	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	171:3a7713b1edbc	316	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	171:3a7713b1edbc	317	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	171:3a7713b1edbc	318	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	171:3a7713b1edbc	319	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	171:3a7713b1edbc	320	/**
AnnaBridge	171:3a7713b1edbc	321	* @}
AnnaBridge	171:3a7713b1edbc	322	*/
AnnaBridge	171:3a7713b1edbc	323
AnnaBridge	171:3a7713b1edbc	324	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	171:3a7713b1edbc	325	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	171:3a7713b1edbc	326	* @{
AnnaBridge	171:3a7713b1edbc	327	*/
AnnaBridge	171:3a7713b1edbc	328	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	171:3a7713b1edbc	329	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	171:3a7713b1edbc	330	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	171:3a7713b1edbc	331	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	171:3a7713b1edbc	332	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	171:3a7713b1edbc	333	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	171:3a7713b1edbc	334	/**
AnnaBridge	171:3a7713b1edbc	335	* @}
AnnaBridge	171:3a7713b1edbc	336	*/
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	171:3a7713b1edbc	339	* @{
AnnaBridge	171:3a7713b1edbc	340	*/
AnnaBridge	171:3a7713b1edbc	341	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	171:3a7713b1edbc	342	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	171:3a7713b1edbc	343	/**
AnnaBridge	171:3a7713b1edbc	344	* @}
AnnaBridge	171:3a7713b1edbc	345	*/
AnnaBridge	171:3a7713b1edbc	346
AnnaBridge	171:3a7713b1edbc	347	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	171:3a7713b1edbc	348	* @{
AnnaBridge	171:3a7713b1edbc	349	*/
AnnaBridge	171:3a7713b1edbc	350	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	171:3a7713b1edbc	351	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	171:3a7713b1edbc	352	/**
AnnaBridge	171:3a7713b1edbc	353	* @}
AnnaBridge	171:3a7713b1edbc	354	*/
AnnaBridge	171:3a7713b1edbc	355
AnnaBridge	171:3a7713b1edbc	356	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	171:3a7713b1edbc	357	* @{
AnnaBridge	171:3a7713b1edbc	358	*/
AnnaBridge	171:3a7713b1edbc	359	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	171:3a7713b1edbc	360	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	171:3a7713b1edbc	361	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	171:3a7713b1edbc	362	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	171:3a7713b1edbc	363	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	171:3a7713b1edbc	364	/**
AnnaBridge	171:3a7713b1edbc	365	* @}
AnnaBridge	171:3a7713b1edbc	366	*/
AnnaBridge	171:3a7713b1edbc	367
AnnaBridge	171:3a7713b1edbc	368	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	171:3a7713b1edbc	369	* @{
AnnaBridge	171:3a7713b1edbc	370	*/
AnnaBridge	171:3a7713b1edbc	371	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	171:3a7713b1edbc	372	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	171:3a7713b1edbc	373	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	171:3a7713b1edbc	374	/**
AnnaBridge	171:3a7713b1edbc	375	* @}
AnnaBridge	171:3a7713b1edbc	376	*/
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	171:3a7713b1edbc	379	* @{
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	171:3a7713b1edbc	382	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	171:3a7713b1edbc	383	/**
AnnaBridge	171:3a7713b1edbc	384	* @}
AnnaBridge	171:3a7713b1edbc	385	*/
AnnaBridge	171:3a7713b1edbc	386
AnnaBridge	171:3a7713b1edbc	387
AnnaBridge	171:3a7713b1edbc	388	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	171:3a7713b1edbc	389	* @{
AnnaBridge	171:3a7713b1edbc	390	*/
AnnaBridge	171:3a7713b1edbc	391	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	171:3a7713b1edbc	392	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	171:3a7713b1edbc	393	/**
AnnaBridge	171:3a7713b1edbc	394	* @}
AnnaBridge	171:3a7713b1edbc	395	*/
AnnaBridge	171:3a7713b1edbc	396
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	171:3a7713b1edbc	399	* @{
AnnaBridge	171:3a7713b1edbc	400	*/
AnnaBridge	171:3a7713b1edbc	401	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	171:3a7713b1edbc	402	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	171:3a7713b1edbc	403	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	171:3a7713b1edbc	404	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	171:3a7713b1edbc	405	/**
AnnaBridge	171:3a7713b1edbc	406	* @}
AnnaBridge	171:3a7713b1edbc	407	*/
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	410	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	171:3a7713b1edbc	411	* @{
AnnaBridge	171:3a7713b1edbc	412	*/
AnnaBridge	171:3a7713b1edbc	413	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	171:3a7713b1edbc	414	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	171:3a7713b1edbc	415	/**
AnnaBridge	171:3a7713b1edbc	416	* @}
AnnaBridge	171:3a7713b1edbc	417	*/
AnnaBridge	171:3a7713b1edbc	418	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	419
AnnaBridge	171:3a7713b1edbc	420	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	171:3a7713b1edbc	421	* @{
AnnaBridge	171:3a7713b1edbc	422	*/
AnnaBridge	171:3a7713b1edbc	423	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	171:3a7713b1edbc	424	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	171:3a7713b1edbc	425	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	171:3a7713b1edbc	426	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	171:3a7713b1edbc	427	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	171:3a7713b1edbc	428	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	171:3a7713b1edbc	429	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	171:3a7713b1edbc	430	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	171:3a7713b1edbc	431	/**
AnnaBridge	171:3a7713b1edbc	432	* @}
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434
AnnaBridge	171:3a7713b1edbc	435	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	171:3a7713b1edbc	436	* @{
AnnaBridge	171:3a7713b1edbc	437	*/
AnnaBridge	171:3a7713b1edbc	438	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	171:3a7713b1edbc	439	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	171:3a7713b1edbc	440	/**
AnnaBridge	171:3a7713b1edbc	441	* @}
AnnaBridge	171:3a7713b1edbc	442	*/
AnnaBridge	171:3a7713b1edbc	443
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445
AnnaBridge	171:3a7713b1edbc	446	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	171:3a7713b1edbc	447	* @{
AnnaBridge	171:3a7713b1edbc	448	*/
AnnaBridge	171:3a7713b1edbc	449	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	171:3a7713b1edbc	450	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	171:3a7713b1edbc	451	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	171:3a7713b1edbc	452	/**
AnnaBridge	171:3a7713b1edbc	453	* @}
AnnaBridge	171:3a7713b1edbc	454	*/
AnnaBridge	171:3a7713b1edbc	455
AnnaBridge	171:3a7713b1edbc	456	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	171:3a7713b1edbc	457	* @{
AnnaBridge	171:3a7713b1edbc	458	*/
AnnaBridge	171:3a7713b1edbc	459	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	171:3a7713b1edbc	460	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	171:3a7713b1edbc	461	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	171:3a7713b1edbc	462	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	171:3a7713b1edbc	463	/**
AnnaBridge	171:3a7713b1edbc	464	* @}
AnnaBridge	171:3a7713b1edbc	465	*/
AnnaBridge	171:3a7713b1edbc	466
AnnaBridge	171:3a7713b1edbc	467	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	171:3a7713b1edbc	468	* @{
AnnaBridge	171:3a7713b1edbc	469	*/
AnnaBridge	171:3a7713b1edbc	470	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	171:3a7713b1edbc	471	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	171:3a7713b1edbc	472	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	171:3a7713b1edbc	473	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	171:3a7713b1edbc	474	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	171:3a7713b1edbc	475	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	171:3a7713b1edbc	476	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	171:3a7713b1edbc	477	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	171:3a7713b1edbc	478	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	171:3a7713b1edbc	479	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	171:3a7713b1edbc	480	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	171:3a7713b1edbc	481	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	171:3a7713b1edbc	482	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	171:3a7713b1edbc	483	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	171:3a7713b1edbc	484	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	171:3a7713b1edbc	485	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	171:3a7713b1edbc	486	/**
AnnaBridge	171:3a7713b1edbc	487	* @}
AnnaBridge	171:3a7713b1edbc	488	*/
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	171:3a7713b1edbc	491	* @{
AnnaBridge	171:3a7713b1edbc	492	*/
AnnaBridge	171:3a7713b1edbc	493	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	171:3a7713b1edbc	494	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	171:3a7713b1edbc	495	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	171:3a7713b1edbc	496	/**
AnnaBridge	171:3a7713b1edbc	497	* @}
AnnaBridge	171:3a7713b1edbc	498	*/
AnnaBridge	171:3a7713b1edbc	499
AnnaBridge	171:3a7713b1edbc	500	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	171:3a7713b1edbc	501	* @{
AnnaBridge	171:3a7713b1edbc	502	*/
AnnaBridge	171:3a7713b1edbc	503	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	171:3a7713b1edbc	504	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	171:3a7713b1edbc	505	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	171:3a7713b1edbc	506	/**
AnnaBridge	171:3a7713b1edbc	507	* @}
AnnaBridge	171:3a7713b1edbc	508	*/
AnnaBridge	171:3a7713b1edbc	509
AnnaBridge	171:3a7713b1edbc	510	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	171:3a7713b1edbc	511	* @{
AnnaBridge	171:3a7713b1edbc	512	*/
AnnaBridge	171:3a7713b1edbc	513	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	171:3a7713b1edbc	514	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	171:3a7713b1edbc	515	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
AnnaBridge	171:3a7713b1edbc	516	/**
AnnaBridge	171:3a7713b1edbc	517	* @}
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519
AnnaBridge	171:3a7713b1edbc	520	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	171:3a7713b1edbc	521	* @{
AnnaBridge	171:3a7713b1edbc	522	*/
AnnaBridge	171:3a7713b1edbc	523	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	171:3a7713b1edbc	524	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	171:3a7713b1edbc	525	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	171:3a7713b1edbc	526	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	171:3a7713b1edbc	527	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	528	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	529	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	530	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	531	/**
AnnaBridge	171:3a7713b1edbc	532	* @}
AnnaBridge	171:3a7713b1edbc	533	*/
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535
AnnaBridge	171:3a7713b1edbc	536	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	171:3a7713b1edbc	537	* @{
AnnaBridge	171:3a7713b1edbc	538	*/
AnnaBridge	171:3a7713b1edbc	539	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	171:3a7713b1edbc	540	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	171:3a7713b1edbc	541	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	171:3a7713b1edbc	542	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	171:3a7713b1edbc	543	/**
AnnaBridge	171:3a7713b1edbc	544	* @}
AnnaBridge	171:3a7713b1edbc	545	*/
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	171:3a7713b1edbc	548	* @{
AnnaBridge	171:3a7713b1edbc	549	*/
AnnaBridge	171:3a7713b1edbc	550	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	551	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	552	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	553	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	554	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	555	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	556	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	557	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	558	/**
AnnaBridge	171:3a7713b1edbc	559	* @}
AnnaBridge	171:3a7713b1edbc	560	*/
AnnaBridge	171:3a7713b1edbc	561
AnnaBridge	171:3a7713b1edbc	562	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	171:3a7713b1edbc	563	* @{
AnnaBridge	171:3a7713b1edbc	564	*/
AnnaBridge	171:3a7713b1edbc	565	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	171:3a7713b1edbc	566	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	171:3a7713b1edbc	567	/**
AnnaBridge	171:3a7713b1edbc	568	* @}
AnnaBridge	171:3a7713b1edbc	569	*/
AnnaBridge	171:3a7713b1edbc	570
AnnaBridge	171:3a7713b1edbc	571	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	171:3a7713b1edbc	572	* @{
AnnaBridge	171:3a7713b1edbc	573	*/
AnnaBridge	171:3a7713b1edbc	574	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	171:3a7713b1edbc	575	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	171:3a7713b1edbc	576	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	171:3a7713b1edbc	577	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	171:3a7713b1edbc	578	/**
AnnaBridge	171:3a7713b1edbc	579	* @}
AnnaBridge	171:3a7713b1edbc	580	*/
AnnaBridge	171:3a7713b1edbc	581
AnnaBridge	171:3a7713b1edbc	582	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	171:3a7713b1edbc	583	* @{
AnnaBridge	171:3a7713b1edbc	584	*/
AnnaBridge	171:3a7713b1edbc	585	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	171:3a7713b1edbc	586	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	171:3a7713b1edbc	587	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	171:3a7713b1edbc	588	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	171:3a7713b1edbc	589	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	171:3a7713b1edbc	590	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	171:3a7713b1edbc	591	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	171:3a7713b1edbc	592	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	171:3a7713b1edbc	593	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	171:3a7713b1edbc	594	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	171:3a7713b1edbc	595	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	171:3a7713b1edbc	596	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	171:3a7713b1edbc	597	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	171:3a7713b1edbc	598	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	171:3a7713b1edbc	599	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	171:3a7713b1edbc	600	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	171:3a7713b1edbc	601	/**
AnnaBridge	171:3a7713b1edbc	602	* @}
AnnaBridge	171:3a7713b1edbc	603	*/
AnnaBridge	171:3a7713b1edbc	604
AnnaBridge	171:3a7713b1edbc	605
AnnaBridge	171:3a7713b1edbc	606
AnnaBridge	171:3a7713b1edbc	607
AnnaBridge	171:3a7713b1edbc	608
AnnaBridge	171:3a7713b1edbc	609
AnnaBridge	171:3a7713b1edbc	610
AnnaBridge	171:3a7713b1edbc	611	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	171:3a7713b1edbc	612	* @{
AnnaBridge	171:3a7713b1edbc	613	*/
AnnaBridge	171:3a7713b1edbc	614	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	615	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	616	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	617	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	618	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	619	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	620	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	621	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	622	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	623	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	624	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	625	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	626	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	627	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	628	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	629	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	630	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	631	/**
AnnaBridge	171:3a7713b1edbc	632	* @}
AnnaBridge	171:3a7713b1edbc	633	*/
AnnaBridge	171:3a7713b1edbc	634
AnnaBridge	171:3a7713b1edbc	635	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	171:3a7713b1edbc	636	* @{
AnnaBridge	171:3a7713b1edbc	637	*/
AnnaBridge	171:3a7713b1edbc	638	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	639	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	640	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	641	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	642	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	643	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	644	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	645	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	646	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	647	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	648	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	649	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	650	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	651	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	652	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	653	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	654	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	655	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	656	/**
AnnaBridge	171:3a7713b1edbc	657	* @}
AnnaBridge	171:3a7713b1edbc	658	*/
AnnaBridge	171:3a7713b1edbc	659
AnnaBridge	171:3a7713b1edbc	660	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability
AnnaBridge	171:3a7713b1edbc	661	* @{
AnnaBridge	171:3a7713b1edbc	662	*/
AnnaBridge	171:3a7713b1edbc	663	#define LL_TIM_TIM10_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM10 channel1 is connected to GPIO /
AnnaBridge	171:3a7713b1edbc	664	#define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSI internal clock /
AnnaBridge	171:3a7713b1edbc	665	#define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSE internal clock /
AnnaBridge	171:3a7713b1edbc	666	#define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RTC wakeup interrupt signal /
AnnaBridge	171:3a7713b1edbc	667	/**
AnnaBridge	171:3a7713b1edbc	668	* @}
AnnaBridge	171:3a7713b1edbc	669	*/
AnnaBridge	171:3a7713b1edbc	670
AnnaBridge	171:3a7713b1edbc	671	/** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap
AnnaBridge	171:3a7713b1edbc	672	* @{
AnnaBridge	171:3a7713b1edbc	673	*/
AnnaBridge	171:3a7713b1edbc	674	#define LL_TIM_TIM10_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM10 ETR input is connected to LSE /
AnnaBridge	171:3a7713b1edbc	675	#define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM10 ETR input is connected to TIM9 TGO /
AnnaBridge	171:3a7713b1edbc	676	/**
AnnaBridge	171:3a7713b1edbc	677	* @}
AnnaBridge	171:3a7713b1edbc	678	*/
AnnaBridge	171:3a7713b1edbc	679
AnnaBridge	171:3a7713b1edbc	680	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
AnnaBridge	171:3a7713b1edbc	681	* @{
AnnaBridge	171:3a7713b1edbc	682	*/
AnnaBridge	171:3a7713b1edbc	683	#define LL_TIM_TIM10_TI1_RMP TIM_OR_RMP_MASK /!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values /
AnnaBridge	171:3a7713b1edbc	684	#define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RI /
AnnaBridge	171:3a7713b1edbc	685	/**
AnnaBridge	171:3a7713b1edbc	686	* @}
AnnaBridge	171:3a7713b1edbc	687	*/
AnnaBridge	171:3a7713b1edbc	688
AnnaBridge	171:3a7713b1edbc	689	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability
AnnaBridge	171:3a7713b1edbc	690	* @{
AnnaBridge	171:3a7713b1edbc	691	*/
AnnaBridge	171:3a7713b1edbc	692	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM11 channel1 is connected to GPIO /
AnnaBridge	171:3a7713b1edbc	693	#define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to MSI internal clock /
AnnaBridge	171:3a7713b1edbc	694	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to HSE RTC clock /
AnnaBridge	171:3a7713b1edbc	695	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to GPIO /
AnnaBridge	171:3a7713b1edbc	696	/**
AnnaBridge	171:3a7713b1edbc	697	* @}
AnnaBridge	171:3a7713b1edbc	698	*/
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	/** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap
AnnaBridge	171:3a7713b1edbc	701	* @{
AnnaBridge	171:3a7713b1edbc	702	*/
AnnaBridge	171:3a7713b1edbc	703	#define LL_TIM_TIM11_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM11 ETR input is connected to LSE /
AnnaBridge	171:3a7713b1edbc	704	#define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM11 ETR input is connected to TIM9 TGO clock /
AnnaBridge	171:3a7713b1edbc	705	/**
AnnaBridge	171:3a7713b1edbc	706	* @}
AnnaBridge	171:3a7713b1edbc	707	*/
AnnaBridge	171:3a7713b1edbc	708
AnnaBridge	171:3a7713b1edbc	709	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
AnnaBridge	171:3a7713b1edbc	710	* @{
AnnaBridge	171:3a7713b1edbc	711	*/
AnnaBridge	171:3a7713b1edbc	712	#define LL_TIM_TIM11_TI1_RMP TIM_OR_RMP_MASK /!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values /
AnnaBridge	171:3a7713b1edbc	713	#define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to RI /
AnnaBridge	171:3a7713b1edbc	714	/**
AnnaBridge	171:3a7713b1edbc	715	* @}
AnnaBridge	171:3a7713b1edbc	716	*/
AnnaBridge	171:3a7713b1edbc	717
AnnaBridge	171:3a7713b1edbc	718	/** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
AnnaBridge	171:3a7713b1edbc	719	* @{
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721	#define LL_TIM_TIM9_TI1_RMP_GPIO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to GPIO /
AnnaBridge	171:3a7713b1edbc	722	#define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to LSE internal clock /
AnnaBridge	171:3a7713b1edbc	723	#define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
AnnaBridge	171:3a7713b1edbc	724	#define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
AnnaBridge	171:3a7713b1edbc	725	/**
AnnaBridge	171:3a7713b1edbc	726	* @}
AnnaBridge	171:3a7713b1edbc	727	*/
AnnaBridge	171:3a7713b1edbc	728
AnnaBridge	171:3a7713b1edbc	729	/** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap
AnnaBridge	171:3a7713b1edbc	730	* @{
AnnaBridge	171:3a7713b1edbc	731	*/
AnnaBridge	171:3a7713b1edbc	732	#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to TIM3 TGO signal /
AnnaBridge	171:3a7713b1edbc	733	#define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to touch sensing I/O /
AnnaBridge	171:3a7713b1edbc	734	/**
AnnaBridge	171:3a7713b1edbc	735	* @}
AnnaBridge	171:3a7713b1edbc	736	*/
AnnaBridge	171:3a7713b1edbc	737
AnnaBridge	171:3a7713b1edbc	738	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap
AnnaBridge	171:3a7713b1edbc	739	* @{
AnnaBridge	171:3a7713b1edbc	740	*/
AnnaBridge	171:3a7713b1edbc	741	#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC TIM9_OR_RMP_MASK /!< TIM2 ITR1 input is connected to TIM10 OC/
AnnaBridge	171:3a7713b1edbc	742	#define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM2 ITR1 input is connected to TIM5 TGO /
AnnaBridge	171:3a7713b1edbc	743	/**
AnnaBridge	171:3a7713b1edbc	744	* @}
AnnaBridge	171:3a7713b1edbc	745	*/
AnnaBridge	171:3a7713b1edbc	746
AnnaBridge	171:3a7713b1edbc	747	/** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap
AnnaBridge	171:3a7713b1edbc	748	* @{
AnnaBridge	171:3a7713b1edbc	749	*/
AnnaBridge	171:3a7713b1edbc	750	#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC TIM9_OR_RMP_MASK /!< TIM3 ITR2 input is connected to TIM11 OC /
AnnaBridge	171:3a7713b1edbc	751	#define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP \| TIM9_OR_RMP_MASK) /!< TIM3 ITR2 input is connected to TIM5 TGO /
AnnaBridge	171:3a7713b1edbc	752	/**
AnnaBridge	171:3a7713b1edbc	753	* @}
AnnaBridge	171:3a7713b1edbc	754	*/
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756
AnnaBridge	171:3a7713b1edbc	757	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
AnnaBridge	171:3a7713b1edbc	758	* @{
AnnaBridge	171:3a7713b1edbc	759	*/
AnnaBridge	171:3a7713b1edbc	760	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
AnnaBridge	171:3a7713b1edbc	761	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
AnnaBridge	171:3a7713b1edbc	762	/**
AnnaBridge	171:3a7713b1edbc	763	* @}
AnnaBridge	171:3a7713b1edbc	764	*/
AnnaBridge	171:3a7713b1edbc	765
AnnaBridge	171:3a7713b1edbc	766	/**
AnnaBridge	171:3a7713b1edbc	767	* @}
AnnaBridge	171:3a7713b1edbc	768	*/
AnnaBridge	171:3a7713b1edbc	769
AnnaBridge	171:3a7713b1edbc	770	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	771	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	171:3a7713b1edbc	772	* @{
AnnaBridge	171:3a7713b1edbc	773	*/
AnnaBridge	171:3a7713b1edbc	774
AnnaBridge	171:3a7713b1edbc	775	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	171:3a7713b1edbc	776	* @{
AnnaBridge	171:3a7713b1edbc	777	*/
AnnaBridge	171:3a7713b1edbc	778	/**
AnnaBridge	171:3a7713b1edbc	779	* @brief Write a value in TIM register.
AnnaBridge	171:3a7713b1edbc	780	* @param __INSTANCE__ TIM Instance
AnnaBridge	171:3a7713b1edbc	781	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	782	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	783	* @retval None
AnnaBridge	171:3a7713b1edbc	784	*/
AnnaBridge	171:3a7713b1edbc	785	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787	/**
AnnaBridge	171:3a7713b1edbc	788	* @brief Read a value in TIM register.
AnnaBridge	171:3a7713b1edbc	789	* @param __INSTANCE__ TIM Instance
AnnaBridge	171:3a7713b1edbc	790	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	791	* @retval Register value
AnnaBridge	171:3a7713b1edbc	792	*/
AnnaBridge	171:3a7713b1edbc	793	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	171:3a7713b1edbc	794	/**
AnnaBridge	171:3a7713b1edbc	795	* @}
AnnaBridge	171:3a7713b1edbc	796	*/
AnnaBridge	171:3a7713b1edbc	797
AnnaBridge	171:3a7713b1edbc	798	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	171:3a7713b1edbc	799	* @{
AnnaBridge	171:3a7713b1edbc	800	*/
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802
AnnaBridge	171:3a7713b1edbc	803	/**
AnnaBridge	171:3a7713b1edbc	804	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	171:3a7713b1edbc	805	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	171:3a7713b1edbc	806	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	807	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	808	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	809	*/
AnnaBridge	171:3a7713b1edbc	810	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	171:3a7713b1edbc	811	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	171:3a7713b1edbc	812
AnnaBridge	171:3a7713b1edbc	813	/**
AnnaBridge	171:3a7713b1edbc	814	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	171:3a7713b1edbc	815	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	171:3a7713b1edbc	816	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	817	* @param __PSC__ prescaler
AnnaBridge	171:3a7713b1edbc	818	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	819	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	820	*/
AnnaBridge	171:3a7713b1edbc	821	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	171:3a7713b1edbc	822	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	171:3a7713b1edbc	823
AnnaBridge	171:3a7713b1edbc	824	/**
AnnaBridge	171:3a7713b1edbc	825	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	171:3a7713b1edbc	826	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	171:3a7713b1edbc	827	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	828	* @param __PSC__ prescaler
AnnaBridge	171:3a7713b1edbc	829	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	171:3a7713b1edbc	830	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	831	*/
AnnaBridge	171:3a7713b1edbc	832	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	171:3a7713b1edbc	833	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	171:3a7713b1edbc	834	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	/**
AnnaBridge	171:3a7713b1edbc	837	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	171:3a7713b1edbc	838	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	171:3a7713b1edbc	839	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	840	* @param __PSC__ prescaler
AnnaBridge	171:3a7713b1edbc	841	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	171:3a7713b1edbc	842	* @param __PULSE__ pulse duration (in us)
AnnaBridge	171:3a7713b1edbc	843	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	844	*/
AnnaBridge	171:3a7713b1edbc	845	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	171:3a7713b1edbc	846	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	171:3a7713b1edbc	847	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	171:3a7713b1edbc	848
AnnaBridge	171:3a7713b1edbc	849	/**
AnnaBridge	171:3a7713b1edbc	850	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	171:3a7713b1edbc	851	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	171:3a7713b1edbc	852	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	853	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	171:3a7713b1edbc	854	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	171:3a7713b1edbc	855	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	171:3a7713b1edbc	856	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	857	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	171:3a7713b1edbc	858	*/
AnnaBridge	171:3a7713b1edbc	859	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	171:3a7713b1edbc	860	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	171:3a7713b1edbc	861
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	/**
AnnaBridge	171:3a7713b1edbc	864	* @}
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866
AnnaBridge	171:3a7713b1edbc	867
AnnaBridge	171:3a7713b1edbc	868	/**
AnnaBridge	171:3a7713b1edbc	869	* @}
AnnaBridge	171:3a7713b1edbc	870	*/
AnnaBridge	171:3a7713b1edbc	871
AnnaBridge	171:3a7713b1edbc	872	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	873	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	171:3a7713b1edbc	874	* @{
AnnaBridge	171:3a7713b1edbc	875	*/
AnnaBridge	171:3a7713b1edbc	876
AnnaBridge	171:3a7713b1edbc	877	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	171:3a7713b1edbc	878	* @{
AnnaBridge	171:3a7713b1edbc	879	*/
AnnaBridge	171:3a7713b1edbc	880	/**
AnnaBridge	171:3a7713b1edbc	881	* @brief Enable timer counter.
AnnaBridge	171:3a7713b1edbc	882	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	171:3a7713b1edbc	883	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	884	* @retval None
AnnaBridge	171:3a7713b1edbc	885	*/
AnnaBridge	171:3a7713b1edbc	886	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	887	{
AnnaBridge	171:3a7713b1edbc	888	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	171:3a7713b1edbc	889	}
AnnaBridge	171:3a7713b1edbc	890
AnnaBridge	171:3a7713b1edbc	891	/**
AnnaBridge	171:3a7713b1edbc	892	* @brief Disable timer counter.
AnnaBridge	171:3a7713b1edbc	893	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	171:3a7713b1edbc	894	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	895	* @retval None
AnnaBridge	171:3a7713b1edbc	896	*/
AnnaBridge	171:3a7713b1edbc	897	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	898	{
AnnaBridge	171:3a7713b1edbc	899	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	171:3a7713b1edbc	900	}
AnnaBridge	171:3a7713b1edbc	901
AnnaBridge	171:3a7713b1edbc	902	/**
AnnaBridge	171:3a7713b1edbc	903	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	171:3a7713b1edbc	904	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	171:3a7713b1edbc	905	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	906	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	907	*/
AnnaBridge	171:3a7713b1edbc	908	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	909	{
AnnaBridge	171:3a7713b1edbc	910	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	171:3a7713b1edbc	911	}
AnnaBridge	171:3a7713b1edbc	912
AnnaBridge	171:3a7713b1edbc	913	/**
AnnaBridge	171:3a7713b1edbc	914	* @brief Enable update event generation.
AnnaBridge	171:3a7713b1edbc	915	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	171:3a7713b1edbc	916	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	917	* @retval None
AnnaBridge	171:3a7713b1edbc	918	*/
AnnaBridge	171:3a7713b1edbc	919	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	920	{
AnnaBridge	171:3a7713b1edbc	921	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	171:3a7713b1edbc	922	}
AnnaBridge	171:3a7713b1edbc	923
AnnaBridge	171:3a7713b1edbc	924	/**
AnnaBridge	171:3a7713b1edbc	925	* @brief Disable update event generation.
AnnaBridge	171:3a7713b1edbc	926	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	171:3a7713b1edbc	927	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	928	* @retval None
AnnaBridge	171:3a7713b1edbc	929	*/
AnnaBridge	171:3a7713b1edbc	930	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	931	{
AnnaBridge	171:3a7713b1edbc	932	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	171:3a7713b1edbc	933	}
AnnaBridge	171:3a7713b1edbc	934
AnnaBridge	171:3a7713b1edbc	935	/**
AnnaBridge	171:3a7713b1edbc	936	* @brief Indicates whether update event generation is enabled.
AnnaBridge	171:3a7713b1edbc	937	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	171:3a7713b1edbc	938	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	939	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	940	*/
AnnaBridge	171:3a7713b1edbc	941	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	942	{
AnnaBridge	171:3a7713b1edbc	943	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
AnnaBridge	171:3a7713b1edbc	944	}
AnnaBridge	171:3a7713b1edbc	945
AnnaBridge	171:3a7713b1edbc	946	/**
AnnaBridge	171:3a7713b1edbc	947	* @brief Set update event source
AnnaBridge	171:3a7713b1edbc	948	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	171:3a7713b1edbc	949	* generate an update interrupt or DMA request if enabled:
AnnaBridge	171:3a7713b1edbc	950	* - Counter overflow/underflow
AnnaBridge	171:3a7713b1edbc	951	* - Setting the UG bit
AnnaBridge	171:3a7713b1edbc	952	* - Update generation through the slave mode controller
AnnaBridge	171:3a7713b1edbc	953	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	171:3a7713b1edbc	954	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	171:3a7713b1edbc	955	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	171:3a7713b1edbc	956	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	957	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	958	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	171:3a7713b1edbc	959	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	171:3a7713b1edbc	960	* @retval None
AnnaBridge	171:3a7713b1edbc	961	*/
AnnaBridge	171:3a7713b1edbc	962	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	171:3a7713b1edbc	963	{
AnnaBridge	171:3a7713b1edbc	964	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	171:3a7713b1edbc	965	}
AnnaBridge	171:3a7713b1edbc	966
AnnaBridge	171:3a7713b1edbc	967	/**
AnnaBridge	171:3a7713b1edbc	968	* @brief Get actual event update source
AnnaBridge	171:3a7713b1edbc	969	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	171:3a7713b1edbc	970	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	971	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	972	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	171:3a7713b1edbc	973	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	171:3a7713b1edbc	974	*/
AnnaBridge	171:3a7713b1edbc	975	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	976	{
AnnaBridge	171:3a7713b1edbc	977	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	171:3a7713b1edbc	978	}
AnnaBridge	171:3a7713b1edbc	979
AnnaBridge	171:3a7713b1edbc	980	/**
AnnaBridge	171:3a7713b1edbc	981	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	171:3a7713b1edbc	982	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	171:3a7713b1edbc	983	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	984	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	985	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	171:3a7713b1edbc	986	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	171:3a7713b1edbc	987	* @retval None
AnnaBridge	171:3a7713b1edbc	988	*/
AnnaBridge	171:3a7713b1edbc	989	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	171:3a7713b1edbc	990	{
AnnaBridge	171:3a7713b1edbc	991	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	171:3a7713b1edbc	992	}
AnnaBridge	171:3a7713b1edbc	993
AnnaBridge	171:3a7713b1edbc	994	/**
AnnaBridge	171:3a7713b1edbc	995	* @brief Get actual one pulse mode.
AnnaBridge	171:3a7713b1edbc	996	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	171:3a7713b1edbc	997	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	998	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	999	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	171:3a7713b1edbc	1000	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	171:3a7713b1edbc	1001	*/
AnnaBridge	171:3a7713b1edbc	1002	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1003	{
AnnaBridge	171:3a7713b1edbc	1004	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	171:3a7713b1edbc	1005	}
AnnaBridge	171:3a7713b1edbc	1006
AnnaBridge	171:3a7713b1edbc	1007	/**
AnnaBridge	171:3a7713b1edbc	1008	* @brief Set the timer counter counting mode.
AnnaBridge	171:3a7713b1edbc	1009	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	171:3a7713b1edbc	1010	* check whether or not the counter mode selection feature is supported
AnnaBridge	171:3a7713b1edbc	1011	* by a timer instance.
AnnaBridge	171:3a7713b1edbc	1012	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	171:3a7713b1edbc	1013	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	171:3a7713b1edbc	1014	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1015	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1016	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	171:3a7713b1edbc	1017	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	171:3a7713b1edbc	1018	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	171:3a7713b1edbc	1019	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	171:3a7713b1edbc	1020	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	171:3a7713b1edbc	1021	* @retval None
AnnaBridge	171:3a7713b1edbc	1022	*/
AnnaBridge	171:3a7713b1edbc	1023	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	171:3a7713b1edbc	1024	{
AnnaBridge	171:3a7713b1edbc	1025	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	171:3a7713b1edbc	1026	}
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	/**
AnnaBridge	171:3a7713b1edbc	1029	* @brief Get actual counter mode.
AnnaBridge	171:3a7713b1edbc	1030	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	171:3a7713b1edbc	1031	* check whether or not the counter mode selection feature is supported
AnnaBridge	171:3a7713b1edbc	1032	* by a timer instance.
AnnaBridge	171:3a7713b1edbc	1033	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	171:3a7713b1edbc	1034	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	171:3a7713b1edbc	1035	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1036	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1037	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	171:3a7713b1edbc	1038	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	171:3a7713b1edbc	1039	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	171:3a7713b1edbc	1040	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	171:3a7713b1edbc	1041	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	171:3a7713b1edbc	1042	*/
AnnaBridge	171:3a7713b1edbc	1043	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1044	{
AnnaBridge	171:3a7713b1edbc	1045	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	171:3a7713b1edbc	1046	}
AnnaBridge	171:3a7713b1edbc	1047
AnnaBridge	171:3a7713b1edbc	1048	/**
AnnaBridge	171:3a7713b1edbc	1049	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	171:3a7713b1edbc	1050	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	171:3a7713b1edbc	1051	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1052	* @retval None
AnnaBridge	171:3a7713b1edbc	1053	*/
AnnaBridge	171:3a7713b1edbc	1054	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1055	{
AnnaBridge	171:3a7713b1edbc	1056	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	171:3a7713b1edbc	1057	}
AnnaBridge	171:3a7713b1edbc	1058
AnnaBridge	171:3a7713b1edbc	1059	/**
AnnaBridge	171:3a7713b1edbc	1060	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	171:3a7713b1edbc	1061	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	171:3a7713b1edbc	1062	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1063	* @retval None
AnnaBridge	171:3a7713b1edbc	1064	*/
AnnaBridge	171:3a7713b1edbc	1065	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1066	{
AnnaBridge	171:3a7713b1edbc	1067	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	171:3a7713b1edbc	1068	}
AnnaBridge	171:3a7713b1edbc	1069
AnnaBridge	171:3a7713b1edbc	1070	/**
AnnaBridge	171:3a7713b1edbc	1071	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	171:3a7713b1edbc	1072	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	171:3a7713b1edbc	1073	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1074	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1075	*/
AnnaBridge	171:3a7713b1edbc	1076	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1077	{
AnnaBridge	171:3a7713b1edbc	1078	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	171:3a7713b1edbc	1079	}
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	/**
AnnaBridge	171:3a7713b1edbc	1082	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	171:3a7713b1edbc	1083	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1084	* whether or not the clock division feature is supported by the timer
AnnaBridge	171:3a7713b1edbc	1085	* instance.
AnnaBridge	171:3a7713b1edbc	1086	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	171:3a7713b1edbc	1087	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1088	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1089	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	1090	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	1091	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	1092	* @retval None
AnnaBridge	171:3a7713b1edbc	1093	*/
AnnaBridge	171:3a7713b1edbc	1094	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	171:3a7713b1edbc	1095	{
AnnaBridge	171:3a7713b1edbc	1096	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	171:3a7713b1edbc	1097	}
AnnaBridge	171:3a7713b1edbc	1098
AnnaBridge	171:3a7713b1edbc	1099	/**
AnnaBridge	171:3a7713b1edbc	1100	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	171:3a7713b1edbc	1101	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1102	* whether or not the clock division feature is supported by the timer
AnnaBridge	171:3a7713b1edbc	1103	* instance.
AnnaBridge	171:3a7713b1edbc	1104	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	171:3a7713b1edbc	1105	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1106	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1107	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	1108	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	1109	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	1110	*/
AnnaBridge	171:3a7713b1edbc	1111	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1112	{
AnnaBridge	171:3a7713b1edbc	1113	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	171:3a7713b1edbc	1114	}
AnnaBridge	171:3a7713b1edbc	1115
AnnaBridge	171:3a7713b1edbc	1116	/**
AnnaBridge	171:3a7713b1edbc	1117	* @brief Set the counter value.
AnnaBridge	171:3a7713b1edbc	1118	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1119	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1120	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	171:3a7713b1edbc	1121	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1122	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	1123	* @retval None
AnnaBridge	171:3a7713b1edbc	1124	*/
AnnaBridge	171:3a7713b1edbc	1125	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	171:3a7713b1edbc	1126	{
AnnaBridge	171:3a7713b1edbc	1127	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	171:3a7713b1edbc	1128	}
AnnaBridge	171:3a7713b1edbc	1129
AnnaBridge	171:3a7713b1edbc	1130	/**
AnnaBridge	171:3a7713b1edbc	1131	* @brief Get the counter value.
AnnaBridge	171:3a7713b1edbc	1132	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1133	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1134	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	171:3a7713b1edbc	1135	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1136	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	1137	*/
AnnaBridge	171:3a7713b1edbc	1138	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1139	{
AnnaBridge	171:3a7713b1edbc	1140	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	171:3a7713b1edbc	1141	}
AnnaBridge	171:3a7713b1edbc	1142
AnnaBridge	171:3a7713b1edbc	1143	/**
AnnaBridge	171:3a7713b1edbc	1144	* @brief Get the current direction of the counter
AnnaBridge	171:3a7713b1edbc	1145	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	171:3a7713b1edbc	1146	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1147	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1148	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	171:3a7713b1edbc	1149	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	171:3a7713b1edbc	1150	*/
AnnaBridge	171:3a7713b1edbc	1151	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1152	{
AnnaBridge	171:3a7713b1edbc	1153	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	171:3a7713b1edbc	1154	}
AnnaBridge	171:3a7713b1edbc	1155
AnnaBridge	171:3a7713b1edbc	1156	/**
AnnaBridge	171:3a7713b1edbc	1157	* @brief Set the prescaler value.
AnnaBridge	171:3a7713b1edbc	1158	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	171:3a7713b1edbc	1159	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	171:3a7713b1edbc	1160	* prescaler ratio is taken into account at the next update event.
AnnaBridge	171:3a7713b1edbc	1161	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	171:3a7713b1edbc	1162	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	171:3a7713b1edbc	1163	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1164	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1165	* @retval None
AnnaBridge	171:3a7713b1edbc	1166	*/
AnnaBridge	171:3a7713b1edbc	1167	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	1168	{
AnnaBridge	171:3a7713b1edbc	1169	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	171:3a7713b1edbc	1170	}
AnnaBridge	171:3a7713b1edbc	1171
AnnaBridge	171:3a7713b1edbc	1172	/**
AnnaBridge	171:3a7713b1edbc	1173	* @brief Get the prescaler value.
AnnaBridge	171:3a7713b1edbc	1174	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	171:3a7713b1edbc	1175	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1176	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1177	*/
AnnaBridge	171:3a7713b1edbc	1178	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1179	{
AnnaBridge	171:3a7713b1edbc	1180	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	171:3a7713b1edbc	1181	}
AnnaBridge	171:3a7713b1edbc	1182
AnnaBridge	171:3a7713b1edbc	1183	/**
AnnaBridge	171:3a7713b1edbc	1184	* @brief Set the auto-reload value.
AnnaBridge	171:3a7713b1edbc	1185	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	171:3a7713b1edbc	1186	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1187	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1188	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	171:3a7713b1edbc	1189	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	171:3a7713b1edbc	1190	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1191	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1192	* @retval None
AnnaBridge	171:3a7713b1edbc	1193	*/
AnnaBridge	171:3a7713b1edbc	1194	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	171:3a7713b1edbc	1195	{
AnnaBridge	171:3a7713b1edbc	1196	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	171:3a7713b1edbc	1197	}
AnnaBridge	171:3a7713b1edbc	1198
AnnaBridge	171:3a7713b1edbc	1199	/**
AnnaBridge	171:3a7713b1edbc	1200	* @brief Get the auto-reload value.
AnnaBridge	171:3a7713b1edbc	1201	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	171:3a7713b1edbc	1202	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1203	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1204	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1205	* @retval Auto-reload value
AnnaBridge	171:3a7713b1edbc	1206	*/
AnnaBridge	171:3a7713b1edbc	1207	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1208	{
AnnaBridge	171:3a7713b1edbc	1209	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	171:3a7713b1edbc	1210	}
AnnaBridge	171:3a7713b1edbc	1211
AnnaBridge	171:3a7713b1edbc	1212	/**
AnnaBridge	171:3a7713b1edbc	1213	* @}
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215
AnnaBridge	171:3a7713b1edbc	1216	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	171:3a7713b1edbc	1217	* @{
AnnaBridge	171:3a7713b1edbc	1218	*/
AnnaBridge	171:3a7713b1edbc	1219	/**
AnnaBridge	171:3a7713b1edbc	1220	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	171:3a7713b1edbc	1221	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	171:3a7713b1edbc	1222	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1223	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1224	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	171:3a7713b1edbc	1225	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	171:3a7713b1edbc	1226	* @retval None
AnnaBridge	171:3a7713b1edbc	1227	*/
AnnaBridge	171:3a7713b1edbc	1228	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	171:3a7713b1edbc	1229	{
AnnaBridge	171:3a7713b1edbc	1230	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	171:3a7713b1edbc	1231	}
AnnaBridge	171:3a7713b1edbc	1232
AnnaBridge	171:3a7713b1edbc	1233	/**
AnnaBridge	171:3a7713b1edbc	1234	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	171:3a7713b1edbc	1235	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	171:3a7713b1edbc	1236	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1237	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1238	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	171:3a7713b1edbc	1239	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	171:3a7713b1edbc	1240	*/
AnnaBridge	171:3a7713b1edbc	1241	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1242	{
AnnaBridge	171:3a7713b1edbc	1243	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	171:3a7713b1edbc	1244	}
AnnaBridge	171:3a7713b1edbc	1245
AnnaBridge	171:3a7713b1edbc	1246	/**
AnnaBridge	171:3a7713b1edbc	1247	* @brief Enable capture/compare channels.
AnnaBridge	171:3a7713b1edbc	1248	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1249	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1250	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1251	* CCER CC4E LL_TIM_CC_EnableChannel
AnnaBridge	171:3a7713b1edbc	1252	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1253	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1254	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1255	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1256	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1257	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1258	* @retval None
AnnaBridge	171:3a7713b1edbc	1259	*/
AnnaBridge	171:3a7713b1edbc	1260	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	171:3a7713b1edbc	1261	{
AnnaBridge	171:3a7713b1edbc	1262	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	171:3a7713b1edbc	1263	}
AnnaBridge	171:3a7713b1edbc	1264
AnnaBridge	171:3a7713b1edbc	1265	/**
AnnaBridge	171:3a7713b1edbc	1266	* @brief Disable capture/compare channels.
AnnaBridge	171:3a7713b1edbc	1267	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1268	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1269	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1270	* CCER CC4E LL_TIM_CC_DisableChannel
AnnaBridge	171:3a7713b1edbc	1271	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1272	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1273	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1274	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1275	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1276	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1277	* @retval None
AnnaBridge	171:3a7713b1edbc	1278	*/
AnnaBridge	171:3a7713b1edbc	1279	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	171:3a7713b1edbc	1280	{
AnnaBridge	171:3a7713b1edbc	1281	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	171:3a7713b1edbc	1282	}
AnnaBridge	171:3a7713b1edbc	1283
AnnaBridge	171:3a7713b1edbc	1284	/**
AnnaBridge	171:3a7713b1edbc	1285	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	171:3a7713b1edbc	1286	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1287	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1288	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1289	* CCER CC4E LL_TIM_CC_IsEnabledChannel
AnnaBridge	171:3a7713b1edbc	1290	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1291	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1292	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1293	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1294	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1295	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1296	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1297	*/
AnnaBridge	171:3a7713b1edbc	1298	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	171:3a7713b1edbc	1299	{
AnnaBridge	171:3a7713b1edbc	1300	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	171:3a7713b1edbc	1301	}
AnnaBridge	171:3a7713b1edbc	1302
AnnaBridge	171:3a7713b1edbc	1303	/**
AnnaBridge	171:3a7713b1edbc	1304	* @}
AnnaBridge	171:3a7713b1edbc	1305	*/
AnnaBridge	171:3a7713b1edbc	1306
AnnaBridge	171:3a7713b1edbc	1307	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	171:3a7713b1edbc	1308	* @{
AnnaBridge	171:3a7713b1edbc	1309	*/
AnnaBridge	171:3a7713b1edbc	1310	/**
AnnaBridge	171:3a7713b1edbc	1311	* @brief Configure an output channel.
AnnaBridge	171:3a7713b1edbc	1312	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1313	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1314	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1315	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1316	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1317	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1318	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1319	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1320	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1321	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1322	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1323	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1324	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1325	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1326	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	171:3a7713b1edbc	1327	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	171:3a7713b1edbc	1328	* @retval None
AnnaBridge	171:3a7713b1edbc	1329	*/
AnnaBridge	171:3a7713b1edbc	1330	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	171:3a7713b1edbc	1331	{
AnnaBridge	171:3a7713b1edbc	1332	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1333	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1334	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1335	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	171:3a7713b1edbc	1336	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1337	}
AnnaBridge	171:3a7713b1edbc	1338
AnnaBridge	171:3a7713b1edbc	1339	/**
AnnaBridge	171:3a7713b1edbc	1340	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	171:3a7713b1edbc	1341	* OCx and OCxN (when relevant) are derived.
AnnaBridge	171:3a7713b1edbc	1342	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	171:3a7713b1edbc	1343	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	171:3a7713b1edbc	1344	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	171:3a7713b1edbc	1345	* CCMR2 OC4M LL_TIM_OC_SetMode
AnnaBridge	171:3a7713b1edbc	1346	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1347	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1348	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1349	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1350	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1351	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1352	* @param Mode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1353	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	171:3a7713b1edbc	1354	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	171:3a7713b1edbc	1355	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	171:3a7713b1edbc	1356	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	171:3a7713b1edbc	1357	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	171:3a7713b1edbc	1358	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	171:3a7713b1edbc	1359	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	171:3a7713b1edbc	1360	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	171:3a7713b1edbc	1361	* @retval None
AnnaBridge	171:3a7713b1edbc	1362	*/
AnnaBridge	171:3a7713b1edbc	1363	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	171:3a7713b1edbc	1364	{
AnnaBridge	171:3a7713b1edbc	1365	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1366	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1367	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1368	}
AnnaBridge	171:3a7713b1edbc	1369
AnnaBridge	171:3a7713b1edbc	1370	/**
AnnaBridge	171:3a7713b1edbc	1371	* @brief Get the output compare mode of an output channel.
AnnaBridge	171:3a7713b1edbc	1372	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	171:3a7713b1edbc	1373	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	171:3a7713b1edbc	1374	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	171:3a7713b1edbc	1375	* CCMR2 OC4M LL_TIM_OC_GetMode
AnnaBridge	171:3a7713b1edbc	1376	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1377	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1378	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1379	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1380	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1381	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1382	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1383	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	171:3a7713b1edbc	1384	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	171:3a7713b1edbc	1385	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	171:3a7713b1edbc	1386	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	171:3a7713b1edbc	1387	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	171:3a7713b1edbc	1388	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	171:3a7713b1edbc	1389	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	171:3a7713b1edbc	1390	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	171:3a7713b1edbc	1391	*/
AnnaBridge	171:3a7713b1edbc	1392	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1393	{
AnnaBridge	171:3a7713b1edbc	1394	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1395	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1396	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1397	}
AnnaBridge	171:3a7713b1edbc	1398
AnnaBridge	171:3a7713b1edbc	1399	/**
AnnaBridge	171:3a7713b1edbc	1400	* @brief Set the polarity of an output channel.
AnnaBridge	171:3a7713b1edbc	1401	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1402	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1403	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1404	* CCER CC4P LL_TIM_OC_SetPolarity
AnnaBridge	171:3a7713b1edbc	1405	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1406	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1407	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1408	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1409	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1410	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1411	* @param Polarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1412	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	171:3a7713b1edbc	1413	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	171:3a7713b1edbc	1414	* @retval None
AnnaBridge	171:3a7713b1edbc	1415	*/
AnnaBridge	171:3a7713b1edbc	1416	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	171:3a7713b1edbc	1417	{
AnnaBridge	171:3a7713b1edbc	1418	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1419	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1420	}
AnnaBridge	171:3a7713b1edbc	1421
AnnaBridge	171:3a7713b1edbc	1422	/**
AnnaBridge	171:3a7713b1edbc	1423	* @brief Get the polarity of an output channel.
AnnaBridge	171:3a7713b1edbc	1424	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1425	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1426	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1427	* CCER CC4P LL_TIM_OC_GetPolarity
AnnaBridge	171:3a7713b1edbc	1428	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1429	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1430	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1431	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1432	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1433	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1434	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1435	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	171:3a7713b1edbc	1436	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	171:3a7713b1edbc	1437	*/
AnnaBridge	171:3a7713b1edbc	1438	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1439	{
AnnaBridge	171:3a7713b1edbc	1440	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1441	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1442	}
AnnaBridge	171:3a7713b1edbc	1443
AnnaBridge	171:3a7713b1edbc	1444	/**
AnnaBridge	171:3a7713b1edbc	1445	* @brief Enable fast mode for the output channel.
AnnaBridge	171:3a7713b1edbc	1446	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	171:3a7713b1edbc	1447	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	171:3a7713b1edbc	1448	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	171:3a7713b1edbc	1449	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	171:3a7713b1edbc	1450	* CCMR2 OC4FE LL_TIM_OC_EnableFast
AnnaBridge	171:3a7713b1edbc	1451	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1452	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1453	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1454	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1455	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1456	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1457	* @retval None
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1460	{
AnnaBridge	171:3a7713b1edbc	1461	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1462	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1463	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1464
AnnaBridge	171:3a7713b1edbc	1465	}
AnnaBridge	171:3a7713b1edbc	1466
AnnaBridge	171:3a7713b1edbc	1467	/**
AnnaBridge	171:3a7713b1edbc	1468	* @brief Disable fast mode for the output channel.
AnnaBridge	171:3a7713b1edbc	1469	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	171:3a7713b1edbc	1470	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	171:3a7713b1edbc	1471	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	171:3a7713b1edbc	1472	* CCMR2 OC4FE LL_TIM_OC_DisableFast
AnnaBridge	171:3a7713b1edbc	1473	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1474	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1475	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1476	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1477	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1478	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1479	* @retval None
AnnaBridge	171:3a7713b1edbc	1480	*/
AnnaBridge	171:3a7713b1edbc	1481	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1482	{
AnnaBridge	171:3a7713b1edbc	1483	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1484	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1485	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1486
AnnaBridge	171:3a7713b1edbc	1487	}
AnnaBridge	171:3a7713b1edbc	1488
AnnaBridge	171:3a7713b1edbc	1489	/**
AnnaBridge	171:3a7713b1edbc	1490	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	171:3a7713b1edbc	1491	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1492	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1493	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1494	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1495	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1496	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1497	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1498	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1499	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1500	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1501	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1502	*/
AnnaBridge	171:3a7713b1edbc	1503	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1504	{
AnnaBridge	171:3a7713b1edbc	1505	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1506	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1507	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	171:3a7713b1edbc	1508	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	171:3a7713b1edbc	1509	}
AnnaBridge	171:3a7713b1edbc	1510
AnnaBridge	171:3a7713b1edbc	1511	/**
AnnaBridge	171:3a7713b1edbc	1512	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	171:3a7713b1edbc	1513	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	171:3a7713b1edbc	1514	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	171:3a7713b1edbc	1515	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	171:3a7713b1edbc	1516	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
AnnaBridge	171:3a7713b1edbc	1517	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1518	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1519	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1520	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1521	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1522	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1523	* @retval None
AnnaBridge	171:3a7713b1edbc	1524	*/
AnnaBridge	171:3a7713b1edbc	1525	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1526	{
AnnaBridge	171:3a7713b1edbc	1527	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1528	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1529	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1530	}
AnnaBridge	171:3a7713b1edbc	1531
AnnaBridge	171:3a7713b1edbc	1532	/**
AnnaBridge	171:3a7713b1edbc	1533	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	171:3a7713b1edbc	1534	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	171:3a7713b1edbc	1535	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	171:3a7713b1edbc	1536	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	171:3a7713b1edbc	1537	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
AnnaBridge	171:3a7713b1edbc	1538	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1539	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1540	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1541	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1542	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1543	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1544	* @retval None
AnnaBridge	171:3a7713b1edbc	1545	*/
AnnaBridge	171:3a7713b1edbc	1546	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1547	{
AnnaBridge	171:3a7713b1edbc	1548	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1549	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1550	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1551	}
AnnaBridge	171:3a7713b1edbc	1552
AnnaBridge	171:3a7713b1edbc	1553	/**
AnnaBridge	171:3a7713b1edbc	1554	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	171:3a7713b1edbc	1555	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1556	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1557	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1558	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1559	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1560	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1561	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1562	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1563	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1564	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1565	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1566	*/
AnnaBridge	171:3a7713b1edbc	1567	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1568	{
AnnaBridge	171:3a7713b1edbc	1569	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1570	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1571	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	171:3a7713b1edbc	1572	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	171:3a7713b1edbc	1573	}
AnnaBridge	171:3a7713b1edbc	1574
AnnaBridge	171:3a7713b1edbc	1575	/**
AnnaBridge	171:3a7713b1edbc	1576	* @brief Enable clearing the output channel on an external event.
AnnaBridge	171:3a7713b1edbc	1577	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	171:3a7713b1edbc	1578	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	171:3a7713b1edbc	1579	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	171:3a7713b1edbc	1580	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	171:3a7713b1edbc	1581	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	171:3a7713b1edbc	1582	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	171:3a7713b1edbc	1583	* CCMR2 OC4CE LL_TIM_OC_EnableClear
AnnaBridge	171:3a7713b1edbc	1584	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1585	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1586	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1587	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1588	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1589	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1590	* @retval None
AnnaBridge	171:3a7713b1edbc	1591	*/
AnnaBridge	171:3a7713b1edbc	1592	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1593	{
AnnaBridge	171:3a7713b1edbc	1594	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1595	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1596	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1597	}
AnnaBridge	171:3a7713b1edbc	1598
AnnaBridge	171:3a7713b1edbc	1599	/**
AnnaBridge	171:3a7713b1edbc	1600	* @brief Disable clearing the output channel on an external event.
AnnaBridge	171:3a7713b1edbc	1601	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	171:3a7713b1edbc	1602	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	171:3a7713b1edbc	1603	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	171:3a7713b1edbc	1604	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	171:3a7713b1edbc	1605	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	171:3a7713b1edbc	1606	* CCMR2 OC4CE LL_TIM_OC_DisableClear
AnnaBridge	171:3a7713b1edbc	1607	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1608	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1609	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1610	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1611	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1612	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1613	* @retval None
AnnaBridge	171:3a7713b1edbc	1614	*/
AnnaBridge	171:3a7713b1edbc	1615	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1616	{
AnnaBridge	171:3a7713b1edbc	1617	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1618	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1619	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1620	}
AnnaBridge	171:3a7713b1edbc	1621
AnnaBridge	171:3a7713b1edbc	1622	/**
AnnaBridge	171:3a7713b1edbc	1623	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	171:3a7713b1edbc	1624	* @note This function enables clearing the output channel on an external event.
AnnaBridge	171:3a7713b1edbc	1625	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	171:3a7713b1edbc	1626	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	171:3a7713b1edbc	1627	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	171:3a7713b1edbc	1628	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1629	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1630	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1631	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1632	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1633	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1634	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1635	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1636	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1637	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1638	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1639	*/
AnnaBridge	171:3a7713b1edbc	1640	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1641	{
AnnaBridge	171:3a7713b1edbc	1642	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1643	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1644	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	171:3a7713b1edbc	1645	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	171:3a7713b1edbc	1646	}
AnnaBridge	171:3a7713b1edbc	1647
AnnaBridge	171:3a7713b1edbc	1648	/**
AnnaBridge	171:3a7713b1edbc	1649	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	171:3a7713b1edbc	1650	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1651	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1652	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1653	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1654	* output channel 1 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1655	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	171:3a7713b1edbc	1656	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1657	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1658	* @retval None
AnnaBridge	171:3a7713b1edbc	1659	*/
AnnaBridge	171:3a7713b1edbc	1660	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	1661	{
AnnaBridge	171:3a7713b1edbc	1662	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	171:3a7713b1edbc	1663	}
AnnaBridge	171:3a7713b1edbc	1664
AnnaBridge	171:3a7713b1edbc	1665	/**
AnnaBridge	171:3a7713b1edbc	1666	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	171:3a7713b1edbc	1667	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1668	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1669	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1670	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1671	* output channel 2 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1672	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	171:3a7713b1edbc	1673	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1674	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1675	* @retval None
AnnaBridge	171:3a7713b1edbc	1676	*/
AnnaBridge	171:3a7713b1edbc	1677	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	1678	{
AnnaBridge	171:3a7713b1edbc	1679	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	171:3a7713b1edbc	1680	}
AnnaBridge	171:3a7713b1edbc	1681
AnnaBridge	171:3a7713b1edbc	1682	/**
AnnaBridge	171:3a7713b1edbc	1683	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	171:3a7713b1edbc	1684	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1685	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1686	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1687	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1688	* output channel is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1689	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	171:3a7713b1edbc	1690	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1691	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1692	* @retval None
AnnaBridge	171:3a7713b1edbc	1693	*/
AnnaBridge	171:3a7713b1edbc	1694	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	1695	{
AnnaBridge	171:3a7713b1edbc	1696	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	171:3a7713b1edbc	1697	}
AnnaBridge	171:3a7713b1edbc	1698
AnnaBridge	171:3a7713b1edbc	1699	/**
AnnaBridge	171:3a7713b1edbc	1700	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	171:3a7713b1edbc	1701	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1702	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1703	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1704	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1705	* output channel 4 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1706	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	171:3a7713b1edbc	1707	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1708	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1709	* @retval None
AnnaBridge	171:3a7713b1edbc	1710	*/
AnnaBridge	171:3a7713b1edbc	1711	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	1712	{
AnnaBridge	171:3a7713b1edbc	1713	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	171:3a7713b1edbc	1714	}
AnnaBridge	171:3a7713b1edbc	1715
AnnaBridge	171:3a7713b1edbc	1716	/**
AnnaBridge	171:3a7713b1edbc	1717	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	171:3a7713b1edbc	1718	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1719	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1720	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1721	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1722	* output channel 1 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1723	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	171:3a7713b1edbc	1724	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1725	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	1726	*/
AnnaBridge	171:3a7713b1edbc	1727	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1728	{
AnnaBridge	171:3a7713b1edbc	1729	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	171:3a7713b1edbc	1730	}
AnnaBridge	171:3a7713b1edbc	1731
AnnaBridge	171:3a7713b1edbc	1732	/**
AnnaBridge	171:3a7713b1edbc	1733	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	171:3a7713b1edbc	1734	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1735	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1736	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1737	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1738	* output channel 2 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1739	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	171:3a7713b1edbc	1740	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1741	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	1742	*/
AnnaBridge	171:3a7713b1edbc	1743	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1744	{
AnnaBridge	171:3a7713b1edbc	1745	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	171:3a7713b1edbc	1746	}
AnnaBridge	171:3a7713b1edbc	1747
AnnaBridge	171:3a7713b1edbc	1748	/**
AnnaBridge	171:3a7713b1edbc	1749	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	171:3a7713b1edbc	1750	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1751	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1752	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1753	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1754	* output channel 3 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1755	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	171:3a7713b1edbc	1756	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1757	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	1758	*/
AnnaBridge	171:3a7713b1edbc	1759	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1760	{
AnnaBridge	171:3a7713b1edbc	1761	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	171:3a7713b1edbc	1762	}
AnnaBridge	171:3a7713b1edbc	1763
AnnaBridge	171:3a7713b1edbc	1764	/**
AnnaBridge	171:3a7713b1edbc	1765	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	171:3a7713b1edbc	1766	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	1767	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1768	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1769	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1770	* output channel 4 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1771	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	171:3a7713b1edbc	1772	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1773	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	1774	*/
AnnaBridge	171:3a7713b1edbc	1775	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1776	{
AnnaBridge	171:3a7713b1edbc	1777	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	171:3a7713b1edbc	1778	}
AnnaBridge	171:3a7713b1edbc	1779
AnnaBridge	171:3a7713b1edbc	1780	/**
AnnaBridge	171:3a7713b1edbc	1781	* @}
AnnaBridge	171:3a7713b1edbc	1782	*/
AnnaBridge	171:3a7713b1edbc	1783
AnnaBridge	171:3a7713b1edbc	1784	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	171:3a7713b1edbc	1785	* @{
AnnaBridge	171:3a7713b1edbc	1786	*/
AnnaBridge	171:3a7713b1edbc	1787	/**
AnnaBridge	171:3a7713b1edbc	1788	* @brief Configure input channel.
AnnaBridge	171:3a7713b1edbc	1789	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1790	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1791	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1792	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1793	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1794	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1795	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1796	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1797	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1798	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1799	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1800	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1801	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1802	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1803	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1804	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1805	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1806	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1807	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	1808	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	171:3a7713b1edbc	1809	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1810	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1811	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1812	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1813	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1814	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1815	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	171:3a7713b1edbc	1816	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	171:3a7713b1edbc	1817	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	1818	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	1819	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	1820	* @retval None
AnnaBridge	171:3a7713b1edbc	1821	*/
AnnaBridge	171:3a7713b1edbc	1822	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	171:3a7713b1edbc	1823	{
AnnaBridge	171:3a7713b1edbc	1824	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1825	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1826	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	171:3a7713b1edbc	1827	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1828	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	171:3a7713b1edbc	1829	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1830	}
AnnaBridge	171:3a7713b1edbc	1831
AnnaBridge	171:3a7713b1edbc	1832	/**
AnnaBridge	171:3a7713b1edbc	1833	* @brief Set the active input.
AnnaBridge	171:3a7713b1edbc	1834	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	171:3a7713b1edbc	1835	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	171:3a7713b1edbc	1836	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	171:3a7713b1edbc	1837	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	171:3a7713b1edbc	1838	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1839	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1840	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1841	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1842	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1843	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1844	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1845	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	171:3a7713b1edbc	1846	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	171:3a7713b1edbc	1847	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	171:3a7713b1edbc	1848	* @retval None
AnnaBridge	171:3a7713b1edbc	1849	*/
AnnaBridge	171:3a7713b1edbc	1850	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	171:3a7713b1edbc	1851	{
AnnaBridge	171:3a7713b1edbc	1852	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1853	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1854	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1855	}
AnnaBridge	171:3a7713b1edbc	1856
AnnaBridge	171:3a7713b1edbc	1857	/**
AnnaBridge	171:3a7713b1edbc	1858	* @brief Get the current active input.
AnnaBridge	171:3a7713b1edbc	1859	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	171:3a7713b1edbc	1860	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	171:3a7713b1edbc	1861	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	171:3a7713b1edbc	1862	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	171:3a7713b1edbc	1863	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1864	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1865	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1866	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1867	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1868	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1869	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1870	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	171:3a7713b1edbc	1871	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	171:3a7713b1edbc	1872	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	171:3a7713b1edbc	1873	*/
AnnaBridge	171:3a7713b1edbc	1874	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1875	{
AnnaBridge	171:3a7713b1edbc	1876	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1877	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1878	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	171:3a7713b1edbc	1879	}
AnnaBridge	171:3a7713b1edbc	1880
AnnaBridge	171:3a7713b1edbc	1881	/**
AnnaBridge	171:3a7713b1edbc	1882	* @brief Set the prescaler of input channel.
AnnaBridge	171:3a7713b1edbc	1883	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	171:3a7713b1edbc	1884	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	171:3a7713b1edbc	1885	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	171:3a7713b1edbc	1886	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	171:3a7713b1edbc	1887	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1888	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1889	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1890	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1891	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1892	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1893	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1894	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	171:3a7713b1edbc	1895	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	171:3a7713b1edbc	1896	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	171:3a7713b1edbc	1897	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	1898	* @retval None
AnnaBridge	171:3a7713b1edbc	1899	*/
AnnaBridge	171:3a7713b1edbc	1900	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	171:3a7713b1edbc	1901	{
AnnaBridge	171:3a7713b1edbc	1902	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1903	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1904	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1905	}
AnnaBridge	171:3a7713b1edbc	1906
AnnaBridge	171:3a7713b1edbc	1907	/**
AnnaBridge	171:3a7713b1edbc	1908	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	171:3a7713b1edbc	1909	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	171:3a7713b1edbc	1910	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	171:3a7713b1edbc	1911	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	171:3a7713b1edbc	1912	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	171:3a7713b1edbc	1913	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1914	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1915	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1916	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1917	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1918	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1919	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1920	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	171:3a7713b1edbc	1921	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	171:3a7713b1edbc	1922	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	171:3a7713b1edbc	1923	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	1924	*/
AnnaBridge	171:3a7713b1edbc	1925	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1926	{
AnnaBridge	171:3a7713b1edbc	1927	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1928	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1929	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	171:3a7713b1edbc	1930	}
AnnaBridge	171:3a7713b1edbc	1931
AnnaBridge	171:3a7713b1edbc	1932	/**
AnnaBridge	171:3a7713b1edbc	1933	* @brief Set the input filter duration.
AnnaBridge	171:3a7713b1edbc	1934	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	171:3a7713b1edbc	1935	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	171:3a7713b1edbc	1936	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	171:3a7713b1edbc	1937	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	171:3a7713b1edbc	1938	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1939	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1940	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1941	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1942	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1943	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1944	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1945	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	171:3a7713b1edbc	1946	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	171:3a7713b1edbc	1947	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	171:3a7713b1edbc	1948	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	171:3a7713b1edbc	1949	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	171:3a7713b1edbc	1950	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	171:3a7713b1edbc	1951	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	171:3a7713b1edbc	1952	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	171:3a7713b1edbc	1953	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	171:3a7713b1edbc	1954	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	171:3a7713b1edbc	1955	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	171:3a7713b1edbc	1956	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	171:3a7713b1edbc	1957	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	171:3a7713b1edbc	1958	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	171:3a7713b1edbc	1959	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	171:3a7713b1edbc	1960	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	1961	* @retval None
AnnaBridge	171:3a7713b1edbc	1962	*/
AnnaBridge	171:3a7713b1edbc	1963	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	171:3a7713b1edbc	1964	{
AnnaBridge	171:3a7713b1edbc	1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1966	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1967	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1968	}
AnnaBridge	171:3a7713b1edbc	1969
AnnaBridge	171:3a7713b1edbc	1970	/**
AnnaBridge	171:3a7713b1edbc	1971	* @brief Get the input filter duration.
AnnaBridge	171:3a7713b1edbc	1972	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	171:3a7713b1edbc	1973	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	171:3a7713b1edbc	1974	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	171:3a7713b1edbc	1975	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	171:3a7713b1edbc	1976	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1977	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1978	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1979	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1980	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1981	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1982	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1983	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	171:3a7713b1edbc	1984	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	171:3a7713b1edbc	1985	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	171:3a7713b1edbc	1986	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	171:3a7713b1edbc	1987	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	171:3a7713b1edbc	1988	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	171:3a7713b1edbc	1989	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	171:3a7713b1edbc	1990	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	171:3a7713b1edbc	1991	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	171:3a7713b1edbc	1992	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	171:3a7713b1edbc	1993	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	171:3a7713b1edbc	1994	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	171:3a7713b1edbc	1995	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	171:3a7713b1edbc	1996	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	171:3a7713b1edbc	1997	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	171:3a7713b1edbc	1998	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	1999	*/
AnnaBridge	171:3a7713b1edbc	2000	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	2001	{
AnnaBridge	171:3a7713b1edbc	2002	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2003	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2004	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	171:3a7713b1edbc	2005	}
AnnaBridge	171:3a7713b1edbc	2006
AnnaBridge	171:3a7713b1edbc	2007	/**
AnnaBridge	171:3a7713b1edbc	2008	* @brief Set the input channel polarity.
AnnaBridge	171:3a7713b1edbc	2009	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2010	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2011	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2012	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2013	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2014	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2015	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2016	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	171:3a7713b1edbc	2017	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2018	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2019	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2020	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2021	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2022	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2023	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2024	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	171:3a7713b1edbc	2025	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	171:3a7713b1edbc	2026	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	2027	* @retval None
AnnaBridge	171:3a7713b1edbc	2028	*/
AnnaBridge	171:3a7713b1edbc	2029	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	171:3a7713b1edbc	2030	{
AnnaBridge	171:3a7713b1edbc	2031	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2032	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	171:3a7713b1edbc	2033	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	2034	}
AnnaBridge	171:3a7713b1edbc	2035
AnnaBridge	171:3a7713b1edbc	2036	/**
AnnaBridge	171:3a7713b1edbc	2037	* @brief Get the current input channel polarity.
AnnaBridge	171:3a7713b1edbc	2038	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2039	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2040	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2041	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2042	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2043	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2044	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2045	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	171:3a7713b1edbc	2046	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2047	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2048	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2049	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2050	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2051	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2052	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2053	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	171:3a7713b1edbc	2054	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	171:3a7713b1edbc	2055	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	2056	*/
AnnaBridge	171:3a7713b1edbc	2057	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	2058	{
AnnaBridge	171:3a7713b1edbc	2059	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2060	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	171:3a7713b1edbc	2061	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	2062	}
AnnaBridge	171:3a7713b1edbc	2063
AnnaBridge	171:3a7713b1edbc	2064	/**
AnnaBridge	171:3a7713b1edbc	2065	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	171:3a7713b1edbc	2066	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2067	* a timer instance provides an XOR input.
AnnaBridge	171:3a7713b1edbc	2068	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	171:3a7713b1edbc	2069	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2070	* @retval None
AnnaBridge	171:3a7713b1edbc	2071	*/
AnnaBridge	171:3a7713b1edbc	2072	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2073	{
AnnaBridge	171:3a7713b1edbc	2074	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	171:3a7713b1edbc	2075	}
AnnaBridge	171:3a7713b1edbc	2076
AnnaBridge	171:3a7713b1edbc	2077	/**
AnnaBridge	171:3a7713b1edbc	2078	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	171:3a7713b1edbc	2079	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2080	* a timer instance provides an XOR input.
AnnaBridge	171:3a7713b1edbc	2081	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	171:3a7713b1edbc	2082	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2083	* @retval None
AnnaBridge	171:3a7713b1edbc	2084	*/
AnnaBridge	171:3a7713b1edbc	2085	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2086	{
AnnaBridge	171:3a7713b1edbc	2087	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	171:3a7713b1edbc	2088	}
AnnaBridge	171:3a7713b1edbc	2089
AnnaBridge	171:3a7713b1edbc	2090	/**
AnnaBridge	171:3a7713b1edbc	2091	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	171:3a7713b1edbc	2092	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2093	* a timer instance provides an XOR input.
AnnaBridge	171:3a7713b1edbc	2094	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	171:3a7713b1edbc	2095	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2096	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2097	*/
AnnaBridge	171:3a7713b1edbc	2098	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2099	{
AnnaBridge	171:3a7713b1edbc	2100	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	171:3a7713b1edbc	2101	}
AnnaBridge	171:3a7713b1edbc	2102
AnnaBridge	171:3a7713b1edbc	2103	/**
AnnaBridge	171:3a7713b1edbc	2104	* @brief Get captured value for input channel 1.
AnnaBridge	171:3a7713b1edbc	2105	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2106	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2107	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2108	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2109	* input channel 1 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2110	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	171:3a7713b1edbc	2111	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2112	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2113	*/
AnnaBridge	171:3a7713b1edbc	2114	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2115	{
AnnaBridge	171:3a7713b1edbc	2116	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	171:3a7713b1edbc	2117	}
AnnaBridge	171:3a7713b1edbc	2118
AnnaBridge	171:3a7713b1edbc	2119	/**
AnnaBridge	171:3a7713b1edbc	2120	* @brief Get captured value for input channel 2.
AnnaBridge	171:3a7713b1edbc	2121	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2122	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2123	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2124	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2125	* input channel 2 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2126	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	171:3a7713b1edbc	2127	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2128	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2129	*/
AnnaBridge	171:3a7713b1edbc	2130	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2131	{
AnnaBridge	171:3a7713b1edbc	2132	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	171:3a7713b1edbc	2133	}
AnnaBridge	171:3a7713b1edbc	2134
AnnaBridge	171:3a7713b1edbc	2135	/**
AnnaBridge	171:3a7713b1edbc	2136	* @brief Get captured value for input channel 3.
AnnaBridge	171:3a7713b1edbc	2137	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2138	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2139	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2140	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2141	* input channel 3 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2142	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	171:3a7713b1edbc	2143	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2144	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2145	*/
AnnaBridge	171:3a7713b1edbc	2146	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2147	{
AnnaBridge	171:3a7713b1edbc	2148	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	171:3a7713b1edbc	2149	}
AnnaBridge	171:3a7713b1edbc	2150
AnnaBridge	171:3a7713b1edbc	2151	/**
AnnaBridge	171:3a7713b1edbc	2152	* @brief Get captured value for input channel 4.
AnnaBridge	171:3a7713b1edbc	2153	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2154	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2155	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2156	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2157	* input channel 4 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2158	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	171:3a7713b1edbc	2159	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2160	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2161	*/
AnnaBridge	171:3a7713b1edbc	2162	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2163	{
AnnaBridge	171:3a7713b1edbc	2164	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	171:3a7713b1edbc	2165	}
AnnaBridge	171:3a7713b1edbc	2166
AnnaBridge	171:3a7713b1edbc	2167	/**
AnnaBridge	171:3a7713b1edbc	2168	* @}
AnnaBridge	171:3a7713b1edbc	2169	*/
AnnaBridge	171:3a7713b1edbc	2170
AnnaBridge	171:3a7713b1edbc	2171	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	171:3a7713b1edbc	2172	* @{
AnnaBridge	171:3a7713b1edbc	2173	*/
AnnaBridge	171:3a7713b1edbc	2174	/**
AnnaBridge	171:3a7713b1edbc	2175	* @brief Enable external clock mode 2.
AnnaBridge	171:3a7713b1edbc	2176	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	171:3a7713b1edbc	2177	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2178	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2179	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	171:3a7713b1edbc	2180	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2181	* @retval None
AnnaBridge	171:3a7713b1edbc	2182	*/
AnnaBridge	171:3a7713b1edbc	2183	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2184	{
AnnaBridge	171:3a7713b1edbc	2185	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	171:3a7713b1edbc	2186	}
AnnaBridge	171:3a7713b1edbc	2187
AnnaBridge	171:3a7713b1edbc	2188	/**
AnnaBridge	171:3a7713b1edbc	2189	* @brief Disable external clock mode 2.
AnnaBridge	171:3a7713b1edbc	2190	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2191	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2192	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	171:3a7713b1edbc	2193	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2194	* @retval None
AnnaBridge	171:3a7713b1edbc	2195	*/
AnnaBridge	171:3a7713b1edbc	2196	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2197	{
AnnaBridge	171:3a7713b1edbc	2198	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	171:3a7713b1edbc	2199	}
AnnaBridge	171:3a7713b1edbc	2200
AnnaBridge	171:3a7713b1edbc	2201	/**
AnnaBridge	171:3a7713b1edbc	2202	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	171:3a7713b1edbc	2203	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2204	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2205	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	171:3a7713b1edbc	2206	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2207	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2208	*/
AnnaBridge	171:3a7713b1edbc	2209	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2210	{
AnnaBridge	171:3a7713b1edbc	2211	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	171:3a7713b1edbc	2212	}
AnnaBridge	171:3a7713b1edbc	2213
AnnaBridge	171:3a7713b1edbc	2214	/**
AnnaBridge	171:3a7713b1edbc	2215	* @brief Set the clock source of the counter clock.
AnnaBridge	171:3a7713b1edbc	2216	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	171:3a7713b1edbc	2217	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	171:3a7713b1edbc	2218	* function. This timer input must be configured by calling
AnnaBridge	171:3a7713b1edbc	2219	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	171:3a7713b1edbc	2220	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2221	* whether or not a timer instance supports external clock mode1.
AnnaBridge	171:3a7713b1edbc	2222	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2223	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2224	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	171:3a7713b1edbc	2225	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	171:3a7713b1edbc	2226	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2227	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2228	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	171:3a7713b1edbc	2229	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	171:3a7713b1edbc	2230	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	171:3a7713b1edbc	2231	* @retval None
AnnaBridge	171:3a7713b1edbc	2232	*/
AnnaBridge	171:3a7713b1edbc	2233	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	171:3a7713b1edbc	2234	{
AnnaBridge	171:3a7713b1edbc	2235	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	171:3a7713b1edbc	2236	}
AnnaBridge	171:3a7713b1edbc	2237
AnnaBridge	171:3a7713b1edbc	2238	/**
AnnaBridge	171:3a7713b1edbc	2239	* @brief Set the encoder interface mode.
AnnaBridge	171:3a7713b1edbc	2240	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2241	* whether or not a timer instance supports the encoder mode.
AnnaBridge	171:3a7713b1edbc	2242	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	171:3a7713b1edbc	2243	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2244	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2245	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	171:3a7713b1edbc	2246	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	171:3a7713b1edbc	2247	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	171:3a7713b1edbc	2248	* @retval None
AnnaBridge	171:3a7713b1edbc	2249	*/
AnnaBridge	171:3a7713b1edbc	2250	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	171:3a7713b1edbc	2251	{
AnnaBridge	171:3a7713b1edbc	2252	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	171:3a7713b1edbc	2253	}
AnnaBridge	171:3a7713b1edbc	2254
AnnaBridge	171:3a7713b1edbc	2255	/**
AnnaBridge	171:3a7713b1edbc	2256	* @}
AnnaBridge	171:3a7713b1edbc	2257	*/
AnnaBridge	171:3a7713b1edbc	2258
AnnaBridge	171:3a7713b1edbc	2259	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	171:3a7713b1edbc	2260	* @{
AnnaBridge	171:3a7713b1edbc	2261	*/
AnnaBridge	171:3a7713b1edbc	2262	/**
AnnaBridge	171:3a7713b1edbc	2263	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	171:3a7713b1edbc	2264	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2265	* whether or not a timer instance can operate as a master timer.
AnnaBridge	171:3a7713b1edbc	2266	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	171:3a7713b1edbc	2267	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2268	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2269	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	171:3a7713b1edbc	2270	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	171:3a7713b1edbc	2271	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	171:3a7713b1edbc	2272	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	171:3a7713b1edbc	2273	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	171:3a7713b1edbc	2274	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	171:3a7713b1edbc	2275	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	171:3a7713b1edbc	2276	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	171:3a7713b1edbc	2277	* @retval None
AnnaBridge	171:3a7713b1edbc	2278	*/
AnnaBridge	171:3a7713b1edbc	2279	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	171:3a7713b1edbc	2280	{
AnnaBridge	171:3a7713b1edbc	2281	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	171:3a7713b1edbc	2282	}
AnnaBridge	171:3a7713b1edbc	2283
AnnaBridge	171:3a7713b1edbc	2284	/**
AnnaBridge	171:3a7713b1edbc	2285	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	171:3a7713b1edbc	2286	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2287	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2288	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	171:3a7713b1edbc	2289	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2290	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2291	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	171:3a7713b1edbc	2292	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	171:3a7713b1edbc	2293	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	171:3a7713b1edbc	2294	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	171:3a7713b1edbc	2295	* @retval None
AnnaBridge	171:3a7713b1edbc	2296	*/
AnnaBridge	171:3a7713b1edbc	2297	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	171:3a7713b1edbc	2298	{
AnnaBridge	171:3a7713b1edbc	2299	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	171:3a7713b1edbc	2300	}
AnnaBridge	171:3a7713b1edbc	2301
AnnaBridge	171:3a7713b1edbc	2302	/**
AnnaBridge	171:3a7713b1edbc	2303	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	171:3a7713b1edbc	2304	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2305	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2306	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	171:3a7713b1edbc	2307	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2308	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2309	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	171:3a7713b1edbc	2310	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	171:3a7713b1edbc	2311	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	171:3a7713b1edbc	2312	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	171:3a7713b1edbc	2313	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	171:3a7713b1edbc	2314	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	171:3a7713b1edbc	2315	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	171:3a7713b1edbc	2316	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	171:3a7713b1edbc	2317	* @retval None
AnnaBridge	171:3a7713b1edbc	2318	*/
AnnaBridge	171:3a7713b1edbc	2319	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	171:3a7713b1edbc	2320	{
AnnaBridge	171:3a7713b1edbc	2321	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	171:3a7713b1edbc	2322	}
AnnaBridge	171:3a7713b1edbc	2323
AnnaBridge	171:3a7713b1edbc	2324	/**
AnnaBridge	171:3a7713b1edbc	2325	* @brief Enable the Master/Slave mode.
AnnaBridge	171:3a7713b1edbc	2326	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2327	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2328	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	171:3a7713b1edbc	2329	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2330	* @retval None
AnnaBridge	171:3a7713b1edbc	2331	*/
AnnaBridge	171:3a7713b1edbc	2332	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2333	{
AnnaBridge	171:3a7713b1edbc	2334	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	171:3a7713b1edbc	2335	}
AnnaBridge	171:3a7713b1edbc	2336
AnnaBridge	171:3a7713b1edbc	2337	/**
AnnaBridge	171:3a7713b1edbc	2338	* @brief Disable the Master/Slave mode.
AnnaBridge	171:3a7713b1edbc	2339	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2340	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2341	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	171:3a7713b1edbc	2342	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2343	* @retval None
AnnaBridge	171:3a7713b1edbc	2344	*/
AnnaBridge	171:3a7713b1edbc	2345	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2346	{
AnnaBridge	171:3a7713b1edbc	2347	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	171:3a7713b1edbc	2348	}
AnnaBridge	171:3a7713b1edbc	2349
AnnaBridge	171:3a7713b1edbc	2350	/**
AnnaBridge	171:3a7713b1edbc	2351	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	171:3a7713b1edbc	2352	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2353	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2354	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	171:3a7713b1edbc	2355	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2356	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2357	*/
AnnaBridge	171:3a7713b1edbc	2358	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2359	{
AnnaBridge	171:3a7713b1edbc	2360	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	171:3a7713b1edbc	2361	}
AnnaBridge	171:3a7713b1edbc	2362
AnnaBridge	171:3a7713b1edbc	2363	/**
AnnaBridge	171:3a7713b1edbc	2364	* @brief Configure the external trigger (ETR) input.
AnnaBridge	171:3a7713b1edbc	2365	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2366	* a timer instance provides an external trigger input.
AnnaBridge	171:3a7713b1edbc	2367	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	171:3a7713b1edbc	2368	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	171:3a7713b1edbc	2369	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	171:3a7713b1edbc	2370	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2371	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2372	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	171:3a7713b1edbc	2373	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	171:3a7713b1edbc	2374	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2375	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	171:3a7713b1edbc	2376	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	171:3a7713b1edbc	2377	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	171:3a7713b1edbc	2378	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	171:3a7713b1edbc	2379	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2380	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	171:3a7713b1edbc	2381	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	171:3a7713b1edbc	2382	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	171:3a7713b1edbc	2383	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	171:3a7713b1edbc	2384	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	171:3a7713b1edbc	2385	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	171:3a7713b1edbc	2386	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	171:3a7713b1edbc	2387	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	171:3a7713b1edbc	2388	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	171:3a7713b1edbc	2389	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	171:3a7713b1edbc	2390	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	171:3a7713b1edbc	2391	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	171:3a7713b1edbc	2392	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	171:3a7713b1edbc	2393	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	171:3a7713b1edbc	2394	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	171:3a7713b1edbc	2395	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	2396	* @retval None
AnnaBridge	171:3a7713b1edbc	2397	*/
AnnaBridge	171:3a7713b1edbc	2398	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	171:3a7713b1edbc	2399	uint32_t ETRFilter)
AnnaBridge	171:3a7713b1edbc	2400	{
AnnaBridge	171:3a7713b1edbc	2401	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	171:3a7713b1edbc	2402	}
AnnaBridge	171:3a7713b1edbc	2403
AnnaBridge	171:3a7713b1edbc	2404	/**
AnnaBridge	171:3a7713b1edbc	2405	* @}
AnnaBridge	171:3a7713b1edbc	2406	*/
AnnaBridge	171:3a7713b1edbc	2407
AnnaBridge	171:3a7713b1edbc	2408	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	171:3a7713b1edbc	2409	* @{
AnnaBridge	171:3a7713b1edbc	2410	*/
AnnaBridge	171:3a7713b1edbc	2411	/**
AnnaBridge	171:3a7713b1edbc	2412	* @brief Configures the timer DMA burst feature.
AnnaBridge	171:3a7713b1edbc	2413	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	171:3a7713b1edbc	2414	* not a timer instance supports the DMA burst mode.
AnnaBridge	171:3a7713b1edbc	2415	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	171:3a7713b1edbc	2416	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	171:3a7713b1edbc	2417	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2418	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2419	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	171:3a7713b1edbc	2420	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	171:3a7713b1edbc	2421	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	171:3a7713b1edbc	2422	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	171:3a7713b1edbc	2423	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	171:3a7713b1edbc	2424	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	171:3a7713b1edbc	2425	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	171:3a7713b1edbc	2426	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	171:3a7713b1edbc	2427	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	171:3a7713b1edbc	2428	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	171:3a7713b1edbc	2429	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	171:3a7713b1edbc	2430	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	171:3a7713b1edbc	2431	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	171:3a7713b1edbc	2432	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	171:3a7713b1edbc	2433	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	171:3a7713b1edbc	2434	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	171:3a7713b1edbc	2435	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
AnnaBridge	171:3a7713b1edbc	2436	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2437	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	171:3a7713b1edbc	2438	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	171:3a7713b1edbc	2439	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	171:3a7713b1edbc	2440	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	171:3a7713b1edbc	2441	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	171:3a7713b1edbc	2442	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	171:3a7713b1edbc	2443	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	171:3a7713b1edbc	2444	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	171:3a7713b1edbc	2445	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	171:3a7713b1edbc	2446	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	171:3a7713b1edbc	2447	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	171:3a7713b1edbc	2448	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	171:3a7713b1edbc	2449	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	171:3a7713b1edbc	2450	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	171:3a7713b1edbc	2451	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	171:3a7713b1edbc	2452	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	171:3a7713b1edbc	2453	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	171:3a7713b1edbc	2454	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	171:3a7713b1edbc	2455	* @retval None
AnnaBridge	171:3a7713b1edbc	2456	*/
AnnaBridge	171:3a7713b1edbc	2457	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	171:3a7713b1edbc	2458	{
AnnaBridge	171:3a7713b1edbc	2459	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	171:3a7713b1edbc	2460	}
AnnaBridge	171:3a7713b1edbc	2461
AnnaBridge	171:3a7713b1edbc	2462	/**
AnnaBridge	171:3a7713b1edbc	2463	* @}
AnnaBridge	171:3a7713b1edbc	2464	*/
AnnaBridge	171:3a7713b1edbc	2465
AnnaBridge	171:3a7713b1edbc	2466	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	171:3a7713b1edbc	2467	* @{
AnnaBridge	171:3a7713b1edbc	2468	*/
AnnaBridge	171:3a7713b1edbc	2469	/**
AnnaBridge	171:3a7713b1edbc	2470	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	171:3a7713b1edbc	2471	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2472	* a some timer inputs can be remapped.
AnnaBridge	171:3a7713b1edbc	2473	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2474	* TIM3_OR ITR2_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2475	* TIM9_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2476	* TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2477	* TIM10_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2478	* TIM10_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2479	* TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2480	* TIM11_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2481	* TIM11_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	171:3a7713b1edbc	2482	* TIM11_OR TI1_RMP_RI LL_TIM_SetRemap
AnnaBridge	171:3a7713b1edbc	2483	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2484	* @param Remap Remap params depends on the TIMx. Description available only
AnnaBridge	171:3a7713b1edbc	2485	* in CHM version of the User Manual (not in .pdf).
AnnaBridge	171:3a7713b1edbc	2486	* Otherwise see Reference Manual description of OR registers.
AnnaBridge	171:3a7713b1edbc	2487	*
AnnaBridge	171:3a7713b1edbc	2488	* Below description summarizes "Timer Instance" and "Remap" param combinations:
AnnaBridge	171:3a7713b1edbc	2489	*
AnnaBridge	171:3a7713b1edbc	2490	* TIM2: any combination of ITR1_RMP where
AnnaBridge	171:3a7713b1edbc	2491	*
AnnaBridge	171:3a7713b1edbc	2492	* . . ITR1_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2493	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**)
AnnaBridge	171:3a7713b1edbc	2494	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**)
AnnaBridge	171:3a7713b1edbc	2495	*
AnnaBridge	171:3a7713b1edbc	2496	* TIM3: any combination of ITR2_RMP where
AnnaBridge	171:3a7713b1edbc	2497	*
AnnaBridge	171:3a7713b1edbc	2498	* . . ITR2_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2499	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**)
AnnaBridge	171:3a7713b1edbc	2500	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**)
AnnaBridge	171:3a7713b1edbc	2501	*
AnnaBridge	171:3a7713b1edbc	2502	* TIM9: any combination of TI1_RMP, ITR1_RMP where
AnnaBridge	171:3a7713b1edbc	2503	*
AnnaBridge	171:3a7713b1edbc	2504	* . . TI1_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2505	* @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
AnnaBridge	171:3a7713b1edbc	2506	* @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
AnnaBridge	171:3a7713b1edbc	2507	*
AnnaBridge	171:3a7713b1edbc	2508	* . . ITR1_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2509	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*)
AnnaBridge	171:3a7713b1edbc	2510	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*)
AnnaBridge	171:3a7713b1edbc	2511	*
AnnaBridge	171:3a7713b1edbc	2512	*
AnnaBridge	171:3a7713b1edbc	2513	* TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
AnnaBridge	171:3a7713b1edbc	2514	*
AnnaBridge	171:3a7713b1edbc	2515	* . . TI1_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2516	* @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
AnnaBridge	171:3a7713b1edbc	2517	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
AnnaBridge	171:3a7713b1edbc	2518	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
AnnaBridge	171:3a7713b1edbc	2519	* @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
AnnaBridge	171:3a7713b1edbc	2520	*
AnnaBridge	171:3a7713b1edbc	2521	* . . ETR_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2522	* @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*)
AnnaBridge	171:3a7713b1edbc	2523	*
AnnaBridge	171:3a7713b1edbc	2524	* . . TI1_RMP_RI can be one of the following values
AnnaBridge	171:3a7713b1edbc	2525	* @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*)
AnnaBridge	171:3a7713b1edbc	2526	*
AnnaBridge	171:3a7713b1edbc	2527	*
AnnaBridge	171:3a7713b1edbc	2528	* TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
AnnaBridge	171:3a7713b1edbc	2529	*
AnnaBridge	171:3a7713b1edbc	2530	* . . TI1_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2531	* @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
AnnaBridge	171:3a7713b1edbc	2532	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
AnnaBridge	171:3a7713b1edbc	2533	* @arg @ref LL_TIM_TIM11_TI1_RMP
AnnaBridge	171:3a7713b1edbc	2534	*
AnnaBridge	171:3a7713b1edbc	2535	* . . ETR_RMP can be one of the following values
AnnaBridge	171:3a7713b1edbc	2536	* @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*)
AnnaBridge	171:3a7713b1edbc	2537	*
AnnaBridge	171:3a7713b1edbc	2538	* . . TI1_RMP_RI can be one of the following values
AnnaBridge	171:3a7713b1edbc	2539	* @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*)
AnnaBridge	171:3a7713b1edbc	2540	*
AnnaBridge	171:3a7713b1edbc	2541	* (*) value not available in all devices categories
AnnaBridge	171:3a7713b1edbc	2542	* (**) register not available in all devices categories
AnnaBridge	171:3a7713b1edbc	2543	*
AnnaBridge	171:3a7713b1edbc	2544	* @note Option registers are available only for cat.3, cat.4 and cat.5 devices
AnnaBridge	171:3a7713b1edbc	2545	* @retval None
AnnaBridge	171:3a7713b1edbc	2546	*/
AnnaBridge	171:3a7713b1edbc	2547	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	2548	{
AnnaBridge	171:3a7713b1edbc	2549	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
AnnaBridge	171:3a7713b1edbc	2550	}
AnnaBridge	171:3a7713b1edbc	2551
AnnaBridge	171:3a7713b1edbc	2552	/**
AnnaBridge	171:3a7713b1edbc	2553	* @}
AnnaBridge	171:3a7713b1edbc	2554	*/
AnnaBridge	171:3a7713b1edbc	2555
AnnaBridge	171:3a7713b1edbc	2556	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
AnnaBridge	171:3a7713b1edbc	2557	* @{
AnnaBridge	171:3a7713b1edbc	2558	*/
AnnaBridge	171:3a7713b1edbc	2559	/**
AnnaBridge	171:3a7713b1edbc	2560	* @brief Set the OCREF clear input source
AnnaBridge	171:3a7713b1edbc	2561	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
AnnaBridge	171:3a7713b1edbc	2562	* @note This function can only be used in Output compare and PWM modes.
AnnaBridge	171:3a7713b1edbc	2563	* @note the ETR signal can be connected to the output of a comparator to be used for current handling
AnnaBridge	171:3a7713b1edbc	2564	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
AnnaBridge	171:3a7713b1edbc	2565	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2566	* @param OCRefClearInputSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2567	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
AnnaBridge	171:3a7713b1edbc	2568	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
AnnaBridge	171:3a7713b1edbc	2569	* @retval None
AnnaBridge	171:3a7713b1edbc	2570	*/
AnnaBridge	171:3a7713b1edbc	2571	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
AnnaBridge	171:3a7713b1edbc	2572	{
AnnaBridge	171:3a7713b1edbc	2573	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
AnnaBridge	171:3a7713b1edbc	2574	}
AnnaBridge	171:3a7713b1edbc	2575	/**
AnnaBridge	171:3a7713b1edbc	2576	* @}
AnnaBridge	171:3a7713b1edbc	2577	*/
AnnaBridge	171:3a7713b1edbc	2578
AnnaBridge	171:3a7713b1edbc	2579	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	171:3a7713b1edbc	2580	* @{
AnnaBridge	171:3a7713b1edbc	2581	*/
AnnaBridge	171:3a7713b1edbc	2582	/**
AnnaBridge	171:3a7713b1edbc	2583	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	171:3a7713b1edbc	2584	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	171:3a7713b1edbc	2585	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2586	* @retval None
AnnaBridge	171:3a7713b1edbc	2587	*/
AnnaBridge	171:3a7713b1edbc	2588	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2589	{
AnnaBridge	171:3a7713b1edbc	2590	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	171:3a7713b1edbc	2591	}
AnnaBridge	171:3a7713b1edbc	2592
AnnaBridge	171:3a7713b1edbc	2593	/**
AnnaBridge	171:3a7713b1edbc	2594	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2595	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	171:3a7713b1edbc	2596	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2597	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2598	*/
AnnaBridge	171:3a7713b1edbc	2599	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2600	{
AnnaBridge	171:3a7713b1edbc	2601	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	171:3a7713b1edbc	2602	}
AnnaBridge	171:3a7713b1edbc	2603
AnnaBridge	171:3a7713b1edbc	2604	/**
AnnaBridge	171:3a7713b1edbc	2605	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	171:3a7713b1edbc	2606	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	171:3a7713b1edbc	2607	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2608	* @retval None
AnnaBridge	171:3a7713b1edbc	2609	*/
AnnaBridge	171:3a7713b1edbc	2610	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2611	{
AnnaBridge	171:3a7713b1edbc	2612	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	171:3a7713b1edbc	2613	}
AnnaBridge	171:3a7713b1edbc	2614
AnnaBridge	171:3a7713b1edbc	2615	/**
AnnaBridge	171:3a7713b1edbc	2616	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2617	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	171:3a7713b1edbc	2618	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2619	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2620	*/
AnnaBridge	171:3a7713b1edbc	2621	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2622	{
AnnaBridge	171:3a7713b1edbc	2623	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	171:3a7713b1edbc	2624	}
AnnaBridge	171:3a7713b1edbc	2625
AnnaBridge	171:3a7713b1edbc	2626	/**
AnnaBridge	171:3a7713b1edbc	2627	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	171:3a7713b1edbc	2628	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	171:3a7713b1edbc	2629	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2630	* @retval None
AnnaBridge	171:3a7713b1edbc	2631	*/
AnnaBridge	171:3a7713b1edbc	2632	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2633	{
AnnaBridge	171:3a7713b1edbc	2634	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	171:3a7713b1edbc	2635	}
AnnaBridge	171:3a7713b1edbc	2636
AnnaBridge	171:3a7713b1edbc	2637	/**
AnnaBridge	171:3a7713b1edbc	2638	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2639	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	171:3a7713b1edbc	2640	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2641	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2642	*/
AnnaBridge	171:3a7713b1edbc	2643	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2644	{
AnnaBridge	171:3a7713b1edbc	2645	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	171:3a7713b1edbc	2646	}
AnnaBridge	171:3a7713b1edbc	2647
AnnaBridge	171:3a7713b1edbc	2648	/**
AnnaBridge	171:3a7713b1edbc	2649	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	171:3a7713b1edbc	2650	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	171:3a7713b1edbc	2651	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2652	* @retval None
AnnaBridge	171:3a7713b1edbc	2653	*/
AnnaBridge	171:3a7713b1edbc	2654	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2655	{
AnnaBridge	171:3a7713b1edbc	2656	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	171:3a7713b1edbc	2657	}
AnnaBridge	171:3a7713b1edbc	2658
AnnaBridge	171:3a7713b1edbc	2659	/**
AnnaBridge	171:3a7713b1edbc	2660	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2661	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	171:3a7713b1edbc	2662	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2663	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2664	*/
AnnaBridge	171:3a7713b1edbc	2665	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2666	{
AnnaBridge	171:3a7713b1edbc	2667	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	171:3a7713b1edbc	2668	}
AnnaBridge	171:3a7713b1edbc	2669
AnnaBridge	171:3a7713b1edbc	2670	/**
AnnaBridge	171:3a7713b1edbc	2671	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	171:3a7713b1edbc	2672	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	171:3a7713b1edbc	2673	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2674	* @retval None
AnnaBridge	171:3a7713b1edbc	2675	*/
AnnaBridge	171:3a7713b1edbc	2676	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2677	{
AnnaBridge	171:3a7713b1edbc	2678	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	171:3a7713b1edbc	2679	}
AnnaBridge	171:3a7713b1edbc	2680
AnnaBridge	171:3a7713b1edbc	2681	/**
AnnaBridge	171:3a7713b1edbc	2682	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2683	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	171:3a7713b1edbc	2684	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2685	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2686	*/
AnnaBridge	171:3a7713b1edbc	2687	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2688	{
AnnaBridge	171:3a7713b1edbc	2689	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	171:3a7713b1edbc	2690	}
AnnaBridge	171:3a7713b1edbc	2691
AnnaBridge	171:3a7713b1edbc	2692	/**
AnnaBridge	171:3a7713b1edbc	2693	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	171:3a7713b1edbc	2694	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	171:3a7713b1edbc	2695	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2696	* @retval None
AnnaBridge	171:3a7713b1edbc	2697	*/
AnnaBridge	171:3a7713b1edbc	2698	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2699	{
AnnaBridge	171:3a7713b1edbc	2700	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	171:3a7713b1edbc	2701	}
AnnaBridge	171:3a7713b1edbc	2702
AnnaBridge	171:3a7713b1edbc	2703	/**
AnnaBridge	171:3a7713b1edbc	2704	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2705	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	171:3a7713b1edbc	2706	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2707	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2708	*/
AnnaBridge	171:3a7713b1edbc	2709	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2710	{
AnnaBridge	171:3a7713b1edbc	2711	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	171:3a7713b1edbc	2712	}
AnnaBridge	171:3a7713b1edbc	2713
AnnaBridge	171:3a7713b1edbc	2714	/**
AnnaBridge	171:3a7713b1edbc	2715	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	171:3a7713b1edbc	2716	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	171:3a7713b1edbc	2717	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2718	* @retval None
AnnaBridge	171:3a7713b1edbc	2719	*/
AnnaBridge	171:3a7713b1edbc	2720	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2721	{
AnnaBridge	171:3a7713b1edbc	2722	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	171:3a7713b1edbc	2723	}
AnnaBridge	171:3a7713b1edbc	2724
AnnaBridge	171:3a7713b1edbc	2725	/**
AnnaBridge	171:3a7713b1edbc	2726	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2727	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	171:3a7713b1edbc	2728	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2729	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2730	*/
AnnaBridge	171:3a7713b1edbc	2731	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2732	{
AnnaBridge	171:3a7713b1edbc	2733	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	171:3a7713b1edbc	2734	}
AnnaBridge	171:3a7713b1edbc	2735
AnnaBridge	171:3a7713b1edbc	2736	/**
AnnaBridge	171:3a7713b1edbc	2737	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	171:3a7713b1edbc	2738	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	171:3a7713b1edbc	2739	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2740	* @retval None
AnnaBridge	171:3a7713b1edbc	2741	*/
AnnaBridge	171:3a7713b1edbc	2742	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2743	{
AnnaBridge	171:3a7713b1edbc	2744	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	171:3a7713b1edbc	2745	}
AnnaBridge	171:3a7713b1edbc	2746
AnnaBridge	171:3a7713b1edbc	2747	/**
AnnaBridge	171:3a7713b1edbc	2748	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2749	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	171:3a7713b1edbc	2750	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2751	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2752	*/
AnnaBridge	171:3a7713b1edbc	2753	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2754	{
AnnaBridge	171:3a7713b1edbc	2755	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	171:3a7713b1edbc	2756	}
AnnaBridge	171:3a7713b1edbc	2757
AnnaBridge	171:3a7713b1edbc	2758	/**
AnnaBridge	171:3a7713b1edbc	2759	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	171:3a7713b1edbc	2760	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	171:3a7713b1edbc	2761	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2762	* @retval None
AnnaBridge	171:3a7713b1edbc	2763	*/
AnnaBridge	171:3a7713b1edbc	2764	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2765	{
AnnaBridge	171:3a7713b1edbc	2766	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	171:3a7713b1edbc	2767	}
AnnaBridge	171:3a7713b1edbc	2768
AnnaBridge	171:3a7713b1edbc	2769	/**
AnnaBridge	171:3a7713b1edbc	2770	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2771	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	171:3a7713b1edbc	2772	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2773	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2774	*/
AnnaBridge	171:3a7713b1edbc	2775	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2776	{
AnnaBridge	171:3a7713b1edbc	2777	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	171:3a7713b1edbc	2778	}
AnnaBridge	171:3a7713b1edbc	2779
AnnaBridge	171:3a7713b1edbc	2780	/**
AnnaBridge	171:3a7713b1edbc	2781	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	171:3a7713b1edbc	2782	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	171:3a7713b1edbc	2783	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2784	* @retval None
AnnaBridge	171:3a7713b1edbc	2785	*/
AnnaBridge	171:3a7713b1edbc	2786	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2787	{
AnnaBridge	171:3a7713b1edbc	2788	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	171:3a7713b1edbc	2789	}
AnnaBridge	171:3a7713b1edbc	2790
AnnaBridge	171:3a7713b1edbc	2791	/**
AnnaBridge	171:3a7713b1edbc	2792	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	171:3a7713b1edbc	2793	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	171:3a7713b1edbc	2794	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2795	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2796	*/
AnnaBridge	171:3a7713b1edbc	2797	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2798	{
AnnaBridge	171:3a7713b1edbc	2799	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	171:3a7713b1edbc	2800	}
AnnaBridge	171:3a7713b1edbc	2801
AnnaBridge	171:3a7713b1edbc	2802	/**
AnnaBridge	171:3a7713b1edbc	2803	* @}
AnnaBridge	171:3a7713b1edbc	2804	*/
AnnaBridge	171:3a7713b1edbc	2805
AnnaBridge	171:3a7713b1edbc	2806	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	171:3a7713b1edbc	2807	* @{
AnnaBridge	171:3a7713b1edbc	2808	*/
AnnaBridge	171:3a7713b1edbc	2809	/**
AnnaBridge	171:3a7713b1edbc	2810	* @brief Enable update interrupt (UIE).
AnnaBridge	171:3a7713b1edbc	2811	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	171:3a7713b1edbc	2812	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2813	* @retval None
AnnaBridge	171:3a7713b1edbc	2814	*/
AnnaBridge	171:3a7713b1edbc	2815	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2816	{
AnnaBridge	171:3a7713b1edbc	2817	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	171:3a7713b1edbc	2818	}
AnnaBridge	171:3a7713b1edbc	2819
AnnaBridge	171:3a7713b1edbc	2820	/**
AnnaBridge	171:3a7713b1edbc	2821	* @brief Disable update interrupt (UIE).
AnnaBridge	171:3a7713b1edbc	2822	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	171:3a7713b1edbc	2823	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2824	* @retval None
AnnaBridge	171:3a7713b1edbc	2825	*/
AnnaBridge	171:3a7713b1edbc	2826	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2827	{
AnnaBridge	171:3a7713b1edbc	2828	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	171:3a7713b1edbc	2829	}
AnnaBridge	171:3a7713b1edbc	2830
AnnaBridge	171:3a7713b1edbc	2831	/**
AnnaBridge	171:3a7713b1edbc	2832	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	171:3a7713b1edbc	2833	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	171:3a7713b1edbc	2834	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2835	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2836	*/
AnnaBridge	171:3a7713b1edbc	2837	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2838	{
AnnaBridge	171:3a7713b1edbc	2839	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	171:3a7713b1edbc	2840	}
AnnaBridge	171:3a7713b1edbc	2841
AnnaBridge	171:3a7713b1edbc	2842	/**
AnnaBridge	171:3a7713b1edbc	2843	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	171:3a7713b1edbc	2844	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	171:3a7713b1edbc	2845	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2846	* @retval None
AnnaBridge	171:3a7713b1edbc	2847	*/
AnnaBridge	171:3a7713b1edbc	2848	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2849	{
AnnaBridge	171:3a7713b1edbc	2850	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	171:3a7713b1edbc	2851	}
AnnaBridge	171:3a7713b1edbc	2852
AnnaBridge	171:3a7713b1edbc	2853	/**
AnnaBridge	171:3a7713b1edbc	2854	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	171:3a7713b1edbc	2855	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	171:3a7713b1edbc	2856	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2857	* @retval None
AnnaBridge	171:3a7713b1edbc	2858	*/
AnnaBridge	171:3a7713b1edbc	2859	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2860	{
AnnaBridge	171:3a7713b1edbc	2861	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	171:3a7713b1edbc	2862	}
AnnaBridge	171:3a7713b1edbc	2863
AnnaBridge	171:3a7713b1edbc	2864	/**
AnnaBridge	171:3a7713b1edbc	2865	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	171:3a7713b1edbc	2866	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	171:3a7713b1edbc	2867	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2868	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2869	*/
AnnaBridge	171:3a7713b1edbc	2870	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2871	{
AnnaBridge	171:3a7713b1edbc	2872	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	171:3a7713b1edbc	2873	}
AnnaBridge	171:3a7713b1edbc	2874
AnnaBridge	171:3a7713b1edbc	2875	/**
AnnaBridge	171:3a7713b1edbc	2876	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	171:3a7713b1edbc	2877	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	171:3a7713b1edbc	2878	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2879	* @retval None
AnnaBridge	171:3a7713b1edbc	2880	*/
AnnaBridge	171:3a7713b1edbc	2881	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2882	{
AnnaBridge	171:3a7713b1edbc	2883	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	171:3a7713b1edbc	2884	}
AnnaBridge	171:3a7713b1edbc	2885
AnnaBridge	171:3a7713b1edbc	2886	/**
AnnaBridge	171:3a7713b1edbc	2887	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	171:3a7713b1edbc	2888	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	171:3a7713b1edbc	2889	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2890	* @retval None
AnnaBridge	171:3a7713b1edbc	2891	*/
AnnaBridge	171:3a7713b1edbc	2892	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2893	{
AnnaBridge	171:3a7713b1edbc	2894	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	171:3a7713b1edbc	2895	}
AnnaBridge	171:3a7713b1edbc	2896
AnnaBridge	171:3a7713b1edbc	2897	/**
AnnaBridge	171:3a7713b1edbc	2898	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	171:3a7713b1edbc	2899	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	171:3a7713b1edbc	2900	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2901	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2902	*/
AnnaBridge	171:3a7713b1edbc	2903	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2904	{
AnnaBridge	171:3a7713b1edbc	2905	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	171:3a7713b1edbc	2906	}
AnnaBridge	171:3a7713b1edbc	2907
AnnaBridge	171:3a7713b1edbc	2908	/**
AnnaBridge	171:3a7713b1edbc	2909	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	171:3a7713b1edbc	2910	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	171:3a7713b1edbc	2911	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2912	* @retval None
AnnaBridge	171:3a7713b1edbc	2913	*/
AnnaBridge	171:3a7713b1edbc	2914	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2915	{
AnnaBridge	171:3a7713b1edbc	2916	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	171:3a7713b1edbc	2917	}
AnnaBridge	171:3a7713b1edbc	2918
AnnaBridge	171:3a7713b1edbc	2919	/**
AnnaBridge	171:3a7713b1edbc	2920	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	171:3a7713b1edbc	2921	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	171:3a7713b1edbc	2922	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2923	* @retval None
AnnaBridge	171:3a7713b1edbc	2924	*/
AnnaBridge	171:3a7713b1edbc	2925	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2926	{
AnnaBridge	171:3a7713b1edbc	2927	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	171:3a7713b1edbc	2928	}
AnnaBridge	171:3a7713b1edbc	2929
AnnaBridge	171:3a7713b1edbc	2930	/**
AnnaBridge	171:3a7713b1edbc	2931	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	171:3a7713b1edbc	2932	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	171:3a7713b1edbc	2933	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2934	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2935	*/
AnnaBridge	171:3a7713b1edbc	2936	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2937	{
AnnaBridge	171:3a7713b1edbc	2938	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	171:3a7713b1edbc	2939	}
AnnaBridge	171:3a7713b1edbc	2940
AnnaBridge	171:3a7713b1edbc	2941	/**
AnnaBridge	171:3a7713b1edbc	2942	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	171:3a7713b1edbc	2943	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	171:3a7713b1edbc	2944	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2945	* @retval None
AnnaBridge	171:3a7713b1edbc	2946	*/
AnnaBridge	171:3a7713b1edbc	2947	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2948	{
AnnaBridge	171:3a7713b1edbc	2949	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	171:3a7713b1edbc	2950	}
AnnaBridge	171:3a7713b1edbc	2951
AnnaBridge	171:3a7713b1edbc	2952	/**
AnnaBridge	171:3a7713b1edbc	2953	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	171:3a7713b1edbc	2954	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	171:3a7713b1edbc	2955	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2956	* @retval None
AnnaBridge	171:3a7713b1edbc	2957	*/
AnnaBridge	171:3a7713b1edbc	2958	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2959	{
AnnaBridge	171:3a7713b1edbc	2960	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	171:3a7713b1edbc	2961	}
AnnaBridge	171:3a7713b1edbc	2962
AnnaBridge	171:3a7713b1edbc	2963	/**
AnnaBridge	171:3a7713b1edbc	2964	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	171:3a7713b1edbc	2965	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	171:3a7713b1edbc	2966	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2967	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2968	*/
AnnaBridge	171:3a7713b1edbc	2969	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2970	{
AnnaBridge	171:3a7713b1edbc	2971	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	171:3a7713b1edbc	2972	}
AnnaBridge	171:3a7713b1edbc	2973
AnnaBridge	171:3a7713b1edbc	2974	/**
AnnaBridge	171:3a7713b1edbc	2975	* @brief Enable trigger interrupt (TIE).
AnnaBridge	171:3a7713b1edbc	2976	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	171:3a7713b1edbc	2977	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2978	* @retval None
AnnaBridge	171:3a7713b1edbc	2979	*/
AnnaBridge	171:3a7713b1edbc	2980	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2981	{
AnnaBridge	171:3a7713b1edbc	2982	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	171:3a7713b1edbc	2983	}
AnnaBridge	171:3a7713b1edbc	2984
AnnaBridge	171:3a7713b1edbc	2985	/**
AnnaBridge	171:3a7713b1edbc	2986	* @brief Disable trigger interrupt (TIE).
AnnaBridge	171:3a7713b1edbc	2987	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	171:3a7713b1edbc	2988	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2989	* @retval None
AnnaBridge	171:3a7713b1edbc	2990	*/
AnnaBridge	171:3a7713b1edbc	2991	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2992	{
AnnaBridge	171:3a7713b1edbc	2993	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	171:3a7713b1edbc	2994	}
AnnaBridge	171:3a7713b1edbc	2995
AnnaBridge	171:3a7713b1edbc	2996	/**
AnnaBridge	171:3a7713b1edbc	2997	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	171:3a7713b1edbc	2998	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	171:3a7713b1edbc	2999	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3000	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3001	*/
AnnaBridge	171:3a7713b1edbc	3002	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3003	{
AnnaBridge	171:3a7713b1edbc	3004	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	171:3a7713b1edbc	3005	}
AnnaBridge	171:3a7713b1edbc	3006
AnnaBridge	171:3a7713b1edbc	3007	/**
AnnaBridge	171:3a7713b1edbc	3008	* @}
AnnaBridge	171:3a7713b1edbc	3009	*/
AnnaBridge	171:3a7713b1edbc	3010
AnnaBridge	171:3a7713b1edbc	3011	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	171:3a7713b1edbc	3012	* @{
AnnaBridge	171:3a7713b1edbc	3013	*/
AnnaBridge	171:3a7713b1edbc	3014	/**
AnnaBridge	171:3a7713b1edbc	3015	* @brief Enable update DMA request (UDE).
AnnaBridge	171:3a7713b1edbc	3016	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	171:3a7713b1edbc	3017	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3018	* @retval None
AnnaBridge	171:3a7713b1edbc	3019	*/
AnnaBridge	171:3a7713b1edbc	3020	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3021	{
AnnaBridge	171:3a7713b1edbc	3022	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	171:3a7713b1edbc	3023	}
AnnaBridge	171:3a7713b1edbc	3024
AnnaBridge	171:3a7713b1edbc	3025	/**
AnnaBridge	171:3a7713b1edbc	3026	* @brief Disable update DMA request (UDE).
AnnaBridge	171:3a7713b1edbc	3027	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	171:3a7713b1edbc	3028	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3029	* @retval None
AnnaBridge	171:3a7713b1edbc	3030	*/
AnnaBridge	171:3a7713b1edbc	3031	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3032	{
AnnaBridge	171:3a7713b1edbc	3033	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	171:3a7713b1edbc	3034	}
AnnaBridge	171:3a7713b1edbc	3035
AnnaBridge	171:3a7713b1edbc	3036	/**
AnnaBridge	171:3a7713b1edbc	3037	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	171:3a7713b1edbc	3038	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	171:3a7713b1edbc	3039	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3040	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3041	*/
AnnaBridge	171:3a7713b1edbc	3042	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3043	{
AnnaBridge	171:3a7713b1edbc	3044	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	171:3a7713b1edbc	3045	}
AnnaBridge	171:3a7713b1edbc	3046
AnnaBridge	171:3a7713b1edbc	3047	/**
AnnaBridge	171:3a7713b1edbc	3048	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	171:3a7713b1edbc	3049	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	171:3a7713b1edbc	3050	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3051	* @retval None
AnnaBridge	171:3a7713b1edbc	3052	*/
AnnaBridge	171:3a7713b1edbc	3053	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3054	{
AnnaBridge	171:3a7713b1edbc	3055	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	171:3a7713b1edbc	3056	}
AnnaBridge	171:3a7713b1edbc	3057
AnnaBridge	171:3a7713b1edbc	3058	/**
AnnaBridge	171:3a7713b1edbc	3059	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	171:3a7713b1edbc	3060	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	171:3a7713b1edbc	3061	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3062	* @retval None
AnnaBridge	171:3a7713b1edbc	3063	*/
AnnaBridge	171:3a7713b1edbc	3064	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3065	{
AnnaBridge	171:3a7713b1edbc	3066	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	171:3a7713b1edbc	3067	}
AnnaBridge	171:3a7713b1edbc	3068
AnnaBridge	171:3a7713b1edbc	3069	/**
AnnaBridge	171:3a7713b1edbc	3070	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3071	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	171:3a7713b1edbc	3072	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3073	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3074	*/
AnnaBridge	171:3a7713b1edbc	3075	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3076	{
AnnaBridge	171:3a7713b1edbc	3077	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	171:3a7713b1edbc	3078	}
AnnaBridge	171:3a7713b1edbc	3079
AnnaBridge	171:3a7713b1edbc	3080	/**
AnnaBridge	171:3a7713b1edbc	3081	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	171:3a7713b1edbc	3082	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	171:3a7713b1edbc	3083	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3084	* @retval None
AnnaBridge	171:3a7713b1edbc	3085	*/
AnnaBridge	171:3a7713b1edbc	3086	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3087	{
AnnaBridge	171:3a7713b1edbc	3088	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	171:3a7713b1edbc	3089	}
AnnaBridge	171:3a7713b1edbc	3090
AnnaBridge	171:3a7713b1edbc	3091	/**
AnnaBridge	171:3a7713b1edbc	3092	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	171:3a7713b1edbc	3093	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	171:3a7713b1edbc	3094	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3095	* @retval None
AnnaBridge	171:3a7713b1edbc	3096	*/
AnnaBridge	171:3a7713b1edbc	3097	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3098	{
AnnaBridge	171:3a7713b1edbc	3099	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	171:3a7713b1edbc	3100	}
AnnaBridge	171:3a7713b1edbc	3101
AnnaBridge	171:3a7713b1edbc	3102	/**
AnnaBridge	171:3a7713b1edbc	3103	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3104	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	171:3a7713b1edbc	3105	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3106	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3107	*/
AnnaBridge	171:3a7713b1edbc	3108	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3109	{
AnnaBridge	171:3a7713b1edbc	3110	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	171:3a7713b1edbc	3111	}
AnnaBridge	171:3a7713b1edbc	3112
AnnaBridge	171:3a7713b1edbc	3113	/**
AnnaBridge	171:3a7713b1edbc	3114	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	171:3a7713b1edbc	3115	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	171:3a7713b1edbc	3116	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3117	* @retval None
AnnaBridge	171:3a7713b1edbc	3118	*/
AnnaBridge	171:3a7713b1edbc	3119	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3120	{
AnnaBridge	171:3a7713b1edbc	3121	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	171:3a7713b1edbc	3122	}
AnnaBridge	171:3a7713b1edbc	3123
AnnaBridge	171:3a7713b1edbc	3124	/**
AnnaBridge	171:3a7713b1edbc	3125	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	171:3a7713b1edbc	3126	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	171:3a7713b1edbc	3127	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3128	* @retval None
AnnaBridge	171:3a7713b1edbc	3129	*/
AnnaBridge	171:3a7713b1edbc	3130	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3131	{
AnnaBridge	171:3a7713b1edbc	3132	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	171:3a7713b1edbc	3133	}
AnnaBridge	171:3a7713b1edbc	3134
AnnaBridge	171:3a7713b1edbc	3135	/**
AnnaBridge	171:3a7713b1edbc	3136	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3137	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	171:3a7713b1edbc	3138	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3139	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3140	*/
AnnaBridge	171:3a7713b1edbc	3141	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3142	{
AnnaBridge	171:3a7713b1edbc	3143	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	171:3a7713b1edbc	3144	}
AnnaBridge	171:3a7713b1edbc	3145
AnnaBridge	171:3a7713b1edbc	3146	/**
AnnaBridge	171:3a7713b1edbc	3147	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	171:3a7713b1edbc	3148	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	171:3a7713b1edbc	3149	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3150	* @retval None
AnnaBridge	171:3a7713b1edbc	3151	*/
AnnaBridge	171:3a7713b1edbc	3152	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3153	{
AnnaBridge	171:3a7713b1edbc	3154	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	171:3a7713b1edbc	3155	}
AnnaBridge	171:3a7713b1edbc	3156
AnnaBridge	171:3a7713b1edbc	3157	/**
AnnaBridge	171:3a7713b1edbc	3158	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	171:3a7713b1edbc	3159	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	171:3a7713b1edbc	3160	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3161	* @retval None
AnnaBridge	171:3a7713b1edbc	3162	*/
AnnaBridge	171:3a7713b1edbc	3163	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3164	{
AnnaBridge	171:3a7713b1edbc	3165	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	171:3a7713b1edbc	3166	}
AnnaBridge	171:3a7713b1edbc	3167
AnnaBridge	171:3a7713b1edbc	3168	/**
AnnaBridge	171:3a7713b1edbc	3169	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3170	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	171:3a7713b1edbc	3171	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3172	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3173	*/
AnnaBridge	171:3a7713b1edbc	3174	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3175	{
AnnaBridge	171:3a7713b1edbc	3176	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	171:3a7713b1edbc	3177	}
AnnaBridge	171:3a7713b1edbc	3178
AnnaBridge	171:3a7713b1edbc	3179	/**
AnnaBridge	171:3a7713b1edbc	3180	* @brief Enable trigger interrupt (TDE).
AnnaBridge	171:3a7713b1edbc	3181	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	171:3a7713b1edbc	3182	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3183	* @retval None
AnnaBridge	171:3a7713b1edbc	3184	*/
AnnaBridge	171:3a7713b1edbc	3185	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3186	{
AnnaBridge	171:3a7713b1edbc	3187	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	171:3a7713b1edbc	3188	}
AnnaBridge	171:3a7713b1edbc	3189
AnnaBridge	171:3a7713b1edbc	3190	/**
AnnaBridge	171:3a7713b1edbc	3191	* @brief Disable trigger interrupt (TDE).
AnnaBridge	171:3a7713b1edbc	3192	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	171:3a7713b1edbc	3193	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3194	* @retval None
AnnaBridge	171:3a7713b1edbc	3195	*/
AnnaBridge	171:3a7713b1edbc	3196	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3197	{
AnnaBridge	171:3a7713b1edbc	3198	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	171:3a7713b1edbc	3199	}
AnnaBridge	171:3a7713b1edbc	3200
AnnaBridge	171:3a7713b1edbc	3201	/**
AnnaBridge	171:3a7713b1edbc	3202	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	171:3a7713b1edbc	3203	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	171:3a7713b1edbc	3204	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3205	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3206	*/
AnnaBridge	171:3a7713b1edbc	3207	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3208	{
AnnaBridge	171:3a7713b1edbc	3209	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	171:3a7713b1edbc	3210	}
AnnaBridge	171:3a7713b1edbc	3211
AnnaBridge	171:3a7713b1edbc	3212	/**
AnnaBridge	171:3a7713b1edbc	3213	* @}
AnnaBridge	171:3a7713b1edbc	3214	*/
AnnaBridge	171:3a7713b1edbc	3215
AnnaBridge	171:3a7713b1edbc	3216	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	171:3a7713b1edbc	3217	* @{
AnnaBridge	171:3a7713b1edbc	3218	*/
AnnaBridge	171:3a7713b1edbc	3219	/**
AnnaBridge	171:3a7713b1edbc	3220	* @brief Generate an update event.
AnnaBridge	171:3a7713b1edbc	3221	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	171:3a7713b1edbc	3222	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3223	* @retval None
AnnaBridge	171:3a7713b1edbc	3224	*/
AnnaBridge	171:3a7713b1edbc	3225	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3226	{
AnnaBridge	171:3a7713b1edbc	3227	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	171:3a7713b1edbc	3228	}
AnnaBridge	171:3a7713b1edbc	3229
AnnaBridge	171:3a7713b1edbc	3230	/**
AnnaBridge	171:3a7713b1edbc	3231	* @brief Generate Capture/Compare 1 event.
AnnaBridge	171:3a7713b1edbc	3232	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	171:3a7713b1edbc	3233	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3234	* @retval None
AnnaBridge	171:3a7713b1edbc	3235	*/
AnnaBridge	171:3a7713b1edbc	3236	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3237	{
AnnaBridge	171:3a7713b1edbc	3238	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	171:3a7713b1edbc	3239	}
AnnaBridge	171:3a7713b1edbc	3240
AnnaBridge	171:3a7713b1edbc	3241	/**
AnnaBridge	171:3a7713b1edbc	3242	* @brief Generate Capture/Compare 2 event.
AnnaBridge	171:3a7713b1edbc	3243	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	171:3a7713b1edbc	3244	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3245	* @retval None
AnnaBridge	171:3a7713b1edbc	3246	*/
AnnaBridge	171:3a7713b1edbc	3247	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3248	{
AnnaBridge	171:3a7713b1edbc	3249	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	171:3a7713b1edbc	3250	}
AnnaBridge	171:3a7713b1edbc	3251
AnnaBridge	171:3a7713b1edbc	3252	/**
AnnaBridge	171:3a7713b1edbc	3253	* @brief Generate Capture/Compare 3 event.
AnnaBridge	171:3a7713b1edbc	3254	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	171:3a7713b1edbc	3255	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3256	* @retval None
AnnaBridge	171:3a7713b1edbc	3257	*/
AnnaBridge	171:3a7713b1edbc	3258	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3259	{
AnnaBridge	171:3a7713b1edbc	3260	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	171:3a7713b1edbc	3261	}
AnnaBridge	171:3a7713b1edbc	3262
AnnaBridge	171:3a7713b1edbc	3263	/**
AnnaBridge	171:3a7713b1edbc	3264	* @brief Generate Capture/Compare 4 event.
AnnaBridge	171:3a7713b1edbc	3265	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	171:3a7713b1edbc	3266	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3267	* @retval None
AnnaBridge	171:3a7713b1edbc	3268	*/
AnnaBridge	171:3a7713b1edbc	3269	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3270	{
AnnaBridge	171:3a7713b1edbc	3271	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	171:3a7713b1edbc	3272	}
AnnaBridge	171:3a7713b1edbc	3273
AnnaBridge	171:3a7713b1edbc	3274	/**
AnnaBridge	171:3a7713b1edbc	3275	* @brief Generate trigger event.
AnnaBridge	171:3a7713b1edbc	3276	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	171:3a7713b1edbc	3277	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3278	* @retval None
AnnaBridge	171:3a7713b1edbc	3279	*/
AnnaBridge	171:3a7713b1edbc	3280	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3281	{
AnnaBridge	171:3a7713b1edbc	3282	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	171:3a7713b1edbc	3283	}
AnnaBridge	171:3a7713b1edbc	3284
AnnaBridge	171:3a7713b1edbc	3285	/**
AnnaBridge	171:3a7713b1edbc	3286	* @}
AnnaBridge	171:3a7713b1edbc	3287	*/
AnnaBridge	171:3a7713b1edbc	3288
AnnaBridge	171:3a7713b1edbc	3289	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	3290	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	171:3a7713b1edbc	3291	* @{
AnnaBridge	171:3a7713b1edbc	3292	*/
AnnaBridge	171:3a7713b1edbc	3293
AnnaBridge	171:3a7713b1edbc	3294	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	171:3a7713b1edbc	3295	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	171:3a7713b1edbc	3296	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	171:3a7713b1edbc	3297	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	171:3a7713b1edbc	3298	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	171:3a7713b1edbc	3299	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	171:3a7713b1edbc	3300	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	171:3a7713b1edbc	3301	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	171:3a7713b1edbc	3302	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	171:3a7713b1edbc	3303	/**
AnnaBridge	171:3a7713b1edbc	3304	* @}
AnnaBridge	171:3a7713b1edbc	3305	*/
AnnaBridge	171:3a7713b1edbc	3306	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	3307
AnnaBridge	171:3a7713b1edbc	3308	/**
AnnaBridge	171:3a7713b1edbc	3309	* @}
AnnaBridge	171:3a7713b1edbc	3310	*/
AnnaBridge	171:3a7713b1edbc	3311
AnnaBridge	171:3a7713b1edbc	3312	/**
AnnaBridge	171:3a7713b1edbc	3313	* @}
AnnaBridge	171:3a7713b1edbc	3314	*/
AnnaBridge	171:3a7713b1edbc	3315
AnnaBridge	171:3a7713b1edbc	3316	#endif /* TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM9 \|\| TIM10 \|\| TIM11 TIM6 \|\| TIM7 */
AnnaBridge	171:3a7713b1edbc	3317
AnnaBridge	171:3a7713b1edbc	3318	/**
AnnaBridge	171:3a7713b1edbc	3319	* @}
AnnaBridge	171:3a7713b1edbc	3320	*/
AnnaBridge	171:3a7713b1edbc	3321
AnnaBridge	171:3a7713b1edbc	3322	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	3323	}
AnnaBridge	171:3a7713b1edbc	3324	#endif
AnnaBridge	171:3a7713b1edbc	3325
AnnaBridge	171:3a7713b1edbc	3326	#endif /* __STM32L1xx_LL_TIM_H */
AnnaBridge	171:3a7713b1edbc	3327	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/