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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_hal_lcd.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l1xx_hal_lcd.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of LCD Controller HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32L1xx_HAL_LCD_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32L1xx_HAL_LCD_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 45 * @{
AnnaBridge 171:3a7713b1edbc 46 */
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
AnnaBridge 171:3a7713b1edbc 49 defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
AnnaBridge 171:3a7713b1edbc 50 defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 53 #include "stm32l1xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /** @addtogroup LCD
AnnaBridge 171:3a7713b1edbc 56 * @{
AnnaBridge 171:3a7713b1edbc 57 */
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /** @defgroup LCD_Exported_Types LCD Exported Types
AnnaBridge 171:3a7713b1edbc 62 * @{
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /**
AnnaBridge 171:3a7713b1edbc 66 * @brief LCD Init structure definition
AnnaBridge 171:3a7713b1edbc 67 */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 typedef struct
AnnaBridge 171:3a7713b1edbc 70 {
AnnaBridge 171:3a7713b1edbc 71 uint32_t Prescaler; /*!< Configures the LCD Prescaler.
AnnaBridge 171:3a7713b1edbc 72 This parameter can be one value of @ref LCD_Prescaler */
AnnaBridge 171:3a7713b1edbc 73 uint32_t Divider; /*!< Configures the LCD Divider.
AnnaBridge 171:3a7713b1edbc 74 This parameter can be one value of @ref LCD_Divider */
AnnaBridge 171:3a7713b1edbc 75 uint32_t Duty; /*!< Configures the LCD Duty.
AnnaBridge 171:3a7713b1edbc 76 This parameter can be one value of @ref LCD_Duty */
AnnaBridge 171:3a7713b1edbc 77 uint32_t Bias; /*!< Configures the LCD Bias.
AnnaBridge 171:3a7713b1edbc 78 This parameter can be one value of @ref LCD_Bias */
AnnaBridge 171:3a7713b1edbc 79 uint32_t VoltageSource; /*!< Selects the LCD Voltage source.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be one value of @ref LCD_Voltage_Source */
AnnaBridge 171:3a7713b1edbc 81 uint32_t Contrast; /*!< Configures the LCD Contrast.
AnnaBridge 171:3a7713b1edbc 82 This parameter can be one value of @ref LCD_Contrast */
AnnaBridge 171:3a7713b1edbc 83 uint32_t DeadTime; /*!< Configures the LCD Dead Time.
AnnaBridge 171:3a7713b1edbc 84 This parameter can be one value of @ref LCD_DeadTime */
AnnaBridge 171:3a7713b1edbc 85 uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
AnnaBridge 171:3a7713b1edbc 86 This parameter can be one value of @ref LCD_PulseOnDuration */
AnnaBridge 171:3a7713b1edbc 87 uint32_t HighDrive; /*!< Configures the LCD High Drive.
AnnaBridge 171:3a7713b1edbc 88 This parameter can be one value of @ref LCD_HighDrive */
AnnaBridge 171:3a7713b1edbc 89 uint32_t BlinkMode; /*!< Configures the LCD Blink Mode.
AnnaBridge 171:3a7713b1edbc 90 This parameter can be one value of @ref LCD_BlinkMode */
AnnaBridge 171:3a7713b1edbc 91 uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency.
AnnaBridge 171:3a7713b1edbc 92 This parameter can be one value of @ref LCD_BlinkFrequency */
AnnaBridge 171:3a7713b1edbc 93 uint32_t MuxSegment; /*!< Enable or disable mux segment.
AnnaBridge 171:3a7713b1edbc 94 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 95 }LCD_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /**
AnnaBridge 171:3a7713b1edbc 98 * @brief HAL LCD State structures definition
AnnaBridge 171:3a7713b1edbc 99 */
AnnaBridge 171:3a7713b1edbc 100 typedef enum
AnnaBridge 171:3a7713b1edbc 101 {
AnnaBridge 171:3a7713b1edbc 102 HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
AnnaBridge 171:3a7713b1edbc 103 HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 104 HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
AnnaBridge 171:3a7713b1edbc 105 HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
AnnaBridge 171:3a7713b1edbc 106 HAL_LCD_STATE_ERROR = 0x04 /*!< Error */
AnnaBridge 171:3a7713b1edbc 107 }HAL_LCD_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 /**
AnnaBridge 171:3a7713b1edbc 110 * @brief UART handle Structure definition
AnnaBridge 171:3a7713b1edbc 111 */
AnnaBridge 171:3a7713b1edbc 112 typedef struct
AnnaBridge 171:3a7713b1edbc 113 {
AnnaBridge 171:3a7713b1edbc 114 LCD_TypeDef *Instance; /* LCD registers base address */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 LCD_InitTypeDef Init; /* LCD communication parameters */
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 __IO HAL_LCD_StateTypeDef State; /* LCD communication state */
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 __IO uint32_t ErrorCode; /* LCD Error code */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 }LCD_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /**
AnnaBridge 171:3a7713b1edbc 127 * @}
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 /** @defgroup LCD_Exported_Constants LCD Exported Constants
AnnaBridge 171:3a7713b1edbc 133 * @{
AnnaBridge 171:3a7713b1edbc 134 */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /** @defgroup LCD_Error_Codes LCD Error Codes
AnnaBridge 171:3a7713b1edbc 137 * @{
AnnaBridge 171:3a7713b1edbc 138 */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #define HAL_LCD_ERROR_NONE (0x00U) /*!< No error */
AnnaBridge 171:3a7713b1edbc 141 #define HAL_LCD_ERROR_FCRSF (0x01U) /*!< Synchro flag timeout error */
AnnaBridge 171:3a7713b1edbc 142 #define HAL_LCD_ERROR_UDR (0x02U) /*!< Update display request flag timeout error */
AnnaBridge 171:3a7713b1edbc 143 #define HAL_LCD_ERROR_UDD (0x04U) /*!< Update display done flag timeout error */
AnnaBridge 171:3a7713b1edbc 144 #define HAL_LCD_ERROR_ENS (0x08U) /*!< LCD enabled status flag timeout error */
AnnaBridge 171:3a7713b1edbc 145 #define HAL_LCD_ERROR_RDY (0x10U) /*!< LCD Booster ready timeout error */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 /**
AnnaBridge 171:3a7713b1edbc 148 * @}
AnnaBridge 171:3a7713b1edbc 149 */
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /** @defgroup LCD_Prescaler LCD Prescaler
AnnaBridge 171:3a7713b1edbc 152 * @{
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 #define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */
AnnaBridge 171:3a7713b1edbc 156 #define LCD_PRESCALER_2 (0x00400000U) /*!< CLKPS = LCDCLK/2 */
AnnaBridge 171:3a7713b1edbc 157 #define LCD_PRESCALER_4 (0x00800000U) /*!< CLKPS = LCDCLK/4 */
AnnaBridge 171:3a7713b1edbc 158 #define LCD_PRESCALER_8 (0x00C00000U) /*!< CLKPS = LCDCLK/8 */
AnnaBridge 171:3a7713b1edbc 159 #define LCD_PRESCALER_16 (0x01000000U) /*!< CLKPS = LCDCLK/16 */
AnnaBridge 171:3a7713b1edbc 160 #define LCD_PRESCALER_32 (0x01400000U) /*!< CLKPS = LCDCLK/32 */
AnnaBridge 171:3a7713b1edbc 161 #define LCD_PRESCALER_64 (0x01800000U) /*!< CLKPS = LCDCLK/64 */
AnnaBridge 171:3a7713b1edbc 162 #define LCD_PRESCALER_128 (0x01C00000U) /*!< CLKPS = LCDCLK/128 */
AnnaBridge 171:3a7713b1edbc 163 #define LCD_PRESCALER_256 (0x02000000U) /*!< CLKPS = LCDCLK/256 */
AnnaBridge 171:3a7713b1edbc 164 #define LCD_PRESCALER_512 (0x02400000U) /*!< CLKPS = LCDCLK/512 */
AnnaBridge 171:3a7713b1edbc 165 #define LCD_PRESCALER_1024 (0x02800000U) /*!< CLKPS = LCDCLK/1024 */
AnnaBridge 171:3a7713b1edbc 166 #define LCD_PRESCALER_2048 (0x02C00000U) /*!< CLKPS = LCDCLK/2048 */
AnnaBridge 171:3a7713b1edbc 167 #define LCD_PRESCALER_4096 (0x03000000U) /*!< CLKPS = LCDCLK/4096 */
AnnaBridge 171:3a7713b1edbc 168 #define LCD_PRESCALER_8192 (0x03400000U) /*!< CLKPS = LCDCLK/8192 */
AnnaBridge 171:3a7713b1edbc 169 #define LCD_PRESCALER_16384 (0x03800000U) /*!< CLKPS = LCDCLK/16384 */
AnnaBridge 171:3a7713b1edbc 170 #define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \
AnnaBridge 171:3a7713b1edbc 173 ((__PRESCALER__) == LCD_PRESCALER_2) || \
AnnaBridge 171:3a7713b1edbc 174 ((__PRESCALER__) == LCD_PRESCALER_4) || \
AnnaBridge 171:3a7713b1edbc 175 ((__PRESCALER__) == LCD_PRESCALER_8) || \
AnnaBridge 171:3a7713b1edbc 176 ((__PRESCALER__) == LCD_PRESCALER_16) || \
AnnaBridge 171:3a7713b1edbc 177 ((__PRESCALER__) == LCD_PRESCALER_32) || \
AnnaBridge 171:3a7713b1edbc 178 ((__PRESCALER__) == LCD_PRESCALER_64) || \
AnnaBridge 171:3a7713b1edbc 179 ((__PRESCALER__) == LCD_PRESCALER_128) || \
AnnaBridge 171:3a7713b1edbc 180 ((__PRESCALER__) == LCD_PRESCALER_256) || \
AnnaBridge 171:3a7713b1edbc 181 ((__PRESCALER__) == LCD_PRESCALER_512) || \
AnnaBridge 171:3a7713b1edbc 182 ((__PRESCALER__) == LCD_PRESCALER_1024) || \
AnnaBridge 171:3a7713b1edbc 183 ((__PRESCALER__) == LCD_PRESCALER_2048) || \
AnnaBridge 171:3a7713b1edbc 184 ((__PRESCALER__) == LCD_PRESCALER_4096) || \
AnnaBridge 171:3a7713b1edbc 185 ((__PRESCALER__) == LCD_PRESCALER_8192) || \
AnnaBridge 171:3a7713b1edbc 186 ((__PRESCALER__) == LCD_PRESCALER_16384) || \
AnnaBridge 171:3a7713b1edbc 187 ((__PRESCALER__) == LCD_PRESCALER_32768))
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /**
AnnaBridge 171:3a7713b1edbc 190 * @}
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /** @defgroup LCD_Divider LCD Divider
AnnaBridge 171:3a7713b1edbc 194 * @{
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 #define LCD_DIVIDER_16 (0x00000000U) /*!< LCD frequency = CLKPS/16 */
AnnaBridge 171:3a7713b1edbc 198 #define LCD_DIVIDER_17 (0x00040000U) /*!< LCD frequency = CLKPS/17 */
AnnaBridge 171:3a7713b1edbc 199 #define LCD_DIVIDER_18 (0x00080000U) /*!< LCD frequency = CLKPS/18 */
AnnaBridge 171:3a7713b1edbc 200 #define LCD_DIVIDER_19 (0x000C0000U) /*!< LCD frequency = CLKPS/19 */
AnnaBridge 171:3a7713b1edbc 201 #define LCD_DIVIDER_20 (0x00100000U) /*!< LCD frequency = CLKPS/20 */
AnnaBridge 171:3a7713b1edbc 202 #define LCD_DIVIDER_21 (0x00140000U) /*!< LCD frequency = CLKPS/21 */
AnnaBridge 171:3a7713b1edbc 203 #define LCD_DIVIDER_22 (0x00180000U) /*!< LCD frequency = CLKPS/22 */
AnnaBridge 171:3a7713b1edbc 204 #define LCD_DIVIDER_23 (0x001C0000U) /*!< LCD frequency = CLKPS/23 */
AnnaBridge 171:3a7713b1edbc 205 #define LCD_DIVIDER_24 (0x00200000U) /*!< LCD frequency = CLKPS/24 */
AnnaBridge 171:3a7713b1edbc 206 #define LCD_DIVIDER_25 (0x00240000U) /*!< LCD frequency = CLKPS/25 */
AnnaBridge 171:3a7713b1edbc 207 #define LCD_DIVIDER_26 (0x00280000U) /*!< LCD frequency = CLKPS/26 */
AnnaBridge 171:3a7713b1edbc 208 #define LCD_DIVIDER_27 (0x002C0000U) /*!< LCD frequency = CLKPS/27 */
AnnaBridge 171:3a7713b1edbc 209 #define LCD_DIVIDER_28 (0x00300000U) /*!< LCD frequency = CLKPS/28 */
AnnaBridge 171:3a7713b1edbc 210 #define LCD_DIVIDER_29 (0x00340000U) /*!< LCD frequency = CLKPS/29 */
AnnaBridge 171:3a7713b1edbc 211 #define LCD_DIVIDER_30 (0x00380000U) /*!< LCD frequency = CLKPS/30 */
AnnaBridge 171:3a7713b1edbc 212 #define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
AnnaBridge 171:3a7713b1edbc 215 ((__DIVIDER__) == LCD_DIVIDER_17) || \
AnnaBridge 171:3a7713b1edbc 216 ((__DIVIDER__) == LCD_DIVIDER_18) || \
AnnaBridge 171:3a7713b1edbc 217 ((__DIVIDER__) == LCD_DIVIDER_19) || \
AnnaBridge 171:3a7713b1edbc 218 ((__DIVIDER__) == LCD_DIVIDER_20) || \
AnnaBridge 171:3a7713b1edbc 219 ((__DIVIDER__) == LCD_DIVIDER_21) || \
AnnaBridge 171:3a7713b1edbc 220 ((__DIVIDER__) == LCD_DIVIDER_22) || \
AnnaBridge 171:3a7713b1edbc 221 ((__DIVIDER__) == LCD_DIVIDER_23) || \
AnnaBridge 171:3a7713b1edbc 222 ((__DIVIDER__) == LCD_DIVIDER_24) || \
AnnaBridge 171:3a7713b1edbc 223 ((__DIVIDER__) == LCD_DIVIDER_25) || \
AnnaBridge 171:3a7713b1edbc 224 ((__DIVIDER__) == LCD_DIVIDER_26) || \
AnnaBridge 171:3a7713b1edbc 225 ((__DIVIDER__) == LCD_DIVIDER_27) || \
AnnaBridge 171:3a7713b1edbc 226 ((__DIVIDER__) == LCD_DIVIDER_28) || \
AnnaBridge 171:3a7713b1edbc 227 ((__DIVIDER__) == LCD_DIVIDER_29) || \
AnnaBridge 171:3a7713b1edbc 228 ((__DIVIDER__) == LCD_DIVIDER_30) || \
AnnaBridge 171:3a7713b1edbc 229 ((__DIVIDER__) == LCD_DIVIDER_31))
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /**
AnnaBridge 171:3a7713b1edbc 232 * @}
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /** @defgroup LCD_Duty LCD Duty
AnnaBridge 171:3a7713b1edbc 237 * @{
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 #define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */
AnnaBridge 171:3a7713b1edbc 241 #define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */
AnnaBridge 171:3a7713b1edbc 242 #define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */
AnnaBridge 171:3a7713b1edbc 243 #define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */
AnnaBridge 171:3a7713b1edbc 244 #define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 #define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \
AnnaBridge 171:3a7713b1edbc 247 ((__DUTY__) == LCD_DUTY_1_2) || \
AnnaBridge 171:3a7713b1edbc 248 ((__DUTY__) == LCD_DUTY_1_3) || \
AnnaBridge 171:3a7713b1edbc 249 ((__DUTY__) == LCD_DUTY_1_4) || \
AnnaBridge 171:3a7713b1edbc 250 ((__DUTY__) == LCD_DUTY_1_8))
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 /**
AnnaBridge 171:3a7713b1edbc 253 * @}
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 /** @defgroup LCD_Bias LCD Bias
AnnaBridge 171:3a7713b1edbc 258 * @{
AnnaBridge 171:3a7713b1edbc 259 */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 #define LCD_BIAS_1_4 (0x00000000U) /*!< 1/4 Bias */
AnnaBridge 171:3a7713b1edbc 262 #define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
AnnaBridge 171:3a7713b1edbc 263 #define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 #define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
AnnaBridge 171:3a7713b1edbc 266 ((__BIAS__) == LCD_BIAS_1_2) || \
AnnaBridge 171:3a7713b1edbc 267 ((__BIAS__) == LCD_BIAS_1_3))
AnnaBridge 171:3a7713b1edbc 268 /**
AnnaBridge 171:3a7713b1edbc 269 * @}
AnnaBridge 171:3a7713b1edbc 270 */
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /** @defgroup LCD_Voltage_Source LCD Voltage Source
AnnaBridge 171:3a7713b1edbc 273 * @{
AnnaBridge 171:3a7713b1edbc 274 */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */
AnnaBridge 171:3a7713b1edbc 277 #define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
AnnaBridge 171:3a7713b1edbc 280 ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 /**
AnnaBridge 171:3a7713b1edbc 283 * @}
AnnaBridge 171:3a7713b1edbc 284 */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /** @defgroup LCD_Interrupts LCD Interrupts
AnnaBridge 171:3a7713b1edbc 287 * @{
AnnaBridge 171:3a7713b1edbc 288 */
AnnaBridge 171:3a7713b1edbc 289 #define LCD_IT_SOF LCD_FCR_SOFIE
AnnaBridge 171:3a7713b1edbc 290 #define LCD_IT_UDD LCD_FCR_UDDIE
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 /**
AnnaBridge 171:3a7713b1edbc 293 * @}
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
AnnaBridge 171:3a7713b1edbc 297 * @{
AnnaBridge 171:3a7713b1edbc 298 */
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300 #define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */
AnnaBridge 171:3a7713b1edbc 301 #define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */
AnnaBridge 171:3a7713b1edbc 302 #define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */
AnnaBridge 171:3a7713b1edbc 303 #define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */
AnnaBridge 171:3a7713b1edbc 304 #define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */
AnnaBridge 171:3a7713b1edbc 305 #define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */
AnnaBridge 171:3a7713b1edbc 306 #define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */
AnnaBridge 171:3a7713b1edbc 307 #define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 #define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
AnnaBridge 171:3a7713b1edbc 310 ((__DURATION__) == LCD_PULSEONDURATION_1) || \
AnnaBridge 171:3a7713b1edbc 311 ((__DURATION__) == LCD_PULSEONDURATION_2) || \
AnnaBridge 171:3a7713b1edbc 312 ((__DURATION__) == LCD_PULSEONDURATION_3) || \
AnnaBridge 171:3a7713b1edbc 313 ((__DURATION__) == LCD_PULSEONDURATION_4) || \
AnnaBridge 171:3a7713b1edbc 314 ((__DURATION__) == LCD_PULSEONDURATION_5) || \
AnnaBridge 171:3a7713b1edbc 315 ((__DURATION__) == LCD_PULSEONDURATION_6) || \
AnnaBridge 171:3a7713b1edbc 316 ((__DURATION__) == LCD_PULSEONDURATION_7))
AnnaBridge 171:3a7713b1edbc 317 /**
AnnaBridge 171:3a7713b1edbc 318 * @}
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /** @defgroup LCD_HighDrive LCD HighDrive
AnnaBridge 171:3a7713b1edbc 322 * @{
AnnaBridge 171:3a7713b1edbc 323 */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 #define LCD_HIGHDRIVE_0 (0x00000000U) /*!< Low resistance Drive */
AnnaBridge 171:3a7713b1edbc 326 #define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 #define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
AnnaBridge 171:3a7713b1edbc 329 ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1))
AnnaBridge 171:3a7713b1edbc 330 /**
AnnaBridge 171:3a7713b1edbc 331 * @}
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /** @defgroup LCD_DeadTime LCD Dead Time
AnnaBridge 171:3a7713b1edbc 335 * @{
AnnaBridge 171:3a7713b1edbc 336 */
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 #define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */
AnnaBridge 171:3a7713b1edbc 339 #define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 340 #define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 341 #define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 342 #define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 343 #define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 344 #define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 345 #define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 #define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
AnnaBridge 171:3a7713b1edbc 348 ((__TIME__) == LCD_DEADTIME_1) || \
AnnaBridge 171:3a7713b1edbc 349 ((__TIME__) == LCD_DEADTIME_2) || \
AnnaBridge 171:3a7713b1edbc 350 ((__TIME__) == LCD_DEADTIME_3) || \
AnnaBridge 171:3a7713b1edbc 351 ((__TIME__) == LCD_DEADTIME_4) || \
AnnaBridge 171:3a7713b1edbc 352 ((__TIME__) == LCD_DEADTIME_5) || \
AnnaBridge 171:3a7713b1edbc 353 ((__TIME__) == LCD_DEADTIME_6) || \
AnnaBridge 171:3a7713b1edbc 354 ((__TIME__) == LCD_DEADTIME_7))
AnnaBridge 171:3a7713b1edbc 355 /**
AnnaBridge 171:3a7713b1edbc 356 * @}
AnnaBridge 171:3a7713b1edbc 357 */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 /** @defgroup LCD_BlinkMode LCD Blink Mode
AnnaBridge 171:3a7713b1edbc 360 * @{
AnnaBridge 171:3a7713b1edbc 361 */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 #define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disabled */
AnnaBridge 171:3a7713b1edbc 364 #define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
AnnaBridge 171:3a7713b1edbc 365 #define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to
AnnaBridge 171:3a7713b1edbc 366 8 pixels according to the programmed duty) */
AnnaBridge 171:3a7713b1edbc 367 #define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 #define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \
AnnaBridge 171:3a7713b1edbc 370 ((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \
AnnaBridge 171:3a7713b1edbc 371 ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \
AnnaBridge 171:3a7713b1edbc 372 ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
AnnaBridge 171:3a7713b1edbc 373 /**
AnnaBridge 171:3a7713b1edbc 374 * @}
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 /** @defgroup LCD_BlinkFrequency LCD Blink Frequency
AnnaBridge 171:3a7713b1edbc 378 * @{
AnnaBridge 171:3a7713b1edbc 379 */
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 #define LCD_BLINKFREQUENCY_DIV8 (0x00000000U) /*!< The Blink frequency = fLCD/8 */
AnnaBridge 171:3a7713b1edbc 382 #define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */
AnnaBridge 171:3a7713b1edbc 383 #define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */
AnnaBridge 171:3a7713b1edbc 384 #define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */
AnnaBridge 171:3a7713b1edbc 385 #define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */
AnnaBridge 171:3a7713b1edbc 386 #define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */
AnnaBridge 171:3a7713b1edbc 387 #define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */
AnnaBridge 171:3a7713b1edbc 388 #define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 #define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \
AnnaBridge 171:3a7713b1edbc 391 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \
AnnaBridge 171:3a7713b1edbc 392 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \
AnnaBridge 171:3a7713b1edbc 393 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \
AnnaBridge 171:3a7713b1edbc 394 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
AnnaBridge 171:3a7713b1edbc 395 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
AnnaBridge 171:3a7713b1edbc 396 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
AnnaBridge 171:3a7713b1edbc 397 ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
AnnaBridge 171:3a7713b1edbc 398 /**
AnnaBridge 171:3a7713b1edbc 399 * @}
AnnaBridge 171:3a7713b1edbc 400 */
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /** @defgroup LCD_Contrast LCD Contrast
AnnaBridge 171:3a7713b1edbc 403 * @{
AnnaBridge 171:3a7713b1edbc 404 */
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406 #define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */
AnnaBridge 171:3a7713b1edbc 407 #define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */
AnnaBridge 171:3a7713b1edbc 408 #define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */
AnnaBridge 171:3a7713b1edbc 409 #define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */
AnnaBridge 171:3a7713b1edbc 410 #define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */
AnnaBridge 171:3a7713b1edbc 411 #define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V */
AnnaBridge 171:3a7713b1edbc 412 #define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V */
AnnaBridge 171:3a7713b1edbc 413 #define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.51V */
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 #define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
AnnaBridge 171:3a7713b1edbc 416 ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
AnnaBridge 171:3a7713b1edbc 417 ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
AnnaBridge 171:3a7713b1edbc 418 ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
AnnaBridge 171:3a7713b1edbc 419 ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
AnnaBridge 171:3a7713b1edbc 420 ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
AnnaBridge 171:3a7713b1edbc 421 ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
AnnaBridge 171:3a7713b1edbc 422 ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
AnnaBridge 171:3a7713b1edbc 423 /**
AnnaBridge 171:3a7713b1edbc 424 * @}
AnnaBridge 171:3a7713b1edbc 425 */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /** @defgroup LCD_MuxSegment LCD Mux Segment
AnnaBridge 171:3a7713b1edbc 428 * @{
AnnaBridge 171:3a7713b1edbc 429 */
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 #define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< SEG pin multiplexing disabled */
AnnaBridge 171:3a7713b1edbc 432 #define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 #define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 435 ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
AnnaBridge 171:3a7713b1edbc 436 /**
AnnaBridge 171:3a7713b1edbc 437 * @}
AnnaBridge 171:3a7713b1edbc 438 */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 /** @defgroup LCD_Flag LCD Flag
AnnaBridge 171:3a7713b1edbc 441 * @{
AnnaBridge 171:3a7713b1edbc 442 */
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 #define LCD_FLAG_ENS LCD_SR_ENS
AnnaBridge 171:3a7713b1edbc 445 #define LCD_FLAG_SOF LCD_SR_SOF
AnnaBridge 171:3a7713b1edbc 446 #define LCD_FLAG_UDR LCD_SR_UDR
AnnaBridge 171:3a7713b1edbc 447 #define LCD_FLAG_UDD LCD_SR_UDD
AnnaBridge 171:3a7713b1edbc 448 #define LCD_FLAG_RDY LCD_SR_RDY
AnnaBridge 171:3a7713b1edbc 449 #define LCD_FLAG_FCRSF LCD_SR_FCRSR
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /**
AnnaBridge 171:3a7713b1edbc 452 * @}
AnnaBridge 171:3a7713b1edbc 453 */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 /** @defgroup LCD_RAMRegister LCD RAMRegister
AnnaBridge 171:3a7713b1edbc 456 * @{
AnnaBridge 171:3a7713b1edbc 457 */
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 #define LCD_RAM_REGISTER0 (0x00000000U) /*!< LCD RAM Register 0 */
AnnaBridge 171:3a7713b1edbc 460 #define LCD_RAM_REGISTER1 (0x00000001U) /*!< LCD RAM Register 1 */
AnnaBridge 171:3a7713b1edbc 461 #define LCD_RAM_REGISTER2 (0x00000002U) /*!< LCD RAM Register 2 */
AnnaBridge 171:3a7713b1edbc 462 #define LCD_RAM_REGISTER3 (0x00000003U) /*!< LCD RAM Register 3 */
AnnaBridge 171:3a7713b1edbc 463 #define LCD_RAM_REGISTER4 (0x00000004U) /*!< LCD RAM Register 4 */
AnnaBridge 171:3a7713b1edbc 464 #define LCD_RAM_REGISTER5 (0x00000005U) /*!< LCD RAM Register 5 */
AnnaBridge 171:3a7713b1edbc 465 #define LCD_RAM_REGISTER6 (0x00000006U) /*!< LCD RAM Register 6 */
AnnaBridge 171:3a7713b1edbc 466 #define LCD_RAM_REGISTER7 (0x00000007U) /*!< LCD RAM Register 7 */
AnnaBridge 171:3a7713b1edbc 467 #define LCD_RAM_REGISTER8 (0x00000008U) /*!< LCD RAM Register 8 */
AnnaBridge 171:3a7713b1edbc 468 #define LCD_RAM_REGISTER9 (0x00000009U) /*!< LCD RAM Register 9 */
AnnaBridge 171:3a7713b1edbc 469 #define LCD_RAM_REGISTER10 (0x0000000AU) /*!< LCD RAM Register 10 */
AnnaBridge 171:3a7713b1edbc 470 #define LCD_RAM_REGISTER11 (0x0000000BU) /*!< LCD RAM Register 11 */
AnnaBridge 171:3a7713b1edbc 471 #define LCD_RAM_REGISTER12 (0x0000000CU) /*!< LCD RAM Register 12 */
AnnaBridge 171:3a7713b1edbc 472 #define LCD_RAM_REGISTER13 (0x0000000DU) /*!< LCD RAM Register 13 */
AnnaBridge 171:3a7713b1edbc 473 #define LCD_RAM_REGISTER14 (0x0000000EU) /*!< LCD RAM Register 14 */
AnnaBridge 171:3a7713b1edbc 474 #define LCD_RAM_REGISTER15 (0x0000000FU) /*!< LCD RAM Register 15 */
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \
AnnaBridge 171:3a7713b1edbc 477 ((__REGISTER__) == LCD_RAM_REGISTER1) || \
AnnaBridge 171:3a7713b1edbc 478 ((__REGISTER__) == LCD_RAM_REGISTER2) || \
AnnaBridge 171:3a7713b1edbc 479 ((__REGISTER__) == LCD_RAM_REGISTER3) || \
AnnaBridge 171:3a7713b1edbc 480 ((__REGISTER__) == LCD_RAM_REGISTER4) || \
AnnaBridge 171:3a7713b1edbc 481 ((__REGISTER__) == LCD_RAM_REGISTER5) || \
AnnaBridge 171:3a7713b1edbc 482 ((__REGISTER__) == LCD_RAM_REGISTER6) || \
AnnaBridge 171:3a7713b1edbc 483 ((__REGISTER__) == LCD_RAM_REGISTER7) || \
AnnaBridge 171:3a7713b1edbc 484 ((__REGISTER__) == LCD_RAM_REGISTER8) || \
AnnaBridge 171:3a7713b1edbc 485 ((__REGISTER__) == LCD_RAM_REGISTER9) || \
AnnaBridge 171:3a7713b1edbc 486 ((__REGISTER__) == LCD_RAM_REGISTER10) || \
AnnaBridge 171:3a7713b1edbc 487 ((__REGISTER__) == LCD_RAM_REGISTER11) || \
AnnaBridge 171:3a7713b1edbc 488 ((__REGISTER__) == LCD_RAM_REGISTER12) || \
AnnaBridge 171:3a7713b1edbc 489 ((__REGISTER__) == LCD_RAM_REGISTER13) || \
AnnaBridge 171:3a7713b1edbc 490 ((__REGISTER__) == LCD_RAM_REGISTER14) || \
AnnaBridge 171:3a7713b1edbc 491 ((__REGISTER__) == LCD_RAM_REGISTER15))
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 /**
AnnaBridge 171:3a7713b1edbc 494 * @}
AnnaBridge 171:3a7713b1edbc 495 */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /**
AnnaBridge 171:3a7713b1edbc 498 * @}
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 /** @defgroup LCD_Exported_Macros LCD Exported Macros
AnnaBridge 171:3a7713b1edbc 504 * @{
AnnaBridge 171:3a7713b1edbc 505 */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /** @brief Reset LCD handle state
AnnaBridge 171:3a7713b1edbc 508 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 509 * @retval None
AnnaBridge 171:3a7713b1edbc 510 */
AnnaBridge 171:3a7713b1edbc 511 #define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 /** @brief macros to enables or disables the LCD
AnnaBridge 171:3a7713b1edbc 514 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 515 * @retval None
AnnaBridge 171:3a7713b1edbc 516 */
AnnaBridge 171:3a7713b1edbc 517 #define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
AnnaBridge 171:3a7713b1edbc 518 #define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 /** @brief Macros to enable or disable the low resistance divider. Displays with high
AnnaBridge 171:3a7713b1edbc 521 * internal resistance may need a longer drive time to achieve
AnnaBridge 171:3a7713b1edbc 522 * satisfactory contrast. This function is useful in this case if some
AnnaBridge 171:3a7713b1edbc 523 * additional power consumption can be tolerated.
AnnaBridge 171:3a7713b1edbc 524 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 525 * @note When this mode is enabled, the PulseOn Duration (PON) have to be
AnnaBridge 171:3a7713b1edbc 526 * programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
AnnaBridge 171:3a7713b1edbc 527 * @retval None
AnnaBridge 171:3a7713b1edbc 528 */
AnnaBridge 171:3a7713b1edbc 529 #define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 530 do{ \
AnnaBridge 171:3a7713b1edbc 531 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
AnnaBridge 171:3a7713b1edbc 532 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 533 }while(0)
AnnaBridge 171:3a7713b1edbc 534
AnnaBridge 171:3a7713b1edbc 535 #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 536 do{ \
AnnaBridge 171:3a7713b1edbc 537 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
AnnaBridge 171:3a7713b1edbc 538 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 539 }while(0)
AnnaBridge 171:3a7713b1edbc 540
AnnaBridge 171:3a7713b1edbc 541 /**
AnnaBridge 171:3a7713b1edbc 542 * @brief Macro to configure the LCD pulses on duration.
AnnaBridge 171:3a7713b1edbc 543 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 544 * @param __DURATION__: specifies the LCD pulse on duration in terms of
AnnaBridge 171:3a7713b1edbc 545 * CK_PS (prescaled LCD clock period) pulses.
AnnaBridge 171:3a7713b1edbc 546 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 547 * @arg LCD_PULSEONDURATION_0: 0 pulse
AnnaBridge 171:3a7713b1edbc 548 * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
AnnaBridge 171:3a7713b1edbc 549 * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
AnnaBridge 171:3a7713b1edbc 550 * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
AnnaBridge 171:3a7713b1edbc 551 * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
AnnaBridge 171:3a7713b1edbc 552 * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
AnnaBridge 171:3a7713b1edbc 553 * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
AnnaBridge 171:3a7713b1edbc 554 * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
AnnaBridge 171:3a7713b1edbc 555 * @retval None
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557 #define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \
AnnaBridge 171:3a7713b1edbc 558 do{ \
AnnaBridge 171:3a7713b1edbc 559 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
AnnaBridge 171:3a7713b1edbc 560 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 561 }while(0)
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /**
AnnaBridge 171:3a7713b1edbc 564 * @brief Macro to configure the LCD dead time.
AnnaBridge 171:3a7713b1edbc 565 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 566 * @param __DEADTIME__: specifies the LCD dead time.
AnnaBridge 171:3a7713b1edbc 567 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 568 * @arg LCD_DEADTIME_0: No dead Time
AnnaBridge 171:3a7713b1edbc 569 * @arg LCD_DEADTIME_1: One Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 570 * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 571 * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 572 * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 573 * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 574 * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 575 * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
AnnaBridge 171:3a7713b1edbc 576 * @retval None
AnnaBridge 171:3a7713b1edbc 577 */
AnnaBridge 171:3a7713b1edbc 578 #define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \
AnnaBridge 171:3a7713b1edbc 579 do{ \
AnnaBridge 171:3a7713b1edbc 580 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
AnnaBridge 171:3a7713b1edbc 581 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 582 }while(0)
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 /**
AnnaBridge 171:3a7713b1edbc 585 * @brief Macro to configure the LCD Contrast.
AnnaBridge 171:3a7713b1edbc 586 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 587 * @param __CONTRAST__: specifies the LCD Contrast.
AnnaBridge 171:3a7713b1edbc 588 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 589 * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
AnnaBridge 171:3a7713b1edbc 590 * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
AnnaBridge 171:3a7713b1edbc 591 * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
AnnaBridge 171:3a7713b1edbc 592 * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
AnnaBridge 171:3a7713b1edbc 593 * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
AnnaBridge 171:3a7713b1edbc 594 * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
AnnaBridge 171:3a7713b1edbc 595 * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
AnnaBridge 171:3a7713b1edbc 596 * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
AnnaBridge 171:3a7713b1edbc 597 * @retval None
AnnaBridge 171:3a7713b1edbc 598 */
AnnaBridge 171:3a7713b1edbc 599 #define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \
AnnaBridge 171:3a7713b1edbc 600 do{ \
AnnaBridge 171:3a7713b1edbc 601 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
AnnaBridge 171:3a7713b1edbc 602 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 603 } while(0)
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 /**
AnnaBridge 171:3a7713b1edbc 606 * @brief Macro to configure the LCD Blink mode and Blink frequency.
AnnaBridge 171:3a7713b1edbc 607 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 608 * @param __BLINKMODE__: specifies the LCD blink mode.
AnnaBridge 171:3a7713b1edbc 609 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 610 * @arg LCD_BLINKMODE_OFF: Blink disabled
AnnaBridge 171:3a7713b1edbc 611 * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
AnnaBridge 171:3a7713b1edbc 612 * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8
AnnaBridge 171:3a7713b1edbc 613 * pixels according to the programmed duty)
AnnaBridge 171:3a7713b1edbc 614 * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
AnnaBridge 171:3a7713b1edbc 615 * (all pixels)
AnnaBridge 171:3a7713b1edbc 616 * @param __BLINKFREQUENCY__: specifies the LCD blink frequency.
AnnaBridge 171:3a7713b1edbc 617 * @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8
AnnaBridge 171:3a7713b1edbc 618 * @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16
AnnaBridge 171:3a7713b1edbc 619 * @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32
AnnaBridge 171:3a7713b1edbc 620 * @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64
AnnaBridge 171:3a7713b1edbc 621 * @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128
AnnaBridge 171:3a7713b1edbc 622 * @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256
AnnaBridge 171:3a7713b1edbc 623 * @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512
AnnaBridge 171:3a7713b1edbc 624 * @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
AnnaBridge 171:3a7713b1edbc 625 * @retval None
AnnaBridge 171:3a7713b1edbc 626 */
AnnaBridge 171:3a7713b1edbc 627 #define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \
AnnaBridge 171:3a7713b1edbc 628 do{ \
AnnaBridge 171:3a7713b1edbc 629 MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
AnnaBridge 171:3a7713b1edbc 630 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 631 }while(0)
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 /** @brief Enables or disables the specified LCD interrupt.
AnnaBridge 171:3a7713b1edbc 634 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 635 * @param __INTERRUPT__: specifies the LCD interrupt source to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 636 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 637 * @arg LCD_IT_SOF: Start of Frame Interrupt
AnnaBridge 171:3a7713b1edbc 638 * @arg LCD_IT_UDD: Update Display Done Interrupt
AnnaBridge 171:3a7713b1edbc 639 * @retval None
AnnaBridge 171:3a7713b1edbc 640 */
AnnaBridge 171:3a7713b1edbc 641 #define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge 171:3a7713b1edbc 642 do{ \
AnnaBridge 171:3a7713b1edbc 643 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
AnnaBridge 171:3a7713b1edbc 644 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 645 }while(0)
AnnaBridge 171:3a7713b1edbc 646 #define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge 171:3a7713b1edbc 647 do{ \
AnnaBridge 171:3a7713b1edbc 648 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
AnnaBridge 171:3a7713b1edbc 649 LCD_WaitForSynchro(__HANDLE__); \
AnnaBridge 171:3a7713b1edbc 650 }while(0)
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /** @brief Checks whether the specified LCD interrupt is enabled or not.
AnnaBridge 171:3a7713b1edbc 653 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 654 * @param __IT__: specifies the LCD interrupt source to check.
AnnaBridge 171:3a7713b1edbc 655 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 656 * @arg LCD_IT_SOF: Start of Frame Interrupt
AnnaBridge 171:3a7713b1edbc 657 * @arg LCD_IT_UDD: Update Display Done Interrupt.
AnnaBridge 171:3a7713b1edbc 658 * @note If the device is in STOP mode (PCLK not provided) UDD will not
AnnaBridge 171:3a7713b1edbc 659 * generate an interrupt even if UDDIE = 1.
AnnaBridge 171:3a7713b1edbc 660 * If the display is not enabled the UDD interrupt will never occur.
AnnaBridge 171:3a7713b1edbc 661 * @retval The state of __IT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 662 */
AnnaBridge 171:3a7713b1edbc 663 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 /** @brief Checks whether the specified LCD flag is set or not.
AnnaBridge 171:3a7713b1edbc 666 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 667 * @param __FLAG__: specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 668 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 669 * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
AnnaBridge 171:3a7713b1edbc 670 * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
AnnaBridge 171:3a7713b1edbc 671 * goes from 0 to 1. On deactivation it reflects the real status of
AnnaBridge 171:3a7713b1edbc 672 * LCD so it becomes 0 at the end of the last displayed frame.
AnnaBridge 171:3a7713b1edbc 673 * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
AnnaBridge 171:3a7713b1edbc 674 * the beginning of a new frame, at the same time as the display data is
AnnaBridge 171:3a7713b1edbc 675 * updated.
AnnaBridge 171:3a7713b1edbc 676 * @arg LCD_FLAG_UDR: Update Display Request flag.
AnnaBridge 171:3a7713b1edbc 677 * @arg LCD_FLAG_UDD: Update Display Done flag.
AnnaBridge 171:3a7713b1edbc 678 * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
AnnaBridge 171:3a7713b1edbc 679 * of the step-up converter.
AnnaBridge 171:3a7713b1edbc 680 * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
AnnaBridge 171:3a7713b1edbc 681 * This flag is set by hardware each time the LCD_FCR register is updated
AnnaBridge 171:3a7713b1edbc 682 * in the LCDCLK domain.
AnnaBridge 171:3a7713b1edbc 683 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 684 */
AnnaBridge 171:3a7713b1edbc 685 #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687 /** @brief Clears the specified LCD pending flag.
AnnaBridge 171:3a7713b1edbc 688 * @param __HANDLE__: specifies the LCD Handle.
AnnaBridge 171:3a7713b1edbc 689 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 171:3a7713b1edbc 690 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 691 * @arg LCD_FLAG_SOF: Start of Frame Interrupt
AnnaBridge 171:3a7713b1edbc 692 * @arg LCD_FLAG_UDD: Update Display Done Interrupt
AnnaBridge 171:3a7713b1edbc 693 * @retval None
AnnaBridge 171:3a7713b1edbc 694 */
AnnaBridge 171:3a7713b1edbc 695 #define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLR = (__FLAG__))
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 /**
AnnaBridge 171:3a7713b1edbc 698 * @}
AnnaBridge 171:3a7713b1edbc 699 */
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 /* Exported functions ------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 /** @addtogroup LCD_Exported_Functions
AnnaBridge 171:3a7713b1edbc 704 * @{
AnnaBridge 171:3a7713b1edbc 705 */
AnnaBridge 171:3a7713b1edbc 706
AnnaBridge 171:3a7713b1edbc 707 /** @addtogroup LCD_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 708 * @{
AnnaBridge 171:3a7713b1edbc 709 */
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 /* Initialization/de-initialization methods **********************************/
AnnaBridge 171:3a7713b1edbc 712 HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 713 HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 714 void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 715 void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 716
AnnaBridge 171:3a7713b1edbc 717 /**
AnnaBridge 171:3a7713b1edbc 718 * @}
AnnaBridge 171:3a7713b1edbc 719 */
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 /** @addtogroup LCD_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 722 * @{
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /* IO operation methods *******************************************************/
AnnaBridge 171:3a7713b1edbc 726 HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
AnnaBridge 171:3a7713b1edbc 727 HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 728 HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 729
AnnaBridge 171:3a7713b1edbc 730 /**
AnnaBridge 171:3a7713b1edbc 731 * @}
AnnaBridge 171:3a7713b1edbc 732 */
AnnaBridge 171:3a7713b1edbc 733
AnnaBridge 171:3a7713b1edbc 734 /** @addtogroup LCD_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 735 * @{
AnnaBridge 171:3a7713b1edbc 736 */
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /* Peripheral State methods **************************************************/
AnnaBridge 171:3a7713b1edbc 739 HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 740 uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 /**
AnnaBridge 171:3a7713b1edbc 743 * @}
AnnaBridge 171:3a7713b1edbc 744 */
AnnaBridge 171:3a7713b1edbc 745
AnnaBridge 171:3a7713b1edbc 746 /**
AnnaBridge 171:3a7713b1edbc 747 * @}
AnnaBridge 171:3a7713b1edbc 748 */
AnnaBridge 171:3a7713b1edbc 749
AnnaBridge 171:3a7713b1edbc 750 /** @addtogroup LCD_Private_Functions
AnnaBridge 171:3a7713b1edbc 751 * @{
AnnaBridge 171:3a7713b1edbc 752 */
AnnaBridge 171:3a7713b1edbc 753
AnnaBridge 171:3a7713b1edbc 754 /* Private functions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 755 HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /**
AnnaBridge 171:3a7713b1edbc 758 * @}
AnnaBridge 171:3a7713b1edbc 759 */
AnnaBridge 171:3a7713b1edbc 760
AnnaBridge 171:3a7713b1edbc 761 /**
AnnaBridge 171:3a7713b1edbc 762 * @}
AnnaBridge 171:3a7713b1edbc 763 */
AnnaBridge 171:3a7713b1edbc 764
AnnaBridge 171:3a7713b1edbc 765 #endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767 /**
AnnaBridge 171:3a7713b1edbc 768 * @}
AnnaBridge 171:3a7713b1edbc 769 */
AnnaBridge 171:3a7713b1edbc 770
AnnaBridge 171:3a7713b1edbc 771 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 772 }
AnnaBridge 171:3a7713b1edbc 773 #endif
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775 #endif /* __STM32L1xx_HAL_LCD_H */
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/