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mbed 2

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TARGET_NCS36510/TOOLCHAIN_ARM_STD/macHw_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file macHw_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief MACHW hw module register map
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 3390 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup macHw
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 */
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 #ifndef MACHW_MAP_H_
AnnaBridge 171:3a7713b1edbc 33 #define MACHW_MAP_H_
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*************************************************************************************************
AnnaBridge 171:3a7713b1edbc 36 * *
AnnaBridge 171:3a7713b1edbc 37 * Header files *
AnnaBridge 171:3a7713b1edbc 38 * *
AnnaBridge 171:3a7713b1edbc 39 *************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**************************************************************************************************
AnnaBridge 171:3a7713b1edbc 44 * *
AnnaBridge 171:3a7713b1edbc 45 * Type definitions *
AnnaBridge 171:3a7713b1edbc 46 * *
AnnaBridge 171:3a7713b1edbc 47 **************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** macHw register map (phy, mac and agc parts) */
AnnaBridge 171:3a7713b1edbc 50 typedef struct {
AnnaBridge 171:3a7713b1edbc 51 __O uint32_t SEQUENCER; /**< 0x40014000 */
AnnaBridge 171:3a7713b1edbc 52 union {
AnnaBridge 171:3a7713b1edbc 53 struct {
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t MODE:2;
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t NOACK:1;
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t FT:1;
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t PAD0:3;
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t AUTO:1;
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t NOW:1;
AnnaBridge 171:3a7713b1edbc 61 __IO uint32_t PAD2:1;
AnnaBridge 171:3a7713b1edbc 62 __IO uint32_t PRM:1;
AnnaBridge 171:3a7713b1edbc 63 __IO uint32_t NFCS:1;
AnnaBridge 171:3a7713b1edbc 64 __IO uint32_t PAN:1;
AnnaBridge 171:3a7713b1edbc 65 __IO uint32_t RSTT:1;
AnnaBridge 171:3a7713b1edbc 66 __IO uint32_t RSTR:1;
AnnaBridge 171:3a7713b1edbc 67 __IO uint32_t ACK_ENABLE:1;
AnnaBridge 171:3a7713b1edbc 68 __IO uint32_t BEA_ENABLE:1;
AnnaBridge 171:3a7713b1edbc 69 __IO uint32_t CMD_ENABLE:1;
AnnaBridge 171:3a7713b1edbc 70 __IO uint32_t DATA_ENABLE:1;
AnnaBridge 171:3a7713b1edbc 71 __IO uint32_t RES_ENABLE:1;
AnnaBridge 171:3a7713b1edbc 72 } BITS;
AnnaBridge 171:3a7713b1edbc 73 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 74 } SEQ_OPTIONS; /**< 0x40014004 */
AnnaBridge 171:3a7713b1edbc 75 union {
AnnaBridge 171:3a7713b1edbc 76 struct {
AnnaBridge 171:3a7713b1edbc 77 __IO uint32_t SRST:1;
AnnaBridge 171:3a7713b1edbc 78 __IO uint32_t ON:1;
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t CLKDIV:1;
AnnaBridge 171:3a7713b1edbc 80 } BITS;
AnnaBridge 171:3a7713b1edbc 81 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 82 } CONTROL; /**< 0x40014008 */
AnnaBridge 171:3a7713b1edbc 83 __O uint32_t PAD0; /**< 0x4001400C */
AnnaBridge 171:3a7713b1edbc 84 union {
AnnaBridge 171:3a7713b1edbc 85 struct {
AnnaBridge 171:3a7713b1edbc 86 __I uint32_t CODE:4;
AnnaBridge 171:3a7713b1edbc 87 __I uint32_t PAD0:8;
AnnaBridge 171:3a7713b1edbc 88 __I uint32_t MSO:1;
AnnaBridge 171:3a7713b1edbc 89 __I uint32_t CB:1;
AnnaBridge 171:3a7713b1edbc 90 __I uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 91 __I uint32_t MST:1;
AnnaBridge 171:3a7713b1edbc 92 } BITS;
AnnaBridge 171:3a7713b1edbc 93 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 94 } STATUS; /**< 0x40014010 */
AnnaBridge 171:3a7713b1edbc 95 union {
AnnaBridge 171:3a7713b1edbc 96 struct {
AnnaBridge 171:3a7713b1edbc 97 __IO uint32_t TFP:1;
AnnaBridge 171:3a7713b1edbc 98 __IO uint32_t SDC:1;
AnnaBridge 171:3a7713b1edbc 99 __IO uint32_t IC:1;
AnnaBridge 171:3a7713b1edbc 100 __IO uint32_t SDB:1;
AnnaBridge 171:3a7713b1edbc 101 __IO uint32_t SSP:1;
AnnaBridge 171:3a7713b1edbc 102 __IO uint32_t TFPO:1;
AnnaBridge 171:3a7713b1edbc 103 } BITS;
AnnaBridge 171:3a7713b1edbc 104 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 105 } OPTIONS; /**< 0x40014014 */
AnnaBridge 171:3a7713b1edbc 106 __IO uint32_t PANID; /**< 0x40014018 */
AnnaBridge 171:3a7713b1edbc 107 __IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
AnnaBridge 171:3a7713b1edbc 108 __IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
AnnaBridge 171:3a7713b1edbc 109 __IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
AnnaBridge 171:3a7713b1edbc 110 union {
AnnaBridge 171:3a7713b1edbc 111 struct {
AnnaBridge 171:3a7713b1edbc 112 __IO uint32_t BIT_CLOCK_DIVIDER:8;
AnnaBridge 171:3a7713b1edbc 113 __IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
AnnaBridge 171:3a7713b1edbc 114 __IO uint32_t CHIP_CLOCK_DIVIDER:8;
AnnaBridge 171:3a7713b1edbc 115 } BITS;
AnnaBridge 171:3a7713b1edbc 116 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 117 } DIVIDER; /**< 0x40014028 */
AnnaBridge 171:3a7713b1edbc 118 union {
AnnaBridge 171:3a7713b1edbc 119 struct {
AnnaBridge 171:3a7713b1edbc 120 __IO uint32_t RECEIVE_WARMPUP:12;
AnnaBridge 171:3a7713b1edbc 121 __IO uint32_t PAD0:4;
AnnaBridge 171:3a7713b1edbc 122 __IO uint32_t TRANSMIT_WARMPUP:12;
AnnaBridge 171:3a7713b1edbc 123 } BITS;
AnnaBridge 171:3a7713b1edbc 124 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 125 } RX_TX_WARMPUPS; /**< 0x4001402c */
AnnaBridge 171:3a7713b1edbc 126 union {
AnnaBridge 171:3a7713b1edbc 127 struct {
AnnaBridge 171:3a7713b1edbc 128 __O uint32_t EC:1;
AnnaBridge 171:3a7713b1edbc 129 __O uint32_t ES:1;
AnnaBridge 171:3a7713b1edbc 130 __O uint32_t DATA:1;
AnnaBridge 171:3a7713b1edbc 131 __O uint32_t FS:1;
AnnaBridge 171:3a7713b1edbc 132 __O uint32_t FP:1;
AnnaBridge 171:3a7713b1edbc 133 __O uint32_t FMD:1;
AnnaBridge 171:3a7713b1edbc 134 __I uint32_t PC:1;
AnnaBridge 171:3a7713b1edbc 135 } BITS;
AnnaBridge 171:3a7713b1edbc 136 __O uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 137 } CLEAR_IRQ; /**< 0x40014030 */
AnnaBridge 171:3a7713b1edbc 138 union {
AnnaBridge 171:3a7713b1edbc 139 struct {
AnnaBridge 171:3a7713b1edbc 140 __IO uint32_t EC:1;
AnnaBridge 171:3a7713b1edbc 141 __IO uint32_t ES:1;
AnnaBridge 171:3a7713b1edbc 142 __IO uint32_t DATA:1;
AnnaBridge 171:3a7713b1edbc 143 __IO uint32_t FS:1;
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t FP:1;
AnnaBridge 171:3a7713b1edbc 145 __IO uint32_t FM:1;
AnnaBridge 171:3a7713b1edbc 146 __I uint32_t PC:1;
AnnaBridge 171:3a7713b1edbc 147 } BITS;
AnnaBridge 171:3a7713b1edbc 148 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 149 } MASK_IRQ; /**< 0x40014034 */
AnnaBridge 171:3a7713b1edbc 150 union {
AnnaBridge 171:3a7713b1edbc 151 struct {
AnnaBridge 171:3a7713b1edbc 152 __I uint32_t EC:1;
AnnaBridge 171:3a7713b1edbc 153 __I uint32_t ES:1;
AnnaBridge 171:3a7713b1edbc 154 __I uint32_t DATA:1;
AnnaBridge 171:3a7713b1edbc 155 __I uint32_t FS:1;
AnnaBridge 171:3a7713b1edbc 156 __I uint32_t FP:1;
AnnaBridge 171:3a7713b1edbc 157 __I uint32_t FM:1;
AnnaBridge 171:3a7713b1edbc 158 __I uint32_t PC:1;
AnnaBridge 171:3a7713b1edbc 159 } BITS;
AnnaBridge 171:3a7713b1edbc 160 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 161 } IRQ_STATUS; /**< 0x40014038 */
AnnaBridge 171:3a7713b1edbc 162 __O uint32_t PAD1; /**< 0x4001403C */
AnnaBridge 171:3a7713b1edbc 163 union {
AnnaBridge 171:3a7713b1edbc 164 struct {
AnnaBridge 171:3a7713b1edbc 165 __IO uint32_t START:1;
AnnaBridge 171:3a7713b1edbc 166 __IO uint32_t STOP:1;
AnnaBridge 171:3a7713b1edbc 167 } BITS;
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 169 } TIMER_ENABLE; /**< 0x40014040 */
AnnaBridge 171:3a7713b1edbc 170 union {
AnnaBridge 171:3a7713b1edbc 171 struct {
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t START:1;
AnnaBridge 171:3a7713b1edbc 173 __IO uint32_t STOP:1;
AnnaBridge 171:3a7713b1edbc 174 } BITS;
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 176 } TIMER_DISABLE; /**< 0x40014044 */
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t TIMER; /**< 0x40014048 */
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t START_TIME; /**< 0x4001404C */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t STOP_TIME; /**< 0x40014050 */
AnnaBridge 171:3a7713b1edbc 180 union {
AnnaBridge 171:3a7713b1edbc 181 struct {
AnnaBridge 171:3a7713b1edbc 182 __I uint32_t START:1;
AnnaBridge 171:3a7713b1edbc 183 __I uint32_t STOP:1;
AnnaBridge 171:3a7713b1edbc 184 } BITS;
AnnaBridge 171:3a7713b1edbc 185 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 186 } TIMER_STATUS; /**< 0x40014054 */
AnnaBridge 171:3a7713b1edbc 187 __I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
AnnaBridge 171:3a7713b1edbc 188 __O uint32_t PAD4; /**< 0x4001405C */
AnnaBridge 171:3a7713b1edbc 189 __I uint32_t FINISH_TIME; /**< 0x40014060 */
AnnaBridge 171:3a7713b1edbc 190 union {
AnnaBridge 171:3a7713b1edbc 191 struct {
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t TX_SLOT_OFFSET:12;
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t PAD0:4;
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t RX_SLOT_OFFSET:12;
AnnaBridge 171:3a7713b1edbc 195 } BITS;
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 197 } SLOT_OFFSET; /**< 0x40014064 */
AnnaBridge 171:3a7713b1edbc 198 __I uint32_t TIME_STAMP; /**< 0x40014068 */
AnnaBridge 171:3a7713b1edbc 199 union {
AnnaBridge 171:3a7713b1edbc 200 struct {
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t CRD_SHORT_ADDRESS:16;
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t PAD0:13;
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t ASSOC_PAN_COORD:1;
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t PAN_COORD_ADDR_L:1;
AnnaBridge 171:3a7713b1edbc 205 __IO uint32_t PAN_COORD_ADDR_S:1;
AnnaBridge 171:3a7713b1edbc 206 } BITS;
AnnaBridge 171:3a7713b1edbc 207 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 208 } CRD_SHORT_ADDR; /**< 0x4001406C */
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
AnnaBridge 171:3a7713b1edbc 211 __O uint32_t PAD5; /**< 0x40014078 */
AnnaBridge 171:3a7713b1edbc 212 __O uint32_t PAD9; /**< 0x4001407C */
AnnaBridge 171:3a7713b1edbc 213 __O uint32_t PAD10; /**< 0x40014080 */
AnnaBridge 171:3a7713b1edbc 214 __O uint32_t PAD11; /**< 0x40014084 */
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t RX_LENGTH; /**< 0x40014088 */
AnnaBridge 171:3a7713b1edbc 216 union {
AnnaBridge 171:3a7713b1edbc 217 struct {
AnnaBridge 171:3a7713b1edbc 218 __IO uint32_t TXLENGTH:7;
AnnaBridge 171:3a7713b1edbc 219 __O uint32_t PAD0:1;
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t TX_PRE_CHIPS:4;
AnnaBridge 171:3a7713b1edbc 221 } BITS;
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 223 } TX_LENGTH; /**< 0x4001408C */
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
AnnaBridge 171:3a7713b1edbc 226 union {
AnnaBridge 171:3a7713b1edbc 227 struct {
AnnaBridge 171:3a7713b1edbc 228 __IO uint32_t RXACKDELAY:12;
AnnaBridge 171:3a7713b1edbc 229 __IO uint32_t PAD0:4;
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t RXAUTODELAY:12;
AnnaBridge 171:3a7713b1edbc 231 } BITS;
AnnaBridge 171:3a7713b1edbc 232 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 233 } RX_ACK_DELAY; /**< 0x40014098 */
AnnaBridge 171:3a7713b1edbc 234 __IO uint32_t TX_FLUSH; /**< 0x4001409C */
AnnaBridge 171:3a7713b1edbc 235 union {
AnnaBridge 171:3a7713b1edbc 236 struct {
AnnaBridge 171:3a7713b1edbc 237 __IO uint32_t CCA_DELAY:12;
AnnaBridge 171:3a7713b1edbc 238 __IO uint32_t PAD0:4;
AnnaBridge 171:3a7713b1edbc 239 __IO uint32_t CCA_LENGTH:12;
AnnaBridge 171:3a7713b1edbc 240 } BITS;
AnnaBridge 171:3a7713b1edbc 241 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 242 } CCA; /**< 0x400140A0 */
AnnaBridge 171:3a7713b1edbc 243 union {
AnnaBridge 171:3a7713b1edbc 244 struct {
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t RXACK_END:12;
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t PAD0:4;
AnnaBridge 171:3a7713b1edbc 247 __IO uint32_t RXSLOTTED_END:12;
AnnaBridge 171:3a7713b1edbc 248 } BITS;
AnnaBridge 171:3a7713b1edbc 249 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 250 } ACK_STOP; /**< 0x400140A4 */
AnnaBridge 171:3a7713b1edbc 251 __IO uint32_t TXCCA; /**< 0x400140A8 */
AnnaBridge 171:3a7713b1edbc 252 __IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
AnnaBridge 171:3a7713b1edbc 253 __IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
AnnaBridge 171:3a7713b1edbc 257 union {
AnnaBridge 171:3a7713b1edbc 258 struct {
AnnaBridge 171:3a7713b1edbc 259 __IO uint32_t AA:1;
AnnaBridge 171:3a7713b1edbc 260 __IO uint32_t AFA:1;
AnnaBridge 171:3a7713b1edbc 261 __IO uint32_t PRE:1;
AnnaBridge 171:3a7713b1edbc 262 __IO uint32_t PAD0:25;
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t GAIN_START:4;
AnnaBridge 171:3a7713b1edbc 264 } BITS;
AnnaBridge 171:3a7713b1edbc 265 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 266 } AGC_CONTROL; /**< 0x400140C0 */
AnnaBridge 171:3a7713b1edbc 267 union {
AnnaBridge 171:3a7713b1edbc 268 struct {
AnnaBridge 171:3a7713b1edbc 269 __IO uint32_t SETTLE_DELAY:8;
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t MEASURE_DELAY:8;
AnnaBridge 171:3a7713b1edbc 271 __IO uint32_t DIVIDER:8;
AnnaBridge 171:3a7713b1edbc 272 __IO uint32_t HIGH_THRESHOLD:4;
AnnaBridge 171:3a7713b1edbc 273 __IO uint32_t LOW_THRESHOLD:4;
AnnaBridge 171:3a7713b1edbc 274 } BITS;
AnnaBridge 171:3a7713b1edbc 275 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 276 } AGC_SETTINGS; /**< 0x400140C4 */
AnnaBridge 171:3a7713b1edbc 277 union {
AnnaBridge 171:3a7713b1edbc 278 struct {
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t GC1:3;
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t GC2:3;
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t GC3:1;
AnnaBridge 171:3a7713b1edbc 282 __IO uint32_t PAD:1;
AnnaBridge 171:3a7713b1edbc 283 __IO uint32_t AGC_STATE:4;
AnnaBridge 171:3a7713b1edbc 284 } BITS;
AnnaBridge 171:3a7713b1edbc 285 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 286 } AGC_STATUS; /**< 0x400140C8 */
AnnaBridge 171:3a7713b1edbc 287 union {
AnnaBridge 171:3a7713b1edbc 288 struct {
AnnaBridge 171:3a7713b1edbc 289 __IO uint32_t GAIN3:7;
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t PAD0:1;
AnnaBridge 171:3a7713b1edbc 291 __IO uint32_t GAIN2:7;
AnnaBridge 171:3a7713b1edbc 292 __IO uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 293 __IO uint32_t GAIN1:7;
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t PAD2:1;
AnnaBridge 171:3a7713b1edbc 295 __IO uint32_t GAIN0:7;
AnnaBridge 171:3a7713b1edbc 296 __IO uint32_t PAD3:1;
AnnaBridge 171:3a7713b1edbc 297 } BITS;
AnnaBridge 171:3a7713b1edbc 298 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 299 } AGC_GAIN_TABLE0; /**< 0x400140CC */
AnnaBridge 171:3a7713b1edbc 300 union {
AnnaBridge 171:3a7713b1edbc 301 struct {
AnnaBridge 171:3a7713b1edbc 302 __IO uint32_t GAIN7:7;
AnnaBridge 171:3a7713b1edbc 303 __IO uint32_t PAD0:1;
AnnaBridge 171:3a7713b1edbc 304 __IO uint32_t GAIN6:7;
AnnaBridge 171:3a7713b1edbc 305 __IO uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 306 __IO uint32_t GAIN5:7;
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t PAD2:1;
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t GAIN4:7;
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t PAD3:1;
AnnaBridge 171:3a7713b1edbc 310 } BITS;
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 312 } AGC_GAIN_TABLE1; /**< 0x400140D0 */
AnnaBridge 171:3a7713b1edbc 313 union {
AnnaBridge 171:3a7713b1edbc 314 struct {
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t GAIN11:7;
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t PAD0:1;
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t GAIN10:7;
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t GAIN9:7;
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t PAD2:1;
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t GAIN8:7;
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t PAD3:1;
AnnaBridge 171:3a7713b1edbc 323 } BITS;
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 325 } AGC_GAIN_TABLE2; /**< 0x400140D4 */
AnnaBridge 171:3a7713b1edbc 326 union {
AnnaBridge 171:3a7713b1edbc 327 struct {
AnnaBridge 171:3a7713b1edbc 328 __IO uint32_t GAIN15:7;
AnnaBridge 171:3a7713b1edbc 329 __IO uint32_t PAD0:1;
AnnaBridge 171:3a7713b1edbc 330 __IO uint32_t GAIN14:7;
AnnaBridge 171:3a7713b1edbc 331 __IO uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 332 __IO uint32_t GAIN13:7;
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t PAD2:1;
AnnaBridge 171:3a7713b1edbc 334 __IO uint32_t GAIN12:7;
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t PAD3:1;
AnnaBridge 171:3a7713b1edbc 336 } BITS;
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 338 } AGC_GAIN_TABLE3; /**< 0x400140D8 */
AnnaBridge 171:3a7713b1edbc 339 } MacHwReg_t, *MacHwReg_pt;
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /** macHw register map (demodulator part) */
AnnaBridge 171:3a7713b1edbc 342 typedef struct {
AnnaBridge 171:3a7713b1edbc 343 union {
AnnaBridge 171:3a7713b1edbc 344 struct {
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t DRC:1; /**< Reserved */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
AnnaBridge 171:3a7713b1edbc 348 __IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
AnnaBridge 171:3a7713b1edbc 349 __IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
AnnaBridge 171:3a7713b1edbc 351 __IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t PAD1:9;
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
AnnaBridge 171:3a7713b1edbc 354 } BITS;
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 356 } DMD_CONTROL0; /**< 0x40014100 */
AnnaBridge 171:3a7713b1edbc 357 union {
AnnaBridge 171:3a7713b1edbc 358 struct {
AnnaBridge 171:3a7713b1edbc 359 __IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
AnnaBridge 171:3a7713b1edbc 360 __IO uint32_t PAD0:4;
AnnaBridge 171:3a7713b1edbc 361 __IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t PAD1:2;
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
AnnaBridge 171:3a7713b1edbc 364 __IO uint32_t PAD2:4;
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 } BITS;
AnnaBridge 171:3a7713b1edbc 368 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 369 } DMD_CONTROL1; /**< 0x40014104 */
AnnaBridge 171:3a7713b1edbc 370 union {
AnnaBridge 171:3a7713b1edbc 371 struct {
AnnaBridge 171:3a7713b1edbc 372 __IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
AnnaBridge 171:3a7713b1edbc 373 __IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
AnnaBridge 171:3a7713b1edbc 374 } BITS;
AnnaBridge 171:3a7713b1edbc 375 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 376 } DMD_CONTROL2; /**< 0x40014108 */
AnnaBridge 171:3a7713b1edbc 377 union {
AnnaBridge 171:3a7713b1edbc 378 struct {
AnnaBridge 171:3a7713b1edbc 379 __I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
AnnaBridge 171:3a7713b1edbc 380 __I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
AnnaBridge 171:3a7713b1edbc 381 __I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
AnnaBridge 171:3a7713b1edbc 382 __I uint32_t PAD0:3;
AnnaBridge 171:3a7713b1edbc 383 __I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
AnnaBridge 171:3a7713b1edbc 384 } BITS;
AnnaBridge 171:3a7713b1edbc 385 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 386 } DMD_STATUS; /**< 0x4001410C */
AnnaBridge 171:3a7713b1edbc 387 } DmdReg_t, *DmdReg_pt;
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 #endif /* MACHW_MAP_H_ */