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TARGET_NCS36510/TOOLCHAIN_ARM_STD/clock_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file clock_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief CLOCK hw module register map
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 2848 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup clock
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 */
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 #ifndef CLOCK_MAP_H_
AnnaBridge 171:3a7713b1edbc 33 #define CLOCK_MAP_H_
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*************************************************************************************************
AnnaBridge 171:3a7713b1edbc 36 * *
AnnaBridge 171:3a7713b1edbc 37 * Header files *
AnnaBridge 171:3a7713b1edbc 38 * *
AnnaBridge 171:3a7713b1edbc 39 *************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**************************************************************************************************
AnnaBridge 171:3a7713b1edbc 44 * *
AnnaBridge 171:3a7713b1edbc 45 * Type definitions *
AnnaBridge 171:3a7713b1edbc 46 * *
AnnaBridge 171:3a7713b1edbc 47 **************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** Clock control HW structure overlay */
AnnaBridge 171:3a7713b1edbc 50 typedef struct {
AnnaBridge 171:3a7713b1edbc 51 union {
AnnaBridge 171:3a7713b1edbc 52 struct {
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t OSC_SEL:1;
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t PAD0:1;
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t CAL32K:1;
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t CAL32M:1;
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t RTCEN:1;
AnnaBridge 171:3a7713b1edbc 58 } BITS;
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 60 } CCR; /**< 0x4001B000 Clock control register */
AnnaBridge 171:3a7713b1edbc 61 union {
AnnaBridge 171:3a7713b1edbc 62 struct {
AnnaBridge 171:3a7713b1edbc 63 __I uint32_t XTAL32M:1;
AnnaBridge 171:3a7713b1edbc 64 __I uint32_t XTAL32K:1;
AnnaBridge 171:3a7713b1edbc 65 __I uint32_t CAL32K:1;
AnnaBridge 171:3a7713b1edbc 66 __I uint32_t DONE32K:1;
AnnaBridge 171:3a7713b1edbc 67 __I uint32_t CAL32MFAIL:1;
AnnaBridge 171:3a7713b1edbc 68 __I uint32_t CAL32MDONE:1;
AnnaBridge 171:3a7713b1edbc 69 } BITS;
AnnaBridge 171:3a7713b1edbc 70 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 71 } CSR; /**< 0x4001B004 Clock status register */
AnnaBridge 171:3a7713b1edbc 72 union {
AnnaBridge 171:3a7713b1edbc 73 struct {
AnnaBridge 171:3a7713b1edbc 74 __IO uint32_t IE32K:1;
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t IE32M:1;
AnnaBridge 171:3a7713b1edbc 76 } BITS;
AnnaBridge 171:3a7713b1edbc 77 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 78 } IER; /**< 0x4001B008 Interrup enable register */
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
AnnaBridge 171:3a7713b1edbc 80 union {
AnnaBridge 171:3a7713b1edbc 81 struct {
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t TIMER0:1;
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t TIMER1:1;
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t TIMER2:1;
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t PAD0:2;
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t UART1:1;
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t SPI:1;
AnnaBridge 171:3a7713b1edbc 88 __IO uint32_t I2C:1;
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t UART2:1;
AnnaBridge 171:3a7713b1edbc 90 __IO uint32_t PAD1:1;
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t WDOG:1;
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t PWM:1;
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t GPIO:1;
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t PAD2:2;
AnnaBridge 171:3a7713b1edbc 95 __IO uint32_t RTC:1;
AnnaBridge 171:3a7713b1edbc 96 __IO uint32_t XBAR:1;
AnnaBridge 171:3a7713b1edbc 97 __IO uint32_t RAND:1;
AnnaBridge 171:3a7713b1edbc 98 __IO uint32_t PAD3:2;
AnnaBridge 171:3a7713b1edbc 99 __IO uint32_t MACHW:1;
AnnaBridge 171:3a7713b1edbc 100 __IO uint32_t ADC:1;
AnnaBridge 171:3a7713b1edbc 101 __IO uint32_t AES:1;
AnnaBridge 171:3a7713b1edbc 102 __IO uint32_t FLASH:1;
AnnaBridge 171:3a7713b1edbc 103 __IO uint32_t PAD4:1;
AnnaBridge 171:3a7713b1edbc 104 __IO uint32_t RFANA:1;
AnnaBridge 171:3a7713b1edbc 105 __IO uint32_t IO:1;
AnnaBridge 171:3a7713b1edbc 106 __IO uint32_t PAD5:1;
AnnaBridge 171:3a7713b1edbc 107 __IO uint32_t PAD:1;
AnnaBridge 171:3a7713b1edbc 108 __IO uint32_t PMU:1;
AnnaBridge 171:3a7713b1edbc 109 __IO uint32_t PAD6:1;
AnnaBridge 171:3a7713b1edbc 110 __IO uint32_t TEST:1;
AnnaBridge 171:3a7713b1edbc 111 } BITS;
AnnaBridge 171:3a7713b1edbc 112 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 113 } PDIS; /**< 0x4001B010 Periphery disable */
AnnaBridge 171:3a7713b1edbc 114 __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
AnnaBridge 171:3a7713b1edbc 115 __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
AnnaBridge 171:3a7713b1edbc 116 __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
AnnaBridge 171:3a7713b1edbc 117 __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
AnnaBridge 171:3a7713b1edbc 118 __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
AnnaBridge 171:3a7713b1edbc 119 union {
AnnaBridge 171:3a7713b1edbc 120 struct {
AnnaBridge 171:3a7713b1edbc 121 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
AnnaBridge 171:3a7713b1edbc 122 __IO uint32_t BOOST :2; /* Boost done signal tap control */
AnnaBridge 171:3a7713b1edbc 123 __IO uint32_t READY :2; /* Ready signal tap control */
AnnaBridge 171:3a7713b1edbc 124 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
AnnaBridge 171:3a7713b1edbc 125 __IO uint32_t PAD :20; /* Unused bits */
AnnaBridge 171:3a7713b1edbc 126 } BITS;
AnnaBridge 171:3a7713b1edbc 127 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 128 } TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 union {
AnnaBridge 171:3a7713b1edbc 131 struct {
AnnaBridge 171:3a7713b1edbc 132 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
AnnaBridge 171:3a7713b1edbc 133 __IO uint32_t BOOST :2; /* Boost done signal tap control */
AnnaBridge 171:3a7713b1edbc 134 __IO uint32_t READY :2; /* Ready signal tap control */
AnnaBridge 171:3a7713b1edbc 135 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
AnnaBridge 171:3a7713b1edbc 136 __IO uint32_t PAD :20; /* Unused bits */
AnnaBridge 171:3a7713b1edbc 137 } BITS;
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 139 } TRIM_32K_EXT;
AnnaBridge 171:3a7713b1edbc 140 union {
AnnaBridge 171:3a7713b1edbc 141 struct {
AnnaBridge 171:3a7713b1edbc 142 __IO uint32_t OV32M;
AnnaBridge 171:3a7713b1edbc 143 __IO uint32_t EN32M;
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t OV32K;
AnnaBridge 171:3a7713b1edbc 145 __IO uint32_t EN32K;
AnnaBridge 171:3a7713b1edbc 146 } BITS;
AnnaBridge 171:3a7713b1edbc 147 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 148 } CER; /**< 0x4001B038 clock enable register*/
AnnaBridge 171:3a7713b1edbc 149 } ClockReg_t, *ClockReg_pt;
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 #endif /* CLOCK_MAP_H_ */