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TARGET_NCS36510/TOOLCHAIN_ARM_STD/NCS36510.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************/
AnnaBridge 171:3a7713b1edbc 2 /**
AnnaBridge 171:3a7713b1edbc 3 * @file NCS36510.h
AnnaBridge 171:3a7713b1edbc 4 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 5 * for CM3 Device Series
AnnaBridge 171:3a7713b1edbc 6 * @version V1.05
AnnaBridge 171:3a7713b1edbc 7 * @date 26. July 2011
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * @note
AnnaBridge 171:3a7713b1edbc 10 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * @par
AnnaBridge 171:3a7713b1edbc 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
AnnaBridge 171:3a7713b1edbc 14 * processor based microcontrollers. This file can be freely distributed
AnnaBridge 171:3a7713b1edbc 15 * within development tools that are supporting such ARM based processors.
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * @par
AnnaBridge 171:3a7713b1edbc 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
AnnaBridge 171:3a7713b1edbc 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 25
AnnaBridge 171:3a7713b1edbc 26 #ifndef ARMCM3_H
AnnaBridge 171:3a7713b1edbc 27 #define ARMCM3_H
AnnaBridge 171:3a7713b1edbc 28
AnnaBridge 171:3a7713b1edbc 29 /**
AnnaBridge 171:3a7713b1edbc 30 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 31 * ---------- Interrupt Number Definition -----------------------------------
AnnaBridge 171:3a7713b1edbc 32 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 33 */
AnnaBridge 171:3a7713b1edbc 34 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
AnnaBridge 171:3a7713b1edbc 36 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 37 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 38 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 39 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 40 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 41 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 42 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 43 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 44 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /****** ARMCM3 specific Interrupt Numbers ********************************************************/
AnnaBridge 171:3a7713b1edbc 47 Tim0_IRQn = 0,
AnnaBridge 171:3a7713b1edbc 48 Tim1_IRQn = 1,
AnnaBridge 171:3a7713b1edbc 49 Tim2_IRQn = 2,
AnnaBridge 171:3a7713b1edbc 50 Uart1_IRQn = 3,
AnnaBridge 171:3a7713b1edbc 51 Spi_IRQn = 4,
AnnaBridge 171:3a7713b1edbc 52 I2C_IRQn = 5,
AnnaBridge 171:3a7713b1edbc 53 Gpio_IRQn = 6,
AnnaBridge 171:3a7713b1edbc 54 Rtc_IRQn = 7,
AnnaBridge 171:3a7713b1edbc 55 Flash_IRQn = 8,
AnnaBridge 171:3a7713b1edbc 56 MacHw_IRQn = 9,
AnnaBridge 171:3a7713b1edbc 57 Aes_IRQn = 10,
AnnaBridge 171:3a7713b1edbc 58 Adc_IRQn = 11,
AnnaBridge 171:3a7713b1edbc 59 ClockCal_IRQn = 12,
AnnaBridge 171:3a7713b1edbc 60 Uart2_IRQn = 13,
AnnaBridge 171:3a7713b1edbc 61 Uvi_IRQn = 14,
AnnaBridge 171:3a7713b1edbc 62 Dma_IRQn = 15,
AnnaBridge 171:3a7713b1edbc 63 DbgPwrUp_IRQn = 16,
AnnaBridge 171:3a7713b1edbc 64 Spi2_IRQn = 17,
AnnaBridge 171:3a7713b1edbc 65 I2C2_IRQn = 18,
AnnaBridge 171:3a7713b1edbc 66 FVDDHComp_IRQn = 19
AnnaBridge 171:3a7713b1edbc 67 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 /**
AnnaBridge 171:3a7713b1edbc 70 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 71 * ----------- Processor and Core Peripheral Section ------------------------
AnnaBridge 171:3a7713b1edbc 72 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /** Configuration of the Cortex-M3 Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 76 #define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
AnnaBridge 171:3a7713b1edbc 77 #define __MPU_PRESENT 1 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 78 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 79 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 //#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 84 #include "system_NCS36510.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 #endif /* ARMCM3_H */