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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_pxp.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /*
AnnaBridge 170:e95d10626187 2 * The Clear BSD License
AnnaBridge 161:aa5281ff4a02 3 * Copyright (c) 2017, NXP Semiconductors, Inc.
AnnaBridge 161:aa5281ff4a02 4 * All rights reserved.
AnnaBridge 161:aa5281ff4a02 5 *
AnnaBridge 170:e95d10626187 6 *
AnnaBridge 161:aa5281ff4a02 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 170:e95d10626187 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 170:e95d10626187 9 * that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 10 *
AnnaBridge 161:aa5281ff4a02 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 161:aa5281ff4a02 12 * of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 13 *
AnnaBridge 161:aa5281ff4a02 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 161:aa5281ff4a02 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 161:aa5281ff4a02 16 * other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 161:aa5281ff4a02 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 161:aa5281ff4a02 20 * software without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 21 *
AnnaBridge 170:e95d10626187 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 161:aa5281ff4a02 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 161:aa5281ff4a02 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 161:aa5281ff4a02 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 161:aa5281ff4a02 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 161:aa5281ff4a02 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 161:aa5281ff4a02 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 161:aa5281ff4a02 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 161:aa5281ff4a02 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 161:aa5281ff4a02 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 33 */
AnnaBridge 161:aa5281ff4a02 34
AnnaBridge 161:aa5281ff4a02 35 #ifndef _FSL_PXP_H_
AnnaBridge 161:aa5281ff4a02 36 #define _FSL_PXP_H_
AnnaBridge 161:aa5281ff4a02 37
AnnaBridge 161:aa5281ff4a02 38 #include "fsl_common.h"
AnnaBridge 161:aa5281ff4a02 39
AnnaBridge 161:aa5281ff4a02 40 /* Compatibility macro map. */
AnnaBridge 161:aa5281ff4a02 41 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK))
AnnaBridge 161:aa5281ff4a02 42 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
AnnaBridge 161:aa5281ff4a02 43 #endif
AnnaBridge 161:aa5281ff4a02 44
AnnaBridge 161:aa5281ff4a02 45 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK))
AnnaBridge 161:aa5281ff4a02 46 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
AnnaBridge 161:aa5281ff4a02 47 #endif
AnnaBridge 161:aa5281ff4a02 48
AnnaBridge 161:aa5281ff4a02 49 #if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK))
AnnaBridge 161:aa5281ff4a02 50 #define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK
AnnaBridge 161:aa5281ff4a02 51 #endif
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 #if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK))
AnnaBridge 161:aa5281ff4a02 54 #define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK
AnnaBridge 161:aa5281ff4a02 55 #endif
AnnaBridge 161:aa5281ff4a02 56
AnnaBridge 161:aa5281ff4a02 57 #if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK))
AnnaBridge 161:aa5281ff4a02 58 #define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK
AnnaBridge 161:aa5281ff4a02 59 #endif
AnnaBridge 161:aa5281ff4a02 60
AnnaBridge 161:aa5281ff4a02 61 /*!
AnnaBridge 161:aa5281ff4a02 62 * @addtogroup pxp_driver
AnnaBridge 161:aa5281ff4a02 63 * @{
AnnaBridge 161:aa5281ff4a02 64 */
AnnaBridge 161:aa5281ff4a02 65
AnnaBridge 161:aa5281ff4a02 66 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 67 * Definitions
AnnaBridge 161:aa5281ff4a02 68 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 69
AnnaBridge 161:aa5281ff4a02 70 /* PXP global LUT table is 16K. */
AnnaBridge 161:aa5281ff4a02 71 #define PXP_LUT_TABLE_BYTE (16 * 1024)
AnnaBridge 161:aa5281ff4a02 72 /* Intenral memory for LUT, the size is 256 bytes. */
AnnaBridge 161:aa5281ff4a02 73 #define PXP_INTERNAL_RAM_LUT_BYTE (256)
AnnaBridge 161:aa5281ff4a02 74
AnnaBridge 161:aa5281ff4a02 75 /*! @name Driver version */
AnnaBridge 161:aa5281ff4a02 76 /*@{*/
AnnaBridge 161:aa5281ff4a02 77 #define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
AnnaBridge 161:aa5281ff4a02 78 /*@}*/
AnnaBridge 161:aa5281ff4a02 79
AnnaBridge 161:aa5281ff4a02 80 /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
AnnaBridge 161:aa5281ff4a02 81 #if defined(PXP_CTRL_ROT_POS_MASK)
AnnaBridge 161:aa5281ff4a02 82 #define PXP_SHARE_ROTATE 1
AnnaBridge 161:aa5281ff4a02 83 #else
AnnaBridge 161:aa5281ff4a02 84 #define PXP_SHARE_ROTATE 0
AnnaBridge 161:aa5281ff4a02 85 #endif
AnnaBridge 161:aa5281ff4a02 86
AnnaBridge 161:aa5281ff4a02 87 /*! @brief PXP interrupts to enable. */
AnnaBridge 161:aa5281ff4a02 88 enum _pxp_interrupt_enable
AnnaBridge 161:aa5281ff4a02 89 {
AnnaBridge 161:aa5281ff4a02 90 kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set
AnnaBridge 161:aa5281ff4a02 91 by @ref PXP_SetNextCommand has been loaded. */
AnnaBridge 161:aa5281ff4a02 92 kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. */
AnnaBridge 161:aa5281ff4a02 93 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
AnnaBridge 161:aa5281ff4a02 94 kPXP_LutDmaLoadInterruptEnable = PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. */
AnnaBridge 161:aa5281ff4a02 95 #endif
AnnaBridge 161:aa5281ff4a02 96 };
AnnaBridge 161:aa5281ff4a02 97
AnnaBridge 161:aa5281ff4a02 98 /*!
AnnaBridge 161:aa5281ff4a02 99 * @brief PXP status flags.
AnnaBridge 161:aa5281ff4a02 100 *
AnnaBridge 161:aa5281ff4a02 101 * @note These enumerations are meant to be OR'd together to form a bit mask.
AnnaBridge 161:aa5281ff4a02 102 */
AnnaBridge 161:aa5281ff4a02 103 enum _pxp_flags
AnnaBridge 161:aa5281ff4a02 104 {
AnnaBridge 161:aa5281ff4a02 105 kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand
AnnaBridge 161:aa5281ff4a02 106 has been loaded, could set new command. */
AnnaBridge 161:aa5281ff4a02 107 kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. */
AnnaBridge 161:aa5281ff4a02 108 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
AnnaBridge 161:aa5281ff4a02 109 kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. */
AnnaBridge 161:aa5281ff4a02 110 #endif
AnnaBridge 161:aa5281ff4a02 111 kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error
AnnaBridge 161:aa5281ff4a02 112 and processing has been terminated. */
AnnaBridge 161:aa5281ff4a02 113 kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error
AnnaBridge 161:aa5281ff4a02 114 and processing has been terminated. */
AnnaBridge 161:aa5281ff4a02 115 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
AnnaBridge 161:aa5281ff4a02 116 kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error
AnnaBridge 161:aa5281ff4a02 117 and processing has been terminated. */
AnnaBridge 161:aa5281ff4a02 118 kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error
AnnaBridge 161:aa5281ff4a02 119 and processing has been terminated. */
AnnaBridge 161:aa5281ff4a02 120 #endif
AnnaBridge 161:aa5281ff4a02 121 };
AnnaBridge 161:aa5281ff4a02 122
AnnaBridge 161:aa5281ff4a02 123 /*! @brief PXP output flip mode. */
AnnaBridge 161:aa5281ff4a02 124 typedef enum _pxp_flip_mode
AnnaBridge 161:aa5281ff4a02 125 {
AnnaBridge 161:aa5281ff4a02 126 kPXP_FlipDisable = 0U, /*!< Flip disable. */
AnnaBridge 161:aa5281ff4a02 127 kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */
AnnaBridge 161:aa5281ff4a02 128 kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */
AnnaBridge 161:aa5281ff4a02 129 kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */
AnnaBridge 161:aa5281ff4a02 130 } pxp_flip_mode_t;
AnnaBridge 161:aa5281ff4a02 131
AnnaBridge 161:aa5281ff4a02 132 /*! @brief PXP rotate mode. */
AnnaBridge 161:aa5281ff4a02 133 typedef enum _pxp_rotate_position
AnnaBridge 161:aa5281ff4a02 134 {
AnnaBridge 161:aa5281ff4a02 135 kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */
AnnaBridge 161:aa5281ff4a02 136 kPXP_RotateProcessSurface, /*!< Rotate the process surface. */
AnnaBridge 161:aa5281ff4a02 137 } pxp_rotate_position_t;
AnnaBridge 161:aa5281ff4a02 138
AnnaBridge 161:aa5281ff4a02 139 /*! @brief PXP rotate degree. */
AnnaBridge 161:aa5281ff4a02 140 typedef enum _pxp_rotate_degree
AnnaBridge 161:aa5281ff4a02 141 {
AnnaBridge 161:aa5281ff4a02 142 kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */
AnnaBridge 161:aa5281ff4a02 143 kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */
AnnaBridge 161:aa5281ff4a02 144 kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */
AnnaBridge 161:aa5281ff4a02 145 kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */
AnnaBridge 161:aa5281ff4a02 146 } pxp_rotate_degree_t;
AnnaBridge 161:aa5281ff4a02 147
AnnaBridge 161:aa5281ff4a02 148 /*! @brief PXP interlaced output mode. */
AnnaBridge 161:aa5281ff4a02 149 typedef enum _pxp_interlaced_output_mode
AnnaBridge 161:aa5281ff4a02 150 {
AnnaBridge 161:aa5281ff4a02 151 kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */
AnnaBridge 161:aa5281ff4a02 152 kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */
AnnaBridge 161:aa5281ff4a02 153 kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */
AnnaBridge 161:aa5281ff4a02 154 kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */
AnnaBridge 161:aa5281ff4a02 155 } pxp_interlaced_output_mode_t;
AnnaBridge 161:aa5281ff4a02 156
AnnaBridge 161:aa5281ff4a02 157 /*! @brief PXP output buffer format. */
AnnaBridge 161:aa5281ff4a02 158 typedef enum _pxp_output_pixel_format
AnnaBridge 161:aa5281ff4a02 159 {
AnnaBridge 161:aa5281ff4a02 160 kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
AnnaBridge 161:aa5281ff4a02 161 kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
AnnaBridge 161:aa5281ff4a02 162 kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */
AnnaBridge 161:aa5281ff4a02 163 kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
AnnaBridge 161:aa5281ff4a02 164 kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
AnnaBridge 161:aa5281ff4a02 165 kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 166 kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 167 kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 168 kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
AnnaBridge 161:aa5281ff4a02 169 kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 170 kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 171 kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
AnnaBridge 161:aa5281ff4a02 172 kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
AnnaBridge 161:aa5281ff4a02 173 kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 174 kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
AnnaBridge 161:aa5281ff4a02 175 kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 176 kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
AnnaBridge 161:aa5281ff4a02 177 } pxp_output_pixel_format_t;
AnnaBridge 161:aa5281ff4a02 178
AnnaBridge 161:aa5281ff4a02 179 /*! @brief PXP output buffer configuration. */
AnnaBridge 161:aa5281ff4a02 180 typedef struct _pxp_output_buffer_config
AnnaBridge 161:aa5281ff4a02 181 {
AnnaBridge 161:aa5281ff4a02 182 pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */
AnnaBridge 161:aa5281ff4a02 183 pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */
AnnaBridge 161:aa5281ff4a02 184 uint32_t buffer0Addr; /*!< Output buffer 0 address. */
AnnaBridge 161:aa5281ff4a02 185 uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or
AnnaBridge 161:aa5281ff4a02 186 field 1 in output interlaced mode. */
AnnaBridge 161:aa5281ff4a02 187 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
AnnaBridge 161:aa5281ff4a02 188 uint16_t width; /*!< Pixels per line. */
AnnaBridge 161:aa5281ff4a02 189 uint16_t height; /*!< How many lines in output buffer. */
AnnaBridge 161:aa5281ff4a02 190 } pxp_output_buffer_config_t;
AnnaBridge 161:aa5281ff4a02 191
AnnaBridge 161:aa5281ff4a02 192 /*! @brief PXP process surface buffer pixel format. */
AnnaBridge 161:aa5281ff4a02 193 typedef enum _pxp_ps_pixel_format
AnnaBridge 161:aa5281ff4a02 194 {
AnnaBridge 161:aa5281ff4a02 195 kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
AnnaBridge 161:aa5281ff4a02 196 kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 197 kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 198 kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 199 kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
AnnaBridge 161:aa5281ff4a02 200 kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 201 kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 202 kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
AnnaBridge 161:aa5281ff4a02 203 kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
AnnaBridge 161:aa5281ff4a02 204 kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 205 kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
AnnaBridge 161:aa5281ff4a02 206 kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
AnnaBridge 161:aa5281ff4a02 207 kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
AnnaBridge 161:aa5281ff4a02 208 kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */
AnnaBridge 161:aa5281ff4a02 209 kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */
AnnaBridge 161:aa5281ff4a02 210 } pxp_ps_pixel_format_t;
AnnaBridge 161:aa5281ff4a02 211
AnnaBridge 161:aa5281ff4a02 212 /*! @brief PXP process surface buffer configuration. */
AnnaBridge 161:aa5281ff4a02 213 typedef struct _pxp_ps_buffer_config
AnnaBridge 161:aa5281ff4a02 214 {
AnnaBridge 161:aa5281ff4a02 215 pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */
AnnaBridge 161:aa5281ff4a02 216 bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */
AnnaBridge 161:aa5281ff4a02 217 uint32_t bufferAddr; /*!< Input buffer address for the first panel. */
AnnaBridge 161:aa5281ff4a02 218 uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */
AnnaBridge 161:aa5281ff4a02 219 uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */
AnnaBridge 161:aa5281ff4a02 220 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
AnnaBridge 161:aa5281ff4a02 221 } pxp_ps_buffer_config_t;
AnnaBridge 161:aa5281ff4a02 222
AnnaBridge 161:aa5281ff4a02 223 /*! @brief PXP alpha surface buffer pixel format. */
AnnaBridge 161:aa5281ff4a02 224 typedef enum _pxp_as_pixel_format
AnnaBridge 161:aa5281ff4a02 225 {
AnnaBridge 161:aa5281ff4a02 226 kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
AnnaBridge 161:aa5281ff4a02 227 kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
AnnaBridge 161:aa5281ff4a02 228 kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
AnnaBridge 161:aa5281ff4a02 229 kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
AnnaBridge 161:aa5281ff4a02 230 kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 231 kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 232 kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
AnnaBridge 161:aa5281ff4a02 233 } pxp_as_pixel_format_t;
AnnaBridge 161:aa5281ff4a02 234
AnnaBridge 161:aa5281ff4a02 235 /*! @brief PXP alphs surface buffer configuration. */
AnnaBridge 161:aa5281ff4a02 236 typedef struct _pxp_as_buffer_config
AnnaBridge 161:aa5281ff4a02 237 {
AnnaBridge 161:aa5281ff4a02 238 pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */
AnnaBridge 161:aa5281ff4a02 239 uint32_t bufferAddr; /*!< Input buffer address. */
AnnaBridge 161:aa5281ff4a02 240 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
AnnaBridge 161:aa5281ff4a02 241 } pxp_as_buffer_config_t;
AnnaBridge 161:aa5281ff4a02 242
AnnaBridge 161:aa5281ff4a02 243 /*!
AnnaBridge 161:aa5281ff4a02 244 * @brief PXP alpha mode during blending.
AnnaBridge 161:aa5281ff4a02 245 */
AnnaBridge 161:aa5281ff4a02 246 typedef enum _pxp_alpha_mode
AnnaBridge 161:aa5281ff4a02 247 {
AnnaBridge 161:aa5281ff4a02 248 kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
AnnaBridge 161:aa5281ff4a02 249 kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
AnnaBridge 161:aa5281ff4a02 250 kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
AnnaBridge 161:aa5281ff4a02 251 alpha value will be used for blend, for example, pixel alpha set
AnnaBridge 161:aa5281ff4a02 252 set to 200, user defined alpha set to 100, then the reault alpha
AnnaBridge 161:aa5281ff4a02 253 is 200 * 100 / 255. */
AnnaBridge 161:aa5281ff4a02 254 kPXP_AlphaRop /*!< Raster operation. */
AnnaBridge 161:aa5281ff4a02 255 } pxp_alpha_mode_t;
AnnaBridge 161:aa5281ff4a02 256
AnnaBridge 161:aa5281ff4a02 257 /*!
AnnaBridge 161:aa5281ff4a02 258 * @brief PXP ROP mode during blending.
AnnaBridge 161:aa5281ff4a02 259 *
AnnaBridge 161:aa5281ff4a02 260 * Explanation:
AnnaBridge 161:aa5281ff4a02 261 * - AS: Alpha surface
AnnaBridge 161:aa5281ff4a02 262 * - PS: Process surface
AnnaBridge 161:aa5281ff4a02 263 * - nAS: Alpha surface NOT value
AnnaBridge 161:aa5281ff4a02 264 * - nPS: Process surface NOT value
AnnaBridge 161:aa5281ff4a02 265 */
AnnaBridge 161:aa5281ff4a02 266 typedef enum _pxp_rop_mode
AnnaBridge 161:aa5281ff4a02 267 {
AnnaBridge 161:aa5281ff4a02 268 kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */
AnnaBridge 161:aa5281ff4a02 269 kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
AnnaBridge 161:aa5281ff4a02 270 kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
AnnaBridge 161:aa5281ff4a02 271 kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */
AnnaBridge 161:aa5281ff4a02 272 kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
AnnaBridge 161:aa5281ff4a02 273 kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
AnnaBridge 161:aa5281ff4a02 274 kPXP_RopNotCopyAs = 0x6, /*!< nAS. */
AnnaBridge 161:aa5281ff4a02 275 kPXP_RopNot = 0x7, /*!< nPS. */
AnnaBridge 161:aa5281ff4a02 276 kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
AnnaBridge 161:aa5281ff4a02 277 kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
AnnaBridge 161:aa5281ff4a02 278 kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */
AnnaBridge 161:aa5281ff4a02 279 kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */
AnnaBridge 161:aa5281ff4a02 280 } pxp_rop_mode_t;
AnnaBridge 161:aa5281ff4a02 281
AnnaBridge 161:aa5281ff4a02 282 /*!
AnnaBridge 161:aa5281ff4a02 283 * @brief PXP alpha surface blending configuration.
AnnaBridge 161:aa5281ff4a02 284 */
AnnaBridge 161:aa5281ff4a02 285 typedef struct _pxp_as_blend_config
AnnaBridge 161:aa5281ff4a02 286 {
AnnaBridge 161:aa5281ff4a02 287 uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref
AnnaBridge 161:aa5281ff4a02 288 kPXP_AlphaRop. */
AnnaBridge 161:aa5281ff4a02 289 bool invertAlpha; /*!< Set true to invert the alpha. */
AnnaBridge 161:aa5281ff4a02 290 pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */
AnnaBridge 161:aa5281ff4a02 291 pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */
AnnaBridge 161:aa5281ff4a02 292 } pxp_as_blend_config_t;
AnnaBridge 161:aa5281ff4a02 293
AnnaBridge 161:aa5281ff4a02 294 /*! @brief PXP process block size. */
AnnaBridge 161:aa5281ff4a02 295 typedef enum _pxp_block_size
AnnaBridge 161:aa5281ff4a02 296 {
AnnaBridge 161:aa5281ff4a02 297 kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */
AnnaBridge 161:aa5281ff4a02 298 kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */
AnnaBridge 161:aa5281ff4a02 299 } pxp_block_size_t;
AnnaBridge 161:aa5281ff4a02 300
AnnaBridge 161:aa5281ff4a02 301 /*! @brief PXP CSC1 mode. */
AnnaBridge 161:aa5281ff4a02 302 typedef enum _pxp_csc1_mode
AnnaBridge 161:aa5281ff4a02 303 {
AnnaBridge 161:aa5281ff4a02 304 kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */
AnnaBridge 161:aa5281ff4a02 305 kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */
AnnaBridge 161:aa5281ff4a02 306 } pxp_csc1_mode_t;
AnnaBridge 161:aa5281ff4a02 307
AnnaBridge 161:aa5281ff4a02 308 /*! @brief PXP CSC2 mode. */
AnnaBridge 161:aa5281ff4a02 309 typedef enum _pxp_csc2_mode
AnnaBridge 161:aa5281ff4a02 310 {
AnnaBridge 161:aa5281ff4a02 311 kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */
AnnaBridge 161:aa5281ff4a02 312 kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */
AnnaBridge 161:aa5281ff4a02 313 kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */
AnnaBridge 161:aa5281ff4a02 314 kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */
AnnaBridge 161:aa5281ff4a02 315 } pxp_csc2_mode_t;
AnnaBridge 161:aa5281ff4a02 316
AnnaBridge 161:aa5281ff4a02 317 /*!
AnnaBridge 161:aa5281ff4a02 318 * @brief PXP CSC2 configuration.
AnnaBridge 161:aa5281ff4a02 319 *
AnnaBridge 161:aa5281ff4a02 320 * Converting from YUV/YCbCr color spaces to the RGB color space uses the
AnnaBridge 161:aa5281ff4a02 321 * following equation structure:
AnnaBridge 161:aa5281ff4a02 322 *
AnnaBridge 161:aa5281ff4a02 323 * R = A1(Y+D1) + A2(U+D2) + A3(V+D3)
AnnaBridge 161:aa5281ff4a02 324 * G = B1(Y+D1) + B2(U+D2) + B3(V+D3)
AnnaBridge 161:aa5281ff4a02 325 * B = C1(Y+D1) + C2(U+D2) + C3(V+D3)
AnnaBridge 161:aa5281ff4a02 326 *
AnnaBridge 161:aa5281ff4a02 327 * Converting from the RGB color space to YUV/YCbCr color spaces uses the
AnnaBridge 161:aa5281ff4a02 328 * following equation structure:
AnnaBridge 161:aa5281ff4a02 329 *
AnnaBridge 161:aa5281ff4a02 330 * Y = A1*R + A2*G + A3*B + D1
AnnaBridge 161:aa5281ff4a02 331 * U = B1*R + B2*G + B3*B + D2
AnnaBridge 161:aa5281ff4a02 332 * V = C1*R + C2*G + C3*B + D3
AnnaBridge 161:aa5281ff4a02 333 */
AnnaBridge 161:aa5281ff4a02 334 typedef struct _pxp_csc2_config
AnnaBridge 161:aa5281ff4a02 335 {
AnnaBridge 161:aa5281ff4a02 336 pxp_csc2_mode_t mode; /*!< Convertion mode. */
AnnaBridge 161:aa5281ff4a02 337 float A1; /*!< A1. */
AnnaBridge 161:aa5281ff4a02 338 float A2; /*!< A2. */
AnnaBridge 161:aa5281ff4a02 339 float A3; /*!< A3. */
AnnaBridge 161:aa5281ff4a02 340 float B1; /*!< B1. */
AnnaBridge 161:aa5281ff4a02 341 float B2; /*!< B2. */
AnnaBridge 161:aa5281ff4a02 342 float B3; /*!< B3. */
AnnaBridge 161:aa5281ff4a02 343 float C1; /*!< C1. */
AnnaBridge 161:aa5281ff4a02 344 float C2; /*!< C2. */
AnnaBridge 161:aa5281ff4a02 345 float C3; /*!< C3. */
AnnaBridge 161:aa5281ff4a02 346 int16_t D1; /*!< D1. */
AnnaBridge 161:aa5281ff4a02 347 int16_t D2; /*!< D2. */
AnnaBridge 161:aa5281ff4a02 348 int16_t D3; /*!< D3. */
AnnaBridge 161:aa5281ff4a02 349 } pxp_csc2_config_t;
AnnaBridge 161:aa5281ff4a02 350
AnnaBridge 161:aa5281ff4a02 351 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
AnnaBridge 161:aa5281ff4a02 352 /*! @brief PXP LUT lookup mode. */
AnnaBridge 161:aa5281ff4a02 353 typedef enum _pxp_lut_lookup_mode
AnnaBridge 161:aa5281ff4a02 354 {
AnnaBridge 161:aa5281ff4a02 355 kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT
AnnaBridge 161:aa5281ff4a02 356 for indirect cached 128KB lookup. */
AnnaBridge 161:aa5281ff4a02 357 kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT.
AnnaBridge 161:aa5281ff4a02 358 Only third data path byte is tranformed. */
AnnaBridge 161:aa5281ff4a02 359 kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT
AnnaBridge 161:aa5281ff4a02 360 selected by @ref PXP_Select8kLutBank. */
AnnaBridge 161:aa5281ff4a02 361 kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */
AnnaBridge 161:aa5281ff4a02 362 } pxp_lut_lookup_mode_t;
AnnaBridge 161:aa5281ff4a02 363
AnnaBridge 161:aa5281ff4a02 364 /*! @brief PXP LUT output mode. */
AnnaBridge 161:aa5281ff4a02 365 typedef enum _pxp_lut_out_mode
AnnaBridge 161:aa5281ff4a02 366 {
AnnaBridge 161:aa5281ff4a02 367 kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */
AnnaBridge 161:aa5281ff4a02 368 kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */
AnnaBridge 161:aa5281ff4a02 369 kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */
AnnaBridge 161:aa5281ff4a02 370 } pxp_lut_out_mode_t;
AnnaBridge 161:aa5281ff4a02 371
AnnaBridge 161:aa5281ff4a02 372 /*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */
AnnaBridge 161:aa5281ff4a02 373 typedef enum _pxp_lut_8k_bank
AnnaBridge 161:aa5281ff4a02 374 {
AnnaBridge 161:aa5281ff4a02 375 kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */
AnnaBridge 161:aa5281ff4a02 376 kPXP_Lut8kBank1, /*!< The second 8K bank used. */
AnnaBridge 161:aa5281ff4a02 377 } pxp_lut_8k_bank_t;
AnnaBridge 161:aa5281ff4a02 378
AnnaBridge 161:aa5281ff4a02 379 /*! @brief PXP LUT configuration. */
AnnaBridge 161:aa5281ff4a02 380 typedef struct _pxp_lut_config
AnnaBridge 161:aa5281ff4a02 381 {
AnnaBridge 161:aa5281ff4a02 382 pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */
AnnaBridge 161:aa5281ff4a02 383 pxp_lut_out_mode_t outMode; /*!< Out mode. */
AnnaBridge 161:aa5281ff4a02 384 uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */
AnnaBridge 161:aa5281ff4a02 385 } pxp_lut_config_t;
AnnaBridge 161:aa5281ff4a02 386 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
AnnaBridge 161:aa5281ff4a02 387
AnnaBridge 161:aa5281ff4a02 388 /*! @brief PXP internal memory. */
AnnaBridge 161:aa5281ff4a02 389 typedef enum _pxp_ram
AnnaBridge 161:aa5281ff4a02 390 {
AnnaBridge 161:aa5281ff4a02 391 kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */
AnnaBridge 161:aa5281ff4a02 392 kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */
AnnaBridge 161:aa5281ff4a02 393 kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */
AnnaBridge 161:aa5281ff4a02 394 } pxp_ram_t;
AnnaBridge 161:aa5281ff4a02 395
AnnaBridge 161:aa5281ff4a02 396 /*! @brief PXP dither mode. */
AnnaBridge 161:aa5281ff4a02 397 enum _pxp_dither_mode
AnnaBridge 161:aa5281ff4a02 398 {
AnnaBridge 161:aa5281ff4a02 399 kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */
AnnaBridge 161:aa5281ff4a02 400 kPXP_DitherOrdered = 3U, /*!< Ordered dither. */
AnnaBridge 161:aa5281ff4a02 401 kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */
AnnaBridge 161:aa5281ff4a02 402 };
AnnaBridge 161:aa5281ff4a02 403
AnnaBridge 161:aa5281ff4a02 404 /*! @brief PXP dither LUT mode. */
AnnaBridge 161:aa5281ff4a02 405 enum _pxp_dither_lut_mode
AnnaBridge 161:aa5281ff4a02 406 {
AnnaBridge 161:aa5281ff4a02 407 kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */
AnnaBridge 161:aa5281ff4a02 408 kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode
AnnaBridge 161:aa5281ff4a02 409 or Atkinson mode, which are not supported by current PXP module. */
AnnaBridge 161:aa5281ff4a02 410 kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */
AnnaBridge 161:aa5281ff4a02 411 };
AnnaBridge 161:aa5281ff4a02 412
AnnaBridge 161:aa5281ff4a02 413 /*! @brief PXP dither matrix size. */
AnnaBridge 161:aa5281ff4a02 414 enum _pxp_dither_matrix_size
AnnaBridge 161:aa5281ff4a02 415 {
AnnaBridge 161:aa5281ff4a02 416 kPXP_DitherMatrix8 = 1, /*!< The dither index matrix is 8x8. */
AnnaBridge 161:aa5281ff4a02 417 kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */
AnnaBridge 161:aa5281ff4a02 418 };
AnnaBridge 161:aa5281ff4a02 419
AnnaBridge 161:aa5281ff4a02 420 /*! @brief PXP dither final LUT data. */
AnnaBridge 161:aa5281ff4a02 421 typedef struct _pxp_dither_final_lut_data
AnnaBridge 161:aa5281ff4a02 422 {
AnnaBridge 161:aa5281ff4a02 423 uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */
AnnaBridge 161:aa5281ff4a02 424 uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */
AnnaBridge 161:aa5281ff4a02 425 uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */
AnnaBridge 161:aa5281ff4a02 426 uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */
AnnaBridge 161:aa5281ff4a02 427 } pxp_dither_final_lut_data_t;
AnnaBridge 161:aa5281ff4a02 428
AnnaBridge 161:aa5281ff4a02 429 /*! @brief PXP dither configuration. */
AnnaBridge 161:aa5281ff4a02 430 typedef struct _pxp_dither_config
AnnaBridge 161:aa5281ff4a02 431 {
AnnaBridge 161:aa5281ff4a02 432 uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */
AnnaBridge 161:aa5281ff4a02 433 uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */
AnnaBridge 161:aa5281ff4a02 434 uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */
AnnaBridge 161:aa5281ff4a02 435 uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */
AnnaBridge 161:aa5281ff4a02 436 uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */
AnnaBridge 161:aa5281ff4a02 437 uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */
AnnaBridge 161:aa5281ff4a02 438 uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */
AnnaBridge 161:aa5281ff4a02 439 uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref
AnnaBridge 161:aa5281ff4a02 440 kPXP_DitherLutOff
AnnaBridge 161:aa5281ff4a02 441 if any dither engine uses @ref kPXP_DitherOrdered mode. */
AnnaBridge 161:aa5281ff4a02 442 uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref
AnnaBridge 161:aa5281ff4a02 443 _pxp_dither_matrix_size. */
AnnaBridge 161:aa5281ff4a02 444 uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref
AnnaBridge 161:aa5281ff4a02 445 _pxp_dither_matrix_size. */
AnnaBridge 161:aa5281ff4a02 446 uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref
AnnaBridge 161:aa5281ff4a02 447 _pxp_dither_matrix_size. */
AnnaBridge 161:aa5281ff4a02 448 uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */
AnnaBridge 161:aa5281ff4a02 449 uint32_t : 8;
AnnaBridge 161:aa5281ff4a02 450 } pxp_dither_config_t;
AnnaBridge 161:aa5281ff4a02 451
AnnaBridge 161:aa5281ff4a02 452 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 453 * API
AnnaBridge 161:aa5281ff4a02 454 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 455
AnnaBridge 161:aa5281ff4a02 456 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 457 extern "C" {
AnnaBridge 161:aa5281ff4a02 458 #endif
AnnaBridge 161:aa5281ff4a02 459
AnnaBridge 161:aa5281ff4a02 460 /*!
AnnaBridge 161:aa5281ff4a02 461 * @name Initialization and deinitialization
AnnaBridge 161:aa5281ff4a02 462 * @{
AnnaBridge 161:aa5281ff4a02 463 */
AnnaBridge 161:aa5281ff4a02 464
AnnaBridge 161:aa5281ff4a02 465 /*!
AnnaBridge 161:aa5281ff4a02 466 * @brief Initialize the PXP.
AnnaBridge 161:aa5281ff4a02 467 *
AnnaBridge 161:aa5281ff4a02 468 * This function enables the PXP peripheral clock, and resets the PXP registers
AnnaBridge 161:aa5281ff4a02 469 * to default status.
AnnaBridge 161:aa5281ff4a02 470 *
AnnaBridge 161:aa5281ff4a02 471 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 472 */
AnnaBridge 161:aa5281ff4a02 473 void PXP_Init(PXP_Type *base);
AnnaBridge 161:aa5281ff4a02 474
AnnaBridge 161:aa5281ff4a02 475 /*!
AnnaBridge 161:aa5281ff4a02 476 * @brief De-initialize the PXP.
AnnaBridge 161:aa5281ff4a02 477 *
AnnaBridge 161:aa5281ff4a02 478 * This function disables the PXP peripheral clock.
AnnaBridge 161:aa5281ff4a02 479 *
AnnaBridge 161:aa5281ff4a02 480 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 481 */
AnnaBridge 161:aa5281ff4a02 482 void PXP_Deinit(PXP_Type *base);
AnnaBridge 161:aa5281ff4a02 483
AnnaBridge 161:aa5281ff4a02 484 /*!
AnnaBridge 161:aa5281ff4a02 485 * @brief Reset the PXP.
AnnaBridge 161:aa5281ff4a02 486 *
AnnaBridge 161:aa5281ff4a02 487 * This function resets the PXP peripheral registers to default status.
AnnaBridge 161:aa5281ff4a02 488 *
AnnaBridge 161:aa5281ff4a02 489 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 490 */
AnnaBridge 161:aa5281ff4a02 491 void PXP_Reset(PXP_Type *base);
AnnaBridge 161:aa5281ff4a02 492 /* @} */
AnnaBridge 161:aa5281ff4a02 493
AnnaBridge 161:aa5281ff4a02 494 /*!
AnnaBridge 161:aa5281ff4a02 495 * @name Global operations
AnnaBridge 161:aa5281ff4a02 496 * @{
AnnaBridge 161:aa5281ff4a02 497 */
AnnaBridge 161:aa5281ff4a02 498
AnnaBridge 161:aa5281ff4a02 499 /*!
AnnaBridge 161:aa5281ff4a02 500 * @brief Start process.
AnnaBridge 161:aa5281ff4a02 501 *
AnnaBridge 161:aa5281ff4a02 502 * Start PXP process using current configuration.
AnnaBridge 161:aa5281ff4a02 503 *
AnnaBridge 161:aa5281ff4a02 504 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 505 */
AnnaBridge 161:aa5281ff4a02 506 static inline void PXP_Start(PXP_Type *base)
AnnaBridge 161:aa5281ff4a02 507 {
AnnaBridge 161:aa5281ff4a02 508 base->CTRL_SET = PXP_CTRL_ENABLE_MASK;
AnnaBridge 161:aa5281ff4a02 509 }
AnnaBridge 161:aa5281ff4a02 510
AnnaBridge 161:aa5281ff4a02 511 /*!
AnnaBridge 161:aa5281ff4a02 512 * @brief Enable or disable LCD hand shake.
AnnaBridge 161:aa5281ff4a02 513 *
AnnaBridge 161:aa5281ff4a02 514 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 515 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 516 */
AnnaBridge 161:aa5281ff4a02 517 static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 518 {
AnnaBridge 161:aa5281ff4a02 519 #if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
AnnaBridge 161:aa5281ff4a02 520 if (enable)
AnnaBridge 161:aa5281ff4a02 521 {
AnnaBridge 161:aa5281ff4a02 522 base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
AnnaBridge 161:aa5281ff4a02 523 }
AnnaBridge 161:aa5281ff4a02 524 else
AnnaBridge 161:aa5281ff4a02 525 {
AnnaBridge 161:aa5281ff4a02 526 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
AnnaBridge 161:aa5281ff4a02 527 }
AnnaBridge 161:aa5281ff4a02 528 #else
AnnaBridge 161:aa5281ff4a02 529 if (enable)
AnnaBridge 161:aa5281ff4a02 530 {
AnnaBridge 161:aa5281ff4a02 531 base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
AnnaBridge 161:aa5281ff4a02 532 }
AnnaBridge 161:aa5281ff4a02 533 else
AnnaBridge 161:aa5281ff4a02 534 {
AnnaBridge 161:aa5281ff4a02 535 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
AnnaBridge 161:aa5281ff4a02 536 }
AnnaBridge 161:aa5281ff4a02 537 #endif
AnnaBridge 161:aa5281ff4a02 538 }
AnnaBridge 161:aa5281ff4a02 539
AnnaBridge 161:aa5281ff4a02 540 #if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT)
AnnaBridge 161:aa5281ff4a02 541 /*!
AnnaBridge 161:aa5281ff4a02 542 * @brief Enable or disable continous run.
AnnaBridge 161:aa5281ff4a02 543 *
AnnaBridge 161:aa5281ff4a02 544 * If continous run not enabled, @ref PXP_Start starts the PXP process. When completed,
AnnaBridge 161:aa5281ff4a02 545 * PXP enters idle mode and flag @ref kPXP_CompleteFlag asserts.
AnnaBridge 161:aa5281ff4a02 546 *
AnnaBridge 161:aa5281ff4a02 547 * If continous run enabled, the PXP will repeat based on the current configuration register
AnnaBridge 161:aa5281ff4a02 548 * settings.
AnnaBridge 161:aa5281ff4a02 549 *
AnnaBridge 161:aa5281ff4a02 550 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 551 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 552 */
AnnaBridge 161:aa5281ff4a02 553 static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 554 {
AnnaBridge 161:aa5281ff4a02 555 if (enable)
AnnaBridge 161:aa5281ff4a02 556 {
AnnaBridge 161:aa5281ff4a02 557 base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK;
AnnaBridge 161:aa5281ff4a02 558 }
AnnaBridge 161:aa5281ff4a02 559 else
AnnaBridge 161:aa5281ff4a02 560 {
AnnaBridge 161:aa5281ff4a02 561 base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK;
AnnaBridge 161:aa5281ff4a02 562 }
AnnaBridge 161:aa5281ff4a02 563 }
AnnaBridge 161:aa5281ff4a02 564 #endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */
AnnaBridge 161:aa5281ff4a02 565
AnnaBridge 161:aa5281ff4a02 566 /*!
AnnaBridge 161:aa5281ff4a02 567 * @brief Set the PXP processing block size
AnnaBridge 161:aa5281ff4a02 568 *
AnnaBridge 161:aa5281ff4a02 569 * This function chooses the pixel block size that PXP using during process.
AnnaBridge 161:aa5281ff4a02 570 * Larger block size means better performace, but be careful that when PXP is
AnnaBridge 161:aa5281ff4a02 571 * rotating, the output must be divisible by the block size selected.
AnnaBridge 161:aa5281ff4a02 572 *
AnnaBridge 161:aa5281ff4a02 573 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 574 * @param size The pixel block size.
AnnaBridge 161:aa5281ff4a02 575 */
AnnaBridge 161:aa5281ff4a02 576 static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)
AnnaBridge 161:aa5281ff4a02 577 {
AnnaBridge 161:aa5281ff4a02 578 base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size);
AnnaBridge 161:aa5281ff4a02 579 }
AnnaBridge 161:aa5281ff4a02 580
AnnaBridge 161:aa5281ff4a02 581 /* @} */
AnnaBridge 161:aa5281ff4a02 582
AnnaBridge 161:aa5281ff4a02 583 /*!
AnnaBridge 161:aa5281ff4a02 584 * @name Status
AnnaBridge 161:aa5281ff4a02 585 * @{
AnnaBridge 161:aa5281ff4a02 586 */
AnnaBridge 161:aa5281ff4a02 587
AnnaBridge 161:aa5281ff4a02 588 /*!
AnnaBridge 161:aa5281ff4a02 589 * @brief Gets PXP status flags.
AnnaBridge 161:aa5281ff4a02 590 *
AnnaBridge 161:aa5281ff4a02 591 * This function gets all PXP status flags. The flags are returned as the logical
AnnaBridge 161:aa5281ff4a02 592 * OR value of the enumerators @ref _pxp_flags. To check a specific status,
AnnaBridge 161:aa5281ff4a02 593 * compare the return value with enumerators in @ref _pxp_flags.
AnnaBridge 161:aa5281ff4a02 594 * For example, to check whether the PXP has completed process, use like this:
AnnaBridge 161:aa5281ff4a02 595 * @code
AnnaBridge 161:aa5281ff4a02 596 if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP))
AnnaBridge 161:aa5281ff4a02 597 {
AnnaBridge 161:aa5281ff4a02 598 ...
AnnaBridge 161:aa5281ff4a02 599 }
AnnaBridge 161:aa5281ff4a02 600 @endcode
AnnaBridge 161:aa5281ff4a02 601 *
AnnaBridge 161:aa5281ff4a02 602 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 603 * @return PXP status flags which are OR'ed by the enumerators in the _pxp_flags.
AnnaBridge 161:aa5281ff4a02 604 */
AnnaBridge 161:aa5281ff4a02 605 static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)
AnnaBridge 161:aa5281ff4a02 606 {
AnnaBridge 161:aa5281ff4a02 607 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
AnnaBridge 161:aa5281ff4a02 608 return base->STAT &
AnnaBridge 161:aa5281ff4a02 609 (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
AnnaBridge 161:aa5281ff4a02 610 PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | PXP_STAT_AXI_WRITE_ERROR_1_MASK);
AnnaBridge 161:aa5281ff4a02 611 #else
AnnaBridge 161:aa5281ff4a02 612 return base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
AnnaBridge 161:aa5281ff4a02 613 PXP_STAT_AXI_WRITE_ERROR_0_MASK);
AnnaBridge 161:aa5281ff4a02 614 #endif
AnnaBridge 161:aa5281ff4a02 615 }
AnnaBridge 161:aa5281ff4a02 616
AnnaBridge 161:aa5281ff4a02 617 /*!
AnnaBridge 161:aa5281ff4a02 618 * @brief Clears status flags with the provided mask.
AnnaBridge 161:aa5281ff4a02 619 *
AnnaBridge 161:aa5281ff4a02 620 * This function clears PXP status flags with a provided mask.
AnnaBridge 161:aa5281ff4a02 621 *
AnnaBridge 161:aa5281ff4a02 622 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 623 * @param statusMask The status flags to be cleared; it is logical OR value of @ref _pxp_flags.
AnnaBridge 161:aa5281ff4a02 624 */
AnnaBridge 161:aa5281ff4a02 625 static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)
AnnaBridge 161:aa5281ff4a02 626 {
AnnaBridge 161:aa5281ff4a02 627 base->STAT_CLR = statusMask;
AnnaBridge 161:aa5281ff4a02 628 }
AnnaBridge 161:aa5281ff4a02 629
AnnaBridge 161:aa5281ff4a02 630 /*!
AnnaBridge 161:aa5281ff4a02 631 * @brief Gets the AXI ID of the failing bus operation.
AnnaBridge 161:aa5281ff4a02 632 *
AnnaBridge 161:aa5281ff4a02 633 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 634 * @param axiIndex Whitch AXI to get
AnnaBridge 161:aa5281ff4a02 635 * - 0: AXI0
AnnaBridge 161:aa5281ff4a02 636 * - 1: AXI1
AnnaBridge 161:aa5281ff4a02 637 * @return The AXI ID of the failing bus operation.
AnnaBridge 161:aa5281ff4a02 638 */
AnnaBridge 161:aa5281ff4a02 639 static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)
AnnaBridge 161:aa5281ff4a02 640 {
AnnaBridge 161:aa5281ff4a02 641 #if defined(PXP_STAT_AXI_ERROR_ID_1_MASK)
AnnaBridge 161:aa5281ff4a02 642 if (0 == axiIndex)
AnnaBridge 161:aa5281ff4a02 643 {
AnnaBridge 161:aa5281ff4a02 644 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT);
AnnaBridge 161:aa5281ff4a02 645 }
AnnaBridge 161:aa5281ff4a02 646 else
AnnaBridge 161:aa5281ff4a02 647 {
AnnaBridge 161:aa5281ff4a02 648 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT);
AnnaBridge 161:aa5281ff4a02 649 }
AnnaBridge 161:aa5281ff4a02 650 #else
AnnaBridge 161:aa5281ff4a02 651 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT);
AnnaBridge 161:aa5281ff4a02 652 #endif
AnnaBridge 161:aa5281ff4a02 653 }
AnnaBridge 161:aa5281ff4a02 654
AnnaBridge 161:aa5281ff4a02 655 /* @} */
AnnaBridge 161:aa5281ff4a02 656
AnnaBridge 161:aa5281ff4a02 657 /*!
AnnaBridge 161:aa5281ff4a02 658 * @name Interrupts
AnnaBridge 161:aa5281ff4a02 659 * @{
AnnaBridge 161:aa5281ff4a02 660 */
AnnaBridge 161:aa5281ff4a02 661
AnnaBridge 161:aa5281ff4a02 662 /*!
AnnaBridge 161:aa5281ff4a02 663 * @brief Enables PXP interrupts according to the provided mask.
AnnaBridge 161:aa5281ff4a02 664 *
AnnaBridge 161:aa5281ff4a02 665 * This function enables the PXP interrupts according to the provided mask. The mask
AnnaBridge 161:aa5281ff4a02 666 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable.
AnnaBridge 161:aa5281ff4a02 667 * For example, to enable PXP process complete interrupt and command loaded
AnnaBridge 161:aa5281ff4a02 668 * interrupt, do the following.
AnnaBridge 161:aa5281ff4a02 669 * @code
AnnaBridge 161:aa5281ff4a02 670 PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable);
AnnaBridge 161:aa5281ff4a02 671 @endcode
AnnaBridge 161:aa5281ff4a02 672 *
AnnaBridge 161:aa5281ff4a02 673 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 674 * @param mask The interrupts to enable. Logical OR of @ref _pxp_interrupt_enable.
AnnaBridge 161:aa5281ff4a02 675 */
AnnaBridge 161:aa5281ff4a02 676 static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 677 {
AnnaBridge 161:aa5281ff4a02 678 base->CTRL_SET = mask;
AnnaBridge 161:aa5281ff4a02 679 }
AnnaBridge 161:aa5281ff4a02 680
AnnaBridge 161:aa5281ff4a02 681 /*!
AnnaBridge 161:aa5281ff4a02 682 * @brief Disables PXP interrupts according to the provided mask.
AnnaBridge 161:aa5281ff4a02 683 *
AnnaBridge 161:aa5281ff4a02 684 * This function disables the PXP interrupts according to the provided mask. The mask
AnnaBridge 161:aa5281ff4a02 685 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable.
AnnaBridge 161:aa5281ff4a02 686 *
AnnaBridge 161:aa5281ff4a02 687 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 688 * @param mask The interrupts to disable. Logical OR of @ref _pxp_interrupt_enable.
AnnaBridge 161:aa5281ff4a02 689 */
AnnaBridge 161:aa5281ff4a02 690 static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 691 {
AnnaBridge 161:aa5281ff4a02 692 base->CTRL_CLR = mask;
AnnaBridge 161:aa5281ff4a02 693 }
AnnaBridge 161:aa5281ff4a02 694
AnnaBridge 161:aa5281ff4a02 695 /* @} */
AnnaBridge 161:aa5281ff4a02 696
AnnaBridge 161:aa5281ff4a02 697 /*!
AnnaBridge 161:aa5281ff4a02 698 * @name Alpha surface
AnnaBridge 161:aa5281ff4a02 699 * @{
AnnaBridge 161:aa5281ff4a02 700 */
AnnaBridge 161:aa5281ff4a02 701
AnnaBridge 161:aa5281ff4a02 702 /*!
AnnaBridge 161:aa5281ff4a02 703 * @brief Set the alpha surface input buffer configuration.
AnnaBridge 161:aa5281ff4a02 704 *
AnnaBridge 161:aa5281ff4a02 705 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 706 * @param config Pointer to the configuration.
AnnaBridge 161:aa5281ff4a02 707 */
AnnaBridge 161:aa5281ff4a02 708 void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config);
AnnaBridge 161:aa5281ff4a02 709
AnnaBridge 161:aa5281ff4a02 710 /*!
AnnaBridge 161:aa5281ff4a02 711 * @brief Set the alpha surface blending configuration.
AnnaBridge 161:aa5281ff4a02 712 *
AnnaBridge 161:aa5281ff4a02 713 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 714 * @param config Pointer to the configuration structure.
AnnaBridge 161:aa5281ff4a02 715 */
AnnaBridge 161:aa5281ff4a02 716 void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config);
AnnaBridge 161:aa5281ff4a02 717
AnnaBridge 161:aa5281ff4a02 718 /*!
AnnaBridge 161:aa5281ff4a02 719 * @brief Set the alpha surface overlay color key.
AnnaBridge 161:aa5281ff4a02 720 *
AnnaBridge 161:aa5281ff4a02 721 * If a pixel in the current overlay image with a color that falls in the range
AnnaBridge 161:aa5281ff4a02 722 * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface
AnnaBridge 161:aa5281ff4a02 723 * pixel value for that location. If no PS image is present or if the PS image also
AnnaBridge 161:aa5281ff4a02 724 * matches its colorkey range, the PS background color is used.
AnnaBridge 161:aa5281ff4a02 725 *
AnnaBridge 161:aa5281ff4a02 726 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 727 * @param colorKeyLow Color key low range.
AnnaBridge 161:aa5281ff4a02 728 * @param colorKeyHigh Color key high range.
AnnaBridge 161:aa5281ff4a02 729 *
AnnaBridge 161:aa5281ff4a02 730 * @note Colorkey operations are higher priority than alpha or ROP operations
AnnaBridge 161:aa5281ff4a02 731 */
AnnaBridge 161:aa5281ff4a02 732 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
AnnaBridge 161:aa5281ff4a02 733
AnnaBridge 161:aa5281ff4a02 734 /*!
AnnaBridge 161:aa5281ff4a02 735 * @brief Enable or disable the alpha surface color key.
AnnaBridge 161:aa5281ff4a02 736 *
AnnaBridge 161:aa5281ff4a02 737 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 738 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 739 */
AnnaBridge 161:aa5281ff4a02 740 static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 741 {
AnnaBridge 161:aa5281ff4a02 742 if (enable)
AnnaBridge 161:aa5281ff4a02 743 {
AnnaBridge 161:aa5281ff4a02 744 base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
AnnaBridge 161:aa5281ff4a02 745 }
AnnaBridge 161:aa5281ff4a02 746 {
AnnaBridge 161:aa5281ff4a02 747 base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
AnnaBridge 161:aa5281ff4a02 748 }
AnnaBridge 161:aa5281ff4a02 749 }
AnnaBridge 161:aa5281ff4a02 750
AnnaBridge 161:aa5281ff4a02 751 /*!
AnnaBridge 161:aa5281ff4a02 752 * @brief Set the alpha surface position in output buffer.
AnnaBridge 161:aa5281ff4a02 753 *
AnnaBridge 161:aa5281ff4a02 754 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 755 * @param upperLeftX X of the upper left corner.
AnnaBridge 161:aa5281ff4a02 756 * @param upperLeftY Y of the upper left corner.
AnnaBridge 161:aa5281ff4a02 757 * @param lowerRightX X of the lower right corner.
AnnaBridge 161:aa5281ff4a02 758 * @param lowerRightY Y of the lower right corner.
AnnaBridge 161:aa5281ff4a02 759 */
AnnaBridge 161:aa5281ff4a02 760 void PXP_SetAlphaSurfacePosition(
AnnaBridge 161:aa5281ff4a02 761 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
AnnaBridge 161:aa5281ff4a02 762 /* @} */
AnnaBridge 161:aa5281ff4a02 763
AnnaBridge 161:aa5281ff4a02 764 /*!
AnnaBridge 161:aa5281ff4a02 765 * @name Process surface
AnnaBridge 161:aa5281ff4a02 766 * @{
AnnaBridge 161:aa5281ff4a02 767 */
AnnaBridge 161:aa5281ff4a02 768
AnnaBridge 161:aa5281ff4a02 769 /*!
AnnaBridge 161:aa5281ff4a02 770 * @brief Set the back ground color of PS.
AnnaBridge 161:aa5281ff4a02 771 *
AnnaBridge 161:aa5281ff4a02 772 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 773 * @param backGroundColor Pixel value of the background color.
AnnaBridge 161:aa5281ff4a02 774 */
AnnaBridge 161:aa5281ff4a02 775 static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor)
AnnaBridge 161:aa5281ff4a02 776 {
AnnaBridge 161:aa5281ff4a02 777 #if defined(PXP_PS_BACKGROUND_0_COLOR_MASK)
AnnaBridge 161:aa5281ff4a02 778 base->PS_BACKGROUND_0 = backGroundColor;
AnnaBridge 161:aa5281ff4a02 779 #else
AnnaBridge 161:aa5281ff4a02 780 base->PS_BACKGROUND = backGroundColor;
AnnaBridge 161:aa5281ff4a02 781 #endif
AnnaBridge 161:aa5281ff4a02 782 }
AnnaBridge 161:aa5281ff4a02 783
AnnaBridge 161:aa5281ff4a02 784 /*!
AnnaBridge 161:aa5281ff4a02 785 * @brief Set the process surface input buffer configuration.
AnnaBridge 161:aa5281ff4a02 786 *
AnnaBridge 161:aa5281ff4a02 787 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 788 * @param config Pointer to the configuration.
AnnaBridge 161:aa5281ff4a02 789 */
AnnaBridge 161:aa5281ff4a02 790 void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config);
AnnaBridge 161:aa5281ff4a02 791
AnnaBridge 161:aa5281ff4a02 792 /*!
AnnaBridge 161:aa5281ff4a02 793 * @brief Set the process surface scaler configuration.
AnnaBridge 161:aa5281ff4a02 794 *
AnnaBridge 161:aa5281ff4a02 795 * The valid down scale fact is 1/(2^12) ~ 16.
AnnaBridge 161:aa5281ff4a02 796 *
AnnaBridge 161:aa5281ff4a02 797 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 798 * @param inputWidth Input image width.
AnnaBridge 161:aa5281ff4a02 799 * @param inputHeight Input image height.
AnnaBridge 161:aa5281ff4a02 800 * @param outputWidth Output image width.
AnnaBridge 161:aa5281ff4a02 801 * @param outputHeight Output image height.
AnnaBridge 161:aa5281ff4a02 802 */
AnnaBridge 161:aa5281ff4a02 803 void PXP_SetProcessSurfaceScaler(
AnnaBridge 161:aa5281ff4a02 804 PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight);
AnnaBridge 161:aa5281ff4a02 805
AnnaBridge 161:aa5281ff4a02 806 /*!
AnnaBridge 161:aa5281ff4a02 807 * @brief Set the process surface position in output buffer.
AnnaBridge 161:aa5281ff4a02 808 *
AnnaBridge 161:aa5281ff4a02 809 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 810 * @param upperLeftX X of the upper left corner.
AnnaBridge 161:aa5281ff4a02 811 * @param upperLeftY Y of the upper left corner.
AnnaBridge 161:aa5281ff4a02 812 * @param lowerRightX X of the lower right corner.
AnnaBridge 161:aa5281ff4a02 813 * @param lowerRightY Y of the lower right corner.
AnnaBridge 161:aa5281ff4a02 814 */
AnnaBridge 161:aa5281ff4a02 815 void PXP_SetProcessSurfacePosition(
AnnaBridge 161:aa5281ff4a02 816 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
AnnaBridge 161:aa5281ff4a02 817
AnnaBridge 161:aa5281ff4a02 818 /*!
AnnaBridge 161:aa5281ff4a02 819 * @brief Set the process surface color key.
AnnaBridge 161:aa5281ff4a02 820 *
AnnaBridge 161:aa5281ff4a02 821 * If the PS image matches colorkey range, the PS background color is output. Set
AnnaBridge 161:aa5281ff4a02 822 * @p colorKeyLow to 0xFFFFFFFF and @p colorKeyHigh to 0 will disable the colorkeying.
AnnaBridge 161:aa5281ff4a02 823 *
AnnaBridge 161:aa5281ff4a02 824 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 825 * @param colorKeyLow Color key low range.
AnnaBridge 161:aa5281ff4a02 826 * @param colorKeyHigh Color key high range.
AnnaBridge 161:aa5281ff4a02 827 */
AnnaBridge 161:aa5281ff4a02 828 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
AnnaBridge 161:aa5281ff4a02 829 /* @} */
AnnaBridge 161:aa5281ff4a02 830
AnnaBridge 161:aa5281ff4a02 831 /*!
AnnaBridge 161:aa5281ff4a02 832 * @name Output buffer
AnnaBridge 161:aa5281ff4a02 833 * @{
AnnaBridge 161:aa5281ff4a02 834 */
AnnaBridge 161:aa5281ff4a02 835
AnnaBridge 161:aa5281ff4a02 836 /*!
AnnaBridge 161:aa5281ff4a02 837 * @brief Set the PXP outpt buffer configuration.
AnnaBridge 161:aa5281ff4a02 838 *
AnnaBridge 161:aa5281ff4a02 839 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 840 * @param config Pointer to the configuration.
AnnaBridge 161:aa5281ff4a02 841 */
AnnaBridge 161:aa5281ff4a02 842 void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config);
AnnaBridge 161:aa5281ff4a02 843
AnnaBridge 161:aa5281ff4a02 844 /*!
AnnaBridge 161:aa5281ff4a02 845 * @brief Set the global overwritten alpha value.
AnnaBridge 161:aa5281ff4a02 846 *
AnnaBridge 161:aa5281ff4a02 847 * If global overwritten alpha is enabled, the alpha component in output buffer pixels
AnnaBridge 161:aa5281ff4a02 848 * will be overwritten, otherwise the computed alpha value is used.
AnnaBridge 161:aa5281ff4a02 849 *
AnnaBridge 161:aa5281ff4a02 850 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 851 * @param alpha The alpha value.
AnnaBridge 161:aa5281ff4a02 852 */
AnnaBridge 161:aa5281ff4a02 853 static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)
AnnaBridge 161:aa5281ff4a02 854 {
AnnaBridge 161:aa5281ff4a02 855 base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha);
AnnaBridge 161:aa5281ff4a02 856 }
AnnaBridge 161:aa5281ff4a02 857
AnnaBridge 161:aa5281ff4a02 858 /*!
AnnaBridge 161:aa5281ff4a02 859 * @brief Enable or disable the global overwritten alpha value.
AnnaBridge 161:aa5281ff4a02 860 *
AnnaBridge 161:aa5281ff4a02 861 * If global overwritten alpha is enabled, the alpha component in output buffer pixels
AnnaBridge 161:aa5281ff4a02 862 * will be overwritten, otherwise the computed alpha value is used.
AnnaBridge 161:aa5281ff4a02 863 *
AnnaBridge 161:aa5281ff4a02 864 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 865 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 866 */
AnnaBridge 161:aa5281ff4a02 867 static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 868 {
AnnaBridge 161:aa5281ff4a02 869 if (enable)
AnnaBridge 161:aa5281ff4a02 870 {
AnnaBridge 161:aa5281ff4a02 871 base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
AnnaBridge 161:aa5281ff4a02 872 }
AnnaBridge 161:aa5281ff4a02 873 else
AnnaBridge 161:aa5281ff4a02 874 {
AnnaBridge 161:aa5281ff4a02 875 base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
AnnaBridge 161:aa5281ff4a02 876 }
AnnaBridge 161:aa5281ff4a02 877 }
AnnaBridge 161:aa5281ff4a02 878
AnnaBridge 161:aa5281ff4a02 879 /*!
AnnaBridge 161:aa5281ff4a02 880 * @brief Set the rotation configuration.
AnnaBridge 161:aa5281ff4a02 881 *
AnnaBridge 161:aa5281ff4a02 882 * The PXP could rotate the process surface or the output buffer. There are
AnnaBridge 161:aa5281ff4a02 883 * two PXP versions:
AnnaBridge 161:aa5281ff4a02 884 * - Version 1: Only has one rotate sub module, the output buffer and process
AnnaBridge 161:aa5281ff4a02 885 * surface share the same rotate sub module, which means the process surface
AnnaBridge 161:aa5281ff4a02 886 * and output buffer could not be rotate at the same time. When pass in
AnnaBridge 161:aa5281ff4a02 887 * @ref kPXP_RotateOutputBuffer, the process surface could not use the rotate,
AnnaBridge 161:aa5281ff4a02 888 * Also when pass in @ref kPXP_RotateProcessSurface, output buffer could not
AnnaBridge 161:aa5281ff4a02 889 * use the rotate.
AnnaBridge 161:aa5281ff4a02 890 * - Version 2: Has two seperate rotate sub modules, the output buffer and
AnnaBridge 161:aa5281ff4a02 891 * process surface could configure the rotation independently.
AnnaBridge 161:aa5281ff4a02 892 *
AnnaBridge 161:aa5281ff4a02 893 * Upper layer could use the macro PXP_SHARE_ROTATE to check which version is.
AnnaBridge 161:aa5281ff4a02 894 * PXP_SHARE_ROTATE=1 means version 1.
AnnaBridge 161:aa5281ff4a02 895 *
AnnaBridge 161:aa5281ff4a02 896 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 897 * @param position Rotate process surface or output buffer.
AnnaBridge 161:aa5281ff4a02 898 * @param degree Rotate degree.
AnnaBridge 161:aa5281ff4a02 899 * @param flipMode Flip mode.
AnnaBridge 161:aa5281ff4a02 900 *
AnnaBridge 161:aa5281ff4a02 901 * @note This function is different depends on the macro PXP_SHARE_ROTATE.
AnnaBridge 161:aa5281ff4a02 902 */
AnnaBridge 161:aa5281ff4a02 903 static inline void PXP_SetRotateConfig(PXP_Type *base,
AnnaBridge 161:aa5281ff4a02 904 pxp_rotate_position_t position,
AnnaBridge 161:aa5281ff4a02 905 pxp_rotate_degree_t degree,
AnnaBridge 161:aa5281ff4a02 906 pxp_flip_mode_t flipMode)
AnnaBridge 161:aa5281ff4a02 907 {
AnnaBridge 161:aa5281ff4a02 908 #if PXP_SHARE_ROTATE
AnnaBridge 161:aa5281ff4a02 909 base->CTRL =
AnnaBridge 161:aa5281ff4a02 910 (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) |
AnnaBridge 161:aa5281ff4a02 911 PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT);
AnnaBridge 161:aa5281ff4a02 912 #else
AnnaBridge 161:aa5281ff4a02 913 uint32_t ctrl = base->CTRL;
AnnaBridge 161:aa5281ff4a02 914
AnnaBridge 161:aa5281ff4a02 915 if (kPXP_RotateOutputBuffer == position)
AnnaBridge 161:aa5281ff4a02 916 {
AnnaBridge 161:aa5281ff4a02 917 ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK);
AnnaBridge 161:aa5281ff4a02 918 ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT));
AnnaBridge 161:aa5281ff4a02 919 }
AnnaBridge 161:aa5281ff4a02 920 else
AnnaBridge 161:aa5281ff4a02 921 {
AnnaBridge 161:aa5281ff4a02 922 ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK);
AnnaBridge 161:aa5281ff4a02 923 ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT));
AnnaBridge 161:aa5281ff4a02 924 }
AnnaBridge 161:aa5281ff4a02 925
AnnaBridge 161:aa5281ff4a02 926 base->CTRL = ctrl;
AnnaBridge 161:aa5281ff4a02 927 #endif
AnnaBridge 161:aa5281ff4a02 928 }
AnnaBridge 161:aa5281ff4a02 929 /* @} */
AnnaBridge 161:aa5281ff4a02 930
AnnaBridge 161:aa5281ff4a02 931 /*!
AnnaBridge 161:aa5281ff4a02 932 * @name Command queue
AnnaBridge 161:aa5281ff4a02 933 * @{
AnnaBridge 161:aa5281ff4a02 934 */
AnnaBridge 161:aa5281ff4a02 935
AnnaBridge 161:aa5281ff4a02 936 /*!
AnnaBridge 161:aa5281ff4a02 937 * @brief Set the next command.
AnnaBridge 161:aa5281ff4a02 938 *
AnnaBridge 161:aa5281ff4a02 939 * The PXP supports a primitive ability to queue up one operation while the current
AnnaBridge 161:aa5281ff4a02 940 * operation is running. Workflow:
AnnaBridge 161:aa5281ff4a02 941 *
AnnaBridge 161:aa5281ff4a02 942 * 1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory
AnnaBridge 161:aa5281ff4a02 943 * in the order they appear in the register map.
AnnaBridge 161:aa5281ff4a02 944 * 2. Call this function sets the new operation to PXP.
AnnaBridge 161:aa5281ff4a02 945 * 3. There are two methods to check whether the PXP has loaded the new operation.
AnnaBridge 161:aa5281ff4a02 946 * The first method is using @ref PXP_IsNextCommandPending. If there is new operation
AnnaBridge 161:aa5281ff4a02 947 * not loaded by the PXP, this function returns true. The second method is checking
AnnaBridge 161:aa5281ff4a02 948 * the flag @ref kPXP_CommandLoadFlag, if command loaded, this flag asserts. User
AnnaBridge 161:aa5281ff4a02 949 * could enable interrupt @ref kPXP_CommandLoadInterruptEnable to get the loaded
AnnaBridge 161:aa5281ff4a02 950 * signal in interrupt way.
AnnaBridge 161:aa5281ff4a02 951 * 4. When command loaded by PXP, a new command could be set using this function.
AnnaBridge 161:aa5281ff4a02 952 *
AnnaBridge 161:aa5281ff4a02 953 * @code
AnnaBridge 161:aa5281ff4a02 954 uint32_t pxp_command1[48];
AnnaBridge 161:aa5281ff4a02 955 uint32_t pxp_command2[48];
AnnaBridge 161:aa5281ff4a02 956
AnnaBridge 161:aa5281ff4a02 957 // Prepare the register values.
AnnaBridge 161:aa5281ff4a02 958 pxp_command1[0] = ...;
AnnaBridge 161:aa5281ff4a02 959 pxp_command1[1] = ...;
AnnaBridge 161:aa5281ff4a02 960 // ...
AnnaBridge 161:aa5281ff4a02 961 pxp_command2[0] = ...;
AnnaBridge 161:aa5281ff4a02 962 pxp_command2[1] = ...;
AnnaBridge 161:aa5281ff4a02 963 // ...
AnnaBridge 161:aa5281ff4a02 964
AnnaBridge 161:aa5281ff4a02 965 // Make sure no new command pending.
AnnaBridge 161:aa5281ff4a02 966 while (PXP_IsNextCommandPending(PXP))
AnnaBridge 161:aa5281ff4a02 967 {
AnnaBridge 161:aa5281ff4a02 968 }
AnnaBridge 161:aa5281ff4a02 969
AnnaBridge 161:aa5281ff4a02 970 // Set new operation.
AnnaBridge 161:aa5281ff4a02 971 PXP_SetNextCommand(PXP, pxp_command1);
AnnaBridge 161:aa5281ff4a02 972
AnnaBridge 161:aa5281ff4a02 973 // Wait for new command loaded. Here could check @ref kPXP_CommandLoadFlag too.
AnnaBridge 161:aa5281ff4a02 974 while (PXP_IsNextCommandPending(PXP))
AnnaBridge 161:aa5281ff4a02 975 {
AnnaBridge 161:aa5281ff4a02 976 }
AnnaBridge 161:aa5281ff4a02 977
AnnaBridge 161:aa5281ff4a02 978 PXP_SetNextCommand(PXP, pxp_command2);
AnnaBridge 161:aa5281ff4a02 979 @endcode
AnnaBridge 161:aa5281ff4a02 980 *
AnnaBridge 161:aa5281ff4a02 981 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 982 * @param commandAddr Address of the new command.
AnnaBridge 161:aa5281ff4a02 983 */
AnnaBridge 161:aa5281ff4a02 984 static inline void PXP_SetNextCommand(PXP_Type *base, void *commandAddr)
AnnaBridge 161:aa5281ff4a02 985 {
AnnaBridge 161:aa5281ff4a02 986 /* Make sure commands have been saved to memory. */
AnnaBridge 161:aa5281ff4a02 987 __DSB();
AnnaBridge 161:aa5281ff4a02 988
AnnaBridge 161:aa5281ff4a02 989 base->NEXT = (uint32_t)commandAddr & PXP_NEXT_POINTER_MASK;
AnnaBridge 161:aa5281ff4a02 990 }
AnnaBridge 161:aa5281ff4a02 991
AnnaBridge 161:aa5281ff4a02 992 /*!
AnnaBridge 161:aa5281ff4a02 993 * @brief Check whether the next command is pending.
AnnaBridge 161:aa5281ff4a02 994 *
AnnaBridge 161:aa5281ff4a02 995 * @param base UART peripheral base address.
AnnaBridge 161:aa5281ff4a02 996 * @return True is pending, false is not.
AnnaBridge 161:aa5281ff4a02 997 */
AnnaBridge 161:aa5281ff4a02 998 static inline bool PXP_IsNextCommandPending(PXP_Type *base)
AnnaBridge 161:aa5281ff4a02 999 {
AnnaBridge 161:aa5281ff4a02 1000 return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK);
AnnaBridge 161:aa5281ff4a02 1001 }
AnnaBridge 161:aa5281ff4a02 1002
AnnaBridge 161:aa5281ff4a02 1003 /*!
AnnaBridge 161:aa5281ff4a02 1004 * @brief Cancel command set by @ref PXP_SetNextCommand
AnnaBridge 161:aa5281ff4a02 1005 *
AnnaBridge 161:aa5281ff4a02 1006 * @param base UART peripheral base address.
AnnaBridge 161:aa5281ff4a02 1007 */
AnnaBridge 161:aa5281ff4a02 1008 static inline void PXP_CancelNextCommand(PXP_Type *base)
AnnaBridge 161:aa5281ff4a02 1009 {
AnnaBridge 161:aa5281ff4a02 1010 /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */
AnnaBridge 161:aa5281ff4a02 1011 *((volatile uint32_t *)(&(base->NEXT)) + 2U) = PXP_NEXT_ENABLED_MASK;
AnnaBridge 161:aa5281ff4a02 1012 }
AnnaBridge 161:aa5281ff4a02 1013
AnnaBridge 161:aa5281ff4a02 1014 /* @} */
AnnaBridge 161:aa5281ff4a02 1015
AnnaBridge 161:aa5281ff4a02 1016 /*!
AnnaBridge 161:aa5281ff4a02 1017 * @name Color space conversion
AnnaBridge 161:aa5281ff4a02 1018 * @{
AnnaBridge 161:aa5281ff4a02 1019 */
AnnaBridge 161:aa5281ff4a02 1020
AnnaBridge 161:aa5281ff4a02 1021 #if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2)
AnnaBridge 161:aa5281ff4a02 1022 /*!
AnnaBridge 161:aa5281ff4a02 1023 * @brief Set the CSC2 configuration.
AnnaBridge 161:aa5281ff4a02 1024 *
AnnaBridge 161:aa5281ff4a02 1025 * The CSC2 module receives pixels in any color space and can convert the pixels
AnnaBridge 161:aa5281ff4a02 1026 * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed
AnnaBridge 161:aa5281ff4a02 1027 * onto the LUT and rotation engine for further processing
AnnaBridge 161:aa5281ff4a02 1028 *
AnnaBridge 161:aa5281ff4a02 1029 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1030 * @param config Pointer to the configuration.
AnnaBridge 161:aa5281ff4a02 1031 */
AnnaBridge 161:aa5281ff4a02 1032 void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config);
AnnaBridge 161:aa5281ff4a02 1033
AnnaBridge 161:aa5281ff4a02 1034 /*!
AnnaBridge 161:aa5281ff4a02 1035 * @brief Enable or disable the CSC2.
AnnaBridge 161:aa5281ff4a02 1036 *
AnnaBridge 161:aa5281ff4a02 1037 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1038 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 1039 */
AnnaBridge 161:aa5281ff4a02 1040 static inline void PXP_EnableCsc2(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 1041 {
AnnaBridge 161:aa5281ff4a02 1042 if (enable)
AnnaBridge 161:aa5281ff4a02 1043 {
AnnaBridge 161:aa5281ff4a02 1044 base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK;
AnnaBridge 161:aa5281ff4a02 1045 }
AnnaBridge 161:aa5281ff4a02 1046 else
AnnaBridge 161:aa5281ff4a02 1047 {
AnnaBridge 161:aa5281ff4a02 1048 base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK;
AnnaBridge 161:aa5281ff4a02 1049 }
AnnaBridge 161:aa5281ff4a02 1050 }
AnnaBridge 161:aa5281ff4a02 1051 #endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */
AnnaBridge 161:aa5281ff4a02 1052
AnnaBridge 161:aa5281ff4a02 1053 /*!
AnnaBridge 161:aa5281ff4a02 1054 * @brief Set the CSC1 mode.
AnnaBridge 161:aa5281ff4a02 1055 *
AnnaBridge 161:aa5281ff4a02 1056 * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and
AnnaBridge 161:aa5281ff4a02 1057 * converts the pixels to the RGB888 color space. It could only be used by process
AnnaBridge 161:aa5281ff4a02 1058 * surface.
AnnaBridge 161:aa5281ff4a02 1059 *
AnnaBridge 161:aa5281ff4a02 1060 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1061 * @param mode The conversion mode.
AnnaBridge 161:aa5281ff4a02 1062 */
AnnaBridge 161:aa5281ff4a02 1063 void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode);
AnnaBridge 161:aa5281ff4a02 1064
AnnaBridge 161:aa5281ff4a02 1065 /*!
AnnaBridge 161:aa5281ff4a02 1066 * @brief Enable or disable the CSC1.
AnnaBridge 161:aa5281ff4a02 1067 *
AnnaBridge 161:aa5281ff4a02 1068 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1069 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 1070 */
AnnaBridge 161:aa5281ff4a02 1071 static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 1072 {
AnnaBridge 161:aa5281ff4a02 1073 if (enable)
AnnaBridge 161:aa5281ff4a02 1074 {
AnnaBridge 161:aa5281ff4a02 1075 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK;
AnnaBridge 161:aa5281ff4a02 1076 }
AnnaBridge 161:aa5281ff4a02 1077 else
AnnaBridge 161:aa5281ff4a02 1078 {
AnnaBridge 161:aa5281ff4a02 1079 base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK;
AnnaBridge 161:aa5281ff4a02 1080 }
AnnaBridge 161:aa5281ff4a02 1081 }
AnnaBridge 161:aa5281ff4a02 1082 /* @} */
AnnaBridge 161:aa5281ff4a02 1083
AnnaBridge 161:aa5281ff4a02 1084 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
AnnaBridge 161:aa5281ff4a02 1085 /*!
AnnaBridge 161:aa5281ff4a02 1086 * @name LUT operations
AnnaBridge 161:aa5281ff4a02 1087 * @{
AnnaBridge 161:aa5281ff4a02 1088 */
AnnaBridge 161:aa5281ff4a02 1089
AnnaBridge 161:aa5281ff4a02 1090 /*!
AnnaBridge 161:aa5281ff4a02 1091 * @brief Set the LUT configuration.
AnnaBridge 161:aa5281ff4a02 1092 *
AnnaBridge 161:aa5281ff4a02 1093 * The lookup table (LUT) is used to modify pixels in a manner that is not linear
AnnaBridge 161:aa5281ff4a02 1094 * and that cannot be achieved by the color space conversion modules. To setup
AnnaBridge 161:aa5281ff4a02 1095 * the LUT, the complete workflow is:
AnnaBridge 161:aa5281ff4a02 1096 * 1. Use @ref PXP_SetLutConfig to set the configuration, such as the lookup mode.
AnnaBridge 161:aa5281ff4a02 1097 * 2. Use @ref PXP_LoadLutTable to load the lookup table to PXP.
AnnaBridge 161:aa5281ff4a02 1098 * 3. Use @ref PXP_EnableLut to enable the function.
AnnaBridge 161:aa5281ff4a02 1099 *
AnnaBridge 161:aa5281ff4a02 1100 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1101 * @param config Pointer to the configuration.
AnnaBridge 161:aa5281ff4a02 1102 */
AnnaBridge 161:aa5281ff4a02 1103 void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config);
AnnaBridge 161:aa5281ff4a02 1104
AnnaBridge 161:aa5281ff4a02 1105 /*!
AnnaBridge 161:aa5281ff4a02 1106 * @brief Set the look up table to PXP.
AnnaBridge 161:aa5281ff4a02 1107 *
AnnaBridge 161:aa5281ff4a02 1108 * If lookup mode is DIRECT mode, this function loads @p bytesNum of values
AnnaBridge 161:aa5281ff4a02 1109 * from the address @p memAddr into PXP LUT address @p lutStartAddr. So this
AnnaBridge 161:aa5281ff4a02 1110 * function allows only update part of the PXP LUT.
AnnaBridge 161:aa5281ff4a02 1111 *
AnnaBridge 161:aa5281ff4a02 1112 * If lookup mode is CACHE mode, this function sets the new address to @p memAddr
AnnaBridge 161:aa5281ff4a02 1113 * and invalid the PXP LUT cache.
AnnaBridge 161:aa5281ff4a02 1114 *
AnnaBridge 161:aa5281ff4a02 1115 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1116 * @param lookupMode Which lookup mode is used. Note that this parameter is only
AnnaBridge 161:aa5281ff4a02 1117 * used to distinguish DIRECT mode and CACHE mode, it does not change the register
AnnaBridge 161:aa5281ff4a02 1118 * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function @ref PXP_SetLutConfig.
AnnaBridge 161:aa5281ff4a02 1119 * @param bytesNum How many bytes to set. This value must be divisable by 8.
AnnaBridge 161:aa5281ff4a02 1120 * @param memAddr Address of look up table to set.
AnnaBridge 161:aa5281ff4a02 1121 * @param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should
AnnaBridge 161:aa5281ff4a02 1122 * be 8 bytes aligned.
AnnaBridge 161:aa5281ff4a02 1123 *
AnnaBridge 161:aa5281ff4a02 1124 * @retval kStatus_Success Load successfully.
AnnaBridge 161:aa5281ff4a02 1125 * @retval kStatus_InvalidArgument Failed because of invalid argument.
AnnaBridge 161:aa5281ff4a02 1126 */
AnnaBridge 161:aa5281ff4a02 1127 status_t PXP_LoadLutTable(
AnnaBridge 161:aa5281ff4a02 1128 PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr);
AnnaBridge 161:aa5281ff4a02 1129
AnnaBridge 161:aa5281ff4a02 1130 /*!
AnnaBridge 161:aa5281ff4a02 1131 * @brief Enable or disable the LUT.
AnnaBridge 161:aa5281ff4a02 1132 *
AnnaBridge 161:aa5281ff4a02 1133 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1134 * @param enable True to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 1135 */
AnnaBridge 161:aa5281ff4a02 1136 static inline void PXP_EnableLut(PXP_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 1137 {
AnnaBridge 161:aa5281ff4a02 1138 if (enable)
AnnaBridge 161:aa5281ff4a02 1139 {
AnnaBridge 161:aa5281ff4a02 1140 base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK;
AnnaBridge 161:aa5281ff4a02 1141 }
AnnaBridge 161:aa5281ff4a02 1142 else
AnnaBridge 161:aa5281ff4a02 1143 {
AnnaBridge 161:aa5281ff4a02 1144 base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK;
AnnaBridge 161:aa5281ff4a02 1145 }
AnnaBridge 161:aa5281ff4a02 1146 }
AnnaBridge 161:aa5281ff4a02 1147
AnnaBridge 161:aa5281ff4a02 1148 /*!
AnnaBridge 161:aa5281ff4a02 1149 * @brief Select the 8kB LUT bank in DIRECT_RGB444 mode.
AnnaBridge 161:aa5281ff4a02 1150 *
AnnaBridge 161:aa5281ff4a02 1151 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1152 * @param bank The bank to select.
AnnaBridge 161:aa5281ff4a02 1153 */
AnnaBridge 161:aa5281ff4a02 1154 static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank)
AnnaBridge 161:aa5281ff4a02 1155 {
AnnaBridge 161:aa5281ff4a02 1156 base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank);
AnnaBridge 161:aa5281ff4a02 1157 }
AnnaBridge 161:aa5281ff4a02 1158 /* @} */
AnnaBridge 161:aa5281ff4a02 1159 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
AnnaBridge 161:aa5281ff4a02 1160
AnnaBridge 161:aa5281ff4a02 1161 #if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER)
AnnaBridge 161:aa5281ff4a02 1162 /*!
AnnaBridge 161:aa5281ff4a02 1163 * @name Dither
AnnaBridge 161:aa5281ff4a02 1164 * @{
AnnaBridge 161:aa5281ff4a02 1165 */
AnnaBridge 161:aa5281ff4a02 1166
AnnaBridge 161:aa5281ff4a02 1167 /*!
AnnaBridge 161:aa5281ff4a02 1168 * @brief Write data to the PXP internal memory.
AnnaBridge 161:aa5281ff4a02 1169 *
AnnaBridge 161:aa5281ff4a02 1170 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1171 * @param ram Which internal memory to write.
AnnaBridge 161:aa5281ff4a02 1172 * @param bytesNum How many bytes to write.
AnnaBridge 161:aa5281ff4a02 1173 * @param data Pointer to the data to write.
AnnaBridge 161:aa5281ff4a02 1174 * @param memStartAddr The start address in the internal memory to write the data.
AnnaBridge 161:aa5281ff4a02 1175 */
AnnaBridge 161:aa5281ff4a02 1176 void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr);
AnnaBridge 161:aa5281ff4a02 1177
AnnaBridge 161:aa5281ff4a02 1178 /*!
AnnaBridge 161:aa5281ff4a02 1179 * @brief Set the dither final LUT data.
AnnaBridge 161:aa5281ff4a02 1180 *
AnnaBridge 161:aa5281ff4a02 1181 * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4]
AnnaBridge 161:aa5281ff4a02 1182 * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate
AnnaBridge 161:aa5281ff4a02 1183 * the final output pixel to the next process module.
AnnaBridge 161:aa5281ff4a02 1184 *
AnnaBridge 161:aa5281ff4a02 1185 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1186 * @param data Pointer to the LUT data to set.
AnnaBridge 161:aa5281ff4a02 1187 */
AnnaBridge 161:aa5281ff4a02 1188 void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data);
AnnaBridge 161:aa5281ff4a02 1189
AnnaBridge 161:aa5281ff4a02 1190 /*!
AnnaBridge 161:aa5281ff4a02 1191 * @brief Set the configuration for the dither block.
AnnaBridge 161:aa5281ff4a02 1192 *
AnnaBridge 161:aa5281ff4a02 1193 * If the pre-dither LUT, post-dither LUT or ordered dither is used, please call
AnnaBridge 161:aa5281ff4a02 1194 * @ref PXP_SetInternalRamData to set the LUT data to internal memory.
AnnaBridge 161:aa5281ff4a02 1195 *
AnnaBridge 161:aa5281ff4a02 1196 * If the final LUT is used, please call @ref PXP_SetDitherFinalLutData to set
AnnaBridge 161:aa5281ff4a02 1197 * the LUT data.
AnnaBridge 161:aa5281ff4a02 1198 *
AnnaBridge 161:aa5281ff4a02 1199 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1200 * @param config Pointer to the configuration.
AnnaBridge 161:aa5281ff4a02 1201 *
AnnaBridge 161:aa5281ff4a02 1202 * @note When using ordered dithering, please set the PXP process block size same
AnnaBridge 161:aa5281ff4a02 1203 * with the ordered dithering matrix size using function @ref PXP_SetProcessBlockSize.
AnnaBridge 161:aa5281ff4a02 1204 */
AnnaBridge 161:aa5281ff4a02 1205 static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)
AnnaBridge 161:aa5281ff4a02 1206 {
AnnaBridge 161:aa5281ff4a02 1207 base->DITHER_CTRL = *((const uint32_t *)config) & 0x00FFFFFFU;
AnnaBridge 161:aa5281ff4a02 1208 }
AnnaBridge 161:aa5281ff4a02 1209
AnnaBridge 161:aa5281ff4a02 1210 /*!
AnnaBridge 161:aa5281ff4a02 1211 * @brief Enable or disable dither engine in the PXP process path.
AnnaBridge 161:aa5281ff4a02 1212 *
AnnaBridge 161:aa5281ff4a02 1213 * After the initialize function @ref PXP_Init, the dither engine is disabled and not
AnnaBridge 161:aa5281ff4a02 1214 * use in the PXP processing path. This function enables the dither engine and
AnnaBridge 161:aa5281ff4a02 1215 * routes the dither engine output to the output buffer. When the dither engine
AnnaBridge 161:aa5281ff4a02 1216 * is enabled using this function, @ref PXP_SetDitherConfig must be called to
AnnaBridge 161:aa5281ff4a02 1217 * configure dither engine correctly, otherwise there is not output to the output
AnnaBridge 161:aa5281ff4a02 1218 * buffer.
AnnaBridge 161:aa5281ff4a02 1219 *
AnnaBridge 161:aa5281ff4a02 1220 * @param base PXP peripheral base address.
AnnaBridge 161:aa5281ff4a02 1221 * @param enable Pass in true to enable, false to disable.
AnnaBridge 161:aa5281ff4a02 1222 */
AnnaBridge 161:aa5281ff4a02 1223 void PXP_EnableDither(PXP_Type *base, bool enable);
AnnaBridge 161:aa5281ff4a02 1224
AnnaBridge 161:aa5281ff4a02 1225 /* @} */
AnnaBridge 161:aa5281ff4a02 1226
AnnaBridge 161:aa5281ff4a02 1227 #endif /* FSL_FEATURE_PXP_HAS_DITHER */
AnnaBridge 161:aa5281ff4a02 1228
AnnaBridge 161:aa5281ff4a02 1229 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 1230 }
AnnaBridge 161:aa5281ff4a02 1231 #endif
AnnaBridge 161:aa5281ff4a02 1232
AnnaBridge 161:aa5281ff4a02 1233 /*! @}*/
AnnaBridge 161:aa5281ff4a02 1234
AnnaBridge 161:aa5281ff4a02 1235 #endif /* _FSL_PXP_H_ */