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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_pmu.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /*
AnnaBridge 170:e95d10626187 2 * The Clear BSD License
AnnaBridge 161:aa5281ff4a02 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 161:aa5281ff4a02 4 * Copyright 2016-2017 NXP
AnnaBridge 170:e95d10626187 5 * All rights reserved.
AnnaBridge 170:e95d10626187 6 *
AnnaBridge 161:aa5281ff4a02 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 170:e95d10626187 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 170:e95d10626187 9 * that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 10 *
AnnaBridge 161:aa5281ff4a02 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 161:aa5281ff4a02 12 * of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 13 *
AnnaBridge 161:aa5281ff4a02 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 161:aa5281ff4a02 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 161:aa5281ff4a02 16 * other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 161:aa5281ff4a02 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 161:aa5281ff4a02 20 * software without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 21 *
AnnaBridge 170:e95d10626187 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 161:aa5281ff4a02 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 161:aa5281ff4a02 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 161:aa5281ff4a02 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 161:aa5281ff4a02 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 161:aa5281ff4a02 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 161:aa5281ff4a02 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 161:aa5281ff4a02 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 161:aa5281ff4a02 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 161:aa5281ff4a02 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 33 */
AnnaBridge 161:aa5281ff4a02 34 #ifndef _FSL_PMU_H_
AnnaBridge 161:aa5281ff4a02 35 #define _FSL_PMU_H_
AnnaBridge 161:aa5281ff4a02 36
AnnaBridge 161:aa5281ff4a02 37 #include "fsl_common.h"
AnnaBridge 161:aa5281ff4a02 38
AnnaBridge 161:aa5281ff4a02 39 /*! @addtogroup pmu */
AnnaBridge 161:aa5281ff4a02 40 /*! @{ */
AnnaBridge 161:aa5281ff4a02 41
AnnaBridge 161:aa5281ff4a02 42 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 43 * Definitions
AnnaBridge 161:aa5281ff4a02 44 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 45
AnnaBridge 161:aa5281ff4a02 46 /*! @name Driver version */
AnnaBridge 161:aa5281ff4a02 47 /*@{*/
AnnaBridge 161:aa5281ff4a02 48 /*! @brief PMU driver version */
AnnaBridge 161:aa5281ff4a02 49 #define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
AnnaBridge 161:aa5281ff4a02 50 /*@}*/
AnnaBridge 161:aa5281ff4a02 51
AnnaBridge 161:aa5281ff4a02 52 /*!
AnnaBridge 161:aa5281ff4a02 53 * @brief Status flags.
AnnaBridge 161:aa5281ff4a02 54 */
AnnaBridge 161:aa5281ff4a02 55 enum _pmu_status_flags
AnnaBridge 161:aa5281ff4a02 56 {
AnnaBridge 161:aa5281ff4a02 57 kPMU_1P1RegulatorOutputOK = (1U << 0U), /*!< Status bit that signals when the 1p1 regulator output
AnnaBridge 161:aa5281ff4a02 58 is ok. 1 = regulator output > brownout target. */
AnnaBridge 161:aa5281ff4a02 59 kPMU_1P1BrownoutOnOutput = (1U << 1U), /*!< Status bit that signals when a 1p1 brownout is detected
AnnaBridge 161:aa5281ff4a02 60 on the regulator output. */
AnnaBridge 161:aa5281ff4a02 61 kPMU_3P0RegulatorOutputOK = (1U << 2U), /*!< Status bit that signals when the 3p0 regulator output
AnnaBridge 161:aa5281ff4a02 62 is ok. 1 = regulator output > brownout target. */
AnnaBridge 161:aa5281ff4a02 63 kPMU_3P0BrownoutOnOutput = (1U << 3U), /*!< Status bit that signals when a 3p0 brownout is detected
AnnaBridge 161:aa5281ff4a02 64 on the regulator output. */
AnnaBridge 161:aa5281ff4a02 65 kPMU_2P5RegulatorOutputOK = (1U << 4U), /*!< Status bit that signals when the 2p5 regulator output
AnnaBridge 161:aa5281ff4a02 66 is ok. 1 = regulator output > brownout target. */
AnnaBridge 161:aa5281ff4a02 67 kPMU_2P5BrownoutOnOutput = (1U << 5U), /*!< Status bit that signals when a 2p5 brownout is detected
AnnaBridge 161:aa5281ff4a02 68 on the regulator output. */
AnnaBridge 161:aa5281ff4a02 69 };
AnnaBridge 161:aa5281ff4a02 70
AnnaBridge 161:aa5281ff4a02 71 /*!
AnnaBridge 161:aa5281ff4a02 72 * @brief The source for the reference voltage of the weak 1P1 regulator.
AnnaBridge 161:aa5281ff4a02 73 */
AnnaBridge 161:aa5281ff4a02 74 typedef enum _pmu_1p1_weak_reference_source
AnnaBridge 161:aa5281ff4a02 75 {
AnnaBridge 161:aa5281ff4a02 76 kPMU_1P1WeakReferenceSourceAlt0 = 0U, /*!< Weak-linreg output tracks low-power-bandgap voltage. */
AnnaBridge 161:aa5281ff4a02 77 kPMU_1P1WeakReferenceSourceAlt1 = 1U, /*!< Weak-linreg output tracks VDD_SOC_CAP voltage. */
AnnaBridge 161:aa5281ff4a02 78 } pmu_1p1_weak_reference_source_t;
AnnaBridge 161:aa5281ff4a02 79
AnnaBridge 161:aa5281ff4a02 80 /*!
AnnaBridge 161:aa5281ff4a02 81 * @brief Input voltage source for LDO_3P0 from USB VBus.
AnnaBridge 161:aa5281ff4a02 82 */
AnnaBridge 161:aa5281ff4a02 83 typedef enum _pmu_3p0_vbus_voltage_source
AnnaBridge 161:aa5281ff4a02 84 {
AnnaBridge 161:aa5281ff4a02 85 kPMU_3P0VBusVoltageSourceAlt0 = 0U, /*!< USB_OTG1_VBUS - Utilize VBUS OTG1 for power. */
AnnaBridge 161:aa5281ff4a02 86 kPMU_3P0VBusVoltageSourceAlt1 = 1U, /*!< USB_OTG2_VBUS - Utilize VBUS OTG2 for power. */
AnnaBridge 161:aa5281ff4a02 87 } pmu_3p0_vbus_voltage_source_t;
AnnaBridge 161:aa5281ff4a02 88
AnnaBridge 161:aa5281ff4a02 89 /*!
AnnaBridge 161:aa5281ff4a02 90 * @brief Regulator voltage ramp rate.
AnnaBridge 161:aa5281ff4a02 91 */
AnnaBridge 161:aa5281ff4a02 92 typedef enum _pmu_core_reg_voltage_ramp_rate
AnnaBridge 161:aa5281ff4a02 93 {
AnnaBridge 161:aa5281ff4a02 94 kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */
AnnaBridge 161:aa5281ff4a02 95 kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */
AnnaBridge 161:aa5281ff4a02 96 kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */
AnnaBridge 161:aa5281ff4a02 97 kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */
AnnaBridge 161:aa5281ff4a02 98 } pmu_core_reg_voltage_ramp_rate_t;
AnnaBridge 161:aa5281ff4a02 99
AnnaBridge 161:aa5281ff4a02 100 #if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
AnnaBridge 161:aa5281ff4a02 101 /*!
AnnaBridge 161:aa5281ff4a02 102 * @brief Mask values of power gate.
AnnaBridge 161:aa5281ff4a02 103 */
AnnaBridge 161:aa5281ff4a02 104 enum _pmu_power_gate
AnnaBridge 161:aa5281ff4a02 105 {
AnnaBridge 161:aa5281ff4a02 106 kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */
AnnaBridge 161:aa5281ff4a02 107 kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */
AnnaBridge 161:aa5281ff4a02 108 kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */
AnnaBridge 161:aa5281ff4a02 109 kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */
AnnaBridge 161:aa5281ff4a02 110 kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */
AnnaBridge 161:aa5281ff4a02 111 };
AnnaBridge 161:aa5281ff4a02 112 #endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
AnnaBridge 161:aa5281ff4a02 113
AnnaBridge 161:aa5281ff4a02 114 /*!
AnnaBridge 161:aa5281ff4a02 115 * @brief Bandgap select.
AnnaBridge 161:aa5281ff4a02 116 */
AnnaBridge 161:aa5281ff4a02 117 typedef enum _pmu_power_bandgap
AnnaBridge 161:aa5281ff4a02 118 {
AnnaBridge 161:aa5281ff4a02 119 kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */
AnnaBridge 161:aa5281ff4a02 120 kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */
AnnaBridge 161:aa5281ff4a02 121 } pmu_power_bandgap_t;
AnnaBridge 161:aa5281ff4a02 122
AnnaBridge 161:aa5281ff4a02 123 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 124 * API
AnnaBridge 161:aa5281ff4a02 125 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 126
AnnaBridge 161:aa5281ff4a02 127 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 128 extern "C" {
AnnaBridge 161:aa5281ff4a02 129 #endif /* __cplusplus*/
AnnaBridge 161:aa5281ff4a02 130
AnnaBridge 161:aa5281ff4a02 131 /*!
AnnaBridge 161:aa5281ff4a02 132 * @name Status.
AnnaBridge 161:aa5281ff4a02 133 * @{
AnnaBridge 161:aa5281ff4a02 134 */
AnnaBridge 161:aa5281ff4a02 135
AnnaBridge 161:aa5281ff4a02 136 uint32_t PMU_GetStatusFlags(PMU_Type *base);
AnnaBridge 161:aa5281ff4a02 137
AnnaBridge 161:aa5281ff4a02 138 /*@}*/
AnnaBridge 161:aa5281ff4a02 139
AnnaBridge 161:aa5281ff4a02 140 /*!
AnnaBridge 161:aa5281ff4a02 141 * @name 1P1 Regular
AnnaBridge 161:aa5281ff4a02 142 * @{
AnnaBridge 161:aa5281ff4a02 143 */
AnnaBridge 161:aa5281ff4a02 144
AnnaBridge 161:aa5281ff4a02 145 /*!
AnnaBridge 161:aa5281ff4a02 146 * @brief Selects the source for the reference voltage of the weak 1P1 regulator.
AnnaBridge 161:aa5281ff4a02 147 *
AnnaBridge 161:aa5281ff4a02 148 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 149 * @param option The option for reference voltage source, see to #pmu_1p1_weak_reference_source_t.
AnnaBridge 161:aa5281ff4a02 150 */
AnnaBridge 161:aa5281ff4a02 151 static inline void PMU_1P1SetWeakReferenceSource(PMU_Type *base, pmu_1p1_weak_reference_source_t option)
AnnaBridge 161:aa5281ff4a02 152 {
AnnaBridge 161:aa5281ff4a02 153 base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) | PMU_REG_1P1_SELREF_WEAK_LINREG(option);
AnnaBridge 161:aa5281ff4a02 154 }
AnnaBridge 161:aa5281ff4a02 155
AnnaBridge 161:aa5281ff4a02 156 /*!
AnnaBridge 161:aa5281ff4a02 157 * @brief Enables the weak 1P1 regulator.
AnnaBridge 161:aa5281ff4a02 158 *
AnnaBridge 161:aa5281ff4a02 159 * This regulator can be used when the main 1P1 regulator is disabled, under low-power conditions.
AnnaBridge 161:aa5281ff4a02 160 *
AnnaBridge 161:aa5281ff4a02 161 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 162 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 163 */
AnnaBridge 161:aa5281ff4a02 164 static inline void PMU_1P1EnableWeakRegulator(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 165 {
AnnaBridge 161:aa5281ff4a02 166 if (enable)
AnnaBridge 161:aa5281ff4a02 167 {
AnnaBridge 161:aa5281ff4a02 168 base->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 169 }
AnnaBridge 161:aa5281ff4a02 170 else
AnnaBridge 161:aa5281ff4a02 171 {
AnnaBridge 161:aa5281ff4a02 172 base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 173 }
AnnaBridge 161:aa5281ff4a02 174 }
AnnaBridge 161:aa5281ff4a02 175
AnnaBridge 161:aa5281ff4a02 176 /*!
AnnaBridge 161:aa5281ff4a02 177 * @brief Adjust the 1P1 regulator output voltage.
AnnaBridge 161:aa5281ff4a02 178 *
AnnaBridge 161:aa5281ff4a02 179 * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
AnnaBridge 161:aa5281ff4a02 180 * may be interpolated from these examples. Choices must be in this range:
AnnaBridge 161:aa5281ff4a02 181 * - 0x1b(1.375V) >= output_trg >= 0x04(0.8V)
AnnaBridge 161:aa5281ff4a02 182 * - 0x04 : 0.8V
AnnaBridge 161:aa5281ff4a02 183 * - 0x10 : 1.1V (typical)
AnnaBridge 161:aa5281ff4a02 184 * - 0x1b : 1.375V
AnnaBridge 161:aa5281ff4a02 185 * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range.
AnnaBridge 161:aa5281ff4a02 186 *
AnnaBridge 161:aa5281ff4a02 187 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 188 * @param value Setting value for the output.
AnnaBridge 161:aa5281ff4a02 189 */
AnnaBridge 161:aa5281ff4a02 190 static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 191 {
AnnaBridge 161:aa5281ff4a02 192 base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value);
AnnaBridge 161:aa5281ff4a02 193 }
AnnaBridge 161:aa5281ff4a02 194
AnnaBridge 161:aa5281ff4a02 195 /*!
AnnaBridge 161:aa5281ff4a02 196 * @brief Adjust the 1P1 regulator brownout offset voltage.
AnnaBridge 161:aa5281ff4a02 197 *
AnnaBridge 161:aa5281ff4a02 198 * Control bits to adjust the regulator brownout offset voltage in 25mV steps. The reset
AnnaBridge 161:aa5281ff4a02 199 * brown-offset is 175mV below the programmed target code.
AnnaBridge 161:aa5281ff4a02 200 * Brownout target = OUTPUT_TRG - BO_OFFSET.
AnnaBridge 161:aa5281ff4a02 201 * Some steps may be irrelevant because of input supply limitations or load operation.
AnnaBridge 161:aa5281ff4a02 202 *
AnnaBridge 161:aa5281ff4a02 203 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 204 * @param value Setting value for the brownout offset. The available range is in 3-bit.
AnnaBridge 161:aa5281ff4a02 205 */
AnnaBridge 161:aa5281ff4a02 206 static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 207 {
AnnaBridge 161:aa5281ff4a02 208 base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value);
AnnaBridge 161:aa5281ff4a02 209 }
AnnaBridge 161:aa5281ff4a02 210
AnnaBridge 161:aa5281ff4a02 211 /*!
AnnaBridge 161:aa5281ff4a02 212 * @brief Enable the pull-down circuitry in the regulator.
AnnaBridge 161:aa5281ff4a02 213 *
AnnaBridge 161:aa5281ff4a02 214 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 215 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 216 */
AnnaBridge 161:aa5281ff4a02 217 static inline void PMU_1P1EnablePullDown(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 218 {
AnnaBridge 161:aa5281ff4a02 219 if (enable)
AnnaBridge 161:aa5281ff4a02 220 {
AnnaBridge 161:aa5281ff4a02 221 base->REG_1P1 |= PMU_REG_1P1_ENABLE_PULLDOWN_MASK;
AnnaBridge 161:aa5281ff4a02 222 }
AnnaBridge 161:aa5281ff4a02 223 else
AnnaBridge 161:aa5281ff4a02 224 {
AnnaBridge 161:aa5281ff4a02 225 base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_PULLDOWN_MASK;
AnnaBridge 161:aa5281ff4a02 226 }
AnnaBridge 161:aa5281ff4a02 227 }
AnnaBridge 161:aa5281ff4a02 228
AnnaBridge 161:aa5281ff4a02 229 /*!
AnnaBridge 161:aa5281ff4a02 230 * @brief Enable the current-limit circuitry in the regulator.
AnnaBridge 161:aa5281ff4a02 231 *
AnnaBridge 161:aa5281ff4a02 232 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 233 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 234 */
AnnaBridge 161:aa5281ff4a02 235 static inline void PMU_1P1EnableCurrentLimit(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 236 {
AnnaBridge 161:aa5281ff4a02 237 if (enable)
AnnaBridge 161:aa5281ff4a02 238 {
AnnaBridge 161:aa5281ff4a02 239 base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK;
AnnaBridge 161:aa5281ff4a02 240 }
AnnaBridge 161:aa5281ff4a02 241 else
AnnaBridge 161:aa5281ff4a02 242 {
AnnaBridge 161:aa5281ff4a02 243 base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK;
AnnaBridge 161:aa5281ff4a02 244 }
AnnaBridge 161:aa5281ff4a02 245 }
AnnaBridge 161:aa5281ff4a02 246
AnnaBridge 161:aa5281ff4a02 247 /*!
AnnaBridge 161:aa5281ff4a02 248 * @brief Enable the brownout circuitry in the regulator.
AnnaBridge 161:aa5281ff4a02 249 *
AnnaBridge 161:aa5281ff4a02 250 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 251 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 252 */
AnnaBridge 161:aa5281ff4a02 253 static inline void PMU_1P1EnableBrownout(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 254 {
AnnaBridge 161:aa5281ff4a02 255 if (enable)
AnnaBridge 161:aa5281ff4a02 256 {
AnnaBridge 161:aa5281ff4a02 257 base->REG_1P1 |= PMU_REG_1P1_ENABLE_BO_MASK;
AnnaBridge 161:aa5281ff4a02 258 }
AnnaBridge 161:aa5281ff4a02 259 else
AnnaBridge 161:aa5281ff4a02 260 {
AnnaBridge 161:aa5281ff4a02 261 base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_BO_MASK;
AnnaBridge 161:aa5281ff4a02 262 }
AnnaBridge 161:aa5281ff4a02 263 }
AnnaBridge 161:aa5281ff4a02 264
AnnaBridge 161:aa5281ff4a02 265 /*!
AnnaBridge 161:aa5281ff4a02 266 * @brief Enable the regulator output.
AnnaBridge 161:aa5281ff4a02 267 *
AnnaBridge 161:aa5281ff4a02 268 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 269 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 270 */
AnnaBridge 161:aa5281ff4a02 271 static inline void PMU_1P1EnableOutput(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 272 {
AnnaBridge 161:aa5281ff4a02 273 if (enable)
AnnaBridge 161:aa5281ff4a02 274 {
AnnaBridge 161:aa5281ff4a02 275 base->REG_1P1 |= PMU_REG_1P1_ENABLE_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 276 }
AnnaBridge 161:aa5281ff4a02 277 else
AnnaBridge 161:aa5281ff4a02 278 {
AnnaBridge 161:aa5281ff4a02 279 base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 280 }
AnnaBridge 161:aa5281ff4a02 281 }
AnnaBridge 161:aa5281ff4a02 282
AnnaBridge 161:aa5281ff4a02 283 /*@}*/
AnnaBridge 161:aa5281ff4a02 284
AnnaBridge 161:aa5281ff4a02 285 /*!
AnnaBridge 161:aa5281ff4a02 286 * @name 3P0 Regular
AnnaBridge 161:aa5281ff4a02 287 * @{
AnnaBridge 161:aa5281ff4a02 288 */
AnnaBridge 161:aa5281ff4a02 289
AnnaBridge 161:aa5281ff4a02 290 /*!
AnnaBridge 161:aa5281ff4a02 291 * @brief Adjust the 3P0 regulator output voltage.
AnnaBridge 161:aa5281ff4a02 292 *
AnnaBridge 161:aa5281ff4a02 293 * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
AnnaBridge 161:aa5281ff4a02 294 * may be interpolated from these examples. Choices must be in this range:
AnnaBridge 161:aa5281ff4a02 295 * - 0x00(2.625V) >= output_trg >= 0x1f(3.4V)
AnnaBridge 161:aa5281ff4a02 296 * - 0x00 : 2.625V
AnnaBridge 161:aa5281ff4a02 297 * - 0x0f : 3.0V (typical)
AnnaBridge 161:aa5281ff4a02 298 * - 0x1f : 3.4V
AnnaBridge 161:aa5281ff4a02 299 *
AnnaBridge 161:aa5281ff4a02 300 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 301 * @param value Setting value for the output.
AnnaBridge 161:aa5281ff4a02 302 */
AnnaBridge 161:aa5281ff4a02 303 static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 304 {
AnnaBridge 161:aa5281ff4a02 305 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value);
AnnaBridge 161:aa5281ff4a02 306 }
AnnaBridge 161:aa5281ff4a02 307
AnnaBridge 161:aa5281ff4a02 308 /*!
AnnaBridge 161:aa5281ff4a02 309 * @brief Select input voltage source for LDO_3P0.
AnnaBridge 161:aa5281ff4a02 310 *
AnnaBridge 161:aa5281ff4a02 311 * Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS. If only
AnnaBridge 161:aa5281ff4a02 312 * one of the two VBUS voltages is present, it is automatically selected.
AnnaBridge 161:aa5281ff4a02 313 *
AnnaBridge 161:aa5281ff4a02 314 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 315 * @param option User-defined input voltage source for LDO_3P0.
AnnaBridge 161:aa5281ff4a02 316 */
AnnaBridge 161:aa5281ff4a02 317 static inline void PMU_3P0SetVBusVoltageSource(PMU_Type *base, pmu_3p0_vbus_voltage_source_t option)
AnnaBridge 161:aa5281ff4a02 318 {
AnnaBridge 161:aa5281ff4a02 319 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option);
AnnaBridge 161:aa5281ff4a02 320 }
AnnaBridge 161:aa5281ff4a02 321
AnnaBridge 161:aa5281ff4a02 322 /*!
AnnaBridge 161:aa5281ff4a02 323 * @brief Adjust the 3P0 regulator brownout offset voltage.
AnnaBridge 161:aa5281ff4a02 324 *
AnnaBridge 161:aa5281ff4a02 325 * Control bits to adjust the 3P0 regulator brownout offset voltage in 25mV steps. The reset
AnnaBridge 161:aa5281ff4a02 326 * brown-offset is 175mV below the programmed target code.
AnnaBridge 161:aa5281ff4a02 327 * Brownout target = OUTPUT_TRG - BO_OFFSET.
AnnaBridge 161:aa5281ff4a02 328 * Some steps may be irrelevant because of input supply limitations or load operation.
AnnaBridge 161:aa5281ff4a02 329 *
AnnaBridge 161:aa5281ff4a02 330 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 331 * @param value Setting value for the brownout offset. The available range is in 3-bit.
AnnaBridge 161:aa5281ff4a02 332 */
AnnaBridge 161:aa5281ff4a02 333 static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 334 {
AnnaBridge 161:aa5281ff4a02 335 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value);
AnnaBridge 161:aa5281ff4a02 336 }
AnnaBridge 161:aa5281ff4a02 337
AnnaBridge 161:aa5281ff4a02 338 /*!
AnnaBridge 161:aa5281ff4a02 339 * @brief Enable the current-limit circuitry in the 3P0 regulator.
AnnaBridge 161:aa5281ff4a02 340 *
AnnaBridge 161:aa5281ff4a02 341 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 342 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 343 */
AnnaBridge 161:aa5281ff4a02 344 static inline void PMU_3P0EnableCurrentLimit(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 345 {
AnnaBridge 161:aa5281ff4a02 346 if (enable)
AnnaBridge 161:aa5281ff4a02 347 {
AnnaBridge 161:aa5281ff4a02 348 base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK;
AnnaBridge 161:aa5281ff4a02 349 }
AnnaBridge 161:aa5281ff4a02 350 else
AnnaBridge 161:aa5281ff4a02 351 {
AnnaBridge 161:aa5281ff4a02 352 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK;
AnnaBridge 161:aa5281ff4a02 353 }
AnnaBridge 161:aa5281ff4a02 354 }
AnnaBridge 161:aa5281ff4a02 355
AnnaBridge 161:aa5281ff4a02 356 /*!
AnnaBridge 161:aa5281ff4a02 357 * @brief Enable the brownout circuitry in the 3P0 regulator.
AnnaBridge 161:aa5281ff4a02 358 *
AnnaBridge 161:aa5281ff4a02 359 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 360 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 361 */
AnnaBridge 161:aa5281ff4a02 362 static inline void PMU_3P0EnableBrownout(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 363 {
AnnaBridge 161:aa5281ff4a02 364 if (enable)
AnnaBridge 161:aa5281ff4a02 365 {
AnnaBridge 161:aa5281ff4a02 366 base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK;
AnnaBridge 161:aa5281ff4a02 367 }
AnnaBridge 161:aa5281ff4a02 368 else
AnnaBridge 161:aa5281ff4a02 369 {
AnnaBridge 161:aa5281ff4a02 370 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK;
AnnaBridge 161:aa5281ff4a02 371 }
AnnaBridge 161:aa5281ff4a02 372 }
AnnaBridge 161:aa5281ff4a02 373
AnnaBridge 161:aa5281ff4a02 374 /*!
AnnaBridge 161:aa5281ff4a02 375 * @brief Enable the 3P0 regulator output.
AnnaBridge 161:aa5281ff4a02 376 *
AnnaBridge 161:aa5281ff4a02 377 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 378 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 379 */
AnnaBridge 161:aa5281ff4a02 380 static inline void PMU_3P0EnableOutput(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 381 {
AnnaBridge 161:aa5281ff4a02 382 if (enable)
AnnaBridge 161:aa5281ff4a02 383 {
AnnaBridge 161:aa5281ff4a02 384 base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 385 }
AnnaBridge 161:aa5281ff4a02 386 else
AnnaBridge 161:aa5281ff4a02 387 {
AnnaBridge 161:aa5281ff4a02 388 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 389 }
AnnaBridge 161:aa5281ff4a02 390 }
AnnaBridge 161:aa5281ff4a02 391
AnnaBridge 161:aa5281ff4a02 392 /* @} */
AnnaBridge 161:aa5281ff4a02 393
AnnaBridge 161:aa5281ff4a02 394 /*!
AnnaBridge 161:aa5281ff4a02 395 * @name 2P5 Regulator
AnnaBridge 161:aa5281ff4a02 396 * @{
AnnaBridge 161:aa5281ff4a02 397 */
AnnaBridge 161:aa5281ff4a02 398
AnnaBridge 161:aa5281ff4a02 399 /*!
AnnaBridge 161:aa5281ff4a02 400 * @brief Enables the weak 2P5 regulator.
AnnaBridge 161:aa5281ff4a02 401 *
AnnaBridge 161:aa5281ff4a02 402 * This low power regulator is used when the main 2P5 regulator is disabled
AnnaBridge 161:aa5281ff4a02 403 * to keep the 2.5V output roughly at 2.5V. Scales directly with the value of VDDHIGH_IN.
AnnaBridge 161:aa5281ff4a02 404 *
AnnaBridge 161:aa5281ff4a02 405 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 406 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 407 */
AnnaBridge 161:aa5281ff4a02 408 static inline void PMU_2P5EnableWeakRegulator(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 409 {
AnnaBridge 161:aa5281ff4a02 410 if (enable)
AnnaBridge 161:aa5281ff4a02 411 {
AnnaBridge 161:aa5281ff4a02 412 base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 413 }
AnnaBridge 161:aa5281ff4a02 414 else
AnnaBridge 161:aa5281ff4a02 415 {
AnnaBridge 161:aa5281ff4a02 416 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 417 }
AnnaBridge 161:aa5281ff4a02 418 }
AnnaBridge 161:aa5281ff4a02 419
AnnaBridge 161:aa5281ff4a02 420 /*!
AnnaBridge 161:aa5281ff4a02 421 * @brief Adjust the 1P1 regulator output voltage.
AnnaBridge 161:aa5281ff4a02 422 *
AnnaBridge 161:aa5281ff4a02 423 * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
AnnaBridge 161:aa5281ff4a02 424 * may be interpolated from these examples. Choices must be in this range:
AnnaBridge 161:aa5281ff4a02 425 * - 0x00(2.1V) >= output_trg >= 0x1f(2.875V)
AnnaBridge 161:aa5281ff4a02 426 * - 0x00 : 2.1V
AnnaBridge 161:aa5281ff4a02 427 * - 0x10 : 2.5V (typical)
AnnaBridge 161:aa5281ff4a02 428 * - 0x1f : 2.875V
AnnaBridge 161:aa5281ff4a02 429 * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range.
AnnaBridge 161:aa5281ff4a02 430 *
AnnaBridge 161:aa5281ff4a02 431 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 432 * @param value Setting value for the output.
AnnaBridge 161:aa5281ff4a02 433 */
AnnaBridge 161:aa5281ff4a02 434 static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 435 {
AnnaBridge 161:aa5281ff4a02 436 base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value);
AnnaBridge 161:aa5281ff4a02 437 }
AnnaBridge 161:aa5281ff4a02 438
AnnaBridge 161:aa5281ff4a02 439 /*!
AnnaBridge 161:aa5281ff4a02 440 * @brief Adjust the 2P5 regulator brownout offset voltage.
AnnaBridge 161:aa5281ff4a02 441 *
AnnaBridge 161:aa5281ff4a02 442 * Adjust the regulator brownout offset voltage in 25mV steps. The reset
AnnaBridge 161:aa5281ff4a02 443 * brown-offset is 175mV below the programmed target code.
AnnaBridge 161:aa5281ff4a02 444 * Brownout target = OUTPUT_TRG - BO_OFFSET.
AnnaBridge 161:aa5281ff4a02 445 * Some steps may be irrelevant because of input supply limitations or load operation.
AnnaBridge 161:aa5281ff4a02 446 *
AnnaBridge 161:aa5281ff4a02 447 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 448 * @param value Setting value for the brownout offset. The available range is in 3-bit.
AnnaBridge 161:aa5281ff4a02 449 */
AnnaBridge 161:aa5281ff4a02 450 static inline void PMU_2P5SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 451 {
AnnaBridge 161:aa5281ff4a02 452 base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value);
AnnaBridge 161:aa5281ff4a02 453 }
AnnaBridge 161:aa5281ff4a02 454
AnnaBridge 161:aa5281ff4a02 455 /*!
AnnaBridge 161:aa5281ff4a02 456 * @brief Enable the pull-down circuitry in the 2P5 regulator.
AnnaBridge 161:aa5281ff4a02 457 *
AnnaBridge 161:aa5281ff4a02 458 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 459 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 460 */
AnnaBridge 161:aa5281ff4a02 461 static inline void PMU_2P5EnablePullDown(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 462 {
AnnaBridge 161:aa5281ff4a02 463 if (enable)
AnnaBridge 161:aa5281ff4a02 464 {
AnnaBridge 161:aa5281ff4a02 465 base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
AnnaBridge 161:aa5281ff4a02 466 }
AnnaBridge 161:aa5281ff4a02 467 else
AnnaBridge 161:aa5281ff4a02 468 {
AnnaBridge 161:aa5281ff4a02 469 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
AnnaBridge 161:aa5281ff4a02 470 }
AnnaBridge 161:aa5281ff4a02 471 }
AnnaBridge 161:aa5281ff4a02 472
AnnaBridge 161:aa5281ff4a02 473 /*!
AnnaBridge 161:aa5281ff4a02 474 * @brief Enable the pull-down circuitry in the 2P5 regulator.
AnnaBridge 161:aa5281ff4a02 475 * @deprecated Do not use this function. It has been superceded by @ref PMU_2P5EnablePullDown.
AnnaBridge 161:aa5281ff4a02 476 */
AnnaBridge 161:aa5281ff4a02 477 static inline void PMU_2P1EnablePullDown(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 478 {
AnnaBridge 161:aa5281ff4a02 479 if (enable)
AnnaBridge 161:aa5281ff4a02 480 {
AnnaBridge 161:aa5281ff4a02 481 base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
AnnaBridge 161:aa5281ff4a02 482 }
AnnaBridge 161:aa5281ff4a02 483 else
AnnaBridge 161:aa5281ff4a02 484 {
AnnaBridge 161:aa5281ff4a02 485 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
AnnaBridge 161:aa5281ff4a02 486 }
AnnaBridge 161:aa5281ff4a02 487 }
AnnaBridge 161:aa5281ff4a02 488
AnnaBridge 161:aa5281ff4a02 489 /*!
AnnaBridge 161:aa5281ff4a02 490 * @brief Enable the current-limit circuitry in the 2P5 regulator.
AnnaBridge 161:aa5281ff4a02 491 *
AnnaBridge 161:aa5281ff4a02 492 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 493 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 494 */
AnnaBridge 161:aa5281ff4a02 495 static inline void PMU_2P5EnableCurrentLimit(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 496 {
AnnaBridge 161:aa5281ff4a02 497 if (enable)
AnnaBridge 161:aa5281ff4a02 498 {
AnnaBridge 161:aa5281ff4a02 499 base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK;
AnnaBridge 161:aa5281ff4a02 500 }
AnnaBridge 161:aa5281ff4a02 501 else
AnnaBridge 161:aa5281ff4a02 502 {
AnnaBridge 161:aa5281ff4a02 503 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK;
AnnaBridge 161:aa5281ff4a02 504 }
AnnaBridge 161:aa5281ff4a02 505 }
AnnaBridge 161:aa5281ff4a02 506
AnnaBridge 161:aa5281ff4a02 507 /*!
AnnaBridge 161:aa5281ff4a02 508 * @brief Enable the brownout circuitry in the 2P5 regulator.
AnnaBridge 161:aa5281ff4a02 509 *
AnnaBridge 161:aa5281ff4a02 510 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 511 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 512 */
AnnaBridge 161:aa5281ff4a02 513 static inline void PMU_2P5nableBrownout(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 514 {
AnnaBridge 161:aa5281ff4a02 515 if (enable)
AnnaBridge 161:aa5281ff4a02 516 {
AnnaBridge 161:aa5281ff4a02 517 base->REG_2P5 |= PMU_REG_2P5_ENABLE_BO_MASK;
AnnaBridge 161:aa5281ff4a02 518 }
AnnaBridge 161:aa5281ff4a02 519 else
AnnaBridge 161:aa5281ff4a02 520 {
AnnaBridge 161:aa5281ff4a02 521 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_BO_MASK;
AnnaBridge 161:aa5281ff4a02 522 }
AnnaBridge 161:aa5281ff4a02 523 }
AnnaBridge 161:aa5281ff4a02 524
AnnaBridge 161:aa5281ff4a02 525 /*!
AnnaBridge 161:aa5281ff4a02 526 * @brief Enable the 2P5 regulator output.
AnnaBridge 161:aa5281ff4a02 527 *
AnnaBridge 161:aa5281ff4a02 528 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 529 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 530 */
AnnaBridge 161:aa5281ff4a02 531 static inline void PMU_2P5EnableOutput(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 532 {
AnnaBridge 161:aa5281ff4a02 533 if (enable)
AnnaBridge 161:aa5281ff4a02 534 {
AnnaBridge 161:aa5281ff4a02 535 base->REG_2P5 |= PMU_REG_2P5_ENABLE_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 536 }
AnnaBridge 161:aa5281ff4a02 537 else
AnnaBridge 161:aa5281ff4a02 538 {
AnnaBridge 161:aa5281ff4a02 539 base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK;
AnnaBridge 161:aa5281ff4a02 540 }
AnnaBridge 161:aa5281ff4a02 541 }
AnnaBridge 161:aa5281ff4a02 542
AnnaBridge 161:aa5281ff4a02 543 /* @} */
AnnaBridge 161:aa5281ff4a02 544
AnnaBridge 161:aa5281ff4a02 545 /*!
AnnaBridge 161:aa5281ff4a02 546 * @name Core Regulator
AnnaBridge 161:aa5281ff4a02 547 * @{
AnnaBridge 161:aa5281ff4a02 548 */
AnnaBridge 161:aa5281ff4a02 549
AnnaBridge 161:aa5281ff4a02 550 /*!
AnnaBridge 161:aa5281ff4a02 551 * @brief Increase the gate drive on power gating FETs.
AnnaBridge 161:aa5281ff4a02 552 *
AnnaBridge 161:aa5281ff4a02 553 * If set, increases the gate drive on power gating FETs to reduce leakage in the off state.
AnnaBridge 161:aa5281ff4a02 554 * Care must be taken to apply this bit only when the input supply voltage to the power FET
AnnaBridge 161:aa5281ff4a02 555 * is less than 1.1V.
AnnaBridge 161:aa5281ff4a02 556 * NOTE: This bit should only be used in low-power modes where the external input supply voltage
AnnaBridge 161:aa5281ff4a02 557 * is nominally 0.9V.
AnnaBridge 161:aa5281ff4a02 558 *
AnnaBridge 161:aa5281ff4a02 559 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 560 * @param enable Enable the feature or not.
AnnaBridge 161:aa5281ff4a02 561 */
AnnaBridge 161:aa5281ff4a02 562 static inline void PMU_CoreEnableIncreaseGateDrive(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 563 {
AnnaBridge 161:aa5281ff4a02 564 if (enable)
AnnaBridge 161:aa5281ff4a02 565 {
AnnaBridge 161:aa5281ff4a02 566 base->REG_CORE |= PMU_REG_CORE_FET_ODRIVE_MASK;
AnnaBridge 161:aa5281ff4a02 567 }
AnnaBridge 161:aa5281ff4a02 568 else
AnnaBridge 161:aa5281ff4a02 569 {
AnnaBridge 161:aa5281ff4a02 570 base->REG_CORE &= ~PMU_REG_CORE_FET_ODRIVE_MASK;
AnnaBridge 161:aa5281ff4a02 571 }
AnnaBridge 161:aa5281ff4a02 572 }
AnnaBridge 161:aa5281ff4a02 573
AnnaBridge 161:aa5281ff4a02 574 /*!
AnnaBridge 161:aa5281ff4a02 575 * @brief Set the CORE regulator voltage ramp rate.
AnnaBridge 161:aa5281ff4a02 576 *
AnnaBridge 161:aa5281ff4a02 577 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 578 * @param option User-defined option for voltage ramp rate, see to #pmu_core_reg_voltage_ramp_rate_t.
AnnaBridge 161:aa5281ff4a02 579 */
AnnaBridge 161:aa5281ff4a02 580 static inline void PMU_CoreSetRegulatorVoltageRampRate(PMU_Type *base, pmu_core_reg_voltage_ramp_rate_t option)
AnnaBridge 161:aa5281ff4a02 581 {
AnnaBridge 161:aa5281ff4a02 582 base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_RAMP_RATE_MASK) | PMU_REG_CORE_RAMP_RATE(option);
AnnaBridge 161:aa5281ff4a02 583 }
AnnaBridge 161:aa5281ff4a02 584
AnnaBridge 161:aa5281ff4a02 585 /*!
AnnaBridge 161:aa5281ff4a02 586 * @brief Define the target voltage for the SOC power domain.
AnnaBridge 161:aa5281ff4a02 587 *
AnnaBridge 161:aa5281ff4a02 588 * Define the target voltage for the SOC power domain. Single-bit increments reflect 25mV core
AnnaBridge 161:aa5281ff4a02 589 * voltage steps. Some steps may not be relevant because of input supply limitations or load operation.
AnnaBridge 161:aa5281ff4a02 590 * - 0x00 : Power gated off.
AnnaBridge 161:aa5281ff4a02 591 * - 0x01 : Target core voltage = 0.725V
AnnaBridge 161:aa5281ff4a02 592 * - 0x02 : Target core voltage = 0.750V
AnnaBridge 161:aa5281ff4a02 593 * - ...
AnnaBridge 161:aa5281ff4a02 594 * - 0x10 : Target core voltage = 1.100V
AnnaBridge 161:aa5281ff4a02 595 * - ...
AnnaBridge 161:aa5281ff4a02 596 * - 0x1e : Target core voltage = 1.450V
AnnaBridge 161:aa5281ff4a02 597 * - 0x1F : Power FET switched full on. No regulation.
AnnaBridge 161:aa5281ff4a02 598 * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the
AnnaBridge 161:aa5281ff4a02 599 * datasheet Operating Ranges table for the allowed voltages.
AnnaBridge 161:aa5281ff4a02 600 *
AnnaBridge 161:aa5281ff4a02 601 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 602 * @param value Setting value for target voltage. 5-bit available
AnnaBridge 161:aa5281ff4a02 603 */
AnnaBridge 161:aa5281ff4a02 604 static inline void PMU_CoreSetSOCDomainVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 605 {
AnnaBridge 161:aa5281ff4a02 606 base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG2_TARG_MASK) | PMU_REG_CORE_REG2_TARG(value);
AnnaBridge 161:aa5281ff4a02 607 }
AnnaBridge 161:aa5281ff4a02 608
AnnaBridge 161:aa5281ff4a02 609 /*!
AnnaBridge 161:aa5281ff4a02 610 * @brief Define the target voltage for the ARM Core power domain.
AnnaBridge 161:aa5281ff4a02 611 *
AnnaBridge 161:aa5281ff4a02 612 * Define the target voltage for the ARM Core power domain. Single-bit increments reflect 25mV core
AnnaBridge 161:aa5281ff4a02 613 * voltage steps. Some steps may not be relevant because of input supply limitations or load operation.
AnnaBridge 161:aa5281ff4a02 614 * - 0x00 : Power gated off.
AnnaBridge 161:aa5281ff4a02 615 * - 0x01 : Target core voltage = 0.725V
AnnaBridge 161:aa5281ff4a02 616 * - 0x02 : Target core voltage = 0.750V
AnnaBridge 161:aa5281ff4a02 617 * - ...
AnnaBridge 161:aa5281ff4a02 618 * - 0x10 : Target core voltage = 1.100V
AnnaBridge 161:aa5281ff4a02 619 * - ...
AnnaBridge 161:aa5281ff4a02 620 * - 0x1e : Target core voltage = 1.450V
AnnaBridge 161:aa5281ff4a02 621 * - 0x1F : Power FET switched full on. No regulation.
AnnaBridge 161:aa5281ff4a02 622 * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the
AnnaBridge 161:aa5281ff4a02 623 * datasheet Operating Ranges table for the allowed voltages.
AnnaBridge 161:aa5281ff4a02 624 *
AnnaBridge 161:aa5281ff4a02 625 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 626 * @param value Setting value for target voltage. 5-bit available
AnnaBridge 161:aa5281ff4a02 627 */
AnnaBridge 161:aa5281ff4a02 628 static inline void PMU_CoreSetARMCoreDomainVoltage(PMU_Type *base, uint32_t value)
AnnaBridge 161:aa5281ff4a02 629 {
AnnaBridge 161:aa5281ff4a02 630 base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG0_TARG_MASK) | PMU_REG_CORE_REG0_TARG(value);
AnnaBridge 161:aa5281ff4a02 631 }
AnnaBridge 161:aa5281ff4a02 632
AnnaBridge 161:aa5281ff4a02 633 /* @} */
AnnaBridge 161:aa5281ff4a02 634
AnnaBridge 161:aa5281ff4a02 635 #if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
AnnaBridge 161:aa5281ff4a02 636 /*!
AnnaBridge 161:aa5281ff4a02 637 * @name Power Gate Controller & other
AnnaBridge 161:aa5281ff4a02 638 * @{
AnnaBridge 161:aa5281ff4a02 639 */
AnnaBridge 161:aa5281ff4a02 640
AnnaBridge 161:aa5281ff4a02 641 /*!
AnnaBridge 161:aa5281ff4a02 642 * @brief Gate the power to modules.
AnnaBridge 161:aa5281ff4a02 643 *
AnnaBridge 161:aa5281ff4a02 644 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 645 * @param gates Mask value for the module to be gated. See to #_pmu_power_gate.
AnnaBridge 161:aa5281ff4a02 646 */
AnnaBridge 161:aa5281ff4a02 647 static inline void PMU_GatePower(PMU_Type *base, uint32_t gates)
AnnaBridge 161:aa5281ff4a02 648 {
AnnaBridge 161:aa5281ff4a02 649 base->LOWPWR_CTRL_SET = gates;
AnnaBridge 161:aa5281ff4a02 650 }
AnnaBridge 161:aa5281ff4a02 651
AnnaBridge 161:aa5281ff4a02 652 /*!
AnnaBridge 161:aa5281ff4a02 653 * @brief Ungate the power to modules.
AnnaBridge 161:aa5281ff4a02 654 *
AnnaBridge 161:aa5281ff4a02 655 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 656 * @param gates Mask value for the module to be gated. See to #_pmu_power_gate.
AnnaBridge 161:aa5281ff4a02 657 */
AnnaBridge 161:aa5281ff4a02 658 static inline void PMU_UngatePower(PMU_Type *base, uint32_t gates)
AnnaBridge 161:aa5281ff4a02 659 {
AnnaBridge 161:aa5281ff4a02 660 base->LOWPWR_CTRL_CLR = gates;
AnnaBridge 161:aa5281ff4a02 661 }
AnnaBridge 161:aa5281ff4a02 662
AnnaBridge 161:aa5281ff4a02 663 /*!
AnnaBridge 161:aa5281ff4a02 664 * @brief Enable the low power bandgap.
AnnaBridge 161:aa5281ff4a02 665 *
AnnaBridge 161:aa5281ff4a02 666 * @param base PMU peripheral base address.
AnnaBridge 161:aa5281ff4a02 667 * @param enable Enable the low power bandgap or use the normal power bandgap.
AnnaBridge 161:aa5281ff4a02 668 * @
AnnaBridge 161:aa5281ff4a02 669 */
AnnaBridge 161:aa5281ff4a02 670 static inline void PMU_EnableLowPowerBandgap(PMU_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 671 {
AnnaBridge 161:aa5281ff4a02 672 if (enable)
AnnaBridge 161:aa5281ff4a02 673 {
AnnaBridge 161:aa5281ff4a02 674 base->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the low power bandgap. */
AnnaBridge 161:aa5281ff4a02 675 }
AnnaBridge 161:aa5281ff4a02 676 else
AnnaBridge 161:aa5281ff4a02 677 {
AnnaBridge 161:aa5281ff4a02 678 base->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the normal power bandgap. */
AnnaBridge 161:aa5281ff4a02 679 }
AnnaBridge 161:aa5281ff4a02 680 }
AnnaBridge 161:aa5281ff4a02 681 #endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
AnnaBridge 161:aa5281ff4a02 682 /* @} */
AnnaBridge 161:aa5281ff4a02 683
AnnaBridge 161:aa5281ff4a02 684 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 685 }
AnnaBridge 161:aa5281ff4a02 686 #endif /* __cplusplus*/
AnnaBridge 161:aa5281ff4a02 687
AnnaBridge 161:aa5281ff4a02 688 /*! @}*/
AnnaBridge 161:aa5281ff4a02 689
AnnaBridge 161:aa5281ff4a02 690 #endif /* _FSL_PMU_H_*/