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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_iomuxc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 161:aa5281ff4a02 | 1 | /* |
AnnaBridge | 170:e95d10626187 | 2 | * The Clear BSD License |
AnnaBridge | 170:e95d10626187 | 3 | * Copyright 2016 Freescale Semiconductor, Inc. |
AnnaBridge | 170:e95d10626187 | 4 | * Copyright 2016-2018 NXP |
AnnaBridge | 161:aa5281ff4a02 | 5 | * All rights reserved. |
AnnaBridge | 170:e95d10626187 | 6 | * |
AnnaBridge | 170:e95d10626187 | 7 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 170:e95d10626187 | 8 | * modification, are permitted (subject to the limitations in the |
AnnaBridge | 170:e95d10626187 | 9 | * disclaimer below) provided that the following conditions are met: |
AnnaBridge | 170:e95d10626187 | 10 | * |
AnnaBridge | 170:e95d10626187 | 11 | * * Redistributions of source code must retain the above copyright |
AnnaBridge | 170:e95d10626187 | 12 | * notice, this list of conditions and the following disclaimer. |
AnnaBridge | 170:e95d10626187 | 13 | * |
AnnaBridge | 170:e95d10626187 | 14 | * * Redistributions in binary form must reproduce the above copyright |
AnnaBridge | 170:e95d10626187 | 15 | * notice, this list of conditions and the following disclaimer in the |
AnnaBridge | 170:e95d10626187 | 16 | * documentation and/or other materials provided with the distribution. |
AnnaBridge | 170:e95d10626187 | 17 | * |
AnnaBridge | 170:e95d10626187 | 18 | * * Neither the name of the copyright holder nor the names of its |
AnnaBridge | 170:e95d10626187 | 19 | * contributors may be used to endorse or promote products derived from |
AnnaBridge | 170:e95d10626187 | 20 | * this software without specific prior written permission. |
AnnaBridge | 170:e95d10626187 | 21 | * |
AnnaBridge | 170:e95d10626187 | 22 | * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE |
AnnaBridge | 170:e95d10626187 | 23 | * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT |
AnnaBridge | 170:e95d10626187 | 24 | * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 170:e95d10626187 | 25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 170:e95d10626187 | 26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 170:e95d10626187 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
AnnaBridge | 170:e95d10626187 | 28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
AnnaBridge | 170:e95d10626187 | 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
AnnaBridge | 170:e95d10626187 | 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
AnnaBridge | 170:e95d10626187 | 31 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
AnnaBridge | 170:e95d10626187 | 32 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
AnnaBridge | 170:e95d10626187 | 33 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
AnnaBridge | 170:e95d10626187 | 34 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 161:aa5281ff4a02 | 35 | */ |
AnnaBridge | 161:aa5281ff4a02 | 36 | |
AnnaBridge | 161:aa5281ff4a02 | 37 | #ifndef _FSL_IOMUXC_H_ |
AnnaBridge | 161:aa5281ff4a02 | 38 | #define _FSL_IOMUXC_H_ |
AnnaBridge | 161:aa5281ff4a02 | 39 | |
AnnaBridge | 161:aa5281ff4a02 | 40 | #include "fsl_common.h" |
AnnaBridge | 161:aa5281ff4a02 | 41 | |
AnnaBridge | 161:aa5281ff4a02 | 42 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 43 | * @addtogroup iomuxc_driver |
AnnaBridge | 161:aa5281ff4a02 | 44 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 45 | */ |
AnnaBridge | 161:aa5281ff4a02 | 46 | |
AnnaBridge | 161:aa5281ff4a02 | 47 | /*! @file */ |
AnnaBridge | 161:aa5281ff4a02 | 48 | |
AnnaBridge | 161:aa5281ff4a02 | 49 | /******************************************************************************* |
AnnaBridge | 161:aa5281ff4a02 | 50 | * Definitions |
AnnaBridge | 161:aa5281ff4a02 | 51 | ******************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 52 | /* Component ID definition, used by tools. */ |
AnnaBridge | 170:e95d10626187 | 53 | #ifndef FSL_COMPONENT_ID |
AnnaBridge | 170:e95d10626187 | 54 | #define FSL_COMPONENT_ID "platform.drivers.iomuxc" |
AnnaBridge | 170:e95d10626187 | 55 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 56 | |
AnnaBridge | 161:aa5281ff4a02 | 57 | /*! @name Driver version */ |
AnnaBridge | 161:aa5281ff4a02 | 58 | /*@{*/ |
AnnaBridge | 161:aa5281ff4a02 | 59 | /*! @brief IOMUXC driver version 2.0.0. */ |
AnnaBridge | 161:aa5281ff4a02 | 60 | #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
AnnaBridge | 161:aa5281ff4a02 | 61 | /*@}*/ |
AnnaBridge | 161:aa5281ff4a02 | 62 | |
AnnaBridge | 161:aa5281ff4a02 | 63 | /*! @name Pin function ID */ |
AnnaBridge | 161:aa5281ff4a02 | 64 | /*@{*/ |
AnnaBridge | 161:aa5281ff4a02 | 65 | /*! @brief The pin function ID is a tuple of <muxRegister muxMode inputRegister inputDaisy configRegister> */ |
AnnaBridge | 161:aa5281ff4a02 | 66 | #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U |
AnnaBridge | 170:e95d10626187 | 67 | #define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U |
AnnaBridge | 161:aa5281ff4a02 | 68 | |
AnnaBridge | 161:aa5281ff4a02 | 69 | #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU |
AnnaBridge | 161:aa5281ff4a02 | 70 | #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU |
AnnaBridge | 161:aa5281ff4a02 | 71 | |
AnnaBridge | 161:aa5281ff4a02 | 72 | #define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U |
AnnaBridge | 161:aa5281ff4a02 | 73 | #define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U |
AnnaBridge | 161:aa5281ff4a02 | 74 | |
AnnaBridge | 161:aa5281ff4a02 | 75 | #define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU |
AnnaBridge | 161:aa5281ff4a02 | 76 | |
AnnaBridge | 161:aa5281ff4a02 | 77 | #define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U |
AnnaBridge | 161:aa5281ff4a02 | 78 | |
AnnaBridge | 161:aa5281ff4a02 | 79 | #define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U |
AnnaBridge | 161:aa5281ff4a02 | 80 | |
AnnaBridge | 161:aa5281ff4a02 | 81 | #define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U |
AnnaBridge | 161:aa5281ff4a02 | 82 | #define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U |
AnnaBridge | 161:aa5281ff4a02 | 83 | #define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U |
AnnaBridge | 161:aa5281ff4a02 | 84 | #define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U |
AnnaBridge | 161:aa5281ff4a02 | 85 | #define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U |
AnnaBridge | 161:aa5281ff4a02 | 86 | #define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U |
AnnaBridge | 161:aa5281ff4a02 | 87 | |
AnnaBridge | 161:aa5281ff4a02 | 88 | #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U |
AnnaBridge | 161:aa5281ff4a02 | 89 | #define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U |
AnnaBridge | 161:aa5281ff4a02 | 90 | #define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U |
AnnaBridge | 161:aa5281ff4a02 | 91 | #define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U |
AnnaBridge | 161:aa5281ff4a02 | 92 | #define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U |
AnnaBridge | 161:aa5281ff4a02 | 93 | #define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U |
AnnaBridge | 161:aa5281ff4a02 | 94 | |
AnnaBridge | 161:aa5281ff4a02 | 95 | #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU |
AnnaBridge | 161:aa5281ff4a02 | 96 | #define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU |
AnnaBridge | 161:aa5281ff4a02 | 97 | #define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU |
AnnaBridge | 161:aa5281ff4a02 | 98 | #define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU |
AnnaBridge | 161:aa5281ff4a02 | 99 | #define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU |
AnnaBridge | 161:aa5281ff4a02 | 100 | #define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU |
AnnaBridge | 161:aa5281ff4a02 | 101 | |
AnnaBridge | 161:aa5281ff4a02 | 102 | #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U |
AnnaBridge | 161:aa5281ff4a02 | 103 | #define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U |
AnnaBridge | 161:aa5281ff4a02 | 104 | #define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U |
AnnaBridge | 161:aa5281ff4a02 | 105 | #define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U |
AnnaBridge | 161:aa5281ff4a02 | 106 | #define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U |
AnnaBridge | 161:aa5281ff4a02 | 107 | #define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U |
AnnaBridge | 161:aa5281ff4a02 | 108 | |
AnnaBridge | 161:aa5281ff4a02 | 109 | #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U |
AnnaBridge | 161:aa5281ff4a02 | 110 | #define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U |
AnnaBridge | 161:aa5281ff4a02 | 111 | #define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U |
AnnaBridge | 161:aa5281ff4a02 | 112 | #define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U |
AnnaBridge | 161:aa5281ff4a02 | 113 | #define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U |
AnnaBridge | 161:aa5281ff4a02 | 114 | #define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U |
AnnaBridge | 161:aa5281ff4a02 | 115 | |
AnnaBridge | 161:aa5281ff4a02 | 116 | #define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U |
AnnaBridge | 161:aa5281ff4a02 | 117 | #define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U |
AnnaBridge | 161:aa5281ff4a02 | 118 | #define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U |
AnnaBridge | 161:aa5281ff4a02 | 119 | #define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U |
AnnaBridge | 161:aa5281ff4a02 | 120 | #define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U |
AnnaBridge | 161:aa5281ff4a02 | 121 | #define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U |
AnnaBridge | 161:aa5281ff4a02 | 122 | |
AnnaBridge | 161:aa5281ff4a02 | 123 | #define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU |
AnnaBridge | 161:aa5281ff4a02 | 124 | #define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU |
AnnaBridge | 161:aa5281ff4a02 | 125 | #define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU |
AnnaBridge | 161:aa5281ff4a02 | 126 | #define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU |
AnnaBridge | 161:aa5281ff4a02 | 127 | #define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU |
AnnaBridge | 161:aa5281ff4a02 | 128 | #define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU |
AnnaBridge | 161:aa5281ff4a02 | 129 | |
AnnaBridge | 161:aa5281ff4a02 | 130 | #define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U |
AnnaBridge | 161:aa5281ff4a02 | 131 | #define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U |
AnnaBridge | 161:aa5281ff4a02 | 132 | #define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U |
AnnaBridge | 161:aa5281ff4a02 | 133 | #define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U |
AnnaBridge | 161:aa5281ff4a02 | 134 | #define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U |
AnnaBridge | 161:aa5281ff4a02 | 135 | #define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U |
AnnaBridge | 161:aa5281ff4a02 | 136 | |
AnnaBridge | 161:aa5281ff4a02 | 137 | #define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U |
AnnaBridge | 161:aa5281ff4a02 | 138 | #define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U |
AnnaBridge | 161:aa5281ff4a02 | 139 | #define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U |
AnnaBridge | 161:aa5281ff4a02 | 140 | #define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U |
AnnaBridge | 161:aa5281ff4a02 | 141 | #define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U |
AnnaBridge | 161:aa5281ff4a02 | 142 | #define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U |
AnnaBridge | 161:aa5281ff4a02 | 143 | |
AnnaBridge | 161:aa5281ff4a02 | 144 | #define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U |
AnnaBridge | 161:aa5281ff4a02 | 145 | #define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U |
AnnaBridge | 161:aa5281ff4a02 | 146 | #define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U |
AnnaBridge | 161:aa5281ff4a02 | 147 | #define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U |
AnnaBridge | 161:aa5281ff4a02 | 148 | #define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U |
AnnaBridge | 161:aa5281ff4a02 | 149 | #define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U |
AnnaBridge | 161:aa5281ff4a02 | 150 | |
AnnaBridge | 161:aa5281ff4a02 | 151 | #define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU |
AnnaBridge | 161:aa5281ff4a02 | 152 | #define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU |
AnnaBridge | 161:aa5281ff4a02 | 153 | #define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU |
AnnaBridge | 161:aa5281ff4a02 | 154 | #define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU |
AnnaBridge | 161:aa5281ff4a02 | 155 | #define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU |
AnnaBridge | 161:aa5281ff4a02 | 156 | #define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU |
AnnaBridge | 161:aa5281ff4a02 | 157 | |
AnnaBridge | 161:aa5281ff4a02 | 158 | #define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U |
AnnaBridge | 161:aa5281ff4a02 | 159 | #define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U |
AnnaBridge | 161:aa5281ff4a02 | 160 | #define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U |
AnnaBridge | 161:aa5281ff4a02 | 161 | #define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U |
AnnaBridge | 161:aa5281ff4a02 | 162 | #define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U |
AnnaBridge | 161:aa5281ff4a02 | 163 | #define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U |
AnnaBridge | 161:aa5281ff4a02 | 164 | |
AnnaBridge | 161:aa5281ff4a02 | 165 | #define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U |
AnnaBridge | 161:aa5281ff4a02 | 166 | #define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U |
AnnaBridge | 161:aa5281ff4a02 | 167 | #define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U |
AnnaBridge | 161:aa5281ff4a02 | 168 | #define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U |
AnnaBridge | 161:aa5281ff4a02 | 169 | #define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U |
AnnaBridge | 161:aa5281ff4a02 | 170 | #define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U |
AnnaBridge | 161:aa5281ff4a02 | 171 | |
AnnaBridge | 161:aa5281ff4a02 | 172 | #define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U |
AnnaBridge | 161:aa5281ff4a02 | 173 | #define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U |
AnnaBridge | 161:aa5281ff4a02 | 174 | #define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U |
AnnaBridge | 161:aa5281ff4a02 | 175 | #define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U |
AnnaBridge | 161:aa5281ff4a02 | 176 | #define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U |
AnnaBridge | 161:aa5281ff4a02 | 177 | #define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U |
AnnaBridge | 161:aa5281ff4a02 | 178 | |
AnnaBridge | 161:aa5281ff4a02 | 179 | #define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU |
AnnaBridge | 161:aa5281ff4a02 | 180 | #define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU |
AnnaBridge | 161:aa5281ff4a02 | 181 | #define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU |
AnnaBridge | 161:aa5281ff4a02 | 182 | #define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU |
AnnaBridge | 161:aa5281ff4a02 | 183 | #define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU |
AnnaBridge | 161:aa5281ff4a02 | 184 | #define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU |
AnnaBridge | 161:aa5281ff4a02 | 185 | |
AnnaBridge | 161:aa5281ff4a02 | 186 | #define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U |
AnnaBridge | 161:aa5281ff4a02 | 187 | #define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U |
AnnaBridge | 161:aa5281ff4a02 | 188 | #define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U |
AnnaBridge | 161:aa5281ff4a02 | 189 | #define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U |
AnnaBridge | 161:aa5281ff4a02 | 190 | #define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U |
AnnaBridge | 161:aa5281ff4a02 | 191 | #define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U |
AnnaBridge | 161:aa5281ff4a02 | 192 | |
AnnaBridge | 161:aa5281ff4a02 | 193 | #define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U |
AnnaBridge | 161:aa5281ff4a02 | 194 | #define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U |
AnnaBridge | 161:aa5281ff4a02 | 195 | #define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U |
AnnaBridge | 161:aa5281ff4a02 | 196 | #define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U |
AnnaBridge | 161:aa5281ff4a02 | 197 | #define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U |
AnnaBridge | 161:aa5281ff4a02 | 198 | #define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U |
AnnaBridge | 161:aa5281ff4a02 | 199 | |
AnnaBridge | 161:aa5281ff4a02 | 200 | #define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U |
AnnaBridge | 161:aa5281ff4a02 | 201 | #define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U |
AnnaBridge | 161:aa5281ff4a02 | 202 | #define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U |
AnnaBridge | 161:aa5281ff4a02 | 203 | #define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U |
AnnaBridge | 161:aa5281ff4a02 | 204 | #define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U |
AnnaBridge | 161:aa5281ff4a02 | 205 | #define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U |
AnnaBridge | 161:aa5281ff4a02 | 206 | |
AnnaBridge | 161:aa5281ff4a02 | 207 | #define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 208 | #define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 209 | #define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 210 | #define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 211 | #define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 212 | #define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 213 | #define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU |
AnnaBridge | 161:aa5281ff4a02 | 214 | |
AnnaBridge | 161:aa5281ff4a02 | 215 | #define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 216 | #define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 217 | #define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 218 | #define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 219 | #define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 220 | #define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 221 | #define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U |
AnnaBridge | 161:aa5281ff4a02 | 222 | |
AnnaBridge | 161:aa5281ff4a02 | 223 | #define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U |
AnnaBridge | 161:aa5281ff4a02 | 224 | #define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U |
AnnaBridge | 161:aa5281ff4a02 | 225 | #define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U |
AnnaBridge | 161:aa5281ff4a02 | 226 | #define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U |
AnnaBridge | 161:aa5281ff4a02 | 227 | #define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U |
AnnaBridge | 161:aa5281ff4a02 | 228 | #define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U |
AnnaBridge | 161:aa5281ff4a02 | 229 | |
AnnaBridge | 161:aa5281ff4a02 | 230 | #define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U |
AnnaBridge | 161:aa5281ff4a02 | 231 | #define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U |
AnnaBridge | 161:aa5281ff4a02 | 232 | #define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U |
AnnaBridge | 161:aa5281ff4a02 | 233 | #define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U |
AnnaBridge | 161:aa5281ff4a02 | 234 | #define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U |
AnnaBridge | 161:aa5281ff4a02 | 235 | #define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U |
AnnaBridge | 161:aa5281ff4a02 | 236 | |
AnnaBridge | 161:aa5281ff4a02 | 237 | #define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU |
AnnaBridge | 161:aa5281ff4a02 | 238 | #define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU |
AnnaBridge | 161:aa5281ff4a02 | 239 | #define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU |
AnnaBridge | 161:aa5281ff4a02 | 240 | #define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU |
AnnaBridge | 161:aa5281ff4a02 | 241 | #define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU |
AnnaBridge | 161:aa5281ff4a02 | 242 | #define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU |
AnnaBridge | 161:aa5281ff4a02 | 243 | |
AnnaBridge | 161:aa5281ff4a02 | 244 | #define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U |
AnnaBridge | 161:aa5281ff4a02 | 245 | #define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U |
AnnaBridge | 161:aa5281ff4a02 | 246 | #define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U |
AnnaBridge | 161:aa5281ff4a02 | 247 | #define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U |
AnnaBridge | 161:aa5281ff4a02 | 248 | #define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U |
AnnaBridge | 161:aa5281ff4a02 | 249 | #define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U |
AnnaBridge | 161:aa5281ff4a02 | 250 | |
AnnaBridge | 161:aa5281ff4a02 | 251 | #define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U |
AnnaBridge | 161:aa5281ff4a02 | 252 | #define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U |
AnnaBridge | 161:aa5281ff4a02 | 253 | #define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U |
AnnaBridge | 161:aa5281ff4a02 | 254 | #define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U |
AnnaBridge | 161:aa5281ff4a02 | 255 | #define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U |
AnnaBridge | 161:aa5281ff4a02 | 256 | #define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U |
AnnaBridge | 161:aa5281ff4a02 | 257 | |
AnnaBridge | 161:aa5281ff4a02 | 258 | #define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U |
AnnaBridge | 161:aa5281ff4a02 | 259 | #define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U |
AnnaBridge | 161:aa5281ff4a02 | 260 | #define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U |
AnnaBridge | 161:aa5281ff4a02 | 261 | #define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U |
AnnaBridge | 161:aa5281ff4a02 | 262 | #define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U |
AnnaBridge | 161:aa5281ff4a02 | 263 | #define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U |
AnnaBridge | 161:aa5281ff4a02 | 264 | |
AnnaBridge | 161:aa5281ff4a02 | 265 | #define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU |
AnnaBridge | 161:aa5281ff4a02 | 266 | #define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU |
AnnaBridge | 161:aa5281ff4a02 | 267 | #define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU |
AnnaBridge | 161:aa5281ff4a02 | 268 | #define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU |
AnnaBridge | 161:aa5281ff4a02 | 269 | #define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU |
AnnaBridge | 161:aa5281ff4a02 | 270 | #define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU |
AnnaBridge | 161:aa5281ff4a02 | 271 | |
AnnaBridge | 161:aa5281ff4a02 | 272 | #define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U |
AnnaBridge | 161:aa5281ff4a02 | 273 | #define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U |
AnnaBridge | 161:aa5281ff4a02 | 274 | #define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U |
AnnaBridge | 161:aa5281ff4a02 | 275 | #define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U |
AnnaBridge | 161:aa5281ff4a02 | 276 | #define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U |
AnnaBridge | 161:aa5281ff4a02 | 277 | #define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U |
AnnaBridge | 161:aa5281ff4a02 | 278 | |
AnnaBridge | 161:aa5281ff4a02 | 279 | #define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U |
AnnaBridge | 161:aa5281ff4a02 | 280 | #define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U |
AnnaBridge | 161:aa5281ff4a02 | 281 | #define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U |
AnnaBridge | 161:aa5281ff4a02 | 282 | #define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U |
AnnaBridge | 161:aa5281ff4a02 | 283 | #define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U |
AnnaBridge | 161:aa5281ff4a02 | 284 | #define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U |
AnnaBridge | 161:aa5281ff4a02 | 285 | |
AnnaBridge | 161:aa5281ff4a02 | 286 | #define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U |
AnnaBridge | 161:aa5281ff4a02 | 287 | #define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U |
AnnaBridge | 161:aa5281ff4a02 | 288 | #define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U |
AnnaBridge | 161:aa5281ff4a02 | 289 | #define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U |
AnnaBridge | 161:aa5281ff4a02 | 290 | #define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U |
AnnaBridge | 161:aa5281ff4a02 | 291 | #define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U |
AnnaBridge | 161:aa5281ff4a02 | 292 | |
AnnaBridge | 161:aa5281ff4a02 | 293 | #define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU |
AnnaBridge | 161:aa5281ff4a02 | 294 | #define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU |
AnnaBridge | 161:aa5281ff4a02 | 295 | #define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU |
AnnaBridge | 161:aa5281ff4a02 | 296 | #define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU |
AnnaBridge | 161:aa5281ff4a02 | 297 | #define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU |
AnnaBridge | 161:aa5281ff4a02 | 298 | #define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU |
AnnaBridge | 161:aa5281ff4a02 | 299 | |
AnnaBridge | 161:aa5281ff4a02 | 300 | #define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U |
AnnaBridge | 161:aa5281ff4a02 | 301 | #define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U |
AnnaBridge | 161:aa5281ff4a02 | 302 | #define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U |
AnnaBridge | 161:aa5281ff4a02 | 303 | #define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U |
AnnaBridge | 161:aa5281ff4a02 | 304 | #define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U |
AnnaBridge | 161:aa5281ff4a02 | 305 | #define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U |
AnnaBridge | 161:aa5281ff4a02 | 306 | |
AnnaBridge | 161:aa5281ff4a02 | 307 | #define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U |
AnnaBridge | 161:aa5281ff4a02 | 308 | #define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U |
AnnaBridge | 161:aa5281ff4a02 | 309 | #define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U |
AnnaBridge | 161:aa5281ff4a02 | 310 | #define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U |
AnnaBridge | 161:aa5281ff4a02 | 311 | #define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U |
AnnaBridge | 161:aa5281ff4a02 | 312 | #define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U |
AnnaBridge | 161:aa5281ff4a02 | 313 | |
AnnaBridge | 161:aa5281ff4a02 | 314 | #define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U |
AnnaBridge | 161:aa5281ff4a02 | 315 | #define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U |
AnnaBridge | 161:aa5281ff4a02 | 316 | #define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U |
AnnaBridge | 161:aa5281ff4a02 | 317 | #define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U |
AnnaBridge | 161:aa5281ff4a02 | 318 | #define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U |
AnnaBridge | 161:aa5281ff4a02 | 319 | #define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U |
AnnaBridge | 161:aa5281ff4a02 | 320 | |
AnnaBridge | 161:aa5281ff4a02 | 321 | #define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU |
AnnaBridge | 161:aa5281ff4a02 | 322 | #define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU |
AnnaBridge | 161:aa5281ff4a02 | 323 | #define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU |
AnnaBridge | 161:aa5281ff4a02 | 324 | #define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU |
AnnaBridge | 161:aa5281ff4a02 | 325 | #define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU |
AnnaBridge | 161:aa5281ff4a02 | 326 | #define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU |
AnnaBridge | 161:aa5281ff4a02 | 327 | |
AnnaBridge | 161:aa5281ff4a02 | 328 | #define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 329 | #define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 330 | #define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 331 | #define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 332 | #define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 333 | #define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 334 | #define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U |
AnnaBridge | 161:aa5281ff4a02 | 335 | |
AnnaBridge | 161:aa5281ff4a02 | 336 | #define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 337 | #define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 338 | #define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 339 | #define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 340 | #define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 341 | #define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 342 | #define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U |
AnnaBridge | 161:aa5281ff4a02 | 343 | |
AnnaBridge | 161:aa5281ff4a02 | 344 | #define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 345 | #define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 346 | #define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 347 | #define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 348 | #define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 349 | #define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 350 | #define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U |
AnnaBridge | 161:aa5281ff4a02 | 351 | |
AnnaBridge | 161:aa5281ff4a02 | 352 | #define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 353 | #define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 354 | #define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 355 | #define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 356 | #define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 357 | #define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 358 | #define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU |
AnnaBridge | 161:aa5281ff4a02 | 359 | |
AnnaBridge | 161:aa5281ff4a02 | 360 | #define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 361 | #define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 362 | #define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 363 | #define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 364 | #define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 365 | #define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 366 | #define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U |
AnnaBridge | 161:aa5281ff4a02 | 367 | |
AnnaBridge | 161:aa5281ff4a02 | 368 | #define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 369 | #define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 370 | #define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 371 | #define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 372 | #define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 373 | #define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 374 | #define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U |
AnnaBridge | 161:aa5281ff4a02 | 375 | |
AnnaBridge | 161:aa5281ff4a02 | 376 | #define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 377 | #define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 378 | #define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 379 | #define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 380 | #define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 381 | #define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 382 | #define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U |
AnnaBridge | 161:aa5281ff4a02 | 383 | |
AnnaBridge | 161:aa5281ff4a02 | 384 | #define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 385 | #define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 386 | #define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 387 | #define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 388 | #define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 389 | #define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 390 | #define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 391 | #define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU |
AnnaBridge | 161:aa5281ff4a02 | 392 | |
AnnaBridge | 161:aa5281ff4a02 | 393 | #define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 394 | #define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 395 | #define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 396 | #define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 397 | #define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 398 | #define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 399 | #define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 400 | #define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U |
AnnaBridge | 161:aa5281ff4a02 | 401 | |
AnnaBridge | 161:aa5281ff4a02 | 402 | #define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 403 | #define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 404 | #define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 405 | #define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 406 | #define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 407 | #define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 408 | #define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 409 | #define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U |
AnnaBridge | 161:aa5281ff4a02 | 410 | |
AnnaBridge | 161:aa5281ff4a02 | 411 | #define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 412 | #define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 413 | #define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 414 | #define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 415 | #define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 416 | #define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 417 | #define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 418 | #define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U |
AnnaBridge | 161:aa5281ff4a02 | 419 | |
AnnaBridge | 161:aa5281ff4a02 | 420 | #define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 421 | #define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 422 | #define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 423 | #define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 424 | #define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 425 | #define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 426 | #define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 427 | #define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU |
AnnaBridge | 161:aa5281ff4a02 | 428 | |
AnnaBridge | 161:aa5281ff4a02 | 429 | #define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 430 | #define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 431 | #define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 432 | #define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 433 | #define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 434 | #define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 435 | #define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 436 | #define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U |
AnnaBridge | 161:aa5281ff4a02 | 437 | |
AnnaBridge | 161:aa5281ff4a02 | 438 | #define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 439 | #define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 440 | #define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 441 | #define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 442 | #define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 443 | #define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 444 | #define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 445 | #define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U |
AnnaBridge | 161:aa5281ff4a02 | 446 | |
AnnaBridge | 161:aa5281ff4a02 | 447 | #define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 448 | #define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 449 | #define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 450 | #define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 451 | #define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 452 | #define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 453 | #define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 454 | #define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U |
AnnaBridge | 161:aa5281ff4a02 | 455 | |
AnnaBridge | 161:aa5281ff4a02 | 456 | #define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 457 | #define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 458 | #define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 459 | #define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 460 | #define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 461 | #define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 462 | #define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 463 | #define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU |
AnnaBridge | 161:aa5281ff4a02 | 464 | |
AnnaBridge | 161:aa5281ff4a02 | 465 | #define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 466 | #define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 467 | #define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 468 | #define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 469 | #define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 470 | #define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 471 | #define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 472 | #define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U |
AnnaBridge | 161:aa5281ff4a02 | 473 | |
AnnaBridge | 161:aa5281ff4a02 | 474 | #define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 475 | #define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 476 | #define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 477 | #define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 478 | #define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 479 | #define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 480 | #define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 481 | #define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U |
AnnaBridge | 161:aa5281ff4a02 | 482 | |
AnnaBridge | 161:aa5281ff4a02 | 483 | #define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 484 | #define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 485 | #define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 486 | #define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 487 | #define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 488 | #define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 489 | #define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 490 | #define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U |
AnnaBridge | 161:aa5281ff4a02 | 491 | |
AnnaBridge | 161:aa5281ff4a02 | 492 | #define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 493 | #define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 494 | #define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 495 | #define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 496 | #define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 497 | #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 498 | #define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU |
AnnaBridge | 170:e95d10626187 | 499 | #define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU |
AnnaBridge | 161:aa5281ff4a02 | 500 | |
AnnaBridge | 161:aa5281ff4a02 | 501 | #define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 502 | #define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 503 | #define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 504 | #define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 505 | #define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 506 | #define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 507 | #define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 508 | #define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U |
AnnaBridge | 161:aa5281ff4a02 | 509 | |
AnnaBridge | 161:aa5281ff4a02 | 510 | #define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 511 | #define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 512 | #define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 513 | #define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 514 | #define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 515 | #define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 516 | #define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U |
AnnaBridge | 161:aa5281ff4a02 | 517 | |
AnnaBridge | 161:aa5281ff4a02 | 518 | #define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 519 | #define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 520 | #define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 521 | #define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 522 | #define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 523 | #define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 524 | #define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 525 | #define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U |
AnnaBridge | 161:aa5281ff4a02 | 526 | |
AnnaBridge | 161:aa5281ff4a02 | 527 | #define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 528 | #define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 529 | #define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 530 | #define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 531 | #define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 532 | #define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 533 | #define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 534 | #define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU |
AnnaBridge | 161:aa5281ff4a02 | 535 | |
AnnaBridge | 161:aa5281ff4a02 | 536 | #define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 537 | #define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 538 | #define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 539 | #define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 540 | #define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 541 | #define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 542 | #define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 543 | #define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U |
AnnaBridge | 161:aa5281ff4a02 | 544 | |
AnnaBridge | 161:aa5281ff4a02 | 545 | #define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 546 | #define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 547 | #define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 548 | #define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 549 | #define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 550 | #define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 551 | #define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 552 | #define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U |
AnnaBridge | 161:aa5281ff4a02 | 553 | |
AnnaBridge | 161:aa5281ff4a02 | 554 | #define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 555 | #define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 556 | #define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 557 | #define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 558 | #define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 559 | #define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 560 | #define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 561 | #define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U |
AnnaBridge | 161:aa5281ff4a02 | 562 | |
AnnaBridge | 161:aa5281ff4a02 | 563 | #define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 564 | #define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 565 | #define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 566 | #define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 567 | #define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 568 | #define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 569 | #define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 570 | #define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU |
AnnaBridge | 161:aa5281ff4a02 | 571 | |
AnnaBridge | 161:aa5281ff4a02 | 572 | #define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 573 | #define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 574 | #define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 575 | #define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 576 | #define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 577 | #define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 578 | #define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 579 | #define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U |
AnnaBridge | 161:aa5281ff4a02 | 580 | |
AnnaBridge | 161:aa5281ff4a02 | 581 | #define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 582 | #define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 583 | #define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 584 | #define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 585 | #define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 586 | #define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 587 | #define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 588 | #define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U |
AnnaBridge | 161:aa5281ff4a02 | 589 | |
AnnaBridge | 161:aa5281ff4a02 | 590 | #define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 591 | #define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 592 | #define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 593 | #define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 594 | #define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 595 | #define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 596 | #define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 597 | #define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U |
AnnaBridge | 161:aa5281ff4a02 | 598 | |
AnnaBridge | 161:aa5281ff4a02 | 599 | #define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 600 | #define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 601 | #define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 602 | #define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 603 | #define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 604 | #define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 605 | #define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 606 | #define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU |
AnnaBridge | 161:aa5281ff4a02 | 607 | |
AnnaBridge | 161:aa5281ff4a02 | 608 | #define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 609 | #define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 610 | #define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 611 | #define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 612 | #define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 613 | #define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 614 | #define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 615 | #define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U |
AnnaBridge | 161:aa5281ff4a02 | 616 | |
AnnaBridge | 161:aa5281ff4a02 | 617 | #define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 618 | #define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 619 | #define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 620 | #define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 621 | #define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 622 | #define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 623 | #define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 624 | #define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U |
AnnaBridge | 161:aa5281ff4a02 | 625 | |
AnnaBridge | 161:aa5281ff4a02 | 626 | #define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 627 | #define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 628 | #define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 629 | #define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 630 | #define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 631 | #define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 632 | #define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 633 | #define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U |
AnnaBridge | 161:aa5281ff4a02 | 634 | |
AnnaBridge | 161:aa5281ff4a02 | 635 | #define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 636 | #define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 637 | #define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 638 | #define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 639 | #define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 640 | #define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 641 | #define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 642 | #define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU |
AnnaBridge | 161:aa5281ff4a02 | 643 | |
AnnaBridge | 161:aa5281ff4a02 | 644 | #define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 645 | #define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 646 | #define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 647 | #define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 648 | #define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 649 | #define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 650 | #define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 651 | #define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U |
AnnaBridge | 161:aa5281ff4a02 | 652 | |
AnnaBridge | 161:aa5281ff4a02 | 653 | #define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 654 | #define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 655 | #define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 656 | #define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 657 | #define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 658 | #define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 659 | #define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 660 | #define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U |
AnnaBridge | 161:aa5281ff4a02 | 661 | |
AnnaBridge | 161:aa5281ff4a02 | 662 | #define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 663 | #define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 664 | #define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 665 | #define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 666 | #define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 667 | #define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 668 | #define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 669 | #define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U |
AnnaBridge | 161:aa5281ff4a02 | 670 | |
AnnaBridge | 161:aa5281ff4a02 | 671 | #define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 672 | #define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 673 | #define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 674 | #define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 675 | #define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 676 | #define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 677 | #define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU |
AnnaBridge | 161:aa5281ff4a02 | 678 | |
AnnaBridge | 161:aa5281ff4a02 | 679 | #define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 680 | #define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 681 | #define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 682 | #define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 683 | #define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 684 | #define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 685 | #define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U |
AnnaBridge | 161:aa5281ff4a02 | 686 | |
AnnaBridge | 161:aa5281ff4a02 | 687 | #define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 688 | #define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 689 | #define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 690 | #define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 691 | #define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 692 | #define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 693 | #define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U |
AnnaBridge | 161:aa5281ff4a02 | 694 | |
AnnaBridge | 161:aa5281ff4a02 | 695 | #define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 696 | #define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 697 | #define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 698 | #define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 699 | #define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 700 | #define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 701 | #define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U |
AnnaBridge | 161:aa5281ff4a02 | 702 | |
AnnaBridge | 161:aa5281ff4a02 | 703 | #define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU |
AnnaBridge | 161:aa5281ff4a02 | 704 | #define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU |
AnnaBridge | 161:aa5281ff4a02 | 705 | #define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU |
AnnaBridge | 170:e95d10626187 | 706 | #define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU |
AnnaBridge | 161:aa5281ff4a02 | 707 | #define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU |
AnnaBridge | 161:aa5281ff4a02 | 708 | #define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU |
AnnaBridge | 161:aa5281ff4a02 | 709 | #define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU |
AnnaBridge | 161:aa5281ff4a02 | 710 | |
AnnaBridge | 161:aa5281ff4a02 | 711 | #define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U |
AnnaBridge | 161:aa5281ff4a02 | 712 | #define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U |
AnnaBridge | 161:aa5281ff4a02 | 713 | #define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U |
AnnaBridge | 170:e95d10626187 | 714 | #define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U |
AnnaBridge | 161:aa5281ff4a02 | 715 | #define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U |
AnnaBridge | 161:aa5281ff4a02 | 716 | #define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U |
AnnaBridge | 161:aa5281ff4a02 | 717 | #define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U |
AnnaBridge | 161:aa5281ff4a02 | 718 | |
AnnaBridge | 161:aa5281ff4a02 | 719 | #define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U |
AnnaBridge | 161:aa5281ff4a02 | 720 | #define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U |
AnnaBridge | 161:aa5281ff4a02 | 721 | #define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U |
AnnaBridge | 170:e95d10626187 | 722 | #define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U |
AnnaBridge | 161:aa5281ff4a02 | 723 | #define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U |
AnnaBridge | 161:aa5281ff4a02 | 724 | #define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U |
AnnaBridge | 161:aa5281ff4a02 | 725 | #define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U |
AnnaBridge | 161:aa5281ff4a02 | 726 | |
AnnaBridge | 161:aa5281ff4a02 | 727 | #define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U |
AnnaBridge | 161:aa5281ff4a02 | 728 | #define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U |
AnnaBridge | 161:aa5281ff4a02 | 729 | #define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U |
AnnaBridge | 170:e95d10626187 | 730 | #define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U |
AnnaBridge | 161:aa5281ff4a02 | 731 | #define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U |
AnnaBridge | 161:aa5281ff4a02 | 732 | #define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U |
AnnaBridge | 161:aa5281ff4a02 | 733 | #define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U |
AnnaBridge | 161:aa5281ff4a02 | 734 | |
AnnaBridge | 161:aa5281ff4a02 | 735 | #define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 736 | #define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 737 | #define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 738 | #define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 739 | #define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 740 | #define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 741 | #define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU |
AnnaBridge | 161:aa5281ff4a02 | 742 | |
AnnaBridge | 161:aa5281ff4a02 | 743 | #define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 744 | #define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 745 | #define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 746 | #define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 747 | #define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 748 | #define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 749 | #define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U |
AnnaBridge | 161:aa5281ff4a02 | 750 | |
AnnaBridge | 161:aa5281ff4a02 | 751 | #define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 752 | #define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 753 | #define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 754 | #define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 755 | #define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 756 | #define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 757 | #define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U |
AnnaBridge | 161:aa5281ff4a02 | 758 | |
AnnaBridge | 161:aa5281ff4a02 | 759 | #define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 760 | #define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 761 | #define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 762 | #define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 763 | #define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 764 | #define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 765 | #define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U |
AnnaBridge | 161:aa5281ff4a02 | 766 | |
AnnaBridge | 161:aa5281ff4a02 | 767 | #define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU |
AnnaBridge | 161:aa5281ff4a02 | 768 | #define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU |
AnnaBridge | 170:e95d10626187 | 769 | #define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU |
AnnaBridge | 161:aa5281ff4a02 | 770 | #define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU |
AnnaBridge | 161:aa5281ff4a02 | 771 | #define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU |
AnnaBridge | 161:aa5281ff4a02 | 772 | #define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU |
AnnaBridge | 161:aa5281ff4a02 | 773 | #define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU |
AnnaBridge | 161:aa5281ff4a02 | 774 | |
AnnaBridge | 161:aa5281ff4a02 | 775 | #define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U |
AnnaBridge | 161:aa5281ff4a02 | 776 | #define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U |
AnnaBridge | 170:e95d10626187 | 777 | #define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U |
AnnaBridge | 161:aa5281ff4a02 | 778 | #define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U |
AnnaBridge | 161:aa5281ff4a02 | 779 | #define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U |
AnnaBridge | 161:aa5281ff4a02 | 780 | #define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U |
AnnaBridge | 161:aa5281ff4a02 | 781 | #define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U |
AnnaBridge | 161:aa5281ff4a02 | 782 | |
AnnaBridge | 161:aa5281ff4a02 | 783 | #define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 784 | #define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 785 | #define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 786 | #define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 787 | #define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 788 | #define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 789 | #define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U |
AnnaBridge | 161:aa5281ff4a02 | 790 | |
AnnaBridge | 161:aa5281ff4a02 | 791 | #define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 792 | #define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 793 | #define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 794 | #define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 795 | #define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 796 | #define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 797 | #define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U |
AnnaBridge | 161:aa5281ff4a02 | 798 | |
AnnaBridge | 161:aa5281ff4a02 | 799 | #define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 800 | #define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 801 | #define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 802 | #define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 803 | #define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 804 | #define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 805 | #define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU |
AnnaBridge | 161:aa5281ff4a02 | 806 | |
AnnaBridge | 161:aa5281ff4a02 | 807 | #define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 808 | #define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 809 | #define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 810 | #define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 811 | #define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 812 | #define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 813 | #define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U |
AnnaBridge | 161:aa5281ff4a02 | 814 | |
AnnaBridge | 161:aa5281ff4a02 | 815 | #define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 816 | #define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 817 | #define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 818 | #define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 819 | #define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 820 | #define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 821 | #define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U |
AnnaBridge | 161:aa5281ff4a02 | 822 | |
AnnaBridge | 161:aa5281ff4a02 | 823 | #define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 824 | #define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 825 | #define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 826 | #define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 827 | #define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 828 | #define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 829 | #define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U |
AnnaBridge | 161:aa5281ff4a02 | 830 | |
AnnaBridge | 161:aa5281ff4a02 | 831 | #define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU |
AnnaBridge | 161:aa5281ff4a02 | 832 | #define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU |
AnnaBridge | 161:aa5281ff4a02 | 833 | #define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU |
AnnaBridge | 161:aa5281ff4a02 | 834 | #define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU |
AnnaBridge | 161:aa5281ff4a02 | 835 | #define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU |
AnnaBridge | 161:aa5281ff4a02 | 836 | #define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU |
AnnaBridge | 161:aa5281ff4a02 | 837 | |
AnnaBridge | 161:aa5281ff4a02 | 838 | #define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U |
AnnaBridge | 161:aa5281ff4a02 | 839 | #define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U |
AnnaBridge | 161:aa5281ff4a02 | 840 | #define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U |
AnnaBridge | 161:aa5281ff4a02 | 841 | #define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U |
AnnaBridge | 161:aa5281ff4a02 | 842 | #define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U |
AnnaBridge | 161:aa5281ff4a02 | 843 | #define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U |
AnnaBridge | 161:aa5281ff4a02 | 844 | |
AnnaBridge | 161:aa5281ff4a02 | 845 | #define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U |
AnnaBridge | 161:aa5281ff4a02 | 846 | #define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U |
AnnaBridge | 161:aa5281ff4a02 | 847 | #define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U |
AnnaBridge | 161:aa5281ff4a02 | 848 | #define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U |
AnnaBridge | 161:aa5281ff4a02 | 849 | #define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U |
AnnaBridge | 161:aa5281ff4a02 | 850 | #define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U |
AnnaBridge | 161:aa5281ff4a02 | 851 | |
AnnaBridge | 161:aa5281ff4a02 | 852 | #define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U |
AnnaBridge | 161:aa5281ff4a02 | 853 | #define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U |
AnnaBridge | 161:aa5281ff4a02 | 854 | #define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U |
AnnaBridge | 161:aa5281ff4a02 | 855 | #define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U |
AnnaBridge | 161:aa5281ff4a02 | 856 | #define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U |
AnnaBridge | 161:aa5281ff4a02 | 857 | #define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U |
AnnaBridge | 161:aa5281ff4a02 | 858 | |
AnnaBridge | 161:aa5281ff4a02 | 859 | #define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 860 | #define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 861 | #define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 862 | #define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 863 | #define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 864 | #define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 865 | #define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU |
AnnaBridge | 161:aa5281ff4a02 | 866 | |
AnnaBridge | 161:aa5281ff4a02 | 867 | #define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 868 | #define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 869 | #define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 870 | #define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 871 | #define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 872 | #define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 873 | #define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U |
AnnaBridge | 161:aa5281ff4a02 | 874 | |
AnnaBridge | 161:aa5281ff4a02 | 875 | #define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 876 | #define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 877 | #define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 878 | #define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 879 | #define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 880 | #define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 881 | #define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U |
AnnaBridge | 161:aa5281ff4a02 | 882 | |
AnnaBridge | 161:aa5281ff4a02 | 883 | #define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 884 | #define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 885 | #define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 886 | #define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 887 | #define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 888 | #define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 889 | #define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U |
AnnaBridge | 161:aa5281ff4a02 | 890 | |
AnnaBridge | 161:aa5281ff4a02 | 891 | #define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU |
AnnaBridge | 161:aa5281ff4a02 | 892 | #define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU |
AnnaBridge | 161:aa5281ff4a02 | 893 | #define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU |
AnnaBridge | 161:aa5281ff4a02 | 894 | #define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU |
AnnaBridge | 161:aa5281ff4a02 | 895 | #define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU |
AnnaBridge | 161:aa5281ff4a02 | 896 | #define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU |
AnnaBridge | 161:aa5281ff4a02 | 897 | |
AnnaBridge | 161:aa5281ff4a02 | 898 | #define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 899 | #define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 900 | #define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 901 | #define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 902 | #define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 903 | #define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 904 | #define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U |
AnnaBridge | 161:aa5281ff4a02 | 905 | |
AnnaBridge | 161:aa5281ff4a02 | 906 | #define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 907 | #define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 908 | #define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 909 | #define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 910 | #define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 911 | #define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 912 | #define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U |
AnnaBridge | 161:aa5281ff4a02 | 913 | |
AnnaBridge | 161:aa5281ff4a02 | 914 | #define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 915 | #define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 916 | #define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 917 | #define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 918 | #define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 919 | #define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 920 | #define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U |
AnnaBridge | 161:aa5281ff4a02 | 921 | |
AnnaBridge | 161:aa5281ff4a02 | 922 | #define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 923 | #define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 924 | #define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 925 | #define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 926 | #define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 927 | #define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 928 | #define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU |
AnnaBridge | 161:aa5281ff4a02 | 929 | |
AnnaBridge | 161:aa5281ff4a02 | 930 | #define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 931 | #define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 932 | #define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 933 | #define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 934 | #define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 935 | #define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 936 | #define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U |
AnnaBridge | 161:aa5281ff4a02 | 937 | |
AnnaBridge | 161:aa5281ff4a02 | 938 | #define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U |
AnnaBridge | 161:aa5281ff4a02 | 939 | #define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U |
AnnaBridge | 161:aa5281ff4a02 | 940 | #define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U |
AnnaBridge | 161:aa5281ff4a02 | 941 | #define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U |
AnnaBridge | 161:aa5281ff4a02 | 942 | #define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U |
AnnaBridge | 161:aa5281ff4a02 | 943 | #define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U |
AnnaBridge | 161:aa5281ff4a02 | 944 | |
AnnaBridge | 161:aa5281ff4a02 | 945 | #define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U |
AnnaBridge | 161:aa5281ff4a02 | 946 | #define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U |
AnnaBridge | 161:aa5281ff4a02 | 947 | #define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U |
AnnaBridge | 161:aa5281ff4a02 | 948 | #define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U |
AnnaBridge | 161:aa5281ff4a02 | 949 | #define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U |
AnnaBridge | 161:aa5281ff4a02 | 950 | #define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U |
AnnaBridge | 161:aa5281ff4a02 | 951 | |
AnnaBridge | 161:aa5281ff4a02 | 952 | #define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 953 | #define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 954 | #define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 955 | #define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 956 | #define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 957 | #define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 958 | #define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU |
AnnaBridge | 161:aa5281ff4a02 | 959 | |
AnnaBridge | 161:aa5281ff4a02 | 960 | #define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 961 | #define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 962 | #define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 963 | #define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 964 | #define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 965 | #define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 966 | #define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U |
AnnaBridge | 161:aa5281ff4a02 | 967 | |
AnnaBridge | 161:aa5281ff4a02 | 968 | #define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U |
AnnaBridge | 161:aa5281ff4a02 | 969 | #define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U |
AnnaBridge | 161:aa5281ff4a02 | 970 | #define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U |
AnnaBridge | 161:aa5281ff4a02 | 971 | #define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U |
AnnaBridge | 161:aa5281ff4a02 | 972 | #define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U |
AnnaBridge | 161:aa5281ff4a02 | 973 | #define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U |
AnnaBridge | 161:aa5281ff4a02 | 974 | |
AnnaBridge | 161:aa5281ff4a02 | 975 | #define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U |
AnnaBridge | 161:aa5281ff4a02 | 976 | #define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U |
AnnaBridge | 161:aa5281ff4a02 | 977 | #define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U |
AnnaBridge | 161:aa5281ff4a02 | 978 | #define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U |
AnnaBridge | 161:aa5281ff4a02 | 979 | #define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U |
AnnaBridge | 161:aa5281ff4a02 | 980 | #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U |
AnnaBridge | 161:aa5281ff4a02 | 981 | |
AnnaBridge | 161:aa5281ff4a02 | 982 | #define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 983 | #define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 984 | #define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 985 | #define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 986 | #define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 987 | #define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 988 | #define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU |
AnnaBridge | 161:aa5281ff4a02 | 989 | |
AnnaBridge | 161:aa5281ff4a02 | 990 | #define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 991 | #define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 992 | #define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 993 | #define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 994 | #define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 995 | #define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 996 | #define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U |
AnnaBridge | 161:aa5281ff4a02 | 997 | |
AnnaBridge | 161:aa5281ff4a02 | 998 | #define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 999 | #define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 1000 | #define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 1001 | #define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 1002 | #define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 1003 | #define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 1004 | #define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U |
AnnaBridge | 161:aa5281ff4a02 | 1005 | |
AnnaBridge | 161:aa5281ff4a02 | 1006 | #define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U |
AnnaBridge | 161:aa5281ff4a02 | 1007 | #define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U |
AnnaBridge | 161:aa5281ff4a02 | 1008 | #define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U |
AnnaBridge | 161:aa5281ff4a02 | 1009 | #define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U |
AnnaBridge | 161:aa5281ff4a02 | 1010 | #define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U |
AnnaBridge | 161:aa5281ff4a02 | 1011 | #define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U |
AnnaBridge | 161:aa5281ff4a02 | 1012 | |
AnnaBridge | 161:aa5281ff4a02 | 1013 | #define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU |
AnnaBridge | 161:aa5281ff4a02 | 1014 | #define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU |
AnnaBridge | 161:aa5281ff4a02 | 1015 | #define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU |
AnnaBridge | 161:aa5281ff4a02 | 1016 | #define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU |
AnnaBridge | 161:aa5281ff4a02 | 1017 | #define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU |
AnnaBridge | 161:aa5281ff4a02 | 1018 | #define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU |
AnnaBridge | 161:aa5281ff4a02 | 1019 | |
AnnaBridge | 161:aa5281ff4a02 | 1020 | #define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U |
AnnaBridge | 161:aa5281ff4a02 | 1021 | #define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U |
AnnaBridge | 161:aa5281ff4a02 | 1022 | #define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U |
AnnaBridge | 161:aa5281ff4a02 | 1023 | #define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U |
AnnaBridge | 161:aa5281ff4a02 | 1024 | #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U |
AnnaBridge | 161:aa5281ff4a02 | 1025 | #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U |
AnnaBridge | 161:aa5281ff4a02 | 1026 | |
AnnaBridge | 161:aa5281ff4a02 | 1027 | #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1028 | #define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1029 | #define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1030 | #define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1031 | #define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1032 | #define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1033 | #define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U |
AnnaBridge | 161:aa5281ff4a02 | 1034 | |
AnnaBridge | 161:aa5281ff4a02 | 1035 | #define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U |
AnnaBridge | 161:aa5281ff4a02 | 1036 | #define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U |
AnnaBridge | 161:aa5281ff4a02 | 1037 | #define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U |
AnnaBridge | 161:aa5281ff4a02 | 1038 | #define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U |
AnnaBridge | 161:aa5281ff4a02 | 1039 | #define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U |
AnnaBridge | 161:aa5281ff4a02 | 1040 | #define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U |
AnnaBridge | 161:aa5281ff4a02 | 1041 | |
AnnaBridge | 161:aa5281ff4a02 | 1042 | #define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU |
AnnaBridge | 161:aa5281ff4a02 | 1043 | #define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU |
AnnaBridge | 161:aa5281ff4a02 | 1044 | #define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU |
AnnaBridge | 161:aa5281ff4a02 | 1045 | #define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU |
AnnaBridge | 161:aa5281ff4a02 | 1046 | #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU |
AnnaBridge | 161:aa5281ff4a02 | 1047 | #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU |
AnnaBridge | 161:aa5281ff4a02 | 1048 | |
AnnaBridge | 161:aa5281ff4a02 | 1049 | #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U |
AnnaBridge | 161:aa5281ff4a02 | 1050 | #define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U |
AnnaBridge | 161:aa5281ff4a02 | 1051 | #define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U |
AnnaBridge | 161:aa5281ff4a02 | 1052 | #define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U |
AnnaBridge | 161:aa5281ff4a02 | 1053 | #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U |
AnnaBridge | 161:aa5281ff4a02 | 1054 | #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U |
AnnaBridge | 161:aa5281ff4a02 | 1055 | |
AnnaBridge | 161:aa5281ff4a02 | 1056 | #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) |
AnnaBridge | 161:aa5281ff4a02 | 1057 | #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) |
AnnaBridge | 161:aa5281ff4a02 | 1058 | |
AnnaBridge | 161:aa5281ff4a02 | 1059 | typedef enum _iomuxc_gpr_mode |
AnnaBridge | 161:aa5281ff4a02 | 1060 | { |
AnnaBridge | 161:aa5281ff4a02 | 1061 | kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1062 | kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1063 | kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1064 | kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1065 | kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1066 | kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1067 | kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1068 | kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1069 | kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1070 | kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, |
AnnaBridge | 161:aa5281ff4a02 | 1071 | } iomuxc_gpr_mode_t; |
AnnaBridge | 161:aa5281ff4a02 | 1072 | |
AnnaBridge | 161:aa5281ff4a02 | 1073 | typedef enum _iomuxc_gpr_saimclk |
AnnaBridge | 161:aa5281ff4a02 | 1074 | { |
AnnaBridge | 161:aa5281ff4a02 | 1075 | kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, |
AnnaBridge | 161:aa5281ff4a02 | 1076 | kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, |
AnnaBridge | 161:aa5281ff4a02 | 1077 | kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, |
AnnaBridge | 161:aa5281ff4a02 | 1078 | kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, |
AnnaBridge | 161:aa5281ff4a02 | 1079 | kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, |
AnnaBridge | 161:aa5281ff4a02 | 1080 | } iomuxc_gpr_saimclk_t; |
AnnaBridge | 161:aa5281ff4a02 | 1081 | |
AnnaBridge | 161:aa5281ff4a02 | 1082 | typedef enum _iomuxc_mqs_pwm_oversample_rate |
AnnaBridge | 161:aa5281ff4a02 | 1083 | { |
AnnaBridge | 161:aa5281ff4a02 | 1084 | kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ |
AnnaBridge | 161:aa5281ff4a02 | 1085 | kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ |
AnnaBridge | 161:aa5281ff4a02 | 1086 | } iomuxc_mqs_pwm_oversample_rate_t; |
AnnaBridge | 161:aa5281ff4a02 | 1087 | |
AnnaBridge | 161:aa5281ff4a02 | 1088 | /*@}*/ |
AnnaBridge | 161:aa5281ff4a02 | 1089 | |
AnnaBridge | 161:aa5281ff4a02 | 1090 | #if defined(__cplusplus) |
AnnaBridge | 161:aa5281ff4a02 | 1091 | extern "C" { |
AnnaBridge | 161:aa5281ff4a02 | 1092 | #endif /*_cplusplus */ |
AnnaBridge | 161:aa5281ff4a02 | 1093 | |
AnnaBridge | 161:aa5281ff4a02 | 1094 | /*! @name Configuration */ |
AnnaBridge | 161:aa5281ff4a02 | 1095 | /*@{*/ |
AnnaBridge | 161:aa5281ff4a02 | 1096 | |
AnnaBridge | 161:aa5281ff4a02 | 1097 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1098 | * @brief Sets the IOMUXC pin mux mode. |
AnnaBridge | 161:aa5281ff4a02 | 1099 | * @note The first five parameters can be filled with the pin function ID macros. |
AnnaBridge | 161:aa5281ff4a02 | 1100 | * |
AnnaBridge | 161:aa5281ff4a02 | 1101 | * This is an example to set the PTA6 as the lpuart0_tx: |
AnnaBridge | 161:aa5281ff4a02 | 1102 | * @code |
AnnaBridge | 161:aa5281ff4a02 | 1103 | * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); |
AnnaBridge | 161:aa5281ff4a02 | 1104 | * @endcode |
AnnaBridge | 161:aa5281ff4a02 | 1105 | * |
AnnaBridge | 161:aa5281ff4a02 | 1106 | * This is an example to set the PTA0 as GPIOA0: |
AnnaBridge | 161:aa5281ff4a02 | 1107 | * @code |
AnnaBridge | 161:aa5281ff4a02 | 1108 | * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); |
AnnaBridge | 161:aa5281ff4a02 | 1109 | * @endcode |
AnnaBridge | 161:aa5281ff4a02 | 1110 | * |
AnnaBridge | 161:aa5281ff4a02 | 1111 | * @param muxRegister The pin mux register. |
AnnaBridge | 161:aa5281ff4a02 | 1112 | * @param muxMode The pin mux mode. |
AnnaBridge | 161:aa5281ff4a02 | 1113 | * @param inputRegister The select input register. |
AnnaBridge | 161:aa5281ff4a02 | 1114 | * @param inputDaisy The input daisy. |
AnnaBridge | 161:aa5281ff4a02 | 1115 | * @param configRegister The config register. |
AnnaBridge | 161:aa5281ff4a02 | 1116 | * @param inputOnfield Software input on field. |
AnnaBridge | 161:aa5281ff4a02 | 1117 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1118 | static inline void IOMUXC_SetPinMux(uint32_t muxRegister, |
AnnaBridge | 161:aa5281ff4a02 | 1119 | uint32_t muxMode, |
AnnaBridge | 161:aa5281ff4a02 | 1120 | uint32_t inputRegister, |
AnnaBridge | 161:aa5281ff4a02 | 1121 | uint32_t inputDaisy, |
AnnaBridge | 161:aa5281ff4a02 | 1122 | uint32_t configRegister, |
AnnaBridge | 161:aa5281ff4a02 | 1123 | uint32_t inputOnfield) |
AnnaBridge | 161:aa5281ff4a02 | 1124 | { |
AnnaBridge | 161:aa5281ff4a02 | 1125 | *((volatile uint32_t *)muxRegister) = |
AnnaBridge | 161:aa5281ff4a02 | 1126 | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); |
AnnaBridge | 161:aa5281ff4a02 | 1127 | |
AnnaBridge | 161:aa5281ff4a02 | 1128 | if (inputRegister) |
AnnaBridge | 161:aa5281ff4a02 | 1129 | { |
AnnaBridge | 161:aa5281ff4a02 | 1130 | *((volatile uint32_t *)inputRegister) = inputDaisy; |
AnnaBridge | 161:aa5281ff4a02 | 1131 | } |
AnnaBridge | 161:aa5281ff4a02 | 1132 | } |
AnnaBridge | 161:aa5281ff4a02 | 1133 | |
AnnaBridge | 161:aa5281ff4a02 | 1134 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1135 | * @brief Sets the IOMUXC pin configuration. |
AnnaBridge | 161:aa5281ff4a02 | 1136 | * @note The previous five parameters can be filled with the pin function ID macros. |
AnnaBridge | 161:aa5281ff4a02 | 1137 | * |
AnnaBridge | 161:aa5281ff4a02 | 1138 | * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: |
AnnaBridge | 161:aa5281ff4a02 | 1139 | * @code |
AnnaBridge | 161:aa5281ff4a02 | 1140 | * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) |
AnnaBridge | 161:aa5281ff4a02 | 1141 | * @endcode |
AnnaBridge | 161:aa5281ff4a02 | 1142 | * |
AnnaBridge | 161:aa5281ff4a02 | 1143 | * @param muxRegister The pin mux register. |
AnnaBridge | 161:aa5281ff4a02 | 1144 | * @param muxMode The pin mux mode. |
AnnaBridge | 161:aa5281ff4a02 | 1145 | * @param inputRegister The select input register. |
AnnaBridge | 161:aa5281ff4a02 | 1146 | * @param inputDaisy The input daisy. |
AnnaBridge | 161:aa5281ff4a02 | 1147 | * @param configRegister The config register. |
AnnaBridge | 161:aa5281ff4a02 | 1148 | * @param configValue The pin config value. |
AnnaBridge | 161:aa5281ff4a02 | 1149 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1150 | static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, |
AnnaBridge | 161:aa5281ff4a02 | 1151 | uint32_t muxMode, |
AnnaBridge | 161:aa5281ff4a02 | 1152 | uint32_t inputRegister, |
AnnaBridge | 161:aa5281ff4a02 | 1153 | uint32_t inputDaisy, |
AnnaBridge | 161:aa5281ff4a02 | 1154 | uint32_t configRegister, |
AnnaBridge | 161:aa5281ff4a02 | 1155 | uint32_t configValue) |
AnnaBridge | 161:aa5281ff4a02 | 1156 | { |
AnnaBridge | 161:aa5281ff4a02 | 1157 | if (configRegister) |
AnnaBridge | 161:aa5281ff4a02 | 1158 | { |
AnnaBridge | 161:aa5281ff4a02 | 1159 | *((volatile uint32_t *)configRegister) = configValue; |
AnnaBridge | 161:aa5281ff4a02 | 1160 | } |
AnnaBridge | 161:aa5281ff4a02 | 1161 | } |
AnnaBridge | 161:aa5281ff4a02 | 1162 | |
AnnaBridge | 161:aa5281ff4a02 | 1163 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1164 | * @brief Sets IOMUXC general configuration for some mode. |
AnnaBridge | 161:aa5281ff4a02 | 1165 | * |
AnnaBridge | 161:aa5281ff4a02 | 1166 | * @param base The IOMUXC GPR base address. |
AnnaBridge | 161:aa5281ff4a02 | 1167 | * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" |
AnnaBridge | 161:aa5281ff4a02 | 1168 | * @param enable True enable false disable. |
AnnaBridge | 161:aa5281ff4a02 | 1169 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1170 | static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) |
AnnaBridge | 161:aa5281ff4a02 | 1171 | { |
AnnaBridge | 170:e95d10626187 | 1172 | mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK |
AnnaBridge | 170:e95d10626187 | 1173 | | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
AnnaBridge | 170:e95d10626187 | 1174 | | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK |
AnnaBridge | 170:e95d10626187 | 1175 | | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
AnnaBridge | 170:e95d10626187 | 1176 | | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); |
AnnaBridge | 161:aa5281ff4a02 | 1177 | |
AnnaBridge | 161:aa5281ff4a02 | 1178 | if (enable) |
AnnaBridge | 161:aa5281ff4a02 | 1179 | { |
AnnaBridge | 170:e95d10626187 | 1180 | base->GPR1 |= mode; |
AnnaBridge | 161:aa5281ff4a02 | 1181 | } |
AnnaBridge | 161:aa5281ff4a02 | 1182 | else |
AnnaBridge | 161:aa5281ff4a02 | 1183 | { |
AnnaBridge | 161:aa5281ff4a02 | 1184 | base->GPR1 &= ~mode; |
AnnaBridge | 161:aa5281ff4a02 | 1185 | } |
AnnaBridge | 161:aa5281ff4a02 | 1186 | } |
AnnaBridge | 161:aa5281ff4a02 | 1187 | |
AnnaBridge | 161:aa5281ff4a02 | 1188 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1189 | * @brief Sets IOMUXC general configuration for SAI MCLK selection. |
AnnaBridge | 161:aa5281ff4a02 | 1190 | * |
AnnaBridge | 161:aa5281ff4a02 | 1191 | * @param base The IOMUXC GPR base address. |
AnnaBridge | 161:aa5281ff4a02 | 1192 | * @param mclk The SAI MCLK. |
AnnaBridge | 161:aa5281ff4a02 | 1193 | * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. |
AnnaBridge | 161:aa5281ff4a02 | 1194 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1195 | static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) |
AnnaBridge | 161:aa5281ff4a02 | 1196 | { |
AnnaBridge | 161:aa5281ff4a02 | 1197 | uint32_t gpr; |
AnnaBridge | 161:aa5281ff4a02 | 1198 | |
AnnaBridge | 161:aa5281ff4a02 | 1199 | if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) |
AnnaBridge | 161:aa5281ff4a02 | 1200 | { |
AnnaBridge | 161:aa5281ff4a02 | 1201 | gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); |
AnnaBridge | 161:aa5281ff4a02 | 1202 | base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; |
AnnaBridge | 161:aa5281ff4a02 | 1203 | } |
AnnaBridge | 161:aa5281ff4a02 | 1204 | else |
AnnaBridge | 161:aa5281ff4a02 | 1205 | { |
AnnaBridge | 161:aa5281ff4a02 | 1206 | gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); |
AnnaBridge | 161:aa5281ff4a02 | 1207 | base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; |
AnnaBridge | 161:aa5281ff4a02 | 1208 | } |
AnnaBridge | 161:aa5281ff4a02 | 1209 | } |
AnnaBridge | 161:aa5281ff4a02 | 1210 | |
AnnaBridge | 161:aa5281ff4a02 | 1211 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1212 | * @brief Enters or exit MQS software reset. |
AnnaBridge | 161:aa5281ff4a02 | 1213 | * |
AnnaBridge | 161:aa5281ff4a02 | 1214 | * @param base The IOMUXC GPR base address. |
AnnaBridge | 161:aa5281ff4a02 | 1215 | * @param enable Enter or exit MQS software reset. |
AnnaBridge | 161:aa5281ff4a02 | 1216 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1217 | static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) |
AnnaBridge | 161:aa5281ff4a02 | 1218 | { |
AnnaBridge | 161:aa5281ff4a02 | 1219 | if (enable) |
AnnaBridge | 161:aa5281ff4a02 | 1220 | { |
AnnaBridge | 161:aa5281ff4a02 | 1221 | base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; |
AnnaBridge | 161:aa5281ff4a02 | 1222 | } |
AnnaBridge | 161:aa5281ff4a02 | 1223 | else |
AnnaBridge | 161:aa5281ff4a02 | 1224 | { |
AnnaBridge | 161:aa5281ff4a02 | 1225 | base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; |
AnnaBridge | 161:aa5281ff4a02 | 1226 | } |
AnnaBridge | 161:aa5281ff4a02 | 1227 | } |
AnnaBridge | 161:aa5281ff4a02 | 1228 | |
AnnaBridge | 161:aa5281ff4a02 | 1229 | |
AnnaBridge | 161:aa5281ff4a02 | 1230 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1231 | * @brief Enables or disables MQS. |
AnnaBridge | 161:aa5281ff4a02 | 1232 | * |
AnnaBridge | 161:aa5281ff4a02 | 1233 | * @param base The IOMUXC GPR base address. |
AnnaBridge | 161:aa5281ff4a02 | 1234 | * @param enable Enable or disable the MQS. |
AnnaBridge | 161:aa5281ff4a02 | 1235 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1236 | static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) |
AnnaBridge | 161:aa5281ff4a02 | 1237 | { |
AnnaBridge | 161:aa5281ff4a02 | 1238 | if (enable) |
AnnaBridge | 161:aa5281ff4a02 | 1239 | { |
AnnaBridge | 161:aa5281ff4a02 | 1240 | base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; |
AnnaBridge | 161:aa5281ff4a02 | 1241 | } |
AnnaBridge | 161:aa5281ff4a02 | 1242 | else |
AnnaBridge | 161:aa5281ff4a02 | 1243 | { |
AnnaBridge | 161:aa5281ff4a02 | 1244 | base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; |
AnnaBridge | 161:aa5281ff4a02 | 1245 | } |
AnnaBridge | 161:aa5281ff4a02 | 1246 | } |
AnnaBridge | 161:aa5281ff4a02 | 1247 | |
AnnaBridge | 161:aa5281ff4a02 | 1248 | /*! |
AnnaBridge | 161:aa5281ff4a02 | 1249 | * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. |
AnnaBridge | 161:aa5281ff4a02 | 1250 | * |
AnnaBridge | 161:aa5281ff4a02 | 1251 | * @param base The IOMUXC GPR base address. |
AnnaBridge | 161:aa5281ff4a02 | 1252 | * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". |
AnnaBridge | 161:aa5281ff4a02 | 1253 | * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. |
AnnaBridge | 161:aa5281ff4a02 | 1254 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1255 | |
AnnaBridge | 161:aa5281ff4a02 | 1256 | static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) |
AnnaBridge | 161:aa5281ff4a02 | 1257 | { |
AnnaBridge | 161:aa5281ff4a02 | 1258 | uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); |
AnnaBridge | 161:aa5281ff4a02 | 1259 | |
AnnaBridge | 161:aa5281ff4a02 | 1260 | base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); |
AnnaBridge | 161:aa5281ff4a02 | 1261 | } |
AnnaBridge | 161:aa5281ff4a02 | 1262 | |
AnnaBridge | 161:aa5281ff4a02 | 1263 | /*@}*/ |
AnnaBridge | 161:aa5281ff4a02 | 1264 | |
AnnaBridge | 161:aa5281ff4a02 | 1265 | #if defined(__cplusplus) |
AnnaBridge | 161:aa5281ff4a02 | 1266 | } |
AnnaBridge | 161:aa5281ff4a02 | 1267 | #endif /*_cplusplus */ |
AnnaBridge | 161:aa5281ff4a02 | 1268 | |
AnnaBridge | 161:aa5281ff4a02 | 1269 | /*! @}*/ |
AnnaBridge | 161:aa5281ff4a02 | 1270 | |
AnnaBridge | 161:aa5281ff4a02 | 1271 | #endif /* _FSL_IOMUXC_H_ */ |
AnnaBridge | 161:aa5281ff4a02 | 1272 |