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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/*
AnnaBridge	161:aa5281ff4a02	2	* Copyright 2017 NXP
AnnaBridge	170:e95d10626187	3	* All rights reserved.
AnnaBridge	161:aa5281ff4a02	4	*
AnnaBridge	172:65be27845400	5	* SPDX-License-Identifier: BSD-3-Clause
AnnaBridge	161:aa5281ff4a02	6	*/
AnnaBridge	161:aa5281ff4a02	7
AnnaBridge	161:aa5281ff4a02	8	#ifndef _FSL_CLOCK_H_
AnnaBridge	161:aa5281ff4a02	9	#define _FSL_CLOCK_H_
AnnaBridge	161:aa5281ff4a02	10
AnnaBridge	170:e95d10626187	11	#include "fsl_common.h"
AnnaBridge	161:aa5281ff4a02	12
AnnaBridge	170:e95d10626187	13	/! @addtogroup clock /
AnnaBridge	170:e95d10626187	14	/! @{ /
AnnaBridge	170:e95d10626187	15
AnnaBridge	170:e95d10626187	16	/! @file /
AnnaBridge	161:aa5281ff4a02	17
AnnaBridge	161:aa5281ff4a02	18	/*******************************************************************************
AnnaBridge	170:e95d10626187	19	* Configurations
AnnaBridge	161:aa5281ff4a02	20	******************************************************************************/
AnnaBridge	161:aa5281ff4a02	21
AnnaBridge	161:aa5281ff4a02	22	/*! @brief Configure whether driver controls clock
AnnaBridge	161:aa5281ff4a02	23	*
AnnaBridge	161:aa5281ff4a02	24	* When set to 0, peripheral drivers will enable clock in initialize function
AnnaBridge	161:aa5281ff4a02	25	* and disable clock in de-initialize function. When set to 1, peripheral
AnnaBridge	172:65be27845400	26	* driver will not control the clock, application could control the clock out of
AnnaBridge	161:aa5281ff4a02	27	* the driver.
AnnaBridge	161:aa5281ff4a02	28	*
AnnaBridge	161:aa5281ff4a02	29	* @note All drivers share this feature switcher. If it is set to 1, application
AnnaBridge	161:aa5281ff4a02	30	* should handle clock enable and disable for all drivers.
AnnaBridge	161:aa5281ff4a02	31	*/
AnnaBridge	161:aa5281ff4a02	32	#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
AnnaBridge	161:aa5281ff4a02	33	#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
AnnaBridge	161:aa5281ff4a02	34	#endif
AnnaBridge	161:aa5281ff4a02	35
AnnaBridge	170:e95d10626187	36	/*******************************************************************************
AnnaBridge	170:e95d10626187	37	* Definitions
AnnaBridge	170:e95d10626187	38	******************************************************************************/
AnnaBridge	170:e95d10626187	39
AnnaBridge	161:aa5281ff4a02	40	/! @name Driver version /
AnnaBridge	161:aa5281ff4a02	41	/@{/
AnnaBridge	172:65be27845400	42	/! @brief CLOCK driver version 2.1.5. /
AnnaBridge	172:65be27845400	43	#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
AnnaBridge	170:e95d10626187	44
AnnaBridge	170:e95d10626187	45	/* analog pll definition */
AnnaBridge	170:e95d10626187	46	#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
AnnaBridge	170:e95d10626187	47	#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
AnnaBridge	170:e95d10626187	48	#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
AnnaBridge	170:e95d10626187	49
AnnaBridge	172:65be27845400	50
AnnaBridge	161:aa5281ff4a02	51	/@}/
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	/*!
AnnaBridge	172:65be27845400	54	* @brief CCM registers offset.
AnnaBridge	172:65be27845400	55	*/
AnnaBridge	172:65be27845400	56	#define CCSR_OFFSET 0x0C
AnnaBridge	172:65be27845400	57	#define CBCDR_OFFSET 0x14
AnnaBridge	172:65be27845400	58	#define CBCMR_OFFSET 0x18
AnnaBridge	172:65be27845400	59	#define CSCMR1_OFFSET 0x1C
AnnaBridge	172:65be27845400	60	#define CSCMR2_OFFSET 0x20
AnnaBridge	172:65be27845400	61	#define CSCDR1_OFFSET 0x24
AnnaBridge	172:65be27845400	62	#define CDCDR_OFFSET 0x30
AnnaBridge	172:65be27845400	63	#define CSCDR2_OFFSET 0x38
AnnaBridge	172:65be27845400	64	#define CSCDR3_OFFSET 0x3C
AnnaBridge	172:65be27845400	65	#define CACRR_OFFSET 0x10
AnnaBridge	172:65be27845400	66	#define CS1CDR_OFFSET 0x28
AnnaBridge	172:65be27845400	67	#define CS2CDR_OFFSET 0x2C
AnnaBridge	172:65be27845400	68
AnnaBridge	172:65be27845400	69	/*!
AnnaBridge	172:65be27845400	70	* @brief CCM Analog registers offset.
AnnaBridge	172:65be27845400	71	*/
AnnaBridge	172:65be27845400	72	#define PLL_ARM_OFFSET 0x00
AnnaBridge	172:65be27845400	73	#define PLL_SYS_OFFSET 0x30
AnnaBridge	172:65be27845400	74	#define PLL_USB1_OFFSET 0x10
AnnaBridge	172:65be27845400	75	#define PLL_AUDIO_OFFSET 0x70
AnnaBridge	172:65be27845400	76	#define PLL_VIDEO_OFFSET 0xA0
AnnaBridge	172:65be27845400	77	#define PLL_ENET_OFFSET 0xE0
AnnaBridge	172:65be27845400	78	#define PLL_USB2_OFFSET 0x20
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	#define CCM_TUPLE(reg, shift, mask, busyShift) \
AnnaBridge	172:65be27845400	81	(int)((reg & 0xFFU) \| ((shift) << 8U) \| \
AnnaBridge	172:65be27845400	82	((((mask) >> (shift)) & 0x1FFFU) << 13U) \| ((busyShift) << 26U))
AnnaBridge	170:e95d10626187	83	#define CCM_TUPLE_REG(base, tuple) (((volatile uint32_t )(((uint32_t)(base)) + ((tuple)&0xFFU))))
AnnaBridge	170:e95d10626187	84	#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
AnnaBridge	170:e95d10626187	85	#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
AnnaBridge	170:e95d10626187	86	#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)
AnnaBridge	161:aa5281ff4a02	87
AnnaBridge	170:e95d10626187	88	#define CCM_NO_BUSY_WAIT (0x20U)
AnnaBridge	170:e95d10626187	89
AnnaBridge	170:e95d10626187	90	/*!
AnnaBridge	170:e95d10626187	91	* @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
AnnaBridge	170:e95d10626187	92	*/
AnnaBridge	172:65be27845400	93	#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) \| (shift))
AnnaBridge	170:e95d10626187	94	#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
AnnaBridge	170:e95d10626187	95	#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
AnnaBridge	170:e95d10626187	96	(((volatile uint32_t )((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
AnnaBridge	170:e95d10626187	97	#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
AnnaBridge	170:e95d10626187	98
AnnaBridge	170:e95d10626187	99	/*!
AnnaBridge	170:e95d10626187	100	* @brief clock1PN frequency.
AnnaBridge	170:e95d10626187	101	*/
AnnaBridge	170:e95d10626187	102	#define CLKPN_FREQ 0U
AnnaBridge	172:65be27845400	103
AnnaBridge	161:aa5281ff4a02	104	/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
AnnaBridge	161:aa5281ff4a02	105	*
AnnaBridge	161:aa5281ff4a02	106	* The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
AnnaBridge	161:aa5281ff4a02	107	* function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
AnnaBridge	161:aa5281ff4a02	108	* if XTAL is 24MHz,
AnnaBridge	161:aa5281ff4a02	109	* @code
AnnaBridge	161:aa5281ff4a02	110	* CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC
AnnaBridge	161:aa5281ff4a02	111	* CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver.
AnnaBridge	161:aa5281ff4a02	112	* @endcode
AnnaBridge	161:aa5281ff4a02	113	*/
AnnaBridge	172:65be27845400	114	extern volatile uint32_t g_xtalFreq;
AnnaBridge	161:aa5281ff4a02	115
AnnaBridge	161:aa5281ff4a02	116	/*! @brief External RTC XTAL (32K OSC) clock frequency.
AnnaBridge	161:aa5281ff4a02	117	*
AnnaBridge	161:aa5281ff4a02	118	* The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
AnnaBridge	161:aa5281ff4a02	119	* function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
AnnaBridge	161:aa5281ff4a02	120	*/
AnnaBridge	172:65be27845400	121	extern volatile uint32_t g_rtcXtalFreq;
AnnaBridge	161:aa5281ff4a02	122
AnnaBridge	161:aa5281ff4a02	123	/* For compatible with other platforms */
AnnaBridge	161:aa5281ff4a02	124	#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
AnnaBridge	161:aa5281ff4a02	125	#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
AnnaBridge	161:aa5281ff4a02	126
AnnaBridge	170:e95d10626187	127	/! @brief Clock ip name array for ADC. /
AnnaBridge	170:e95d10626187	128	#define ADC_CLOCKS \
AnnaBridge	170:e95d10626187	129	{ \
AnnaBridge	170:e95d10626187	130	kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
AnnaBridge	161:aa5281ff4a02	131	}
AnnaBridge	161:aa5281ff4a02	132
AnnaBridge	161:aa5281ff4a02	133	/! @brief Clock ip name array for AOI. /
AnnaBridge	170:e95d10626187	134	#define AOI_CLOCKS \
AnnaBridge	170:e95d10626187	135	{ \
AnnaBridge	170:e95d10626187	136	kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
AnnaBridge	161:aa5281ff4a02	137	}
AnnaBridge	161:aa5281ff4a02	138
AnnaBridge	161:aa5281ff4a02	139	/! @brief Clock ip name array for BEE. /
AnnaBridge	170:e95d10626187	140	#define BEE_CLOCKS \
AnnaBridge	170:e95d10626187	141	{ \
AnnaBridge	170:e95d10626187	142	kCLOCK_Bee \
AnnaBridge	170:e95d10626187	143	}
AnnaBridge	161:aa5281ff4a02	144
AnnaBridge	161:aa5281ff4a02	145	/! @brief Clock ip name array for CMP. /
AnnaBridge	170:e95d10626187	146	#define CMP_CLOCKS \
AnnaBridge	170:e95d10626187	147	{ \
AnnaBridge	170:e95d10626187	148	kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
AnnaBridge	161:aa5281ff4a02	149	}
AnnaBridge	161:aa5281ff4a02	150
AnnaBridge	161:aa5281ff4a02	151	/! @brief Clock ip name array for CSI. /
AnnaBridge	170:e95d10626187	152	#define CSI_CLOCKS \
AnnaBridge	170:e95d10626187	153	{ \
AnnaBridge	170:e95d10626187	154	kCLOCK_Csi \
AnnaBridge	161:aa5281ff4a02	155	}
AnnaBridge	161:aa5281ff4a02	156
AnnaBridge	161:aa5281ff4a02	157	/! @brief Clock ip name array for DCDC. /
AnnaBridge	170:e95d10626187	158	#define DCDC_CLOCKS \
AnnaBridge	170:e95d10626187	159	{ \
AnnaBridge	170:e95d10626187	160	kCLOCK_Dcdc \
AnnaBridge	161:aa5281ff4a02	161	}
AnnaBridge	161:aa5281ff4a02	162
AnnaBridge	161:aa5281ff4a02	163	/! @brief Clock ip name array for DCP. /
AnnaBridge	170:e95d10626187	164	#define DCP_CLOCKS \
AnnaBridge	170:e95d10626187	165	{ \
AnnaBridge	170:e95d10626187	166	kCLOCK_Dcp \
AnnaBridge	161:aa5281ff4a02	167	}
AnnaBridge	161:aa5281ff4a02	168
AnnaBridge	161:aa5281ff4a02	169	/! @brief Clock ip name array for DMAMUX_CLOCKS. /
AnnaBridge	170:e95d10626187	170	#define DMAMUX_CLOCKS \
AnnaBridge	170:e95d10626187	171	{ \
AnnaBridge	170:e95d10626187	172	kCLOCK_Dma \
AnnaBridge	170:e95d10626187	173	}
AnnaBridge	161:aa5281ff4a02	174
AnnaBridge	161:aa5281ff4a02	175	/! @brief Clock ip name array for DMA. /
AnnaBridge	170:e95d10626187	176	#define EDMA_CLOCKS \
AnnaBridge	170:e95d10626187	177	{ \
AnnaBridge	170:e95d10626187	178	kCLOCK_Dma \
AnnaBridge	170:e95d10626187	179	}
AnnaBridge	161:aa5281ff4a02	180
AnnaBridge	161:aa5281ff4a02	181	/! @brief Clock ip name array for ENC. /
AnnaBridge	170:e95d10626187	182	#define ENC_CLOCKS \
AnnaBridge	170:e95d10626187	183	{ \
AnnaBridge	170:e95d10626187	184	kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
AnnaBridge	161:aa5281ff4a02	185	}
AnnaBridge	161:aa5281ff4a02	186
AnnaBridge	161:aa5281ff4a02	187	/! @brief Clock ip name array for ENET. /
AnnaBridge	170:e95d10626187	188	#define ENET_CLOCKS \
AnnaBridge	170:e95d10626187	189	{ \
AnnaBridge	170:e95d10626187	190	kCLOCK_Enet \
AnnaBridge	161:aa5281ff4a02	191	}
AnnaBridge	161:aa5281ff4a02	192
AnnaBridge	161:aa5281ff4a02	193	/! @brief Clock ip name array for EWM. /
AnnaBridge	170:e95d10626187	194	#define EWM_CLOCKS \
AnnaBridge	170:e95d10626187	195	{ \
AnnaBridge	170:e95d10626187	196	kCLOCK_Ewm0 \
AnnaBridge	170:e95d10626187	197	}
AnnaBridge	161:aa5281ff4a02	198
AnnaBridge	161:aa5281ff4a02	199	/! @brief Clock ip name array for FLEXCAN. /
AnnaBridge	170:e95d10626187	200	#define FLEXCAN_CLOCKS \
AnnaBridge	170:e95d10626187	201	{ \
AnnaBridge	170:e95d10626187	202	kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
AnnaBridge	161:aa5281ff4a02	203	}
AnnaBridge	170:e95d10626187	204
AnnaBridge	161:aa5281ff4a02	205	/! @brief Clock ip name array for FLEXCAN Peripheral clock. /
AnnaBridge	170:e95d10626187	206	#define FLEXCAN_PERIPH_CLOCKS \
AnnaBridge	170:e95d10626187	207	{ \
AnnaBridge	170:e95d10626187	208	kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
AnnaBridge	170:e95d10626187	209	}
AnnaBridge	161:aa5281ff4a02	210
AnnaBridge	161:aa5281ff4a02	211	/! @brief Clock ip name array for FLEXIO. /
AnnaBridge	170:e95d10626187	212	#define FLEXIO_CLOCKS \
AnnaBridge	170:e95d10626187	213	{ \
AnnaBridge	170:e95d10626187	214	kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
AnnaBridge	161:aa5281ff4a02	215	}
AnnaBridge	161:aa5281ff4a02	216
AnnaBridge	161:aa5281ff4a02	217	/! @brief Clock ip name array for FLEXRAM. /
AnnaBridge	170:e95d10626187	218	#define FLEXRAM_CLOCKS \
AnnaBridge	170:e95d10626187	219	{ \
AnnaBridge	170:e95d10626187	220	kCLOCK_FlexRam \
AnnaBridge	170:e95d10626187	221	}
AnnaBridge	161:aa5281ff4a02	222
AnnaBridge	161:aa5281ff4a02	223	/! @brief Clock ip name array for FLEXSPI. /
AnnaBridge	170:e95d10626187	224	#define FLEXSPI_CLOCKS \
AnnaBridge	170:e95d10626187	225	{ \
AnnaBridge	170:e95d10626187	226	kCLOCK_FlexSpi \
AnnaBridge	170:e95d10626187	227	}
AnnaBridge	170:e95d10626187	228
AnnaBridge	170:e95d10626187	229	/! @brief Clock ip name array for FLEXSPI EXSC. /
AnnaBridge	170:e95d10626187	230	#define FLEXSPI_EXSC_CLOCKS \
AnnaBridge	170:e95d10626187	231	{ \
AnnaBridge	170:e95d10626187	232	kCLOCK_FlexSpiExsc \
AnnaBridge	170:e95d10626187	233	}
AnnaBridge	161:aa5281ff4a02	234
AnnaBridge	161:aa5281ff4a02	235	/! @brief Clock ip name array for GPIO. /
AnnaBridge	170:e95d10626187	236	#define GPIO_CLOCKS \
AnnaBridge	170:e95d10626187	237	{ \
AnnaBridge	170:e95d10626187	238	kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
AnnaBridge	161:aa5281ff4a02	239	}
AnnaBridge	161:aa5281ff4a02	240
AnnaBridge	161:aa5281ff4a02	241	/! @brief Clock ip name array for GPT. /
AnnaBridge	170:e95d10626187	242	#define GPT_CLOCKS \
AnnaBridge	170:e95d10626187	243	{ \
AnnaBridge	170:e95d10626187	244	kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
AnnaBridge	161:aa5281ff4a02	245	}
AnnaBridge	161:aa5281ff4a02	246
AnnaBridge	161:aa5281ff4a02	247	/! @brief Clock ip name array for KPP. /
AnnaBridge	170:e95d10626187	248	#define KPP_CLOCKS \
AnnaBridge	170:e95d10626187	249	{ \
AnnaBridge	170:e95d10626187	250	kCLOCK_Kpp \
AnnaBridge	170:e95d10626187	251	}
AnnaBridge	170:e95d10626187	252
AnnaBridge	161:aa5281ff4a02	253	/! @brief Clock ip name array for LCDIF. /
AnnaBridge	170:e95d10626187	254	#define LCDIF_CLOCKS \
AnnaBridge	170:e95d10626187	255	{ \
AnnaBridge	170:e95d10626187	256	kCLOCK_Lcd \
AnnaBridge	161:aa5281ff4a02	257	}
AnnaBridge	161:aa5281ff4a02	258
AnnaBridge	161:aa5281ff4a02	259	/! @brief Clock ip name array for LCDIF PIXEL. /
AnnaBridge	170:e95d10626187	260	#define LCDIF_PERIPH_CLOCKS \
AnnaBridge	170:e95d10626187	261	{ \
AnnaBridge	170:e95d10626187	262	kCLOCK_LcdPixel \
AnnaBridge	161:aa5281ff4a02	263	}
AnnaBridge	161:aa5281ff4a02	264
AnnaBridge	161:aa5281ff4a02	265	/! @brief Clock ip name array for LPI2C. /
AnnaBridge	170:e95d10626187	266	#define LPI2C_CLOCKS \
AnnaBridge	170:e95d10626187	267	{ \
AnnaBridge	170:e95d10626187	268	kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
AnnaBridge	170:e95d10626187	269	}
AnnaBridge	161:aa5281ff4a02	270
AnnaBridge	161:aa5281ff4a02	271	/! @brief Clock ip name array for LPSPI. /
AnnaBridge	170:e95d10626187	272	#define LPSPI_CLOCKS \
AnnaBridge	170:e95d10626187	273	{ \
AnnaBridge	170:e95d10626187	274	kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
AnnaBridge	170:e95d10626187	275	}
AnnaBridge	161:aa5281ff4a02	276
AnnaBridge	161:aa5281ff4a02	277	/! @brief Clock ip name array for LPUART. /
AnnaBridge	170:e95d10626187	278	#define LPUART_CLOCKS \
AnnaBridge	170:e95d10626187	279	{ \
AnnaBridge	170:e95d10626187	280	kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
AnnaBridge	170:e95d10626187	281	kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
AnnaBridge	170:e95d10626187	282	}
AnnaBridge	170:e95d10626187	283
AnnaBridge	170:e95d10626187	284	/! @brief Clock ip name array for MQS. /
AnnaBridge	170:e95d10626187	285	#define MQS_CLOCKS \
AnnaBridge	170:e95d10626187	286	{ \
AnnaBridge	170:e95d10626187	287	kCLOCK_Mqs \
AnnaBridge	170:e95d10626187	288	}
AnnaBridge	170:e95d10626187	289
AnnaBridge	170:e95d10626187	290	/! @brief Clock ip name array for OCRAM EXSC. /
AnnaBridge	170:e95d10626187	291	#define OCRAM_EXSC_CLOCKS \
AnnaBridge	170:e95d10626187	292	{ \
AnnaBridge	170:e95d10626187	293	kCLOCK_OcramExsc \
AnnaBridge	170:e95d10626187	294	}
AnnaBridge	161:aa5281ff4a02	295
AnnaBridge	161:aa5281ff4a02	296	/! @brief Clock ip name array for PIT. /
AnnaBridge	170:e95d10626187	297	#define PIT_CLOCKS \
AnnaBridge	170:e95d10626187	298	{ \
AnnaBridge	170:e95d10626187	299	kCLOCK_Pit \
AnnaBridge	161:aa5281ff4a02	300	}
AnnaBridge	161:aa5281ff4a02	301
AnnaBridge	161:aa5281ff4a02	302	/! @brief Clock ip name array for PWM. /
AnnaBridge	170:e95d10626187	303	#define PWM_CLOCKS \
AnnaBridge	170:e95d10626187	304	{ \
AnnaBridge	170:e95d10626187	305	{ \
AnnaBridge	170:e95d10626187	306	kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \
AnnaBridge	170:e95d10626187	307	} \
AnnaBridge	170:e95d10626187	308	, {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
AnnaBridge	170:e95d10626187	309	{kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
AnnaBridge	170:e95d10626187	310	{ \
AnnaBridge	170:e95d10626187	311	kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
AnnaBridge	170:e95d10626187	312	} \
AnnaBridge	170:e95d10626187	313	}
AnnaBridge	161:aa5281ff4a02	314
AnnaBridge	161:aa5281ff4a02	315	/! @brief Clock ip name array for PXP. /
AnnaBridge	170:e95d10626187	316	#define PXP_CLOCKS \
AnnaBridge	170:e95d10626187	317	{ \
AnnaBridge	170:e95d10626187	318	kCLOCK_Pxp \
AnnaBridge	161:aa5281ff4a02	319	}
AnnaBridge	161:aa5281ff4a02	320
AnnaBridge	161:aa5281ff4a02	321	/! @brief Clock ip name array for RTWDOG. /
AnnaBridge	170:e95d10626187	322	#define RTWDOG_CLOCKS \
AnnaBridge	170:e95d10626187	323	{ \
AnnaBridge	170:e95d10626187	324	kCLOCK_Wdog3 \
AnnaBridge	170:e95d10626187	325	}
AnnaBridge	161:aa5281ff4a02	326
AnnaBridge	161:aa5281ff4a02	327	/! @brief Clock ip name array for SAI. /
AnnaBridge	170:e95d10626187	328	#define SAI_CLOCKS \
AnnaBridge	170:e95d10626187	329	{ \
AnnaBridge	170:e95d10626187	330	kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
AnnaBridge	161:aa5281ff4a02	331	}
AnnaBridge	161:aa5281ff4a02	332
AnnaBridge	161:aa5281ff4a02	333	/! @brief Clock ip name array for SEMC. /
AnnaBridge	170:e95d10626187	334	#define SEMC_CLOCKS \
AnnaBridge	170:e95d10626187	335	{ \
AnnaBridge	170:e95d10626187	336	kCLOCK_Semc \
AnnaBridge	161:aa5281ff4a02	337	}
AnnaBridge	161:aa5281ff4a02	338
AnnaBridge	170:e95d10626187	339	/! @brief Clock ip name array for SEMC EXSC. /
AnnaBridge	170:e95d10626187	340	#define SEMC_EXSC_CLOCKS \
AnnaBridge	170:e95d10626187	341	{ \
AnnaBridge	170:e95d10626187	342	kCLOCK_SemcExsc \
AnnaBridge	170:e95d10626187	343	}
AnnaBridge	161:aa5281ff4a02	344
AnnaBridge	161:aa5281ff4a02	345	/! @brief Clock ip name array for QTIMER. /
AnnaBridge	170:e95d10626187	346	#define TMR_CLOCKS \
AnnaBridge	170:e95d10626187	347	{ \
AnnaBridge	170:e95d10626187	348	kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
AnnaBridge	161:aa5281ff4a02	349	}
AnnaBridge	161:aa5281ff4a02	350
AnnaBridge	161:aa5281ff4a02	351	/! @brief Clock ip name array for TRNG. /
AnnaBridge	170:e95d10626187	352	#define TRNG_CLOCKS \
AnnaBridge	170:e95d10626187	353	{ \
AnnaBridge	170:e95d10626187	354	kCLOCK_Trng \
AnnaBridge	161:aa5281ff4a02	355	}
AnnaBridge	161:aa5281ff4a02	356
AnnaBridge	161:aa5281ff4a02	357	/! @brief Clock ip name array for TSC. /
AnnaBridge	170:e95d10626187	358	#define TSC_CLOCKS \
AnnaBridge	170:e95d10626187	359	{ \
AnnaBridge	170:e95d10626187	360	kCLOCK_Tsc \
AnnaBridge	161:aa5281ff4a02	361	}
AnnaBridge	161:aa5281ff4a02	362
AnnaBridge	170:e95d10626187	363	/! @brief Clock ip name array for WDOG. /
AnnaBridge	170:e95d10626187	364	#define WDOG_CLOCKS \
AnnaBridge	170:e95d10626187	365	{ \
AnnaBridge	170:e95d10626187	366	kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
AnnaBridge	170:e95d10626187	367	}
AnnaBridge	161:aa5281ff4a02	368
AnnaBridge	161:aa5281ff4a02	369	/! @brief Clock ip name array for USDHC. /
AnnaBridge	170:e95d10626187	370	#define USDHC_CLOCKS \
AnnaBridge	170:e95d10626187	371	{ \
AnnaBridge	170:e95d10626187	372	kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
AnnaBridge	161:aa5281ff4a02	373	}
AnnaBridge	170:e95d10626187	374
AnnaBridge	161:aa5281ff4a02	375	/! @brief Clock ip name array for SPDIF. /
AnnaBridge	170:e95d10626187	376	#define SPDIF_CLOCKS \
AnnaBridge	170:e95d10626187	377	{ \
AnnaBridge	170:e95d10626187	378	kCLOCK_Spdif \
AnnaBridge	161:aa5281ff4a02	379	}
AnnaBridge	170:e95d10626187	380
AnnaBridge	161:aa5281ff4a02	381	/! @brief Clock ip name array for XBARA. /
AnnaBridge	170:e95d10626187	382	#define XBARA_CLOCKS \
AnnaBridge	170:e95d10626187	383	{ \
AnnaBridge	170:e95d10626187	384	kCLOCK_Xbar1 \
AnnaBridge	170:e95d10626187	385	}
AnnaBridge	161:aa5281ff4a02	386
AnnaBridge	161:aa5281ff4a02	387	/! @brief Clock ip name array for XBARB. /
AnnaBridge	170:e95d10626187	388	#define XBARB_CLOCKS \
AnnaBridge	170:e95d10626187	389	{ \
AnnaBridge	170:e95d10626187	390	kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
AnnaBridge	170:e95d10626187	391	}
AnnaBridge	161:aa5281ff4a02	392
AnnaBridge	161:aa5281ff4a02	393	/! @brief Clock name used to get clock frequency. /
AnnaBridge	161:aa5281ff4a02	394	typedef enum _clock_name
AnnaBridge	161:aa5281ff4a02	395	{
AnnaBridge	170:e95d10626187	396	kCLOCK_CpuClk = 0x0U, /!< CPU clock /
AnnaBridge	170:e95d10626187	397	kCLOCK_AhbClk = 0x1U, /!< AHB clock /
AnnaBridge	170:e95d10626187	398	kCLOCK_SemcClk = 0x2U, /!< SEMC clock /
AnnaBridge	170:e95d10626187	399	kCLOCK_IpgClk = 0x3U, /!< IPG clock /
AnnaBridge	172:65be27845400	400	kCLOCK_PerClk = 0x4U, /!< PER clock /
AnnaBridge	161:aa5281ff4a02	401
AnnaBridge	172:65be27845400	402	kCLOCK_OscClk = 0x5U, /!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. /
AnnaBridge	172:65be27845400	403	kCLOCK_RtcClk = 0x6U, /!< RTC clock. (RTCCLK) /
AnnaBridge	161:aa5281ff4a02	404
AnnaBridge	172:65be27845400	405	kCLOCK_ArmPllClk = 0x7U, /!< ARMPLLCLK. /
AnnaBridge	172:65be27845400	406
AnnaBridge	172:65be27845400	407	kCLOCK_Usb1PllClk = 0x8U, /!< USB1PLLCLK. /
AnnaBridge	172:65be27845400	408	kCLOCK_Usb1PllPfd0Clk = 0x9U, /!< USB1PLLPDF0CLK. /
AnnaBridge	172:65be27845400	409	kCLOCK_Usb1PllPfd1Clk = 0xAU, /!< USB1PLLPFD1CLK. /
AnnaBridge	172:65be27845400	410	kCLOCK_Usb1PllPfd2Clk = 0xBU, /!< USB1PLLPFD2CLK. /
AnnaBridge	172:65be27845400	411	kCLOCK_Usb1PllPfd3Clk = 0xCU, /!< USB1PLLPFD3CLK. /
AnnaBridge	161:aa5281ff4a02	412
AnnaBridge	172:65be27845400	413	kCLOCK_Usb2PllClk = 0xDU, /!< USB2PLLCLK. /
AnnaBridge	161:aa5281ff4a02	414
AnnaBridge	172:65be27845400	415	kCLOCK_SysPllClk = 0xEU, /!< SYSPLLCLK. /
AnnaBridge	172:65be27845400	416	kCLOCK_SysPllPfd0Clk = 0xFU, /!< SYSPLLPDF0CLK. /
AnnaBridge	172:65be27845400	417	kCLOCK_SysPllPfd1Clk = 0x10U, /!< SYSPLLPFD1CLK. /
AnnaBridge	172:65be27845400	418	kCLOCK_SysPllPfd2Clk = 0x11U, /!< SYSPLLPFD2CLK. /
AnnaBridge	172:65be27845400	419	kCLOCK_SysPllPfd3Clk = 0x12U, /!< SYSPLLPFD3CLK. /
AnnaBridge	161:aa5281ff4a02	420
AnnaBridge	172:65be27845400	421	kCLOCK_EnetPll0Clk = 0x13U, /!< Enet PLLCLK ref_enetpll0. /
AnnaBridge	172:65be27845400	422	kCLOCK_EnetPll1Clk = 0x14U, /!< Enet PLLCLK ref_enetpll1. /
AnnaBridge	161:aa5281ff4a02	423
AnnaBridge	172:65be27845400	424	kCLOCK_AudioPllClk = 0x15U, /!< Audio PLLCLK. /
AnnaBridge	172:65be27845400	425	kCLOCK_VideoPllClk = 0x16U, /!< Video PLLCLK. /
AnnaBridge	161:aa5281ff4a02	426	} clock_name_t;
AnnaBridge	161:aa5281ff4a02	427
AnnaBridge	161:aa5281ff4a02	428	#define kCLOCK_CoreSysClk kCLOCK_CpuClk /!< For compatible with other platforms without CCM. /
AnnaBridge	161:aa5281ff4a02	429	#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /!< For compatible with other platforms without CCM. /
AnnaBridge	161:aa5281ff4a02	430
AnnaBridge	161:aa5281ff4a02	431	/*!
AnnaBridge	161:aa5281ff4a02	432	* @brief CCM CCGR gate control for each module independently.
AnnaBridge	161:aa5281ff4a02	433	*/
AnnaBridge	161:aa5281ff4a02	434	typedef enum _clock_ip_name
AnnaBridge	161:aa5281ff4a02	435	{
AnnaBridge	161:aa5281ff4a02	436	kCLOCK_IpInvalid = -1,
AnnaBridge	161:aa5281ff4a02	437
AnnaBridge	161:aa5281ff4a02	438	/* CCM CCGR0 */
AnnaBridge	170:e95d10626187	439	kCLOCK_Aips_tz1 = (0U << 8U) \| CCM_CCGR0_CG0_SHIFT, /!< CCGR0, CG0 /
AnnaBridge	170:e95d10626187	440	kCLOCK_Aips_tz2 = (0U << 8U) \| CCM_CCGR0_CG1_SHIFT, /!< CCGR0, CG1 /
AnnaBridge	170:e95d10626187	441	kCLOCK_Mqs = (0U << 8U) \| CCM_CCGR0_CG2_SHIFT, /!< CCGR0, CG2 /
AnnaBridge	170:e95d10626187	442	kCLOCK_FlexSpiExsc = (0U << 8U) \| CCM_CCGR0_CG3_SHIFT, /!< CCGR0, CG3 /
AnnaBridge	170:e95d10626187	443	kCLOCK_Sim_M_Main = (0U << 8U) \| CCM_CCGR0_CG4_SHIFT, /!< CCGR0, CG4 /
AnnaBridge	170:e95d10626187	444	kCLOCK_Dcp = (0U << 8U) \| CCM_CCGR0_CG5_SHIFT, /!< CCGR0, CG5 /
AnnaBridge	170:e95d10626187	445	kCLOCK_Lpuart3 = (0U << 8U) \| CCM_CCGR0_CG6_SHIFT, /!< CCGR0, CG6 /
AnnaBridge	170:e95d10626187	446	kCLOCK_Can1 = (0U << 8U) \| CCM_CCGR0_CG7_SHIFT, /!< CCGR0, CG7 /
AnnaBridge	170:e95d10626187	447	kCLOCK_Can1S = (0U << 8U) \| CCM_CCGR0_CG8_SHIFT, /!< CCGR0, CG8 /
AnnaBridge	170:e95d10626187	448	kCLOCK_Can2 = (0U << 8U) \| CCM_CCGR0_CG9_SHIFT, /!< CCGR0, CG9 /
AnnaBridge	170:e95d10626187	449	kCLOCK_Can2S = (0U << 8U) \| CCM_CCGR0_CG10_SHIFT, /!< CCGR0, CG10 /
AnnaBridge	170:e95d10626187	450	kCLOCK_Trace = (0U << 8U) \| CCM_CCGR0_CG11_SHIFT, /!< CCGR0, CG11 /
AnnaBridge	170:e95d10626187	451	kCLOCK_Gpt2 = (0U << 8U) \| CCM_CCGR0_CG12_SHIFT, /!< CCGR0, CG12 /
AnnaBridge	170:e95d10626187	452	kCLOCK_Gpt2S = (0U << 8U) \| CCM_CCGR0_CG13_SHIFT, /!< CCGR0, CG13 /
AnnaBridge	170:e95d10626187	453	kCLOCK_Lpuart2 = (0U << 8U) \| CCM_CCGR0_CG14_SHIFT, /!< CCGR0, CG14 /
AnnaBridge	170:e95d10626187	454	kCLOCK_Gpio2 = (0U << 8U) \| CCM_CCGR0_CG15_SHIFT, /!< CCGR0, CG15 /
AnnaBridge	161:aa5281ff4a02	455
AnnaBridge	161:aa5281ff4a02	456	/* CCM CCGR1 */
AnnaBridge	170:e95d10626187	457	kCLOCK_Lpspi1 = (1U << 8U) \| CCM_CCGR1_CG0_SHIFT, /!< CCGR1, CG0 /
AnnaBridge	170:e95d10626187	458	kCLOCK_Lpspi2 = (1U << 8U) \| CCM_CCGR1_CG1_SHIFT, /!< CCGR1, CG1 /
AnnaBridge	170:e95d10626187	459	kCLOCK_Lpspi3 = (1U << 8U) \| CCM_CCGR1_CG2_SHIFT, /!< CCGR1, CG2 /
AnnaBridge	170:e95d10626187	460	kCLOCK_Lpspi4 = (1U << 8U) \| CCM_CCGR1_CG3_SHIFT, /!< CCGR1, CG3 /
AnnaBridge	170:e95d10626187	461	kCLOCK_Adc2 = (1U << 8U) \| CCM_CCGR1_CG4_SHIFT, /!< CCGR1, CG4 /
AnnaBridge	170:e95d10626187	462	kCLOCK_Enet = (1U << 8U) \| CCM_CCGR1_CG5_SHIFT, /!< CCGR1, CG5 /
AnnaBridge	170:e95d10626187	463	kCLOCK_Pit = (1U << 8U) \| CCM_CCGR1_CG6_SHIFT, /!< CCGR1, CG6 /
AnnaBridge	170:e95d10626187	464	kCLOCK_Aoi2 = (1U << 8U) \| CCM_CCGR1_CG7_SHIFT, /!< CCGR1, CG7 /
AnnaBridge	170:e95d10626187	465	kCLOCK_Adc1 = (1U << 8U) \| CCM_CCGR1_CG8_SHIFT, /!< CCGR1, CG8 /
AnnaBridge	170:e95d10626187	466	kCLOCK_SemcExsc = (1U << 8U) \| CCM_CCGR1_CG9_SHIFT, /!< CCGR1, CG9 /
AnnaBridge	170:e95d10626187	467	kCLOCK_Gpt1 = (1U << 8U) \| CCM_CCGR1_CG10_SHIFT, /!< CCGR1, CG10 /
AnnaBridge	170:e95d10626187	468	kCLOCK_Gpt1S = (1U << 8U) \| CCM_CCGR1_CG11_SHIFT, /!< CCGR1, CG11 /
AnnaBridge	170:e95d10626187	469	kCLOCK_Lpuart4 = (1U << 8U) \| CCM_CCGR1_CG12_SHIFT, /!< CCGR1, CG12 /
AnnaBridge	170:e95d10626187	470	kCLOCK_Gpio1 = (1U << 8U) \| CCM_CCGR1_CG13_SHIFT, /!< CCGR1, CG13 /
AnnaBridge	170:e95d10626187	471	kCLOCK_Csu = (1U << 8U) \| CCM_CCGR1_CG14_SHIFT, /!< CCGR1, CG14 /
AnnaBridge	170:e95d10626187	472	kCLOCK_Gpio5 = (1U << 8U) \| CCM_CCGR1_CG15_SHIFT, /!< CCGR1, CG15 /
AnnaBridge	161:aa5281ff4a02	473
AnnaBridge	161:aa5281ff4a02	474	/* CCM CCGR2 */
AnnaBridge	170:e95d10626187	475	kCLOCK_OcramExsc = (2U << 8U) \| CCM_CCGR2_CG0_SHIFT, /!< CCGR2, CG0 /
AnnaBridge	170:e95d10626187	476	kCLOCK_Csi = (2U << 8U) \| CCM_CCGR2_CG1_SHIFT, /!< CCGR2, CG1 /
AnnaBridge	170:e95d10626187	477	kCLOCK_IomuxcSnvs = (2U << 8U) \| CCM_CCGR2_CG2_SHIFT, /!< CCGR2, CG2 /
AnnaBridge	170:e95d10626187	478	kCLOCK_Lpi2c1 = (2U << 8U) \| CCM_CCGR2_CG3_SHIFT, /!< CCGR2, CG3 /
AnnaBridge	170:e95d10626187	479	kCLOCK_Lpi2c2 = (2U << 8U) \| CCM_CCGR2_CG4_SHIFT, /!< CCGR2, CG4 /
AnnaBridge	170:e95d10626187	480	kCLOCK_Lpi2c3 = (2U << 8U) \| CCM_CCGR2_CG5_SHIFT, /!< CCGR2, CG5 /
AnnaBridge	170:e95d10626187	481	kCLOCK_Ocotp = (2U << 8U) \| CCM_CCGR2_CG6_SHIFT, /!< CCGR2, CG6 /
AnnaBridge	170:e95d10626187	482	kCLOCK_Xbar3 = (2U << 8U) \| CCM_CCGR2_CG7_SHIFT, /!< CCGR2, CG7 /
AnnaBridge	170:e95d10626187	483	kCLOCK_Ipmux1 = (2U << 8U) \| CCM_CCGR2_CG8_SHIFT, /!< CCGR2, CG8 /
AnnaBridge	170:e95d10626187	484	kCLOCK_Ipmux2 = (2U << 8U) \| CCM_CCGR2_CG9_SHIFT, /!< CCGR2, CG9 /
AnnaBridge	170:e95d10626187	485	kCLOCK_Ipmux3 = (2U << 8U) \| CCM_CCGR2_CG10_SHIFT, /!< CCGR2, CG10 /
AnnaBridge	170:e95d10626187	486	kCLOCK_Xbar1 = (2U << 8U) \| CCM_CCGR2_CG11_SHIFT, /!< CCGR2, CG11 /
AnnaBridge	170:e95d10626187	487	kCLOCK_Xbar2 = (2U << 8U) \| CCM_CCGR2_CG12_SHIFT, /!< CCGR2, CG12 /
AnnaBridge	170:e95d10626187	488	kCLOCK_Gpio3 = (2U << 8U) \| CCM_CCGR2_CG13_SHIFT, /!< CCGR2, CG13 /
AnnaBridge	170:e95d10626187	489	kCLOCK_Lcd = (2U << 8U) \| CCM_CCGR2_CG14_SHIFT, /!< CCGR2, CG14 /
AnnaBridge	170:e95d10626187	490	kCLOCK_Pxp = (2U << 8U) \| CCM_CCGR2_CG15_SHIFT, /!< CCGR2, CG15 /
AnnaBridge	161:aa5281ff4a02	491
AnnaBridge	161:aa5281ff4a02	492	/* CCM CCGR3 */
AnnaBridge	170:e95d10626187	493	kCLOCK_Flexio2 = (3U << 8U) \| CCM_CCGR3_CG0_SHIFT, /!< CCGR3, CG0 /
AnnaBridge	170:e95d10626187	494	kCLOCK_Lpuart5 = (3U << 8U) \| CCM_CCGR3_CG1_SHIFT, /!< CCGR3, CG1 /
AnnaBridge	170:e95d10626187	495	kCLOCK_Semc = (3U << 8U) \| CCM_CCGR3_CG2_SHIFT, /!< CCGR3, CG2 /
AnnaBridge	170:e95d10626187	496	kCLOCK_Lpuart6 = (3U << 8U) \| CCM_CCGR3_CG3_SHIFT, /!< CCGR3, CG3 /
AnnaBridge	170:e95d10626187	497	kCLOCK_Aoi1 = (3U << 8U) \| CCM_CCGR3_CG4_SHIFT, /!< CCGR3, CG4 /
AnnaBridge	170:e95d10626187	498	kCLOCK_LcdPixel = (3U << 8U) \| CCM_CCGR3_CG5_SHIFT, /!< CCGR3, CG5 /
AnnaBridge	170:e95d10626187	499	kCLOCK_Gpio4 = (3U << 8U) \| CCM_CCGR3_CG6_SHIFT, /!< CCGR3, CG6 /
AnnaBridge	170:e95d10626187	500	kCLOCK_Ewm0 = (3U << 8U) \| CCM_CCGR3_CG7_SHIFT, /!< CCGR3, CG7 /
AnnaBridge	170:e95d10626187	501	kCLOCK_Wdog1 = (3U << 8U) \| CCM_CCGR3_CG8_SHIFT, /!< CCGR3, CG8 /
AnnaBridge	170:e95d10626187	502	kCLOCK_FlexRam = (3U << 8U) \| CCM_CCGR3_CG9_SHIFT, /!< CCGR3, CG9 /
AnnaBridge	170:e95d10626187	503	kCLOCK_Acmp1 = (3U << 8U) \| CCM_CCGR3_CG10_SHIFT, /!< CCGR3, CG10 /
AnnaBridge	170:e95d10626187	504	kCLOCK_Acmp2 = (3U << 8U) \| CCM_CCGR3_CG11_SHIFT, /!< CCGR3, CG11 /
AnnaBridge	170:e95d10626187	505	kCLOCK_Acmp3 = (3U << 8U) \| CCM_CCGR3_CG12_SHIFT, /!< CCGR3, CG12 /
AnnaBridge	170:e95d10626187	506	kCLOCK_Acmp4 = (3U << 8U) \| CCM_CCGR3_CG13_SHIFT, /!< CCGR3, CG13 /
AnnaBridge	170:e95d10626187	507	kCLOCK_Ocram = (3U << 8U) \| CCM_CCGR3_CG14_SHIFT, /!< CCGR3, CG14 /
AnnaBridge	170:e95d10626187	508	kCLOCK_IomuxcSnvsGpr = (3U << 8U) \| CCM_CCGR3_CG15_SHIFT, /!< CCGR3, CG15 /
AnnaBridge	161:aa5281ff4a02	509
AnnaBridge	161:aa5281ff4a02	510	/* CCM CCGR4 */
AnnaBridge	170:e95d10626187	511	kCLOCK_Iomuxc = (4U << 8U) \| CCM_CCGR4_CG1_SHIFT, /!< CCGR4, CG1 /
AnnaBridge	170:e95d10626187	512	kCLOCK_IomuxcGpr = (4U << 8U) \| CCM_CCGR4_CG2_SHIFT, /!< CCGR4, CG2 /
AnnaBridge	170:e95d10626187	513	kCLOCK_Bee = (4U << 8U) \| CCM_CCGR4_CG3_SHIFT, /!< CCGR4, CG3 /
AnnaBridge	170:e95d10626187	514	kCLOCK_SimM7 = (4U << 8U) \| CCM_CCGR4_CG4_SHIFT, /!< CCGR4, CG4 /
AnnaBridge	170:e95d10626187	515	kCLOCK_Tsc = (4U << 8U) \| CCM_CCGR4_CG5_SHIFT, /!< CCGR4, CG5 /
AnnaBridge	170:e95d10626187	516	kCLOCK_SimM = (4U << 8U) \| CCM_CCGR4_CG6_SHIFT, /!< CCGR4, CG6 /
AnnaBridge	170:e95d10626187	517	kCLOCK_SimEms = (4U << 8U) \| CCM_CCGR4_CG7_SHIFT, /!< CCGR4, CG7 /
AnnaBridge	170:e95d10626187	518	kCLOCK_Pwm1 = (4U << 8U) \| CCM_CCGR4_CG8_SHIFT, /!< CCGR4, CG8 /
AnnaBridge	170:e95d10626187	519	kCLOCK_Pwm2 = (4U << 8U) \| CCM_CCGR4_CG9_SHIFT, /!< CCGR4, CG9 /
AnnaBridge	170:e95d10626187	520	kCLOCK_Pwm3 = (4U << 8U) \| CCM_CCGR4_CG10_SHIFT, /!< CCGR4, CG10 /
AnnaBridge	170:e95d10626187	521	kCLOCK_Pwm4 = (4U << 8U) \| CCM_CCGR4_CG11_SHIFT, /!< CCGR4, CG11 /
AnnaBridge	170:e95d10626187	522	kCLOCK_Enc1 = (4U << 8U) \| CCM_CCGR4_CG12_SHIFT, /!< CCGR4, CG12 /
AnnaBridge	170:e95d10626187	523	kCLOCK_Enc2 = (4U << 8U) \| CCM_CCGR4_CG13_SHIFT, /!< CCGR4, CG13 /
AnnaBridge	170:e95d10626187	524	kCLOCK_Enc3 = (4U << 8U) \| CCM_CCGR4_CG14_SHIFT, /!< CCGR4, CG14 /
AnnaBridge	170:e95d10626187	525	kCLOCK_Enc4 = (4U << 8U) \| CCM_CCGR4_CG15_SHIFT, /!< CCGR4, CG15 /
AnnaBridge	161:aa5281ff4a02	526
AnnaBridge	161:aa5281ff4a02	527	/* CCM CCGR5 */
AnnaBridge	170:e95d10626187	528	kCLOCK_Rom = (5U << 8U) \| CCM_CCGR5_CG0_SHIFT, /!< CCGR5, CG0 /
AnnaBridge	170:e95d10626187	529	kCLOCK_Flexio1 = (5U << 8U) \| CCM_CCGR5_CG1_SHIFT, /!< CCGR5, CG1 /
AnnaBridge	170:e95d10626187	530	kCLOCK_Wdog3 = (5U << 8U) \| CCM_CCGR5_CG2_SHIFT, /!< CCGR5, CG2 /
AnnaBridge	170:e95d10626187	531	kCLOCK_Dma = (5U << 8U) \| CCM_CCGR5_CG3_SHIFT, /!< CCGR5, CG3 /
AnnaBridge	170:e95d10626187	532	kCLOCK_Kpp = (5U << 8U) \| CCM_CCGR5_CG4_SHIFT, /!< CCGR5, CG4 /
AnnaBridge	170:e95d10626187	533	kCLOCK_Wdog2 = (5U << 8U) \| CCM_CCGR5_CG5_SHIFT, /!< CCGR5, CG5 /
AnnaBridge	170:e95d10626187	534	kCLOCK_Aips_tz4 = (5U << 8U) \| CCM_CCGR5_CG6_SHIFT, /!< CCGR5, CG6 /
AnnaBridge	170:e95d10626187	535	kCLOCK_Spdif = (5U << 8U) \| CCM_CCGR5_CG7_SHIFT, /!< CCGR5, CG7 /
AnnaBridge	170:e95d10626187	536	kCLOCK_SimMain = (5U << 8U) \| CCM_CCGR5_CG8_SHIFT, /!< CCGR5, CG8 /
AnnaBridge	170:e95d10626187	537	kCLOCK_Sai1 = (5U << 8U) \| CCM_CCGR5_CG9_SHIFT, /!< CCGR5, CG9 /
AnnaBridge	170:e95d10626187	538	kCLOCK_Sai2 = (5U << 8U) \| CCM_CCGR5_CG10_SHIFT, /!< CCGR5, CG10 /
AnnaBridge	170:e95d10626187	539	kCLOCK_Sai3 = (5U << 8U) \| CCM_CCGR5_CG11_SHIFT, /!< CCGR5, CG11 /
AnnaBridge	170:e95d10626187	540	kCLOCK_Lpuart1 = (5U << 8U) \| CCM_CCGR5_CG12_SHIFT, /!< CCGR5, CG12 /
AnnaBridge	170:e95d10626187	541	kCLOCK_Lpuart7 = (5U << 8U) \| CCM_CCGR5_CG13_SHIFT, /!< CCGR5, CG13 /
AnnaBridge	170:e95d10626187	542	kCLOCK_SnvsHp = (5U << 8U) \| CCM_CCGR5_CG14_SHIFT, /!< CCGR5, CG14 /
AnnaBridge	170:e95d10626187	543	kCLOCK_SnvsLp = (5U << 8U) \| CCM_CCGR5_CG15_SHIFT, /!< CCGR5, CG15 /
AnnaBridge	161:aa5281ff4a02	544
AnnaBridge	161:aa5281ff4a02	545	/* CCM CCGR6 */
AnnaBridge	170:e95d10626187	546	kCLOCK_UsbOh3 = (6U << 8U) \| CCM_CCGR6_CG0_SHIFT, /!< CCGR6, CG0 /
AnnaBridge	170:e95d10626187	547	kCLOCK_Usdhc1 = (6U << 8U) \| CCM_CCGR6_CG1_SHIFT, /!< CCGR6, CG1 /
AnnaBridge	170:e95d10626187	548	kCLOCK_Usdhc2 = (6U << 8U) \| CCM_CCGR6_CG2_SHIFT, /!< CCGR6, CG2 /
AnnaBridge	170:e95d10626187	549	kCLOCK_Dcdc = (6U << 8U) \| CCM_CCGR6_CG3_SHIFT, /!< CCGR6, CG3 /
AnnaBridge	170:e95d10626187	550	kCLOCK_Ipmux4 = (6U << 8U) \| CCM_CCGR6_CG4_SHIFT, /!< CCGR6, CG4 /
AnnaBridge	170:e95d10626187	551	kCLOCK_FlexSpi = (6U << 8U) \| CCM_CCGR6_CG5_SHIFT, /!< CCGR6, CG5 /
AnnaBridge	170:e95d10626187	552	kCLOCK_Trng = (6U << 8U) \| CCM_CCGR6_CG6_SHIFT, /!< CCGR6, CG6 /
AnnaBridge	170:e95d10626187	553	kCLOCK_Lpuart8 = (6U << 8U) \| CCM_CCGR6_CG7_SHIFT, /!< CCGR6, CG7 /
AnnaBridge	170:e95d10626187	554	kCLOCK_Timer4 = (6U << 8U) \| CCM_CCGR6_CG8_SHIFT, /!< CCGR6, CG8 /
AnnaBridge	170:e95d10626187	555	kCLOCK_Aips_tz3 = (6U << 8U) \| CCM_CCGR6_CG9_SHIFT, /!< CCGR6, CG9 /
AnnaBridge	170:e95d10626187	556	kCLOCK_SimPer = (6U << 8U) \| CCM_CCGR6_CG10_SHIFT, /!< CCGR6, CG10 /
AnnaBridge	170:e95d10626187	557	kCLOCK_Anadig = (6U << 8U) \| CCM_CCGR6_CG11_SHIFT, /!< CCGR6, CG11 /
AnnaBridge	170:e95d10626187	558	kCLOCK_Lpi2c4 = (6U << 8U) \| CCM_CCGR6_CG12_SHIFT, /!< CCGR6, CG12 /
AnnaBridge	170:e95d10626187	559	kCLOCK_Timer1 = (6U << 8U) \| CCM_CCGR6_CG13_SHIFT, /!< CCGR6, CG13 /
AnnaBridge	170:e95d10626187	560	kCLOCK_Timer2 = (6U << 8U) \| CCM_CCGR6_CG14_SHIFT, /!< CCGR6, CG14 /
AnnaBridge	170:e95d10626187	561	kCLOCK_Timer3 = (6U << 8U) \| CCM_CCGR6_CG15_SHIFT, /!< CCGR6, CG15 /
AnnaBridge	161:aa5281ff4a02	562
AnnaBridge	161:aa5281ff4a02	563	} clock_ip_name_t;
AnnaBridge	161:aa5281ff4a02	564
AnnaBridge	161:aa5281ff4a02	565	/! @brief OSC 24M sorce select /
AnnaBridge	161:aa5281ff4a02	566	typedef enum _clock_osc
AnnaBridge	161:aa5281ff4a02	567	{
AnnaBridge	170:e95d10626187	568	kCLOCK_RcOsc = 0U, /!< On chip OSC. /
AnnaBridge	170:e95d10626187	569	kCLOCK_XtalOsc = 1U, /!< 24M Xtal OSC /
AnnaBridge	161:aa5281ff4a02	570	} clock_osc_t;
AnnaBridge	161:aa5281ff4a02	571
AnnaBridge	161:aa5281ff4a02	572	/! @brief Clock gate value /
AnnaBridge	161:aa5281ff4a02	573	typedef enum _clock_gate_value
AnnaBridge	161:aa5281ff4a02	574	{
AnnaBridge	170:e95d10626187	575	kCLOCK_ClockNotNeeded = 0U, /!< Clock is off during all modes. /
AnnaBridge	170:e95d10626187	576	kCLOCK_ClockNeededRun = 1U, /!< Clock is on in run mode, but off in WAIT and STOP modes /
AnnaBridge	170:e95d10626187	577	kCLOCK_ClockNeededRunWait = 3U, /!< Clock is on during all modes, except STOP mode /
AnnaBridge	161:aa5281ff4a02	578	} clock_gate_value_t;
AnnaBridge	161:aa5281ff4a02	579
AnnaBridge	161:aa5281ff4a02	580	/! @brief System clock mode /
AnnaBridge	161:aa5281ff4a02	581	typedef enum _clock_mode_t
AnnaBridge	161:aa5281ff4a02	582	{
AnnaBridge	170:e95d10626187	583	kCLOCK_ModeRun = 0U, /!< Remain in run mode. /
AnnaBridge	170:e95d10626187	584	kCLOCK_ModeWait = 1U, /!< Transfer to wait mode. /
AnnaBridge	170:e95d10626187	585	kCLOCK_ModeStop = 2U, /!< Transfer to stop mode. /
AnnaBridge	161:aa5281ff4a02	586	} clock_mode_t;
AnnaBridge	161:aa5281ff4a02	587
AnnaBridge	161:aa5281ff4a02	588	/*!
AnnaBridge	161:aa5281ff4a02	589	* @brief MUX control names for clock mux setting.
AnnaBridge	161:aa5281ff4a02	590	*
AnnaBridge	161:aa5281ff4a02	591	* These constants define the mux control names for clock mux setting.\n
AnnaBridge	161:aa5281ff4a02	592	* - 0:7: REG offset to CCM_BASE in bytes.
AnnaBridge	161:aa5281ff4a02	593	* - 8:15: Root clock setting bit field shift.
AnnaBridge	161:aa5281ff4a02	594	* - 16:31: Root clock setting bit field width.
AnnaBridge	161:aa5281ff4a02	595	*/
AnnaBridge	161:aa5281ff4a02	596	typedef enum _clock_mux
AnnaBridge	161:aa5281ff4a02	597	{
AnnaBridge	172:65be27845400	598	kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
AnnaBridge	170:e95d10626187	599	CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	600	CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	601	CCM_NO_BUSY_WAIT), /!< pll3_sw_clk mux name /
AnnaBridge	161:aa5281ff4a02	602
AnnaBridge	172:65be27845400	603	kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
AnnaBridge	170:e95d10626187	604	CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	605	CCM_CBCDR_PERIPH_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	606	CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /!< periph mux name /
AnnaBridge	172:65be27845400	607	kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
AnnaBridge	170:e95d10626187	608	CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	609	CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	610	CCM_NO_BUSY_WAIT), /!< semc mux name /
AnnaBridge	170:e95d10626187	611	kCLOCK_SemcMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	612	CBCDR_OFFSET, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< semc mux name /
AnnaBridge	170:e95d10626187	613
AnnaBridge	172:65be27845400	614	kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
AnnaBridge	170:e95d10626187	615	CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	616	CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	617	CCM_NO_BUSY_WAIT), /!< pre-periph mux name /
AnnaBridge	170:e95d10626187	618	kCLOCK_TraceMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	619	CBCMR_OFFSET, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< trace mux name /
AnnaBridge	172:65be27845400	620	kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
AnnaBridge	170:e95d10626187	621	CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
AnnaBridge	170:e95d10626187	622	CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
AnnaBridge	170:e95d10626187	623	CCM_NO_BUSY_WAIT), /!< periph clock2 mux name /
AnnaBridge	170:e95d10626187	624	kCLOCK_LpspiMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	625	CBCMR_OFFSET, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< lpspi mux name /
AnnaBridge	161:aa5281ff4a02	626
AnnaBridge	172:65be27845400	627	kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
AnnaBridge	170:e95d10626187	628	CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	629	CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	630	CCM_NO_BUSY_WAIT), /!< flexspi mux name /
AnnaBridge	172:65be27845400	631	kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
AnnaBridge	170:e95d10626187	632	CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	633	CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	634	CCM_NO_BUSY_WAIT), /!< usdhc2 mux name /
AnnaBridge	172:65be27845400	635	kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
AnnaBridge	170:e95d10626187	636	CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	637	CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	638	CCM_NO_BUSY_WAIT), /!< usdhc1 mux name /
AnnaBridge	170:e95d10626187	639	kCLOCK_Sai3Mux = CCM_TUPLE(
AnnaBridge	172:65be27845400	640	CSCMR1_OFFSET, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< sai3 mux name /
AnnaBridge	170:e95d10626187	641	kCLOCK_Sai2Mux = CCM_TUPLE(
AnnaBridge	172:65be27845400	642	CSCMR1_OFFSET, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< sai2 mux name /
AnnaBridge	170:e95d10626187	643	kCLOCK_Sai1Mux = CCM_TUPLE(
AnnaBridge	172:65be27845400	644	CSCMR1_OFFSET, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< sai1 mux name /
AnnaBridge	172:65be27845400	645	kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
AnnaBridge	170:e95d10626187	646	CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	647	CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	648	CCM_NO_BUSY_WAIT), /!< perclk mux name /
AnnaBridge	161:aa5281ff4a02	649
AnnaBridge	172:65be27845400	650	kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
AnnaBridge	170:e95d10626187	651	CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	652	CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	653	CCM_NO_BUSY_WAIT), /!< flexio2 mux name /
AnnaBridge	170:e95d10626187	654	kCLOCK_CanMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	655	CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< can mux name /
AnnaBridge	170:e95d10626187	656
AnnaBridge	170:e95d10626187	657	kCLOCK_UartMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	658	CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< uart mux name /
AnnaBridge	161:aa5281ff4a02	659
AnnaBridge	170:e95d10626187	660	kCLOCK_SpdifMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	661	CDCDR_OFFSET, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< spdif mux name /
AnnaBridge	172:65be27845400	662	kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
AnnaBridge	170:e95d10626187	663	CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	664	CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	665	CCM_NO_BUSY_WAIT), /!< flexio1 mux name /
AnnaBridge	161:aa5281ff4a02	666
AnnaBridge	170:e95d10626187	667	kCLOCK_Lpi2cMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	668	CSCDR2_OFFSET, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< lpi2c mux name /
AnnaBridge	172:65be27845400	669	kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
AnnaBridge	170:e95d10626187	670	CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
AnnaBridge	170:e95d10626187	671	CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
AnnaBridge	170:e95d10626187	672	CCM_NO_BUSY_WAIT), /!< lcdif pre mux name /
AnnaBridge	170:e95d10626187	673
AnnaBridge	170:e95d10626187	674	kCLOCK_CsiMux = CCM_TUPLE(
AnnaBridge	172:65be27845400	675	CSCDR3_OFFSET, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /!< csi mux name /
AnnaBridge	161:aa5281ff4a02	676	} clock_mux_t;
AnnaBridge	161:aa5281ff4a02	677
AnnaBridge	161:aa5281ff4a02	678	/*!
AnnaBridge	161:aa5281ff4a02	679	* @brief DIV control names for clock div setting.
AnnaBridge	161:aa5281ff4a02	680	*
AnnaBridge	161:aa5281ff4a02	681	* These constants define div control names for clock div setting.\n
AnnaBridge	161:aa5281ff4a02	682	* - 0:7: REG offset to CCM_BASE in bytes.
AnnaBridge	161:aa5281ff4a02	683	* - 8:15: Root clock setting bit field shift.
AnnaBridge	161:aa5281ff4a02	684	* - 16:31: Root clock setting bit field width.
AnnaBridge	161:aa5281ff4a02	685	*/
AnnaBridge	161:aa5281ff4a02	686	typedef enum _clock_div
AnnaBridge	161:aa5281ff4a02	687	{
AnnaBridge	170:e95d10626187	688	kCLOCK_ArmDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	689	CACRR_OFFSET, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /!< core div name /
AnnaBridge	161:aa5281ff4a02	690
AnnaBridge	172:65be27845400	691	kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
AnnaBridge	170:e95d10626187	692	CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
AnnaBridge	170:e95d10626187	693	CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
AnnaBridge	170:e95d10626187	694	CCM_NO_BUSY_WAIT), /!< periph clock2 div name /
AnnaBridge	172:65be27845400	695	kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
AnnaBridge	170:e95d10626187	696	CCM_CBCDR_SEMC_PODF_SHIFT,
AnnaBridge	170:e95d10626187	697	CCM_CBCDR_SEMC_PODF_MASK,
AnnaBridge	170:e95d10626187	698	CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /!< semc div name /
AnnaBridge	170:e95d10626187	699	kCLOCK_AhbDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	700	CBCDR_OFFSET, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /!< ahb div name /
AnnaBridge	170:e95d10626187	701	kCLOCK_IpgDiv =
AnnaBridge	172:65be27845400	702	CCM_TUPLE(CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /!< ipg div name /
AnnaBridge	161:aa5281ff4a02	703
AnnaBridge	170:e95d10626187	704	kCLOCK_LpspiDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	705	CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /!< lpspi div name /
AnnaBridge	170:e95d10626187	706	kCLOCK_LcdifDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	707	CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /!< lcdif div name /
AnnaBridge	161:aa5281ff4a02	708
AnnaBridge	170:e95d10626187	709	kCLOCK_FlexspiDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	710	CSCMR1_OFFSET, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /!< flexspi div name /
AnnaBridge	170:e95d10626187	711	kCLOCK_PerclkDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	712	CSCMR1_OFFSET, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /!< perclk div name /
AnnaBridge	161:aa5281ff4a02	713
AnnaBridge	170:e95d10626187	714	kCLOCK_CanDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	715	CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /!< can div name /
AnnaBridge	170:e95d10626187	716
AnnaBridge	170:e95d10626187	717	kCLOCK_TraceDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	718	CSCDR1_OFFSET, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /!< trace div name /
AnnaBridge	170:e95d10626187	719	kCLOCK_Usdhc2Div = CCM_TUPLE(
AnnaBridge	172:65be27845400	720	CSCDR1_OFFSET, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /!< usdhc2 div name /
AnnaBridge	170:e95d10626187	721	kCLOCK_Usdhc1Div = CCM_TUPLE(
AnnaBridge	172:65be27845400	722	CSCDR1_OFFSET, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /!< usdhc1 div name /
AnnaBridge	170:e95d10626187	723	kCLOCK_UartDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	724	CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /!< uart div name /
AnnaBridge	161:aa5281ff4a02	725
AnnaBridge	172:65be27845400	726	kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
AnnaBridge	170:e95d10626187	727	CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
AnnaBridge	170:e95d10626187	728	CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
AnnaBridge	170:e95d10626187	729	CCM_NO_BUSY_WAIT), /!< flexio2 pre div name /
AnnaBridge	172:65be27845400	730	kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
AnnaBridge	170:e95d10626187	731	CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
AnnaBridge	170:e95d10626187	732	CCM_CS1CDR_SAI3_CLK_PRED_MASK,
AnnaBridge	170:e95d10626187	733	CCM_NO_BUSY_WAIT), /!< sai3 pre div name /
AnnaBridge	170:e95d10626187	734	kCLOCK_Sai3Div = CCM_TUPLE(
AnnaBridge	172:65be27845400	735	CS1CDR_OFFSET, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /!< sai3 div name /
AnnaBridge	172:65be27845400	736	kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
AnnaBridge	170:e95d10626187	737	CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
AnnaBridge	170:e95d10626187	738	CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
AnnaBridge	170:e95d10626187	739	CCM_NO_BUSY_WAIT), /!< sai3 pre div name /
AnnaBridge	172:65be27845400	740	kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
AnnaBridge	170:e95d10626187	741	CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
AnnaBridge	170:e95d10626187	742	CCM_CS1CDR_SAI1_CLK_PRED_MASK,
AnnaBridge	170:e95d10626187	743	CCM_NO_BUSY_WAIT), /!< sai1 pre div name /
AnnaBridge	170:e95d10626187	744	kCLOCK_Sai1Div = CCM_TUPLE(
AnnaBridge	172:65be27845400	745	CS1CDR_OFFSET, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /!< sai1 div name /
AnnaBridge	161:aa5281ff4a02	746
AnnaBridge	172:65be27845400	747	kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
AnnaBridge	170:e95d10626187	748	CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
AnnaBridge	170:e95d10626187	749	CCM_CS2CDR_SAI2_CLK_PRED_MASK,
AnnaBridge	170:e95d10626187	750	CCM_NO_BUSY_WAIT), /!< sai2 pre div name /
AnnaBridge	170:e95d10626187	751	kCLOCK_Sai2Div = CCM_TUPLE(
AnnaBridge	172:65be27845400	752	CS2CDR_OFFSET, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /!< sai2 div name /
AnnaBridge	161:aa5281ff4a02	753
AnnaBridge	172:65be27845400	754	kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
AnnaBridge	170:e95d10626187	755	CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
AnnaBridge	170:e95d10626187	756	CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
AnnaBridge	170:e95d10626187	757	CCM_NO_BUSY_WAIT), /!< spdif pre div name /
AnnaBridge	172:65be27845400	758	kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
AnnaBridge	170:e95d10626187	759	CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
AnnaBridge	170:e95d10626187	760	CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
AnnaBridge	170:e95d10626187	761	CCM_NO_BUSY_WAIT), /!< spdif div name /
AnnaBridge	172:65be27845400	762	kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
AnnaBridge	170:e95d10626187	763	CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
AnnaBridge	170:e95d10626187	764	CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
AnnaBridge	170:e95d10626187	765	CCM_NO_BUSY_WAIT), /!< flexio1 pre div name /
AnnaBridge	172:65be27845400	766	kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
AnnaBridge	170:e95d10626187	767	CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
AnnaBridge	170:e95d10626187	768	CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
AnnaBridge	170:e95d10626187	769	CCM_NO_BUSY_WAIT), /!< flexio1 div name /
AnnaBridge	161:aa5281ff4a02	770
AnnaBridge	172:65be27845400	771	kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
AnnaBridge	170:e95d10626187	772	CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
AnnaBridge	170:e95d10626187	773	CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
AnnaBridge	170:e95d10626187	774	CCM_NO_BUSY_WAIT), /!< lpi2c div name /
AnnaBridge	170:e95d10626187	775	kCLOCK_LcdifPreDiv = CCM_TUPLE(
AnnaBridge	172:65be27845400	776	CSCDR2_OFFSET, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /!< lcdif pre div name /
AnnaBridge	170:e95d10626187	777
AnnaBridge	170:e95d10626187	778	kCLOCK_CsiDiv =
AnnaBridge	172:65be27845400	779	CCM_TUPLE(CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /!< csi div name /
AnnaBridge	161:aa5281ff4a02	780	} clock_div_t;
AnnaBridge	161:aa5281ff4a02	781
AnnaBridge	170:e95d10626187	782	/! @brief USB clock source definition. /
AnnaBridge	170:e95d10626187	783	typedef enum _clock_usb_src
AnnaBridge	170:e95d10626187	784	{
AnnaBridge	172:65be27845400	785	kCLOCK_Usb480M = 0, /!< Use 480M. /
AnnaBridge	172:65be27845400	786	kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
AnnaBridge	170:e95d10626187	787	care the clock source. */
AnnaBridge	170:e95d10626187	788	} clock_usb_src_t;
AnnaBridge	170:e95d10626187	789
AnnaBridge	170:e95d10626187	790	/! @brief Source of the USB HS PHY. /
AnnaBridge	170:e95d10626187	791	typedef enum _clock_usb_phy_src
AnnaBridge	170:e95d10626187	792	{
AnnaBridge	170:e95d10626187	793	kCLOCK_Usbphy480M = 0, /!< Use 480M. /
AnnaBridge	170:e95d10626187	794	} clock_usb_phy_src_t;
AnnaBridge	170:e95d10626187	795
AnnaBridge	170:e95d10626187	796	/!@brief PLL clock source, bypass cloco source also /
AnnaBridge	170:e95d10626187	797	enum _clock_pll_clk_src
AnnaBridge	170:e95d10626187	798	{
AnnaBridge	170:e95d10626187	799	kCLOCK_PllClkSrc24M = 0U, /!< Pll clock source 24M /
AnnaBridge	170:e95d10626187	800	kCLOCK_PllSrcClkPN = 1U, /!< Pll clock source CLK1_P and CLK1_N /
AnnaBridge	170:e95d10626187	801	};
AnnaBridge	161:aa5281ff4a02	802
AnnaBridge	161:aa5281ff4a02	803	/! @brief PLL configuration for ARM /
AnnaBridge	161:aa5281ff4a02	804	typedef struct _clock_arm_pll_config
AnnaBridge	161:aa5281ff4a02	805	{
AnnaBridge	170:e95d10626187	806	uint32_t loopDivider; /!< PLL loop divider. Valid range for divider value: 54-108. Fout=FinloopDivider/2. */
AnnaBridge	170:e95d10626187	807	uint8_t src; /!< Pll clock source, reference _clock_pll_clk_src /
AnnaBridge	161:aa5281ff4a02	808	} clock_arm_pll_config_t;
AnnaBridge	161:aa5281ff4a02	809
AnnaBridge	161:aa5281ff4a02	810	/! @brief PLL configuration for USB /
AnnaBridge	161:aa5281ff4a02	811	typedef struct _clock_usb_pll_config
AnnaBridge	161:aa5281ff4a02	812	{
AnnaBridge	170:e95d10626187	813	uint8_t loopDivider; /*!< PLL loop divider.
AnnaBridge	170:e95d10626187	814	0 - Fout=Fref*20;
AnnaBridge	170:e95d10626187	815	1 - Fout=Fref22 /
AnnaBridge	170:e95d10626187	816	uint8_t src; /!< Pll clock source, reference _clock_pll_clk_src /
AnnaBridge	170:e95d10626187	817
AnnaBridge	161:aa5281ff4a02	818	} clock_usb_pll_config_t;
AnnaBridge	161:aa5281ff4a02	819
AnnaBridge	161:aa5281ff4a02	820	/! @brief PLL configuration for System /
AnnaBridge	161:aa5281ff4a02	821	typedef struct _clock_sys_pll_config
AnnaBridge	161:aa5281ff4a02	822	{
AnnaBridge	170:e95d10626187	823	uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
AnnaBridge	170:e95d10626187	824	0 - Fout=Fref*20;
AnnaBridge	170:e95d10626187	825	1 - Fout=Fref22 /
AnnaBridge	170:e95d10626187	826	uint32_t numerator; /!< 30 bit numerator of fractional loop divider./
AnnaBridge	170:e95d10626187	827	uint32_t denominator; /!< 30 bit denominator of fractional loop divider /
AnnaBridge	170:e95d10626187	828	uint8_t src; /!< Pll clock source, reference _clock_pll_clk_src /
AnnaBridge	172:65be27845400	829	uint16_t ss_stop; /!< Stop value to get frequency change. /
AnnaBridge	172:65be27845400	830	uint8_t ss_enable; /!< Enable spread spectrum modulation /
AnnaBridge	172:65be27845400	831	uint16_t ss_step; /!< Step value to get frequency change step. /
AnnaBridge	170:e95d10626187	832
AnnaBridge	161:aa5281ff4a02	833	} clock_sys_pll_config_t;
AnnaBridge	161:aa5281ff4a02	834
AnnaBridge	161:aa5281ff4a02	835	/! @brief PLL configuration for AUDIO and VIDEO /
AnnaBridge	161:aa5281ff4a02	836	typedef struct _clock_audio_pll_config
AnnaBridge	161:aa5281ff4a02	837	{
AnnaBridge	170:e95d10626187	838	uint8_t loopDivider; /!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. /
AnnaBridge	170:e95d10626187	839	uint8_t postDivider; /!< Divider after the PLL, should only be 1, 2, 4, 8, 16. /
AnnaBridge	170:e95d10626187	840	uint32_t numerator; /!< 30 bit numerator of fractional loop divider./
AnnaBridge	170:e95d10626187	841	uint32_t denominator; /!< 30 bit denominator of fractional loop divider /
AnnaBridge	170:e95d10626187	842	uint8_t src; /!< Pll clock source, reference _clock_pll_clk_src /
AnnaBridge	161:aa5281ff4a02	843	} clock_audio_pll_config_t;
AnnaBridge	161:aa5281ff4a02	844
AnnaBridge	161:aa5281ff4a02	845	/! @brief PLL configuration for AUDIO and VIDEO /
AnnaBridge	161:aa5281ff4a02	846	typedef struct _clock_video_pll_config
AnnaBridge	161:aa5281ff4a02	847	{
AnnaBridge	170:e95d10626187	848	uint8_t loopDivider; /!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. /
AnnaBridge	170:e95d10626187	849	uint8_t postDivider; /!< Divider after the PLL, should only be 1, 2, 4, 8, 16. /
AnnaBridge	170:e95d10626187	850	uint32_t numerator; /!< 30 bit numerator of fractional loop divider./
AnnaBridge	170:e95d10626187	851	uint32_t denominator; /!< 30 bit denominator of fractional loop divider /
AnnaBridge	170:e95d10626187	852	uint8_t src; /!< Pll clock source, reference _clock_pll_clk_src /
AnnaBridge	170:e95d10626187	853
AnnaBridge	161:aa5281ff4a02	854	} clock_video_pll_config_t;
AnnaBridge	161:aa5281ff4a02	855
AnnaBridge	161:aa5281ff4a02	856	/! @brief PLL configuration for ENET /
AnnaBridge	161:aa5281ff4a02	857	typedef struct _clock_enet_pll_config
AnnaBridge	161:aa5281ff4a02	858	{
AnnaBridge	170:e95d10626187	859	bool enableClkOutput; /!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). /
AnnaBridge	170:e95d10626187	860
AnnaBridge	170:e95d10626187	861	bool enableClkOutput25M; /!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). /
AnnaBridge	170:e95d10626187	862	uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
AnnaBridge	170:e95d10626187	863	b00 25MHz
AnnaBridge	170:e95d10626187	864	b01 50MHz
AnnaBridge	170:e95d10626187	865	b10 100MHz (not 50% duty cycle)
AnnaBridge	170:e95d10626187	866	b11 125MHz */
AnnaBridge	170:e95d10626187	867	uint8_t src; /!< Pll clock source, reference _clock_pll_clk_src /
AnnaBridge	170:e95d10626187	868
AnnaBridge	161:aa5281ff4a02	869	} clock_enet_pll_config_t;
AnnaBridge	161:aa5281ff4a02	870
AnnaBridge	161:aa5281ff4a02	871	/! @brief PLL name /
AnnaBridge	161:aa5281ff4a02	872	typedef enum _clock_pll
AnnaBridge	161:aa5281ff4a02	873	{
AnnaBridge	172:65be27845400	874	kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /!< PLL ARM /
AnnaBridge	172:65be27845400	875	kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /!< PLL SYS /
AnnaBridge	172:65be27845400	876	kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /!< PLL USB1 /
AnnaBridge	172:65be27845400	877	kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /!< PLL Audio /
AnnaBridge	172:65be27845400	878	kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /!< PLL Video /
AnnaBridge	170:e95d10626187	879
AnnaBridge	172:65be27845400	880	kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /!< PLL Enet0 /
AnnaBridge	170:e95d10626187	881
AnnaBridge	172:65be27845400	882	kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /!< PLL Enet1 /
AnnaBridge	170:e95d10626187	883
AnnaBridge	172:65be27845400	884	kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /!< PLL USB2 /
AnnaBridge	170:e95d10626187	885
AnnaBridge	161:aa5281ff4a02	886	} clock_pll_t;
AnnaBridge	161:aa5281ff4a02	887
AnnaBridge	161:aa5281ff4a02	888	/! @brief PLL PFD name /
AnnaBridge	161:aa5281ff4a02	889	typedef enum _clock_pfd
AnnaBridge	161:aa5281ff4a02	890	{
AnnaBridge	170:e95d10626187	891	kCLOCK_Pfd0 = 0U, /!< PLL PFD0 /
AnnaBridge	170:e95d10626187	892	kCLOCK_Pfd1 = 1U, /!< PLL PFD1 /
AnnaBridge	170:e95d10626187	893	kCLOCK_Pfd2 = 2U, /!< PLL PFD2 /
AnnaBridge	170:e95d10626187	894	kCLOCK_Pfd3 = 3U, /!< PLL PFD3 /
AnnaBridge	161:aa5281ff4a02	895	} clock_pfd_t;
AnnaBridge	161:aa5281ff4a02	896
AnnaBridge	161:aa5281ff4a02	897	/*******************************************************************************
AnnaBridge	161:aa5281ff4a02	898	* API
AnnaBridge	161:aa5281ff4a02	899	******************************************************************************/
AnnaBridge	161:aa5281ff4a02	900
AnnaBridge	161:aa5281ff4a02	901	#if defined(__cplusplus)
AnnaBridge	161:aa5281ff4a02	902	extern "C" {
AnnaBridge	161:aa5281ff4a02	903	#endif /* __cplusplus */
AnnaBridge	161:aa5281ff4a02	904
AnnaBridge	161:aa5281ff4a02	905	/*!
AnnaBridge	161:aa5281ff4a02	906	* @brief Set CCM MUX node to certain value.
AnnaBridge	161:aa5281ff4a02	907	*
AnnaBridge	161:aa5281ff4a02	908	* @param mux Which mux node to set, see \ref clock_mux_t.
AnnaBridge	161:aa5281ff4a02	909	* @param value Clock mux value to set, different mux has different value range.
AnnaBridge	161:aa5281ff4a02	910	*/
AnnaBridge	161:aa5281ff4a02	911	static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
AnnaBridge	161:aa5281ff4a02	912	{
AnnaBridge	161:aa5281ff4a02	913	uint32_t busyShift;
AnnaBridge	161:aa5281ff4a02	914
AnnaBridge	161:aa5281ff4a02	915	busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
AnnaBridge	161:aa5281ff4a02	916	CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) \|
AnnaBridge	161:aa5281ff4a02	917	(((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
AnnaBridge	161:aa5281ff4a02	918
AnnaBridge	161:aa5281ff4a02	919	assert(busyShift <= CCM_NO_BUSY_WAIT);
AnnaBridge	161:aa5281ff4a02	920
AnnaBridge	161:aa5281ff4a02	921	/* Clock switch need Handshake? */
AnnaBridge	161:aa5281ff4a02	922	if (CCM_NO_BUSY_WAIT != busyShift)
AnnaBridge	161:aa5281ff4a02	923	{
AnnaBridge	161:aa5281ff4a02	924	/* Wait until CCM internal handshake finish. */
AnnaBridge	161:aa5281ff4a02	925	while (CCM->CDHIPR & (1U << busyShift))
AnnaBridge	161:aa5281ff4a02	926	{
AnnaBridge	161:aa5281ff4a02	927	}
AnnaBridge	161:aa5281ff4a02	928	}
AnnaBridge	161:aa5281ff4a02	929	}
AnnaBridge	161:aa5281ff4a02	930
AnnaBridge	161:aa5281ff4a02	931	/*!
AnnaBridge	161:aa5281ff4a02	932	* @brief Get CCM MUX value.
AnnaBridge	161:aa5281ff4a02	933	*
AnnaBridge	161:aa5281ff4a02	934	* @param mux Which mux node to get, see \ref clock_mux_t.
AnnaBridge	161:aa5281ff4a02	935	* @return Clock mux value.
AnnaBridge	161:aa5281ff4a02	936	*/
AnnaBridge	161:aa5281ff4a02	937	static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
AnnaBridge	161:aa5281ff4a02	938	{
AnnaBridge	161:aa5281ff4a02	939	return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
AnnaBridge	161:aa5281ff4a02	940	}
AnnaBridge	161:aa5281ff4a02	941
AnnaBridge	161:aa5281ff4a02	942	/*!
AnnaBridge	161:aa5281ff4a02	943	* @brief Set CCM DIV node to certain value.
AnnaBridge	161:aa5281ff4a02	944	*
AnnaBridge	161:aa5281ff4a02	945	* @param divider Which div node to set, see \ref clock_div_t.
AnnaBridge	161:aa5281ff4a02	946	* @param value Clock div value to set, different divider has different value range.
AnnaBridge	161:aa5281ff4a02	947	*/
AnnaBridge	161:aa5281ff4a02	948	static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
AnnaBridge	161:aa5281ff4a02	949	{
AnnaBridge	161:aa5281ff4a02	950	uint32_t busyShift;
AnnaBridge	161:aa5281ff4a02	951
AnnaBridge	161:aa5281ff4a02	952	busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
AnnaBridge	161:aa5281ff4a02	953	CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) \|
AnnaBridge	170:e95d10626187	954	(((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
AnnaBridge	161:aa5281ff4a02	955
AnnaBridge	161:aa5281ff4a02	956	assert(busyShift <= CCM_NO_BUSY_WAIT);
AnnaBridge	161:aa5281ff4a02	957
AnnaBridge	161:aa5281ff4a02	958	/* Clock switch need Handshake? */
AnnaBridge	161:aa5281ff4a02	959	if (CCM_NO_BUSY_WAIT != busyShift)
AnnaBridge	161:aa5281ff4a02	960	{
AnnaBridge	161:aa5281ff4a02	961	/* Wait until CCM internal handshake finish. */
AnnaBridge	161:aa5281ff4a02	962	while (CCM->CDHIPR & (1U << busyShift))
AnnaBridge	161:aa5281ff4a02	963	{
AnnaBridge	161:aa5281ff4a02	964	}
AnnaBridge	161:aa5281ff4a02	965	}
AnnaBridge	161:aa5281ff4a02	966	}
AnnaBridge	161:aa5281ff4a02	967
AnnaBridge	161:aa5281ff4a02	968	/*!
AnnaBridge	161:aa5281ff4a02	969	* @brief Get CCM DIV node value.
AnnaBridge	161:aa5281ff4a02	970	*
AnnaBridge	161:aa5281ff4a02	971	* @param divider Which div node to get, see \ref clock_div_t.
AnnaBridge	161:aa5281ff4a02	972	*/
AnnaBridge	161:aa5281ff4a02	973	static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
AnnaBridge	161:aa5281ff4a02	974	{
AnnaBridge	170:e95d10626187	975	return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
AnnaBridge	161:aa5281ff4a02	976	}
AnnaBridge	161:aa5281ff4a02	977
AnnaBridge	161:aa5281ff4a02	978	/*!
AnnaBridge	161:aa5281ff4a02	979	* @brief Control the clock gate for specific IP.
AnnaBridge	161:aa5281ff4a02	980	*
AnnaBridge	161:aa5281ff4a02	981	* @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge	161:aa5281ff4a02	982	* @param value Clock gate value to set, see \ref clock_gate_value_t.
AnnaBridge	161:aa5281ff4a02	983	*/
AnnaBridge	161:aa5281ff4a02	984	static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
AnnaBridge	161:aa5281ff4a02	985	{
AnnaBridge	161:aa5281ff4a02	986	uint32_t index = ((uint32_t)name) >> 8U;
AnnaBridge	161:aa5281ff4a02	987	uint32_t shift = ((uint32_t)name) & 0x1FU;
AnnaBridge	161:aa5281ff4a02	988	volatile uint32_t *reg;
AnnaBridge	161:aa5281ff4a02	989
AnnaBridge	170:e95d10626187	990	assert(index <= 6);
AnnaBridge	161:aa5281ff4a02	991
AnnaBridge	161:aa5281ff4a02	992	reg = ((volatile uint32_t *)&CCM->CCGR0) + index;
AnnaBridge	161:aa5281ff4a02	993	reg = ((reg) & ~(3U << shift)) \| (((uint32_t)value) << shift);
AnnaBridge	161:aa5281ff4a02	994	}
AnnaBridge	161:aa5281ff4a02	995
AnnaBridge	161:aa5281ff4a02	996	/*!
AnnaBridge	161:aa5281ff4a02	997	* @brief Enable the clock for specific IP.
AnnaBridge	161:aa5281ff4a02	998	*
AnnaBridge	161:aa5281ff4a02	999	* @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge	161:aa5281ff4a02	1000	*/
AnnaBridge	161:aa5281ff4a02	1001	static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge	161:aa5281ff4a02	1002	{
AnnaBridge	161:aa5281ff4a02	1003	CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
AnnaBridge	161:aa5281ff4a02	1004	}
AnnaBridge	161:aa5281ff4a02	1005
AnnaBridge	161:aa5281ff4a02	1006	/*!
AnnaBridge	161:aa5281ff4a02	1007	* @brief Disable the clock for specific IP.
AnnaBridge	161:aa5281ff4a02	1008	*
AnnaBridge	161:aa5281ff4a02	1009	* @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge	161:aa5281ff4a02	1010	*/
AnnaBridge	161:aa5281ff4a02	1011	static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge	161:aa5281ff4a02	1012	{
AnnaBridge	161:aa5281ff4a02	1013	CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
AnnaBridge	161:aa5281ff4a02	1014	}
AnnaBridge	161:aa5281ff4a02	1015
AnnaBridge	161:aa5281ff4a02	1016	/*!
AnnaBridge	161:aa5281ff4a02	1017	* @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
AnnaBridge	161:aa5281ff4a02	1018	*
AnnaBridge	161:aa5281ff4a02	1019	* @param mode Which mode to enter, see \ref clock_mode_t.
AnnaBridge	161:aa5281ff4a02	1020	*/
AnnaBridge	161:aa5281ff4a02	1021	static inline void CLOCK_SetMode(clock_mode_t mode)
AnnaBridge	161:aa5281ff4a02	1022	{
AnnaBridge	161:aa5281ff4a02	1023	CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) \| CCM_CLPCR_LPM((uint32_t)mode);
AnnaBridge	161:aa5281ff4a02	1024	}
AnnaBridge	170:e95d10626187	1025
AnnaBridge	170:e95d10626187	1026	/*!
AnnaBridge	170:e95d10626187	1027	* @brief Gets the OSC clock frequency.
AnnaBridge	170:e95d10626187	1028	*
AnnaBridge	170:e95d10626187	1029	* This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
AnnaBridge	170:e95d10626187	1030	* otherwise internal 24MHz RC OSC frequency will be returned.
AnnaBridge	170:e95d10626187	1031	*
AnnaBridge	170:e95d10626187	1032	* @param osc OSC type to get frequency.
AnnaBridge	170:e95d10626187	1033	*
AnnaBridge	170:e95d10626187	1034	* @return Clock frequency; If the clock is invalid, returns 0.
AnnaBridge	170:e95d10626187	1035	*/
AnnaBridge	170:e95d10626187	1036	static inline uint32_t CLOCK_GetOscFreq(void)
AnnaBridge	170:e95d10626187	1037	{
AnnaBridge	170:e95d10626187	1038	return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq;
AnnaBridge	170:e95d10626187	1039	}
AnnaBridge	170:e95d10626187	1040
AnnaBridge	161:aa5281ff4a02	1041	/*!
AnnaBridge	172:65be27845400	1042	* @brief Gets the AHB clock frequency.
AnnaBridge	172:65be27845400	1043	*
AnnaBridge	172:65be27845400	1044	* @return The AHB clock frequency value in hertz.
AnnaBridge	172:65be27845400	1045	*/
AnnaBridge	172:65be27845400	1046	uint32_t CLOCK_GetAhbFreq(void);
AnnaBridge	172:65be27845400	1047
AnnaBridge	172:65be27845400	1048	/*!
AnnaBridge	172:65be27845400	1049	* @brief Gets the SEMC clock frequency.
AnnaBridge	172:65be27845400	1050	*
AnnaBridge	172:65be27845400	1051	* @return The SEMC clock frequency value in hertz.
AnnaBridge	172:65be27845400	1052	*/
AnnaBridge	172:65be27845400	1053	uint32_t CLOCK_GetSemcFreq(void);
AnnaBridge	172:65be27845400	1054
AnnaBridge	172:65be27845400	1055	/*!
AnnaBridge	172:65be27845400	1056	* @brief Gets the IPG clock frequency.
AnnaBridge	172:65be27845400	1057	*
AnnaBridge	172:65be27845400	1058	* @return The IPG clock frequency value in hertz.
AnnaBridge	172:65be27845400	1059	*/
AnnaBridge	172:65be27845400	1060	uint32_t CLOCK_GetIpgFreq(void);
AnnaBridge	172:65be27845400	1061
AnnaBridge	172:65be27845400	1062	/*!
AnnaBridge	172:65be27845400	1063	* @brief Gets the PER clock frequency.
AnnaBridge	172:65be27845400	1064	*
AnnaBridge	172:65be27845400	1065	* @return The PER clock frequency value in hertz.
AnnaBridge	172:65be27845400	1066	*/
AnnaBridge	172:65be27845400	1067	uint32_t CLOCK_GetPerClkFreq(void);
AnnaBridge	172:65be27845400	1068
AnnaBridge	172:65be27845400	1069	/*!
AnnaBridge	161:aa5281ff4a02	1070	* @brief Gets the clock frequency for a specific clock name.
AnnaBridge	161:aa5281ff4a02	1071	*
AnnaBridge	161:aa5281ff4a02	1072	* This function checks the current clock configurations and then calculates
AnnaBridge	161:aa5281ff4a02	1073	* the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge	161:aa5281ff4a02	1074	*
AnnaBridge	161:aa5281ff4a02	1075	* @param clockName Clock names defined in clock_name_t
AnnaBridge	161:aa5281ff4a02	1076	* @return Clock frequency value in hertz
AnnaBridge	161:aa5281ff4a02	1077	*/
AnnaBridge	161:aa5281ff4a02	1078	uint32_t CLOCK_GetFreq(clock_name_t name);
AnnaBridge	161:aa5281ff4a02	1079
AnnaBridge	161:aa5281ff4a02	1080	/*!
AnnaBridge	161:aa5281ff4a02	1081	* @brief Get the CCM CPU/core/system frequency.
AnnaBridge	161:aa5281ff4a02	1082	*
AnnaBridge	161:aa5281ff4a02	1083	* @return Clock frequency; If the clock is invalid, returns 0.
AnnaBridge	161:aa5281ff4a02	1084	*/
AnnaBridge	161:aa5281ff4a02	1085	static inline uint32_t CLOCK_GetCpuClkFreq(void)
AnnaBridge	161:aa5281ff4a02	1086	{
AnnaBridge	161:aa5281ff4a02	1087	return CLOCK_GetFreq(kCLOCK_CpuClk);
AnnaBridge	161:aa5281ff4a02	1088	}
AnnaBridge	161:aa5281ff4a02	1089
AnnaBridge	161:aa5281ff4a02	1090	/*!
AnnaBridge	161:aa5281ff4a02	1091	* @name OSC operations
AnnaBridge	161:aa5281ff4a02	1092	* @{
AnnaBridge	161:aa5281ff4a02	1093	*/
AnnaBridge	161:aa5281ff4a02	1094
AnnaBridge	161:aa5281ff4a02	1095	/*!
AnnaBridge	161:aa5281ff4a02	1096	* @brief Initialize the external 24MHz clock.
AnnaBridge	161:aa5281ff4a02	1097	*
AnnaBridge	161:aa5281ff4a02	1098	* This function supports two modes:
AnnaBridge	161:aa5281ff4a02	1099	* 1. Use external crystal oscillator.
AnnaBridge	161:aa5281ff4a02	1100	* 2. Bypass the external crystal oscillator, using input source clock directly.
AnnaBridge	161:aa5281ff4a02	1101	*
AnnaBridge	161:aa5281ff4a02	1102	* After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver
AnnaBridge	161:aa5281ff4a02	1103	* the external clock frequency.
AnnaBridge	161:aa5281ff4a02	1104	*
AnnaBridge	161:aa5281ff4a02	1105	* @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
AnnaBridge	161:aa5281ff4a02	1106	* @note This device does not support bypass external crystal oscillator, so
AnnaBridge	161:aa5281ff4a02	1107	* the input parameter should always be false.
AnnaBridge	161:aa5281ff4a02	1108	*/
AnnaBridge	161:aa5281ff4a02	1109	void CLOCK_InitExternalClk(bool bypassXtalOsc);
AnnaBridge	161:aa5281ff4a02	1110
AnnaBridge	161:aa5281ff4a02	1111	/*!
AnnaBridge	161:aa5281ff4a02	1112	* @brief Deinitialize the external 24MHz clock.
AnnaBridge	161:aa5281ff4a02	1113	*
AnnaBridge	161:aa5281ff4a02	1114	* This function disables the external 24MHz clock.
AnnaBridge	161:aa5281ff4a02	1115	*
AnnaBridge	161:aa5281ff4a02	1116	* After this function, please call @ref CLOCK_SetXtal0Freq to set external clock
AnnaBridge	161:aa5281ff4a02	1117	* frequency to 0.
AnnaBridge	161:aa5281ff4a02	1118	*/
AnnaBridge	161:aa5281ff4a02	1119	void CLOCK_DeinitExternalClk(void);
AnnaBridge	161:aa5281ff4a02	1120
AnnaBridge	161:aa5281ff4a02	1121	/*!
AnnaBridge	161:aa5281ff4a02	1122	* @brief Switch the OSC.
AnnaBridge	161:aa5281ff4a02	1123	*
AnnaBridge	161:aa5281ff4a02	1124	* This function switches the OSC source for SoC.
AnnaBridge	161:aa5281ff4a02	1125	*
AnnaBridge	161:aa5281ff4a02	1126	* @param osc OSC source to switch to.
AnnaBridge	161:aa5281ff4a02	1127	*/
AnnaBridge	161:aa5281ff4a02	1128	void CLOCK_SwitchOsc(clock_osc_t osc);
AnnaBridge	161:aa5281ff4a02	1129
AnnaBridge	161:aa5281ff4a02	1130	/*!
AnnaBridge	161:aa5281ff4a02	1131	* @brief Gets the RTC clock frequency.
AnnaBridge	161:aa5281ff4a02	1132	*
AnnaBridge	161:aa5281ff4a02	1133	* @return Clock frequency; If the clock is invalid, returns 0.
AnnaBridge	161:aa5281ff4a02	1134	*/
AnnaBridge	161:aa5281ff4a02	1135	static inline uint32_t CLOCK_GetRtcFreq(void)
AnnaBridge	161:aa5281ff4a02	1136	{
AnnaBridge	161:aa5281ff4a02	1137	return 32768U;
AnnaBridge	161:aa5281ff4a02	1138	}
AnnaBridge	161:aa5281ff4a02	1139
AnnaBridge	161:aa5281ff4a02	1140	/*!
AnnaBridge	161:aa5281ff4a02	1141	* @brief Set the XTAL (24M OSC) frequency based on board setting.
AnnaBridge	161:aa5281ff4a02	1142	*
AnnaBridge	161:aa5281ff4a02	1143	* @param freq The XTAL input clock frequency in Hz.
AnnaBridge	161:aa5281ff4a02	1144	*/
AnnaBridge	161:aa5281ff4a02	1145	static inline void CLOCK_SetXtalFreq(uint32_t freq)
AnnaBridge	161:aa5281ff4a02	1146	{
AnnaBridge	161:aa5281ff4a02	1147	g_xtalFreq = freq;
AnnaBridge	161:aa5281ff4a02	1148	}
AnnaBridge	161:aa5281ff4a02	1149
AnnaBridge	161:aa5281ff4a02	1150	/*!
AnnaBridge	161:aa5281ff4a02	1151	* @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
AnnaBridge	161:aa5281ff4a02	1152	*
AnnaBridge	161:aa5281ff4a02	1153	* @param freq The RTC XTAL input clock frequency in Hz.
AnnaBridge	161:aa5281ff4a02	1154	*/
AnnaBridge	161:aa5281ff4a02	1155	static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
AnnaBridge	161:aa5281ff4a02	1156	{
AnnaBridge	161:aa5281ff4a02	1157	g_rtcXtalFreq = freq;
AnnaBridge	161:aa5281ff4a02	1158	}
AnnaBridge	161:aa5281ff4a02	1159
AnnaBridge	161:aa5281ff4a02	1160	/*!
AnnaBridge	161:aa5281ff4a02	1161	* @brief Initialize the RC oscillator 24MHz clock.
AnnaBridge	161:aa5281ff4a02	1162	*/
AnnaBridge	161:aa5281ff4a02	1163	void CLOCK_InitRcOsc24M(void);
AnnaBridge	161:aa5281ff4a02	1164
AnnaBridge	161:aa5281ff4a02	1165	/*!
AnnaBridge	161:aa5281ff4a02	1166	* @brief Power down the RCOSC 24M clock.
AnnaBridge	161:aa5281ff4a02	1167	*/
AnnaBridge	161:aa5281ff4a02	1168	void CLOCK_DeinitRcOsc24M(void);
AnnaBridge	161:aa5281ff4a02	1169	/* @} */
AnnaBridge	161:aa5281ff4a02	1170
AnnaBridge	170:e95d10626187	1171	/*! @brief Enable USB HS clock.
AnnaBridge	170:e95d10626187	1172	*
AnnaBridge	170:e95d10626187	1173	* This function only enables the access to USB HS prepheral, upper layer
AnnaBridge	170:e95d10626187	1174	* should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
AnnaBridge	170:e95d10626187	1175	* clock to use USB HS.
AnnaBridge	170:e95d10626187	1176	*
AnnaBridge	170:e95d10626187	1177	* @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
AnnaBridge	170:e95d10626187	1178	* @param freq USB HS does not care about the clock source, so this parameter is ignored.
AnnaBridge	170:e95d10626187	1179	* @retval true The clock is set successfully.
AnnaBridge	170:e95d10626187	1180	* @retval false The clock source is invalid to get proper USB HS clock.
AnnaBridge	170:e95d10626187	1181	*/
AnnaBridge	170:e95d10626187	1182	bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge	170:e95d10626187	1183
AnnaBridge	170:e95d10626187	1184	/*! @brief Enable USB HS clock.
AnnaBridge	170:e95d10626187	1185	*
AnnaBridge	170:e95d10626187	1186	* This function only enables the access to USB HS prepheral, upper layer
AnnaBridge	170:e95d10626187	1187	* should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
AnnaBridge	170:e95d10626187	1188	* clock to use USB HS.
AnnaBridge	170:e95d10626187	1189	*
AnnaBridge	170:e95d10626187	1190	* @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
AnnaBridge	170:e95d10626187	1191	* @param freq USB HS does not care about the clock source, so this parameter is ignored.
AnnaBridge	170:e95d10626187	1192	* @retval true The clock is set successfully.
AnnaBridge	170:e95d10626187	1193	* @retval false The clock source is invalid to get proper USB HS clock.
AnnaBridge	170:e95d10626187	1194	*/
AnnaBridge	170:e95d10626187	1195	bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge	170:e95d10626187	1196
AnnaBridge	170:e95d10626187	1197	/*! @brief Disable USB HS PHY PLL clock.
AnnaBridge	170:e95d10626187	1198	*
AnnaBridge	170:e95d10626187	1199	* This function disables USB HS PHY PLL clock.
AnnaBridge	170:e95d10626187	1200	*/
AnnaBridge	170:e95d10626187	1201	void CLOCK_DisableUsbhs1PhyPllClock(void);
AnnaBridge	170:e95d10626187	1202
AnnaBridge	170:e95d10626187	1203	/* @} */
AnnaBridge	170:e95d10626187	1204
AnnaBridge	161:aa5281ff4a02	1205	/*!
AnnaBridge	161:aa5281ff4a02	1206	* @name PLL/PFD operations
AnnaBridge	161:aa5281ff4a02	1207	* @{
AnnaBridge	161:aa5281ff4a02	1208	*/
AnnaBridge	170:e95d10626187	1209	/*!
AnnaBridge	170:e95d10626187	1210	* @brief PLL bypass setting
AnnaBridge	170:e95d10626187	1211	*
AnnaBridge	170:e95d10626187	1212	* @param base CCM_ANALOG base pointer.
AnnaBridge	170:e95d10626187	1213	* @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
AnnaBridge	170:e95d10626187	1214	* @param bypass Bypass the PLL.
AnnaBridge	170:e95d10626187	1215	* - true: Bypass the PLL.
AnnaBridge	170:e95d10626187	1216	* - false:Not bypass the PLL.
AnnaBridge	170:e95d10626187	1217	*/
AnnaBridge	170:e95d10626187	1218	static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
AnnaBridge	170:e95d10626187	1219	{
AnnaBridge	170:e95d10626187	1220	if (bypass)
AnnaBridge	170:e95d10626187	1221	{
AnnaBridge	170:e95d10626187	1222	CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT;
AnnaBridge	170:e95d10626187	1223	}
AnnaBridge	170:e95d10626187	1224	else
AnnaBridge	170:e95d10626187	1225	{
AnnaBridge	170:e95d10626187	1226	CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT;
AnnaBridge	170:e95d10626187	1227	}
AnnaBridge	170:e95d10626187	1228	}
AnnaBridge	170:e95d10626187	1229
AnnaBridge	170:e95d10626187	1230	/*!
AnnaBridge	170:e95d10626187	1231	* @brief Check if PLL is bypassed
AnnaBridge	170:e95d10626187	1232	*
AnnaBridge	170:e95d10626187	1233	* @param base CCM_ANALOG base pointer.
AnnaBridge	170:e95d10626187	1234	* @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
AnnaBridge	170:e95d10626187	1235	* @return PLL bypass status.
AnnaBridge	170:e95d10626187	1236	* - true: The PLL is bypassed.
AnnaBridge	170:e95d10626187	1237	* - false: The PLL is not bypassed.
AnnaBridge	170:e95d10626187	1238	*/
AnnaBridge	170:e95d10626187	1239	static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
AnnaBridge	170:e95d10626187	1240	{
AnnaBridge	170:e95d10626187	1241	return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT));
AnnaBridge	170:e95d10626187	1242	}
AnnaBridge	170:e95d10626187	1243
AnnaBridge	170:e95d10626187	1244	/*!
AnnaBridge	170:e95d10626187	1245	* @brief Check if PLL is enabled
AnnaBridge	170:e95d10626187	1246	*
AnnaBridge	170:e95d10626187	1247	* @param base CCM_ANALOG base pointer.
AnnaBridge	170:e95d10626187	1248	* @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
AnnaBridge	170:e95d10626187	1249	* @return PLL bypass status.
AnnaBridge	170:e95d10626187	1250	* - true: The PLL is enabled.
AnnaBridge	170:e95d10626187	1251	* - false: The PLL is not enabled.
AnnaBridge	170:e95d10626187	1252	*/
AnnaBridge	170:e95d10626187	1253	static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
AnnaBridge	170:e95d10626187	1254	{
AnnaBridge	170:e95d10626187	1255	return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll)));
AnnaBridge	170:e95d10626187	1256	}
AnnaBridge	170:e95d10626187	1257
AnnaBridge	170:e95d10626187	1258	/*!
AnnaBridge	170:e95d10626187	1259	* @brief PLL bypass clock source setting.
AnnaBridge	170:e95d10626187	1260	* Note: change the bypass clock source also change the pll reference clock source.
AnnaBridge	170:e95d10626187	1261	*
AnnaBridge	170:e95d10626187	1262	* @param base CCM_ANALOG base pointer.
AnnaBridge	170:e95d10626187	1263	* @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
AnnaBridge	170:e95d10626187	1264	* @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
AnnaBridge	170:e95d10626187	1265	*/
AnnaBridge	170:e95d10626187	1266	static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
AnnaBridge	170:e95d10626187	1267	{
AnnaBridge	170:e95d10626187	1268	CCM_ANALOG_TUPLE_REG(base, pll) \|= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) \| src;
AnnaBridge	170:e95d10626187	1269	}
AnnaBridge	170:e95d10626187	1270
AnnaBridge	170:e95d10626187	1271	/*!
AnnaBridge	170:e95d10626187	1272	* @brief Get PLL bypass clock value, it is PLL reference clock actually.
AnnaBridge	170:e95d10626187	1273	* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
AnnaBridge	170:e95d10626187	1274	* will be returned.
AnnaBridge	170:e95d10626187	1275	* @param base CCM_ANALOG base pointer.
AnnaBridge	170:e95d10626187	1276	* @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
AnnaBridge	170:e95d10626187	1277	* @retval bypass reference clock frequency value.
AnnaBridge	170:e95d10626187	1278	*/
AnnaBridge	170:e95d10626187	1279	static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
AnnaBridge	170:e95d10626187	1280	{
AnnaBridge	170:e95d10626187	1281	return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
AnnaBridge	170:e95d10626187	1282	CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ?
AnnaBridge	170:e95d10626187	1283	CLOCK_GetOscFreq() :
AnnaBridge	170:e95d10626187	1284	CLKPN_FREQ;
AnnaBridge	170:e95d10626187	1285	}
AnnaBridge	161:aa5281ff4a02	1286
AnnaBridge	161:aa5281ff4a02	1287	/*!
AnnaBridge	161:aa5281ff4a02	1288	* @brief Initialize the ARM PLL.
AnnaBridge	161:aa5281ff4a02	1289	*
AnnaBridge	161:aa5281ff4a02	1290	* This function initialize the ARM PLL with specific settings
AnnaBridge	161:aa5281ff4a02	1291	*
AnnaBridge	161:aa5281ff4a02	1292	* @param config configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1293	*/
AnnaBridge	161:aa5281ff4a02	1294	void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1295
AnnaBridge	161:aa5281ff4a02	1296	/*!
AnnaBridge	161:aa5281ff4a02	1297	* @brief De-initialize the ARM PLL.
AnnaBridge	161:aa5281ff4a02	1298	*/
AnnaBridge	161:aa5281ff4a02	1299	void CLOCK_DeinitArmPll(void);
AnnaBridge	161:aa5281ff4a02	1300
AnnaBridge	161:aa5281ff4a02	1301	/*!
AnnaBridge	161:aa5281ff4a02	1302	* @brief Initialize the System PLL.
AnnaBridge	161:aa5281ff4a02	1303	*
AnnaBridge	161:aa5281ff4a02	1304	* This function initializes the System PLL with specific settings
AnnaBridge	161:aa5281ff4a02	1305	*
AnnaBridge	161:aa5281ff4a02	1306	* @param config Configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1307	*/
AnnaBridge	161:aa5281ff4a02	1308	void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1309
AnnaBridge	161:aa5281ff4a02	1310	/*!
AnnaBridge	161:aa5281ff4a02	1311	* @brief De-initialize the System PLL.
AnnaBridge	161:aa5281ff4a02	1312	*/
AnnaBridge	161:aa5281ff4a02	1313	void CLOCK_DeinitSysPll(void);
AnnaBridge	161:aa5281ff4a02	1314
AnnaBridge	161:aa5281ff4a02	1315	/*!
AnnaBridge	161:aa5281ff4a02	1316	* @brief Initialize the USB1 PLL.
AnnaBridge	161:aa5281ff4a02	1317	*
AnnaBridge	161:aa5281ff4a02	1318	* This function initializes the USB1 PLL with specific settings
AnnaBridge	161:aa5281ff4a02	1319	*
AnnaBridge	161:aa5281ff4a02	1320	* @param config Configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1321	*/
AnnaBridge	161:aa5281ff4a02	1322	void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1323
AnnaBridge	161:aa5281ff4a02	1324	/*!
AnnaBridge	161:aa5281ff4a02	1325	* @brief Deinitialize the USB1 PLL.
AnnaBridge	161:aa5281ff4a02	1326	*/
AnnaBridge	161:aa5281ff4a02	1327	void CLOCK_DeinitUsb1Pll(void);
AnnaBridge	161:aa5281ff4a02	1328
AnnaBridge	161:aa5281ff4a02	1329	/*!
AnnaBridge	161:aa5281ff4a02	1330	* @brief Initialize the USB2 PLL.
AnnaBridge	161:aa5281ff4a02	1331	*
AnnaBridge	161:aa5281ff4a02	1332	* This function initializes the USB2 PLL with specific settings
AnnaBridge	161:aa5281ff4a02	1333	*
AnnaBridge	161:aa5281ff4a02	1334	* @param config Configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1335	*/
AnnaBridge	161:aa5281ff4a02	1336	void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1337
AnnaBridge	161:aa5281ff4a02	1338	/*!
AnnaBridge	161:aa5281ff4a02	1339	* @brief Deinitialize the USB2 PLL.
AnnaBridge	161:aa5281ff4a02	1340	*/
AnnaBridge	161:aa5281ff4a02	1341	void CLOCK_DeinitUsb2Pll(void);
AnnaBridge	161:aa5281ff4a02	1342
AnnaBridge	161:aa5281ff4a02	1343	/*!
AnnaBridge	161:aa5281ff4a02	1344	* @brief Initializes the Audio PLL.
AnnaBridge	161:aa5281ff4a02	1345	*
AnnaBridge	161:aa5281ff4a02	1346	* This function initializes the Audio PLL with specific settings
AnnaBridge	161:aa5281ff4a02	1347	*
AnnaBridge	161:aa5281ff4a02	1348	* @param config Configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1349	*/
AnnaBridge	161:aa5281ff4a02	1350	void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1351
AnnaBridge	161:aa5281ff4a02	1352	/*!
AnnaBridge	161:aa5281ff4a02	1353	* @brief De-initialize the Audio PLL.
AnnaBridge	161:aa5281ff4a02	1354	*/
AnnaBridge	161:aa5281ff4a02	1355	void CLOCK_DeinitAudioPll(void);
AnnaBridge	161:aa5281ff4a02	1356
AnnaBridge	161:aa5281ff4a02	1357	/*!
AnnaBridge	161:aa5281ff4a02	1358	* @brief Initialize the video PLL.
AnnaBridge	161:aa5281ff4a02	1359	*
AnnaBridge	161:aa5281ff4a02	1360	* This function configures the Video PLL with specific settings
AnnaBridge	161:aa5281ff4a02	1361	*
AnnaBridge	161:aa5281ff4a02	1362	* @param config configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1363	*/
AnnaBridge	161:aa5281ff4a02	1364	void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1365
AnnaBridge	161:aa5281ff4a02	1366	/*!
AnnaBridge	161:aa5281ff4a02	1367	* @brief De-initialize the Video PLL.
AnnaBridge	161:aa5281ff4a02	1368	*/
AnnaBridge	161:aa5281ff4a02	1369	void CLOCK_DeinitVideoPll(void);
AnnaBridge	161:aa5281ff4a02	1370	/*!
AnnaBridge	161:aa5281ff4a02	1371	* @brief Initialize the ENET PLL.
AnnaBridge	161:aa5281ff4a02	1372	*
AnnaBridge	161:aa5281ff4a02	1373	* This function initializes the ENET PLL with specific settings.
AnnaBridge	161:aa5281ff4a02	1374	*
AnnaBridge	161:aa5281ff4a02	1375	* @param config Configuration to set to PLL.
AnnaBridge	161:aa5281ff4a02	1376	*/
AnnaBridge	161:aa5281ff4a02	1377	void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
AnnaBridge	161:aa5281ff4a02	1378
AnnaBridge	161:aa5281ff4a02	1379	/*!
AnnaBridge	161:aa5281ff4a02	1380	* @brief Deinitialize the ENET PLL.
AnnaBridge	161:aa5281ff4a02	1381	*
AnnaBridge	161:aa5281ff4a02	1382	* This function disables the ENET PLL.
AnnaBridge	161:aa5281ff4a02	1383	*/
AnnaBridge	161:aa5281ff4a02	1384	void CLOCK_DeinitEnetPll(void);
AnnaBridge	161:aa5281ff4a02	1385
AnnaBridge	161:aa5281ff4a02	1386	/*!
AnnaBridge	161:aa5281ff4a02	1387	* @brief Get current PLL output frequency.
AnnaBridge	161:aa5281ff4a02	1388	*
AnnaBridge	161:aa5281ff4a02	1389	* This function get current output frequency of specific PLL
AnnaBridge	161:aa5281ff4a02	1390	*
AnnaBridge	161:aa5281ff4a02	1391	* @param pll pll name to get frequency.
AnnaBridge	161:aa5281ff4a02	1392	* @return The PLL output frequency in hertz.
AnnaBridge	161:aa5281ff4a02	1393	*/
AnnaBridge	161:aa5281ff4a02	1394	uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
AnnaBridge	161:aa5281ff4a02	1395
AnnaBridge	161:aa5281ff4a02	1396	/*!
AnnaBridge	161:aa5281ff4a02	1397	* @brief Initialize the System PLL PFD.
AnnaBridge	161:aa5281ff4a02	1398	*
AnnaBridge	161:aa5281ff4a02	1399	* This function initializes the System PLL PFD. During new value setting,
AnnaBridge	161:aa5281ff4a02	1400	* the clock output is disabled to prevent glitch.
AnnaBridge	161:aa5281ff4a02	1401	*
AnnaBridge	161:aa5281ff4a02	1402	* @param pfd Which PFD clock to enable.
AnnaBridge	161:aa5281ff4a02	1403	* @param pfdFrac The PFD FRAC value.
AnnaBridge	161:aa5281ff4a02	1404	* @note It is recommended that PFD settings are kept between 12-35.
AnnaBridge	161:aa5281ff4a02	1405	*/
AnnaBridge	161:aa5281ff4a02	1406	void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
AnnaBridge	161:aa5281ff4a02	1407
AnnaBridge	161:aa5281ff4a02	1408	/*!
AnnaBridge	161:aa5281ff4a02	1409	* @brief De-initialize the System PLL PFD.
AnnaBridge	161:aa5281ff4a02	1410	*
AnnaBridge	161:aa5281ff4a02	1411	* This function disables the System PLL PFD.
AnnaBridge	161:aa5281ff4a02	1412	*
AnnaBridge	161:aa5281ff4a02	1413	* @param pfd Which PFD clock to disable.
AnnaBridge	161:aa5281ff4a02	1414	*/
AnnaBridge	161:aa5281ff4a02	1415	void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
AnnaBridge	161:aa5281ff4a02	1416
AnnaBridge	161:aa5281ff4a02	1417	/*!
AnnaBridge	161:aa5281ff4a02	1418	* @brief Initialize the USB1 PLL PFD.
AnnaBridge	161:aa5281ff4a02	1419	*
AnnaBridge	161:aa5281ff4a02	1420	* This function initializes the USB1 PLL PFD. During new value setting,
AnnaBridge	161:aa5281ff4a02	1421	* the clock output is disabled to prevent glitch.
AnnaBridge	161:aa5281ff4a02	1422	*
AnnaBridge	161:aa5281ff4a02	1423	* @param pfd Which PFD clock to enable.
AnnaBridge	161:aa5281ff4a02	1424	* @param pfdFrac The PFD FRAC value.
AnnaBridge	161:aa5281ff4a02	1425	* @note It is recommended that PFD settings are kept between 12-35.
AnnaBridge	161:aa5281ff4a02	1426	*/
AnnaBridge	161:aa5281ff4a02	1427	void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
AnnaBridge	161:aa5281ff4a02	1428
AnnaBridge	161:aa5281ff4a02	1429	/*!
AnnaBridge	161:aa5281ff4a02	1430	* @brief De-initialize the USB1 PLL PFD.
AnnaBridge	161:aa5281ff4a02	1431	*
AnnaBridge	161:aa5281ff4a02	1432	* This function disables the USB1 PLL PFD.
AnnaBridge	161:aa5281ff4a02	1433	*
AnnaBridge	161:aa5281ff4a02	1434	* @param pfd Which PFD clock to disable.
AnnaBridge	161:aa5281ff4a02	1435	*/
AnnaBridge	161:aa5281ff4a02	1436	void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
AnnaBridge	161:aa5281ff4a02	1437
AnnaBridge	161:aa5281ff4a02	1438	/*!
AnnaBridge	161:aa5281ff4a02	1439	* @brief Get current System PLL PFD output frequency.
AnnaBridge	161:aa5281ff4a02	1440	*
AnnaBridge	161:aa5281ff4a02	1441	* This function get current output frequency of specific System PLL PFD
AnnaBridge	161:aa5281ff4a02	1442	*
AnnaBridge	161:aa5281ff4a02	1443	* @param pfd pfd name to get frequency.
AnnaBridge	161:aa5281ff4a02	1444	* @return The PFD output frequency in hertz.
AnnaBridge	161:aa5281ff4a02	1445	*/
AnnaBridge	161:aa5281ff4a02	1446	uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
AnnaBridge	161:aa5281ff4a02	1447
AnnaBridge	161:aa5281ff4a02	1448	/*!
AnnaBridge	161:aa5281ff4a02	1449	* @brief Get current USB1 PLL PFD output frequency.
AnnaBridge	161:aa5281ff4a02	1450	*
AnnaBridge	161:aa5281ff4a02	1451	* This function get current output frequency of specific USB1 PLL PFD
AnnaBridge	161:aa5281ff4a02	1452	*
AnnaBridge	161:aa5281ff4a02	1453	* @param pfd pfd name to get frequency.
AnnaBridge	161:aa5281ff4a02	1454	* @return The PFD output frequency in hertz.
AnnaBridge	161:aa5281ff4a02	1455	*/
AnnaBridge	161:aa5281ff4a02	1456	uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
AnnaBridge	161:aa5281ff4a02	1457
AnnaBridge	161:aa5281ff4a02	1458	/*! @brief Enable USB HS PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1459	*
AnnaBridge	161:aa5281ff4a02	1460	* This function enables the internal 480MHz USB PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1461	*
AnnaBridge	161:aa5281ff4a02	1462	* @param src USB HS PHY PLL clock source.
AnnaBridge	161:aa5281ff4a02	1463	* @param freq The frequency specified by src.
AnnaBridge	161:aa5281ff4a02	1464	* @retval true The clock is set successfully.
AnnaBridge	161:aa5281ff4a02	1465	* @retval false The clock source is invalid to get proper USB HS clock.
AnnaBridge	161:aa5281ff4a02	1466	*/
AnnaBridge	161:aa5281ff4a02	1467	bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
AnnaBridge	161:aa5281ff4a02	1468
AnnaBridge	161:aa5281ff4a02	1469	/*! @brief Disable USB HS PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1470	*
AnnaBridge	161:aa5281ff4a02	1471	* This function disables USB HS PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1472	*/
AnnaBridge	161:aa5281ff4a02	1473	void CLOCK_DisableUsbhs0PhyPllClock(void);
AnnaBridge	161:aa5281ff4a02	1474
AnnaBridge	161:aa5281ff4a02	1475	/*! @brief Enable USB HS PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1476	*
AnnaBridge	161:aa5281ff4a02	1477	* This function enables the internal 480MHz USB PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1478	*
AnnaBridge	161:aa5281ff4a02	1479	* @param src USB HS PHY PLL clock source.
AnnaBridge	161:aa5281ff4a02	1480	* @param freq The frequency specified by src.
AnnaBridge	161:aa5281ff4a02	1481	* @retval true The clock is set successfully.
AnnaBridge	161:aa5281ff4a02	1482	* @retval false The clock source is invalid to get proper USB HS clock.
AnnaBridge	161:aa5281ff4a02	1483	*/
AnnaBridge	161:aa5281ff4a02	1484	bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
AnnaBridge	161:aa5281ff4a02	1485
AnnaBridge	161:aa5281ff4a02	1486	/*! @brief Disable USB HS PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1487	*
AnnaBridge	161:aa5281ff4a02	1488	* This function disables USB HS PHY PLL clock.
AnnaBridge	161:aa5281ff4a02	1489	*/
AnnaBridge	161:aa5281ff4a02	1490	void CLOCK_DisableUsbhs1PhyPllClock(void);
AnnaBridge	161:aa5281ff4a02	1491
AnnaBridge	161:aa5281ff4a02	1492	/* @} */
AnnaBridge	161:aa5281ff4a02	1493
AnnaBridge	161:aa5281ff4a02	1494	#if defined(__cplusplus)
AnnaBridge	161:aa5281ff4a02	1495	}
AnnaBridge	161:aa5281ff4a02	1496	#endif /* __cplusplus */
AnnaBridge	161:aa5281ff4a02	1497
AnnaBridge	161:aa5281ff4a02	1498	/! @} /
AnnaBridge	161:aa5281ff4a02	1499
AnnaBridge	161:aa5281ff4a02	1500	#endif /* _FSL_CLOCK_H_ */