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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/MIMXRT1052_features.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /*
AnnaBridge 161:aa5281ff4a02 2 ** ###################################################################
AnnaBridge 161:aa5281ff4a02 3 ** Version: rev. 0.1, 2017-01-10
AnnaBridge 170:e95d10626187 4 ** Build: b180509
AnnaBridge 161:aa5281ff4a02 5 **
AnnaBridge 161:aa5281ff4a02 6 ** Abstract:
AnnaBridge 161:aa5281ff4a02 7 ** Chip specific module features.
AnnaBridge 161:aa5281ff4a02 8 **
AnnaBridge 170:e95d10626187 9 ** The Clear BSD License
AnnaBridge 161:aa5281ff4a02 10 ** Copyright 2016 Freescale Semiconductor, Inc.
AnnaBridge 170:e95d10626187 11 ** Copyright 2016-2018 NXP
AnnaBridge 170:e95d10626187 12 ** All rights reserved.
AnnaBridge 161:aa5281ff4a02 13 **
AnnaBridge 170:e95d10626187 14 ** Redistribution and use in source and binary forms, with or without
AnnaBridge 170:e95d10626187 15 ** modification, are permitted (subject to the limitations in the
AnnaBridge 170:e95d10626187 16 ** disclaimer below) provided that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 17 **
AnnaBridge 170:e95d10626187 18 ** * Redistributions of source code must retain the above copyright
AnnaBridge 170:e95d10626187 19 ** notice, this list of conditions and the following disclaimer.
AnnaBridge 170:e95d10626187 20 **
AnnaBridge 170:e95d10626187 21 ** * Redistributions in binary form must reproduce the above copyright
AnnaBridge 170:e95d10626187 22 ** notice, this list of conditions and the following disclaimer in the
AnnaBridge 170:e95d10626187 23 ** documentation and/or other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 24 **
AnnaBridge 170:e95d10626187 25 ** * Neither the name of the copyright holder nor the names of its
AnnaBridge 170:e95d10626187 26 ** contributors may be used to endorse or promote products derived from
AnnaBridge 170:e95d10626187 27 ** this software without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 28 **
AnnaBridge 170:e95d10626187 29 ** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
AnnaBridge 170:e95d10626187 30 ** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
AnnaBridge 170:e95d10626187 31 ** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 170:e95d10626187 32 ** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 170:e95d10626187 33 ** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 170:e95d10626187 34 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
AnnaBridge 170:e95d10626187 35 ** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 170:e95d10626187 36 ** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 170:e95d10626187 37 ** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
AnnaBridge 170:e95d10626187 38 ** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
AnnaBridge 170:e95d10626187 39 ** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
AnnaBridge 170:e95d10626187 40 ** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
AnnaBridge 170:e95d10626187 41 ** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 42 **
AnnaBridge 161:aa5281ff4a02 43 ** http: www.nxp.com
AnnaBridge 161:aa5281ff4a02 44 ** mail: support@nxp.com
AnnaBridge 161:aa5281ff4a02 45 **
AnnaBridge 161:aa5281ff4a02 46 ** Revisions:
AnnaBridge 161:aa5281ff4a02 47 ** - rev. 0.1 (2017-01-10)
AnnaBridge 161:aa5281ff4a02 48 ** Initial version.
AnnaBridge 161:aa5281ff4a02 49 **
AnnaBridge 161:aa5281ff4a02 50 ** ###################################################################
AnnaBridge 161:aa5281ff4a02 51 */
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 #ifndef _MIMXRT1052_FEATURES_H_
AnnaBridge 161:aa5281ff4a02 54 #define _MIMXRT1052_FEATURES_H_
AnnaBridge 161:aa5281ff4a02 55
AnnaBridge 161:aa5281ff4a02 56 /* SOC module features */
AnnaBridge 161:aa5281ff4a02 57
AnnaBridge 161:aa5281ff4a02 58 /* @brief ADC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 59 #define FSL_FEATURE_SOC_ADC_COUNT (2)
AnnaBridge 161:aa5281ff4a02 60 /* @brief AIPSTZ availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 61 #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
AnnaBridge 161:aa5281ff4a02 62 /* @brief AOI availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 63 #define FSL_FEATURE_SOC_AOI_COUNT (2)
AnnaBridge 161:aa5281ff4a02 64 /* @brief CCM availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 65 #define FSL_FEATURE_SOC_CCM_COUNT (1)
AnnaBridge 161:aa5281ff4a02 66 /* @brief CCM_ANALOG availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 67 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
AnnaBridge 161:aa5281ff4a02 68 /* @brief CMP availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 69 #define FSL_FEATURE_SOC_CMP_COUNT (4)
AnnaBridge 161:aa5281ff4a02 70 /* @brief CSI availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 71 #define FSL_FEATURE_SOC_CSI_COUNT (1)
AnnaBridge 161:aa5281ff4a02 72 /* @brief DCDC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 73 #define FSL_FEATURE_SOC_DCDC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 74 /* @brief DCP availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 75 #define FSL_FEATURE_SOC_DCP_COUNT (1)
AnnaBridge 161:aa5281ff4a02 76 /* @brief DMAMUX availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 77 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge 161:aa5281ff4a02 78 /* @brief EDMA availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 79 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
AnnaBridge 161:aa5281ff4a02 80 /* @brief ENC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 81 #define FSL_FEATURE_SOC_ENC_COUNT (4)
AnnaBridge 161:aa5281ff4a02 82 /* @brief ENET availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 83 #define FSL_FEATURE_SOC_ENET_COUNT (1)
AnnaBridge 161:aa5281ff4a02 84 /* @brief EWM availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 85 #define FSL_FEATURE_SOC_EWM_COUNT (1)
AnnaBridge 161:aa5281ff4a02 86 /* @brief FLEXCAN availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 87 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
AnnaBridge 161:aa5281ff4a02 88 /* @brief FLEXIO availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 89 #define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
AnnaBridge 161:aa5281ff4a02 90 /* @brief FLEXRAM availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 91 #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
AnnaBridge 161:aa5281ff4a02 92 /* @brief FLEXSPI availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 93 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
AnnaBridge 161:aa5281ff4a02 94 /* @brief GPC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 95 #define FSL_FEATURE_SOC_GPC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 96 /* @brief GPT availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 97 #define FSL_FEATURE_SOC_GPT_COUNT (2)
AnnaBridge 161:aa5281ff4a02 98 /* @brief I2S availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 99 #define FSL_FEATURE_SOC_I2S_COUNT (3)
AnnaBridge 161:aa5281ff4a02 100 /* @brief IGPIO availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 101 #define FSL_FEATURE_SOC_IGPIO_COUNT (5)
AnnaBridge 161:aa5281ff4a02 102 /* @brief IOMUXC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 103 #define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 104 /* @brief IOMUXC_GPR availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 105 #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
AnnaBridge 161:aa5281ff4a02 106 /* @brief IOMUXC_SNVS availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 107 #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
AnnaBridge 161:aa5281ff4a02 108 /* @brief KPP availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 109 #define FSL_FEATURE_SOC_KPP_COUNT (1)
AnnaBridge 161:aa5281ff4a02 110 /* @brief LCDIF availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 111 #define FSL_FEATURE_SOC_LCDIF_COUNT (1)
AnnaBridge 161:aa5281ff4a02 112 /* @brief LPI2C availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 113 #define FSL_FEATURE_SOC_LPI2C_COUNT (4)
AnnaBridge 161:aa5281ff4a02 114 /* @brief LPSPI availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 115 #define FSL_FEATURE_SOC_LPSPI_COUNT (4)
AnnaBridge 161:aa5281ff4a02 116 /* @brief LPUART availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 117 #define FSL_FEATURE_SOC_LPUART_COUNT (8)
AnnaBridge 161:aa5281ff4a02 118 /* @brief OCOTP availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 119 #define FSL_FEATURE_SOC_OCOTP_COUNT (1)
AnnaBridge 161:aa5281ff4a02 120 /* @brief PIT availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 121 #define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge 161:aa5281ff4a02 122 /* @brief PMU availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 123 #define FSL_FEATURE_SOC_PMU_COUNT (1)
AnnaBridge 161:aa5281ff4a02 124 /* @brief PWM availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 125 #define FSL_FEATURE_SOC_PWM_COUNT (4)
AnnaBridge 161:aa5281ff4a02 126 /* @brief PXP availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 127 #define FSL_FEATURE_SOC_PXP_COUNT (1)
AnnaBridge 161:aa5281ff4a02 128 /* @brief ROMC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 129 #define FSL_FEATURE_SOC_ROMC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 130 /* @brief SEMC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 131 #define FSL_FEATURE_SOC_SEMC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 132 /* @brief SNVS availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 133 #define FSL_FEATURE_SOC_SNVS_COUNT (1)
AnnaBridge 161:aa5281ff4a02 134 /* @brief SPDIF availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 135 #define FSL_FEATURE_SOC_SPDIF_COUNT (1)
AnnaBridge 161:aa5281ff4a02 136 /* @brief SRC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 137 #define FSL_FEATURE_SOC_SRC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 138 /* @brief TEMPMON availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 139 #define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
AnnaBridge 161:aa5281ff4a02 140 /* @brief TMR availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 141 #define FSL_FEATURE_SOC_TMR_COUNT (4)
AnnaBridge 161:aa5281ff4a02 142 /* @brief TRNG availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 143 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
AnnaBridge 161:aa5281ff4a02 144 /* @brief TSC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 145 #define FSL_FEATURE_SOC_TSC_COUNT (1)
AnnaBridge 161:aa5281ff4a02 146 /* @brief USBHS availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 147 #define FSL_FEATURE_SOC_USBHS_COUNT (2)
AnnaBridge 161:aa5281ff4a02 148 /* @brief USBNC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 149 #define FSL_FEATURE_SOC_USBNC_COUNT (2)
AnnaBridge 161:aa5281ff4a02 150 /* @brief USBPHY availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 151 #define FSL_FEATURE_SOC_USBPHY_COUNT (2)
AnnaBridge 161:aa5281ff4a02 152 /* @brief USDHC availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 153 #define FSL_FEATURE_SOC_USDHC_COUNT (2)
AnnaBridge 161:aa5281ff4a02 154 /* @brief WDOG availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 155 #define FSL_FEATURE_SOC_WDOG_COUNT (2)
AnnaBridge 161:aa5281ff4a02 156 /* @brief XBARA availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 157 #define FSL_FEATURE_SOC_XBARA_COUNT (1)
AnnaBridge 161:aa5281ff4a02 158 /* @brief XBARB availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 159 #define FSL_FEATURE_SOC_XBARB_COUNT (2)
AnnaBridge 161:aa5281ff4a02 160 /* @brief XTALOSC24M availability on the SoC. */
AnnaBridge 161:aa5281ff4a02 161 #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
AnnaBridge 161:aa5281ff4a02 162
AnnaBridge 161:aa5281ff4a02 163 /* ADC module features */
AnnaBridge 161:aa5281ff4a02 164
AnnaBridge 161:aa5281ff4a02 165 /* @brief Remove Hardware Trigger feature. */
AnnaBridge 161:aa5281ff4a02 166 #define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
AnnaBridge 161:aa5281ff4a02 167 /* @brief Remove ALT Clock selection feature. */
AnnaBridge 161:aa5281ff4a02 168 #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
AnnaBridge 161:aa5281ff4a02 169
AnnaBridge 170:e95d10626187 170 /* ADC_ETC module features */
AnnaBridge 170:e95d10626187 171
AnnaBridge 170:e95d10626187 172 /* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
AnnaBridge 170:e95d10626187 173 #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
AnnaBridge 170:e95d10626187 174
AnnaBridge 161:aa5281ff4a02 175 /* AOI module features */
AnnaBridge 161:aa5281ff4a02 176
AnnaBridge 161:aa5281ff4a02 177 /* @brief Maximum value of input mux. */
AnnaBridge 161:aa5281ff4a02 178 #define FSL_FEATURE_AOI_MODULE_INPUTS (4)
AnnaBridge 161:aa5281ff4a02 179 /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
AnnaBridge 161:aa5281ff4a02 180 #define FSL_FEATURE_AOI_EVENT_COUNT (4)
AnnaBridge 161:aa5281ff4a02 181
AnnaBridge 161:aa5281ff4a02 182 /* FLEXCAN module features */
AnnaBridge 161:aa5281ff4a02 183
AnnaBridge 161:aa5281ff4a02 184 /* @brief Message buffer size */
AnnaBridge 161:aa5281ff4a02 185 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
AnnaBridge 161:aa5281ff4a02 186 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
AnnaBridge 161:aa5281ff4a02 187 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
AnnaBridge 161:aa5281ff4a02 188 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
AnnaBridge 161:aa5281ff4a02 189 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
AnnaBridge 161:aa5281ff4a02 190 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
AnnaBridge 161:aa5281ff4a02 191 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
AnnaBridge 161:aa5281ff4a02 192 /* @brief Has extended bit timing register (register CBT). */
AnnaBridge 161:aa5281ff4a02 193 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
AnnaBridge 161:aa5281ff4a02 194 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
AnnaBridge 161:aa5281ff4a02 195 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
AnnaBridge 161:aa5281ff4a02 196 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
AnnaBridge 161:aa5281ff4a02 197 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
AnnaBridge 161:aa5281ff4a02 198 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
AnnaBridge 161:aa5281ff4a02 199 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
AnnaBridge 161:aa5281ff4a02 200 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
AnnaBridge 161:aa5281ff4a02 201 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
AnnaBridge 161:aa5281ff4a02 202 /* @brief Has extra MB interrupt or common one. */
AnnaBridge 161:aa5281ff4a02 203 #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
AnnaBridge 161:aa5281ff4a02 204
AnnaBridge 161:aa5281ff4a02 205 /* CMP module features */
AnnaBridge 161:aa5281ff4a02 206
AnnaBridge 161:aa5281ff4a02 207 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
AnnaBridge 161:aa5281ff4a02 208 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
AnnaBridge 161:aa5281ff4a02 209 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
AnnaBridge 161:aa5281ff4a02 210 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
AnnaBridge 161:aa5281ff4a02 211 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
AnnaBridge 161:aa5281ff4a02 212 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 213 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
AnnaBridge 161:aa5281ff4a02 214 #define FSL_FEATURE_CMP_HAS_DMA (1)
AnnaBridge 161:aa5281ff4a02 215 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
AnnaBridge 161:aa5281ff4a02 216 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
AnnaBridge 161:aa5281ff4a02 217 /* @brief Has DAC Test function in CMP (register DACTEST). */
AnnaBridge 161:aa5281ff4a02 218 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
AnnaBridge 161:aa5281ff4a02 219
AnnaBridge 161:aa5281ff4a02 220 /* EDMA module features */
AnnaBridge 161:aa5281ff4a02 221
AnnaBridge 161:aa5281ff4a02 222 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
AnnaBridge 161:aa5281ff4a02 223 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
AnnaBridge 161:aa5281ff4a02 224 /* @brief Total number of DMA channels on all modules. */
AnnaBridge 161:aa5281ff4a02 225 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
AnnaBridge 161:aa5281ff4a02 226 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
AnnaBridge 161:aa5281ff4a02 227 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
AnnaBridge 161:aa5281ff4a02 228 /* @brief Has DMA_Error interrupt vector. */
AnnaBridge 161:aa5281ff4a02 229 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
AnnaBridge 161:aa5281ff4a02 230 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
AnnaBridge 161:aa5281ff4a02 231 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
AnnaBridge 161:aa5281ff4a02 232
AnnaBridge 161:aa5281ff4a02 233 /* DMAMUX module features */
AnnaBridge 161:aa5281ff4a02 234
AnnaBridge 161:aa5281ff4a02 235 /* @brief Number of DMA channels (related to number of register CHCFGn). */
AnnaBridge 161:aa5281ff4a02 236 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
AnnaBridge 161:aa5281ff4a02 237 /* @brief Total number of DMA channels on all modules. */
AnnaBridge 161:aa5281ff4a02 238 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
AnnaBridge 161:aa5281ff4a02 239 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
AnnaBridge 161:aa5281ff4a02 240 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
AnnaBridge 161:aa5281ff4a02 241 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
AnnaBridge 161:aa5281ff4a02 242 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
AnnaBridge 161:aa5281ff4a02 243
AnnaBridge 161:aa5281ff4a02 244 /* ENET module features */
AnnaBridge 161:aa5281ff4a02 245
AnnaBridge 161:aa5281ff4a02 246 /* @brief Support Interrupt Coalesce */
AnnaBridge 161:aa5281ff4a02 247 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
AnnaBridge 161:aa5281ff4a02 248 /* @brief Queue Size. */
AnnaBridge 161:aa5281ff4a02 249 #define FSL_FEATURE_ENET_QUEUE (1)
AnnaBridge 161:aa5281ff4a02 250 /* @brief Has AVB Support. */
AnnaBridge 161:aa5281ff4a02 251 #define FSL_FEATURE_ENET_HAS_AVB (0)
AnnaBridge 161:aa5281ff4a02 252 /* @brief Has Timer Pulse Width control. */
AnnaBridge 161:aa5281ff4a02 253 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
AnnaBridge 161:aa5281ff4a02 254 /* @brief Has Extend MDIO Support. */
AnnaBridge 161:aa5281ff4a02 255 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
AnnaBridge 161:aa5281ff4a02 256 /* @brief Has Additional 1588 Timer Channel Interrupt. */
AnnaBridge 161:aa5281ff4a02 257 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
AnnaBridge 161:aa5281ff4a02 258
AnnaBridge 170:e95d10626187 259 /* FLEXIO module features */
AnnaBridge 170:e95d10626187 260
AnnaBridge 170:e95d10626187 261 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
AnnaBridge 170:e95d10626187 262 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
AnnaBridge 170:e95d10626187 263 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */
AnnaBridge 170:e95d10626187 264 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
AnnaBridge 170:e95d10626187 265 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
AnnaBridge 170:e95d10626187 266 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
AnnaBridge 170:e95d10626187 267 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
AnnaBridge 170:e95d10626187 268 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
AnnaBridge 170:e95d10626187 269 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
AnnaBridge 170:e95d10626187 270 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
AnnaBridge 170:e95d10626187 271 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
AnnaBridge 170:e95d10626187 272 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
AnnaBridge 170:e95d10626187 273 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
AnnaBridge 170:e95d10626187 274 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
AnnaBridge 170:e95d10626187 275 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
AnnaBridge 170:e95d10626187 276 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
AnnaBridge 170:e95d10626187 277 /* @brief Reset value of the FLEXIO_VERID register */
AnnaBridge 170:e95d10626187 278 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
AnnaBridge 170:e95d10626187 279 /* @brief Reset value of the FLEXIO_PARAM register */
AnnaBridge 170:e95d10626187 280 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
AnnaBridge 170:e95d10626187 281
AnnaBridge 161:aa5281ff4a02 282 /* FLEXRAM module features */
AnnaBridge 161:aa5281ff4a02 283
AnnaBridge 161:aa5281ff4a02 284 /* @brief Bank size */
AnnaBridge 161:aa5281ff4a02 285 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
AnnaBridge 161:aa5281ff4a02 286 /* @brief Total Bank numbers */
AnnaBridge 161:aa5281ff4a02 287 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
AnnaBridge 161:aa5281ff4a02 288
AnnaBridge 161:aa5281ff4a02 289 /* FLEXSPI module features */
AnnaBridge 161:aa5281ff4a02 290
AnnaBridge 161:aa5281ff4a02 291 /* @brief FlexSPI AHB buffer count */
AnnaBridge 161:aa5281ff4a02 292 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
AnnaBridge 161:aa5281ff4a02 293 /* @brief FlexSPI has no data learn. */
AnnaBridge 161:aa5281ff4a02 294 #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
AnnaBridge 161:aa5281ff4a02 295
AnnaBridge 161:aa5281ff4a02 296 /* GPC module features */
AnnaBridge 161:aa5281ff4a02 297
AnnaBridge 161:aa5281ff4a02 298 /* @brief Has DVFS0 Change Request. */
AnnaBridge 161:aa5281ff4a02 299 #define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0)
AnnaBridge 161:aa5281ff4a02 300 /* @brief Has GPC interrupt/event masking. */
AnnaBridge 161:aa5281ff4a02 301 #define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0)
AnnaBridge 161:aa5281ff4a02 302 /* @brief Has L2 cache power control. */
AnnaBridge 161:aa5281ff4a02 303 #define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0)
AnnaBridge 161:aa5281ff4a02 304 /* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */
AnnaBridge 161:aa5281ff4a02 305 #define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1)
AnnaBridge 161:aa5281ff4a02 306 /* @brief Has VADC power control. */
AnnaBridge 161:aa5281ff4a02 307 #define FSL_FEATURE_GPC_HAS_CNTR_VADC (0)
AnnaBridge 161:aa5281ff4a02 308 /* @brief Has Display power control. */
AnnaBridge 161:aa5281ff4a02 309 #define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0)
AnnaBridge 161:aa5281ff4a02 310 /* @brief Supports IRQ 0-31. */
AnnaBridge 161:aa5281ff4a02 311 #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
AnnaBridge 161:aa5281ff4a02 312
AnnaBridge 170:e95d10626187 313 /* IGPIO module features */
AnnaBridge 170:e95d10626187 314
AnnaBridge 170:e95d10626187 315 /* @brief Has data register set DR_SET. */
AnnaBridge 170:e95d10626187 316 #define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
AnnaBridge 170:e95d10626187 317 /* @brief Has data register clear DR_CLEAR. */
AnnaBridge 170:e95d10626187 318 #define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
AnnaBridge 170:e95d10626187 319 /* @brief Has data register toggle DR_TOGGLE. */
AnnaBridge 170:e95d10626187 320 #define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
AnnaBridge 170:e95d10626187 321
AnnaBridge 161:aa5281ff4a02 322 /* LCDIF module features */
AnnaBridge 161:aa5281ff4a02 323
AnnaBridge 161:aa5281ff4a02 324 /* @brief LCDIF does not support alpha support. */
AnnaBridge 161:aa5281ff4a02 325 #define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
AnnaBridge 161:aa5281ff4a02 326 /* @brief LCDIF does not support output reset pin to LCD panel. */
AnnaBridge 161:aa5281ff4a02 327 #define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
AnnaBridge 161:aa5281ff4a02 328 /* @brief LCDIF supports LUT. */
AnnaBridge 161:aa5281ff4a02 329 #define FSL_FEATURE_LCDIF_HAS_LUT (1)
AnnaBridge 161:aa5281ff4a02 330
AnnaBridge 161:aa5281ff4a02 331 /* LPI2C module features */
AnnaBridge 161:aa5281ff4a02 332
AnnaBridge 161:aa5281ff4a02 333 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 161:aa5281ff4a02 334 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
AnnaBridge 161:aa5281ff4a02 335 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 161:aa5281ff4a02 336 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
AnnaBridge 161:aa5281ff4a02 337
AnnaBridge 161:aa5281ff4a02 338 /* LPSPI module features */
AnnaBridge 161:aa5281ff4a02 339
AnnaBridge 161:aa5281ff4a02 340 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 161:aa5281ff4a02 341 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
AnnaBridge 161:aa5281ff4a02 342 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 161:aa5281ff4a02 343 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge 161:aa5281ff4a02 344
AnnaBridge 161:aa5281ff4a02 345 /* LPUART module features */
AnnaBridge 161:aa5281ff4a02 346
AnnaBridge 161:aa5281ff4a02 347 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge 161:aa5281ff4a02 348 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
AnnaBridge 161:aa5281ff4a02 349 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge 161:aa5281ff4a02 350 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 351 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge 161:aa5281ff4a02 352 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
AnnaBridge 161:aa5281ff4a02 353 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 161:aa5281ff4a02 354 #define FSL_FEATURE_LPUART_HAS_FIFO (1)
AnnaBridge 161:aa5281ff4a02 355 /* @brief Has 32-bit register MODIR */
AnnaBridge 161:aa5281ff4a02 356 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
AnnaBridge 161:aa5281ff4a02 357 /* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge 161:aa5281ff4a02 358 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 359 /* @brief Infrared (modulation) is supported. */
AnnaBridge 161:aa5281ff4a02 360 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 361 /* @brief 2 bits long stop bit is available. */
AnnaBridge 161:aa5281ff4a02 362 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 363 /* @brief If 10-bit mode is supported. */
AnnaBridge 161:aa5281ff4a02 364 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 365 /* @brief If 7-bit mode is supported. */
AnnaBridge 161:aa5281ff4a02 366 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 367 /* @brief Baud rate fine adjustment is available. */
AnnaBridge 161:aa5281ff4a02 368 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
AnnaBridge 161:aa5281ff4a02 369 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge 161:aa5281ff4a02 370 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 371 /* @brief Baud rate oversampling is available. */
AnnaBridge 161:aa5281ff4a02 372 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 373 /* @brief Baud rate oversampling is available. */
AnnaBridge 161:aa5281ff4a02 374 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
AnnaBridge 161:aa5281ff4a02 375 /* @brief Peripheral type. */
AnnaBridge 161:aa5281ff4a02 376 #define FSL_FEATURE_LPUART_IS_SCI (1)
AnnaBridge 161:aa5281ff4a02 377 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 161:aa5281ff4a02 378 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
AnnaBridge 161:aa5281ff4a02 379 /* @brief Maximal data width without parity bit. */
AnnaBridge 161:aa5281ff4a02 380 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
AnnaBridge 161:aa5281ff4a02 381 /* @brief Maximal data width with parity bit. */
AnnaBridge 161:aa5281ff4a02 382 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
AnnaBridge 161:aa5281ff4a02 383 /* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge 161:aa5281ff4a02 384 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
AnnaBridge 161:aa5281ff4a02 385 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge 161:aa5281ff4a02 386 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
AnnaBridge 161:aa5281ff4a02 387 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge 161:aa5281ff4a02 388 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
AnnaBridge 161:aa5281ff4a02 389 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge 161:aa5281ff4a02 390 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge 161:aa5281ff4a02 391 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge 161:aa5281ff4a02 392 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
AnnaBridge 161:aa5281ff4a02 393 /* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge 161:aa5281ff4a02 394 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
AnnaBridge 161:aa5281ff4a02 395 /* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge 161:aa5281ff4a02 396 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge 161:aa5281ff4a02 397 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge 161:aa5281ff4a02 398 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
AnnaBridge 161:aa5281ff4a02 399 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
AnnaBridge 161:aa5281ff4a02 400 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
AnnaBridge 161:aa5281ff4a02 401 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge 161:aa5281ff4a02 402 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
AnnaBridge 161:aa5281ff4a02 403 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 161:aa5281ff4a02 404 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge 161:aa5281ff4a02 405 /* @brief Has separate RX and TX interrupts. */
AnnaBridge 161:aa5281ff4a02 406 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
AnnaBridge 161:aa5281ff4a02 407 /* @brief Has LPAURT_PARAM. */
AnnaBridge 161:aa5281ff4a02 408 #define FSL_FEATURE_LPUART_HAS_PARAM (1)
AnnaBridge 161:aa5281ff4a02 409 /* @brief Has LPUART_VERID. */
AnnaBridge 161:aa5281ff4a02 410 #define FSL_FEATURE_LPUART_HAS_VERID (1)
AnnaBridge 161:aa5281ff4a02 411 /* @brief Has LPUART_GLOBAL. */
AnnaBridge 161:aa5281ff4a02 412 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
AnnaBridge 161:aa5281ff4a02 413 /* @brief Has LPUART_PINCFG. */
AnnaBridge 161:aa5281ff4a02 414 #define FSL_FEATURE_LPUART_HAS_PINCFG (1)
AnnaBridge 161:aa5281ff4a02 415
AnnaBridge 161:aa5281ff4a02 416 /* interrupt module features */
AnnaBridge 161:aa5281ff4a02 417
AnnaBridge 161:aa5281ff4a02 418 /* @brief Lowest interrupt request number. */
AnnaBridge 161:aa5281ff4a02 419 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
AnnaBridge 161:aa5281ff4a02 420 /* @brief Highest interrupt request number. */
AnnaBridge 161:aa5281ff4a02 421 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
AnnaBridge 161:aa5281ff4a02 422
AnnaBridge 161:aa5281ff4a02 423 /* OCOTP module features */
AnnaBridge 161:aa5281ff4a02 424
AnnaBridge 161:aa5281ff4a02 425 /* No feature definitions */
AnnaBridge 161:aa5281ff4a02 426
AnnaBridge 161:aa5281ff4a02 427 /* PIT module features */
AnnaBridge 161:aa5281ff4a02 428
AnnaBridge 161:aa5281ff4a02 429 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
AnnaBridge 161:aa5281ff4a02 430 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
AnnaBridge 161:aa5281ff4a02 431 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
AnnaBridge 161:aa5281ff4a02 432 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
AnnaBridge 161:aa5281ff4a02 433 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
AnnaBridge 161:aa5281ff4a02 434 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
AnnaBridge 161:aa5281ff4a02 435 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge 161:aa5281ff4a02 436 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
AnnaBridge 161:aa5281ff4a02 437 /* @brief Has timer enable control. */
AnnaBridge 161:aa5281ff4a02 438 #define FSL_FEATURE_PIT_HAS_MDIS (1)
AnnaBridge 161:aa5281ff4a02 439
AnnaBridge 161:aa5281ff4a02 440 /* PMU module features */
AnnaBridge 161:aa5281ff4a02 441
AnnaBridge 161:aa5281ff4a02 442 /* @brief PMU supports lower power control. */
AnnaBridge 161:aa5281ff4a02 443 #define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0)
AnnaBridge 161:aa5281ff4a02 444
AnnaBridge 161:aa5281ff4a02 445 /* PWM module features */
AnnaBridge 161:aa5281ff4a02 446
AnnaBridge 161:aa5281ff4a02 447 /* @brief Number of each EflexPWM module channels (outputs). */
AnnaBridge 161:aa5281ff4a02 448 #define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
AnnaBridge 161:aa5281ff4a02 449 /* @brief Number of EflexPWM module A channels (outputs). */
AnnaBridge 161:aa5281ff4a02 450 #define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
AnnaBridge 161:aa5281ff4a02 451 /* @brief Number of EflexPWM module B channels (outputs). */
AnnaBridge 161:aa5281ff4a02 452 #define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
AnnaBridge 161:aa5281ff4a02 453 /* @brief Number of EflexPWM module X channels (outputs). */
AnnaBridge 161:aa5281ff4a02 454 #define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
AnnaBridge 161:aa5281ff4a02 455 /* @brief Number of each EflexPWM module compare channels interrupts. */
AnnaBridge 161:aa5281ff4a02 456 #define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
AnnaBridge 161:aa5281ff4a02 457 /* @brief Number of each EflexPWM module reload channels interrupts. */
AnnaBridge 161:aa5281ff4a02 458 #define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
AnnaBridge 161:aa5281ff4a02 459 /* @brief Number of each EflexPWM module capture channels interrupts. */
AnnaBridge 161:aa5281ff4a02 460 #define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
AnnaBridge 161:aa5281ff4a02 461 /* @brief Number of each EflexPWM module reload error channels interrupts. */
AnnaBridge 161:aa5281ff4a02 462 #define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
AnnaBridge 161:aa5281ff4a02 463 /* @brief Number of each EflexPWM module fault channels interrupts. */
AnnaBridge 161:aa5281ff4a02 464 #define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
AnnaBridge 161:aa5281ff4a02 465 /* @brief Number of submodules in each EflexPWM module. */
AnnaBridge 161:aa5281ff4a02 466 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
AnnaBridge 161:aa5281ff4a02 467
AnnaBridge 161:aa5281ff4a02 468 /* PXP module features */
AnnaBridge 161:aa5281ff4a02 469
AnnaBridge 161:aa5281ff4a02 470 /* @brief PXP module has dither engine. */
AnnaBridge 161:aa5281ff4a02 471 #define FSL_FEATURE_PXP_HAS_DITHER (0)
AnnaBridge 161:aa5281ff4a02 472 /* @brief PXP module supports repeat run */
AnnaBridge 161:aa5281ff4a02 473 #define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
AnnaBridge 161:aa5281ff4a02 474 /* @brief PXP doesn't have CSC */
AnnaBridge 161:aa5281ff4a02 475 #define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
AnnaBridge 161:aa5281ff4a02 476 /* @brief PXP doesn't have LUT */
AnnaBridge 161:aa5281ff4a02 477 #define FSL_FEATURE_PXP_HAS_NO_LUT (1)
AnnaBridge 161:aa5281ff4a02 478
AnnaBridge 161:aa5281ff4a02 479 /* RTWDOG module features */
AnnaBridge 161:aa5281ff4a02 480
AnnaBridge 161:aa5281ff4a02 481 /* @brief Watchdog is available. */
AnnaBridge 161:aa5281ff4a02 482 #define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
AnnaBridge 161:aa5281ff4a02 483 /* @brief RTWDOG_CNT can be 32-bit written. */
AnnaBridge 161:aa5281ff4a02 484 #define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
AnnaBridge 161:aa5281ff4a02 485
AnnaBridge 161:aa5281ff4a02 486 /* SAI module features */
AnnaBridge 161:aa5281ff4a02 487
AnnaBridge 161:aa5281ff4a02 488 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
AnnaBridge 161:aa5281ff4a02 489 #define FSL_FEATURE_SAI_FIFO_COUNT (32)
AnnaBridge 161:aa5281ff4a02 490 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
AnnaBridge 161:aa5281ff4a02 491 #define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
AnnaBridge 161:aa5281ff4a02 492 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
AnnaBridge 161:aa5281ff4a02 493 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
AnnaBridge 161:aa5281ff4a02 494 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
AnnaBridge 161:aa5281ff4a02 495 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
AnnaBridge 161:aa5281ff4a02 496 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
AnnaBridge 161:aa5281ff4a02 497 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
AnnaBridge 161:aa5281ff4a02 498 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
AnnaBridge 161:aa5281ff4a02 499 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
AnnaBridge 161:aa5281ff4a02 500 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
AnnaBridge 161:aa5281ff4a02 501 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
AnnaBridge 161:aa5281ff4a02 502 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
AnnaBridge 161:aa5281ff4a02 503 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
AnnaBridge 161:aa5281ff4a02 504 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
AnnaBridge 161:aa5281ff4a02 505 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
AnnaBridge 161:aa5281ff4a02 506 /* @brief Interrupt source number */
AnnaBridge 161:aa5281ff4a02 507 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
AnnaBridge 161:aa5281ff4a02 508 /* @brief Has register of MCR. */
AnnaBridge 161:aa5281ff4a02 509 #define FSL_FEATURE_SAI_HAS_MCR (0)
AnnaBridge 161:aa5281ff4a02 510 /* @brief Has register of MDR */
AnnaBridge 161:aa5281ff4a02 511 #define FSL_FEATURE_SAI_HAS_MDR (0)
AnnaBridge 161:aa5281ff4a02 512
AnnaBridge 161:aa5281ff4a02 513 /* SNVS module features */
AnnaBridge 161:aa5281ff4a02 514
AnnaBridge 161:aa5281ff4a02 515 /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
AnnaBridge 161:aa5281ff4a02 516 #define FSL_FEATURE_SNVS_HAS_SRTC (1)
AnnaBridge 161:aa5281ff4a02 517
AnnaBridge 161:aa5281ff4a02 518 /* SRC module features */
AnnaBridge 161:aa5281ff4a02 519
AnnaBridge 161:aa5281ff4a02 520 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 521 #define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1)
AnnaBridge 161:aa5281ff4a02 522 /* @brief There is MIX_RST_STRCH bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 523 #define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0)
AnnaBridge 161:aa5281ff4a02 524 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 525 #define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1)
AnnaBridge 161:aa5281ff4a02 526 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 527 #define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0)
AnnaBridge 161:aa5281ff4a02 528 /* @brief There is CORES_DBG_RST bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 529 #define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0)
AnnaBridge 161:aa5281ff4a02 530 /* @brief There is MTSR bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 531 #define FSL_FEATURE_SRC_HAS_SCR_MTSR (0)
AnnaBridge 161:aa5281ff4a02 532 /* @brief There is CORE0_DBG_RST bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 533 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1)
AnnaBridge 161:aa5281ff4a02 534 /* @brief There is CORE0_RST bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 535 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
AnnaBridge 161:aa5281ff4a02 536 /* @brief There is LOCKUP_RST bit in SCR register. */
AnnaBridge 170:e95d10626187 537 #define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
AnnaBridge 161:aa5281ff4a02 538 /* @brief There is SWRC bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 539 #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
AnnaBridge 161:aa5281ff4a02 540 /* @brief There is EIM_RST bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 541 #define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0)
AnnaBridge 161:aa5281ff4a02 542 /* @brief There is LUEN bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 543 #define FSL_FEATURE_SRC_HAS_SCR_LUEN (0)
AnnaBridge 161:aa5281ff4a02 544 /* @brief There is no WRBC bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 545 #define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1)
AnnaBridge 161:aa5281ff4a02 546 /* @brief There is no WRE bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 547 #define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1)
AnnaBridge 161:aa5281ff4a02 548 /* @brief There is SISR register. */
AnnaBridge 161:aa5281ff4a02 549 #define FSL_FEATURE_SRC_HAS_SISR (0)
AnnaBridge 161:aa5281ff4a02 550 /* @brief There is RESET_OUT bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 551 #define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
AnnaBridge 161:aa5281ff4a02 552 /* @brief There is WDOG3_RST_B bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 553 #define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
AnnaBridge 161:aa5281ff4a02 554 /* @brief There is SW bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 555 #define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
AnnaBridge 161:aa5281ff4a02 556 /* @brief There is IPP_USER_RESET_B bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 557 #define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1)
AnnaBridge 161:aa5281ff4a02 558 /* @brief There is SNVS bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 559 #define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0)
AnnaBridge 161:aa5281ff4a02 560 /* @brief There is CSU_RESET_B bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 561 #define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1)
AnnaBridge 161:aa5281ff4a02 562 /* @brief There is LOCKUP bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 563 #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0)
AnnaBridge 161:aa5281ff4a02 564 /* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 565 #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1)
AnnaBridge 161:aa5281ff4a02 566 /* @brief There is POR bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 567 #define FSL_FEATURE_SRC_HAS_SRSR_POR (0)
AnnaBridge 161:aa5281ff4a02 568 /* @brief There is IPP_RESET_B bit in SRSR register. */
AnnaBridge 161:aa5281ff4a02 569 #define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1)
AnnaBridge 161:aa5281ff4a02 570 /* @brief There is no WBI bit in SCR register. */
AnnaBridge 161:aa5281ff4a02 571 #define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1)
AnnaBridge 161:aa5281ff4a02 572
AnnaBridge 161:aa5281ff4a02 573 /* SCB module features */
AnnaBridge 161:aa5281ff4a02 574
AnnaBridge 161:aa5281ff4a02 575 /* @brief L1 ICACHE line size in byte. */
AnnaBridge 161:aa5281ff4a02 576 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
AnnaBridge 161:aa5281ff4a02 577 /* @brief L1 DCACHE line size in byte. */
AnnaBridge 161:aa5281ff4a02 578 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
AnnaBridge 161:aa5281ff4a02 579
AnnaBridge 161:aa5281ff4a02 580 /* TRNG module features */
AnnaBridge 161:aa5281ff4a02 581
AnnaBridge 161:aa5281ff4a02 582 /* @brief TRNG has no TRNG_ACC bitfield. */
AnnaBridge 161:aa5281ff4a02 583 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
AnnaBridge 161:aa5281ff4a02 584
AnnaBridge 161:aa5281ff4a02 585 /* USBHS module features */
AnnaBridge 161:aa5281ff4a02 586
AnnaBridge 161:aa5281ff4a02 587 /* @brief EHCI module instance count */
AnnaBridge 161:aa5281ff4a02 588 #define FSL_FEATURE_USBHS_EHCI_COUNT (2)
AnnaBridge 161:aa5281ff4a02 589 /* @brief Number of endpoints supported */
AnnaBridge 161:aa5281ff4a02 590 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
AnnaBridge 161:aa5281ff4a02 591
AnnaBridge 161:aa5281ff4a02 592 /* USDHC module features */
AnnaBridge 161:aa5281ff4a02 593
AnnaBridge 161:aa5281ff4a02 594 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
AnnaBridge 161:aa5281ff4a02 595 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
AnnaBridge 161:aa5281ff4a02 596 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
AnnaBridge 161:aa5281ff4a02 597 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
AnnaBridge 161:aa5281ff4a02 598 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
AnnaBridge 161:aa5281ff4a02 599 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
AnnaBridge 161:aa5281ff4a02 600 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
AnnaBridge 161:aa5281ff4a02 601 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
AnnaBridge 161:aa5281ff4a02 602
AnnaBridge 161:aa5281ff4a02 603 /* XBARA module features */
AnnaBridge 161:aa5281ff4a02 604
AnnaBridge 161:aa5281ff4a02 605 /* @brief DMA_CH_MUX_REQ_30. */
AnnaBridge 161:aa5281ff4a02 606 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
AnnaBridge 161:aa5281ff4a02 607 /* @brief DMA_CH_MUX_REQ_31. */
AnnaBridge 161:aa5281ff4a02 608 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
AnnaBridge 161:aa5281ff4a02 609 /* @brief DMA_CH_MUX_REQ_94. */
AnnaBridge 161:aa5281ff4a02 610 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
AnnaBridge 161:aa5281ff4a02 611 /* @brief DMA_CH_MUX_REQ_95. */
AnnaBridge 161:aa5281ff4a02 612 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
AnnaBridge 161:aa5281ff4a02 613
AnnaBridge 161:aa5281ff4a02 614 #endif /* _MIMXRT1052_FEATURES_H_ */
AnnaBridge 161:aa5281ff4a02 615