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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/tmr_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the Timer Peripheral
AnnaBridge 171:3a7713b1edbc 4 * Module.
AnnaBridge 171:3a7713b1edbc 5 */
AnnaBridge 171:3a7713b1edbc 6 /* *****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24675 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_TMR_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_TMR_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 ///@cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 ///@endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @ingroup tmr
AnnaBridge 171:3a7713b1edbc 73 * @defgroup tmr_registers Timer Registers
AnnaBridge 171:3a7713b1edbc 74 * @brief Hardware interface definitions for the Timer Peripheral.
AnnaBridge 171:3a7713b1edbc 75 * @details Definitions for the Hardware Access Layer of the Timer
AnnaBridge 171:3a7713b1edbc 76 * Peripherals. Includes:
AnnaBridge 171:3a7713b1edbc 77 * - Registers
AnnaBridge 171:3a7713b1edbc 78 * - Fields
AnnaBridge 171:3a7713b1edbc 79 * - Positions
AnnaBridge 171:3a7713b1edbc 80 * - Values
AnnaBridge 171:3a7713b1edbc 81 * - Masks
AnnaBridge 171:3a7713b1edbc 82 * @{
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /* **** Definitions **** */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /**
AnnaBridge 171:3a7713b1edbc 88 * Structure type to access the Timer Registers, see #MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure.
AnnaBridge 171:3a7713b1edbc 89 */
AnnaBridge 171:3a7713b1edbc 90 typedef struct {
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> - TMR_CTRL Register - Timer Control Register */
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t count32; /**< <tt>\b 0x0004</tt> - TMR_COUNT32 Register - Timer [32 bit] Current Count Value */
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t term_cnt32; /**< <tt>\b 0x0008</tt> - TMR_TERM_CNT32 Register - Timer [32 bit] Terminal Count Setting */
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t pwm_cap32; /**< <tt>\b 0x000C</tt> - TMR_PWM_CAP32 Register - Timer [32 bit] PWM Compare Setting or Capture/Measure Value */
AnnaBridge 171:3a7713b1edbc 95 __IO uint32_t count16_0; /**< <tt>\b 0x0010</tt> - TMR_COUNT16_0 Register - Timer [16 bit] Current Count Value, 16-bit Timer 0 */
AnnaBridge 171:3a7713b1edbc 96 __IO uint32_t term_cnt16_0; /**< <tt>\b 0x0014</tt> - TMR_TERM_CNT16_0 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */
AnnaBridge 171:3a7713b1edbc 97 __IO uint32_t count16_1; /**< <tt>\b 0x0018</tt> - TMR_COUNT16_1 Register - Timer [16 bit] Current Count Value, 16-bit Timer 1 */
AnnaBridge 171:3a7713b1edbc 98 __IO uint32_t term_cnt16_1; /**< <tt>\b 0x001C</tt> - TMR_TERM_CNT16_1 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */
AnnaBridge 171:3a7713b1edbc 99 __IO uint32_t intfl; /**< <tt>\b 0x0020</tt> - TMR_INTFL Register - Timer Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 100 __IO uint32_t inten; /**< <tt>\b 0x0024</tt> - TMR_INTEN Register - Timer Interrupt Enable/Disable Settings */
AnnaBridge 171:3a7713b1edbc 101 } mxc_tmr_regs_t;
AnnaBridge 171:3a7713b1edbc 102 /**@} end of group tmr_registers. */
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 /*
AnnaBridge 171:3a7713b1edbc 106 Register offsets for module TMR.
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108 /**
AnnaBridge 171:3a7713b1edbc 109 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 110 * @defgroup TMR_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 111 * @brief Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_TMR_INSTANCES for the \MXIM_Device. Use #MXC_TMR_GET_BASE(i) to get the base address for a specific timer number.
AnnaBridge 171:3a7713b1edbc 112 * @{
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114 #define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from TMR[n] Base Address: TMR_CTRL : <tt>\b 0x0x0000 </tt> */
AnnaBridge 171:3a7713b1edbc 115 #define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) /**< Offset from TMR[n] Base Address: TMR_COUNT32 : <tt>\b 0x0x0004 </tt> */
AnnaBridge 171:3a7713b1edbc 116 #define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT32 : <tt>\b 0x0x0008 </tt> */
AnnaBridge 171:3a7713b1edbc 117 #define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) /**< Offset from TMR[n] Base Address: TMR_PWM_CAP32 : <tt>\b 0x0x000C </tt> */
AnnaBridge 171:3a7713b1edbc 118 #define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_0 : <tt>\b 0x0x0010 </tt> */
AnnaBridge 171:3a7713b1edbc 119 #define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_0 : <tt>\b 0x0x0014 </tt> */
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_1 : <tt>\b 0x0x0018 </tt> */
AnnaBridge 171:3a7713b1edbc 121 #define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_1 : <tt>\b 0x0x001C </tt> */
AnnaBridge 171:3a7713b1edbc 122 #define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) /**< Offset from TMR[n] Base Address: TMR_INTFL : <tt>\b 0x0x0020 </tt> */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) /**< Offset from TMR[n] Base Address: TMR_INTEN : <tt>\b 0x0x0024 </tt> */
AnnaBridge 171:3a7713b1edbc 124 /**@} end of group TMR_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /**
AnnaBridge 171:3a7713b1edbc 127 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 128 * @defgroup TMR_CTRL_Register TMR_CTRL Register
AnnaBridge 171:3a7713b1edbc 129 * @brief Field Positions and Bit Masks for the TMR_CTRL register
AnnaBridge 171:3a7713b1edbc 130 * @{
AnnaBridge 171:3a7713b1edbc 131 */
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_TMR_CTRL_MODE_POS 0 /**< MODE Field Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) /**< MODE Field Shifted Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_TMR_CTRL_TMR2X16_POS 3 /**< TMR2X16 Field Position */
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) /**< TMR2X16 Field Shifted Position */
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_TMR_CTRL_PRESCALE_POS 4 /**< PRESCALE Field Position */
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< PRESCALE Field Shifted Position */
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_TMR_CTRL_POLARITY_POS 8 /**< POLARITY Field Position */
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) /**< POLARITY Field Shifted Position */
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_TMR_CTRL_ENABLE0_POS 12 /**< ENABLE0 Field Position */
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) /**< ENABLE0 Field Shifted Position */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_TMR_CTRL_ENABLE1_POS 13 /**< ENABLE1 Field Position */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) /**< ENABLE1 Field Shifted Position */
AnnaBridge 171:3a7713b1edbc 144 /**@} end of group TMR_CTRL */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 /**
AnnaBridge 171:3a7713b1edbc 147 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 148 * @defgroup TMR_COUNT16_0_Register TMR_COUNT16_0 Register
AnnaBridge 171:3a7713b1edbc 149 * @brief Field Positions and Bit Masks for the TMR_COUNT16_0 register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
AnnaBridge 171:3a7713b1edbc 150 * @{
AnnaBridge 171:3a7713b1edbc 151 */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_TMR_COUNT16_0_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 154 /**@} end of group TMR_COUNT16_0 */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /**
AnnaBridge 171:3a7713b1edbc 157 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 158 * @defgroup TMR_TERM_CNT16_0_Register TMR_TERM_CNT16_0 Register
AnnaBridge 171:3a7713b1edbc 159 * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. This field indicates the termination count value for the <b> 16-bit Timer 0 </b> instance if the Timer is set to 2 16-bit Timers.
AnnaBridge 171:3a7713b1edbc 160 * @{
AnnaBridge 171:3a7713b1edbc 161 */
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 164 /**@} end of group TMR_TERM_CNT16_0 */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /**
AnnaBridge 171:3a7713b1edbc 167 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 168 * @defgroup TMR_COUNT16_1__Register _TMR_COUNT16_1_ Register
AnnaBridge 171:3a7713b1edbc 169 * @brief Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
AnnaBridge 171:3a7713b1edbc 170 * @{
AnnaBridge 171:3a7713b1edbc 171 */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_TMR_COUNT16_1_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 174 /**@} end of group TMR_COUNT16_1 */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 178 * @defgroup TMR_TERM_CNT16_1_Register TMR_TERM_CNT16_1 Register
AnnaBridge 171:3a7713b1edbc 179 * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. This field indicates the termination count value for the <b> 16-bit Timer 1 </b> instance if the Timer is set to 2 16-bit Timers.
AnnaBridge 171:3a7713b1edbc 180 * @{
AnnaBridge 171:3a7713b1edbc 181 */
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
AnnaBridge 171:3a7713b1edbc 184 /**@} end of group TMR_TERM_CNT16_1 */
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 188 * @defgroup TMR_INTFL_Register TMR_INTFL Register
AnnaBridge 171:3a7713b1edbc 189 * @brief Field Positions and Bit Masks for the TMR_INTFL register. This register includes the interrupt flags for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
AnnaBridge 171:3a7713b1edbc 190 * @{
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_TMR_INTFL_TIMER0_POS 0 /**< TIMER0 Interrupt Flag Field Position */
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) /**< TIMER0 Interrupt Flag Shifted Field */
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_TMR_INTFL_TIMER1_POS 1 /**< TIMER1 Interrupt Flag Field Position */
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) /**< TIMER1 Interrupt Flag Shifted Field */
AnnaBridge 171:3a7713b1edbc 196 /**@} end of group TMR_INTFL */
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /**
AnnaBridge 171:3a7713b1edbc 199 * @ingroup tmr_registers
AnnaBridge 171:3a7713b1edbc 200 * @defgroup TMR_INTEN_Register TMR_INTEN Register
AnnaBridge 171:3a7713b1edbc 201 * @brief Field Positions and Bit Masks for the TMR_INTEN register. This register includes the interrupt enable bits for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
AnnaBridge 171:3a7713b1edbc 202 * @{
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_TMR_INTEN_TIMER0_POS 0 /**< TIMER0 Interrupt Enable Field Position */
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) /**< TIMER0 Interrupt Enable Shifted Field */
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_TMR_INTEN_TIMER1_POS 1 /**< TIMER1 Interrupt Enable Field Position */
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) /**< TIMER1 Interrupt Enable Shifted Field */
AnnaBridge 171:3a7713b1edbc 208 /**@} end of group TMR_INTEN */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /*
AnnaBridge 171:3a7713b1edbc 213 Field values and shifted values for module TMR.
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215 /**
AnnaBridge 171:3a7713b1edbc 216 * @ingroup TMR_CTRL_Register
AnnaBridge 171:3a7713b1edbc 217 * @defgroup TMR_CTRL_field_values TMR_CTRL Field and Shifted Field Values
AnnaBridge 171:3a7713b1edbc 218 * @brief Field values and Shifted Field values for the TMR_CTRL register. Shifted field values are field values shifted to the loacation of the field in the register.
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220 /**
AnnaBridge 171:3a7713b1edbc 221 * @ingroup TMR_CTRL_field_values
AnnaBridge 171:3a7713b1edbc 222 * @defgroup TMR_CTRL_MODE_Field Mode Field for 32-bit Timer Operation.
AnnaBridge 171:3a7713b1edbc 223 * @brief This field is used to select the timer mode for a 32-bit timer.
AnnaBridge 171:3a7713b1edbc 224 * @details The mode field is used to set the 32-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
AnnaBridge 171:3a7713b1edbc 225 * @note If the 32-bit timer is set to operate as 2 16-bit timers, see @ref TMR_CTRL_MODE_16_Field.
AnnaBridge 171:3a7713b1edbc 226 * @{
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228 #define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) /**< Field value to set a 32-bit Timer to 1-Shot Timer mode. */
AnnaBridge 171:3a7713b1edbc 229 #define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) /**< Field value to set a 32-bit Timer to continuous mode. */
AnnaBridge 171:3a7713b1edbc 230 #define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) /**< Field value to set a 32-bit Timer to counter mode. */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) /**< Field value to set a 32-bit Timer to pulse-width mode. */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) /**< Field value to set a 32-bit Timer to capture mode. */
AnnaBridge 171:3a7713b1edbc 233 #define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) /**< Field value to set a 32-bit Timer to compare mode. */
AnnaBridge 171:3a7713b1edbc 234 #define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) /**< Field value to set a 32-bit Timer to gated mode. */
AnnaBridge 171:3a7713b1edbc 235 #define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) /**< Field value to set a 32-bit Timer to measurement mode. */
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 #define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to 1-Shot Timer mode. */
AnnaBridge 171:3a7713b1edbc 238 #define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to continuous mode. */
AnnaBridge 171:3a7713b1edbc 239 #define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to counter mode. */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to pulse-width mode. */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to capture mode. */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to compare mode. */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to gated mode. */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to measurement mode. */
AnnaBridge 171:3a7713b1edbc 245 /**@} end of group TMR_CTRL_MODE_Field */
AnnaBridge 171:3a7713b1edbc 246 /**
AnnaBridge 171:3a7713b1edbc 247 * @ingroup TMR_CTRL_field_values
AnnaBridge 171:3a7713b1edbc 248 * @defgroup TMR_CTRL_MODE_16_Field 16-bit Timer Mode Field and Shifted Field Values.
AnnaBridge 171:3a7713b1edbc 249 * @brief This field is used to select the timer mode when the timer is set to a dual 16-bit timer. The mode field is used to set the 16-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
AnnaBridge 171:3a7713b1edbc 250 * @{
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252 #define MXC_F_TMR_CTRL_MODE_16_0_POS 0
AnnaBridge 171:3a7713b1edbc 253 #define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS))
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_TMR_CTRL_MODE_16_1_POS 1
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS))
AnnaBridge 171:3a7713b1edbc 257 /**@} end of group TMR_CTRL_MODE_16_Field */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @ingroup TMR_CTRL_field_values
AnnaBridge 171:3a7713b1edbc 261 * @defgroup TMR_CTRL_PRESCALE_Field Prescale Divide Selection Field and Shifted Field Values.
AnnaBridge 171:3a7713b1edbc 262 * @brief Timer Clock Prescaler divide values and shifted values. The Prescale Divide field is used to scale the timer instance peripheral clock by the specified value.
AnnaBridge 171:3a7713b1edbc 263 * @{
AnnaBridge 171:3a7713b1edbc 264 */
AnnaBridge 171:3a7713b1edbc 265 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
AnnaBridge 171:3a7713b1edbc 267 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
AnnaBridge 171:3a7713b1edbc 269 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16\f$ */
AnnaBridge 171:3a7713b1edbc 270 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
AnnaBridge 171:3a7713b1edbc 271 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
AnnaBridge 171:3a7713b1edbc 272 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
AnnaBridge 171:3a7713b1edbc 273 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
AnnaBridge 171:3a7713b1edbc 274 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
AnnaBridge 171:3a7713b1edbc 275 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
AnnaBridge 171:3a7713b1edbc 276 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
AnnaBridge 171:3a7713b1edbc 277 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
AnnaBridge 171:3a7713b1edbc 280 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
AnnaBridge 171:3a7713b1edbc 281 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
AnnaBridge 171:3a7713b1edbc 283 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16 \f$ */
AnnaBridge 171:3a7713b1edbc 284 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
AnnaBridge 171:3a7713b1edbc 285 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
AnnaBridge 171:3a7713b1edbc 287 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
AnnaBridge 171:3a7713b1edbc 288 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
AnnaBridge 171:3a7713b1edbc 289 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
AnnaBridge 171:3a7713b1edbc 290 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
AnnaBridge 171:3a7713b1edbc 291 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
AnnaBridge 171:3a7713b1edbc 292 /**@} end of group TMR_CTRL_PRESCALE_Field */
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /*
AnnaBridge 171:3a7713b1edbc 296 * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module
AnnaBridge 171:3a7713b1edbc 297 * is in dual 16-bit timer mode.
AnnaBridge 171:3a7713b1edbc 298 */
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 303 }
AnnaBridge 171:3a7713b1edbc 304 #endif
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 #endif /* _MXC_TMR_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 307