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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/pmu_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the PMU Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24667 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_PMU_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_PMU_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 49 extern "C" {
AnnaBridge 171:3a7713b1edbc 50 #endif
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 ///@cond
AnnaBridge 171:3a7713b1edbc 53 /*
AnnaBridge 171:3a7713b1edbc 54 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 57 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 58 #endif
AnnaBridge 171:3a7713b1edbc 59 #ifndef __I
AnnaBridge 171:3a7713b1edbc 60 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 61 #endif
AnnaBridge 171:3a7713b1edbc 62 #ifndef __O
AnnaBridge 171:3a7713b1edbc 63 #define __O volatile
AnnaBridge 171:3a7713b1edbc 64 #endif
AnnaBridge 171:3a7713b1edbc 65 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 66 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 67 #endif
AnnaBridge 171:3a7713b1edbc 68 ///@endcond
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 /*
AnnaBridge 171:3a7713b1edbc 71 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 171:3a7713b1edbc 72 access to each register in module.
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74 /**
AnnaBridge 171:3a7713b1edbc 75 * @ingroup pmuGroup
AnnaBridge 171:3a7713b1edbc 76 * @defgroup pmu_registers Registers
AnnaBridge 171:3a7713b1edbc 77 * @brief Registers, Bit Masks and Bit Positions for the PMU Module.
AnnaBridge 171:3a7713b1edbc 78 * @{
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 /**
AnnaBridge 171:3a7713b1edbc 81 * Structure type for the PMU Registers
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t dscadr; /**< <tt>\b 0x0000:</tt> PMU Channel Next Descriptor Address */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t cfg; /**< <tt>\b 0x0004:</tt> PMU Channel Configuration */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t loop; /**< <tt>\b 0x0008:</tt> PMU Channel Loop Counters */
AnnaBridge 171:3a7713b1edbc 87 __RO uint32_t rsv00C[5]; /**< <tt>\b 0x000C-0x001C:</tt> RESERVED */
AnnaBridge 171:3a7713b1edbc 88 } mxc_pmu_regs_t;
AnnaBridge 171:3a7713b1edbc 89 /**@} end of group pmu_registers */
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /*
AnnaBridge 171:3a7713b1edbc 92 Register offsets for module PMU.
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94 /**
AnnaBridge 171:3a7713b1edbc 95 * @ingroup pmu_registers
AnnaBridge 171:3a7713b1edbc 96 * @defgroup PMU_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 97 * @brief PMU Register Offsets from the PMU Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 98 * @{
AnnaBridge 171:3a7713b1edbc 99 */
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) /**< Offset from the PMU Base Address: <tt>\b 0x0000</tt>*/
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) /**< Offset from the PMU Base Address: <tt>\b 0x0004</tt>*/
AnnaBridge 171:3a7713b1edbc 102 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PMU Base Address: <tt>\b 0x0008</tt>*/
AnnaBridge 171:3a7713b1edbc 103 /**@} end of group PMU_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 /*
AnnaBridge 171:3a7713b1edbc 106 Field positions and masks for module PMU.
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108 ///@cond
AnnaBridge 171:3a7713b1edbc 109 #define MXC_F_PMU_CFG_ENABLE_POS 0
AnnaBridge 171:3a7713b1edbc 110 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_PMU_CFG_MANUAL_POS 3
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_PMU_CFG_TO_STAT_POS 6
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_PMU_CFG_TO_SEL_POS 11
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_PMU_CFG_PS_SEL_POS 14
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_PMU_CFG_INT_EN_POS 17
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /*
AnnaBridge 171:3a7713b1edbc 136 Field values
AnnaBridge 171:3a7713b1edbc 137 */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 #define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL))
AnnaBridge 171:3a7713b1edbc 140 #define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL))
AnnaBridge 171:3a7713b1edbc 141 #define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL))
AnnaBridge 171:3a7713b1edbc 142 #define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL))
AnnaBridge 171:3a7713b1edbc 143 #define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL))
AnnaBridge 171:3a7713b1edbc 144 #define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL))
AnnaBridge 171:3a7713b1edbc 145 #define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL))
AnnaBridge 171:3a7713b1edbc 146 #define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL))
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 #define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL))
AnnaBridge 171:3a7713b1edbc 149 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL))
AnnaBridge 171:3a7713b1edbc 150 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL))
AnnaBridge 171:3a7713b1edbc 151 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL))
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /* Op codes */
AnnaBridge 171:3a7713b1edbc 154 #define PMU_MOVE_OP 0
AnnaBridge 171:3a7713b1edbc 155 #define PMU_WRITE_OP 1
AnnaBridge 171:3a7713b1edbc 156 #define PMU_WAIT_OP 2
AnnaBridge 171:3a7713b1edbc 157 #define PMU_JUMP_OP 3
AnnaBridge 171:3a7713b1edbc 158 #define PMU_LOOP_OP 4
AnnaBridge 171:3a7713b1edbc 159 #define PMU_POLL_OP 5
AnnaBridge 171:3a7713b1edbc 160 #define PMU_BRANCH_OP 6
AnnaBridge 171:3a7713b1edbc 161 #define PMU_TRANSFER_OP 7
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /* Bit values used in all decroptiors */
AnnaBridge 171:3a7713b1edbc 164 #define PMU_NO_INTERRUPT 0 /**< Interrupt flag is NOT set at end of channel execution */
AnnaBridge 171:3a7713b1edbc 165 #define PMU_INTERRUPT 1 /**< Interrupt flag is set at end of channel execution */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 #define PMU_NO_STOP 0 /**< Do not stop channel after this descriptor ends */
AnnaBridge 171:3a7713b1edbc 168 #define PMU_STOP 1 /**< Halt PMU channel after this descriptor ends */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /* Interrupt and Stop bit positions */
AnnaBridge 171:3a7713b1edbc 171 #define PMU_INT_POS 3
AnnaBridge 171:3a7713b1edbc 172 #define PMU_STOP_POS 4
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 /* MOVE descriptor bit values */
AnnaBridge 171:3a7713b1edbc 175 #define PMU_MOVE_READ_8_BIT 0 /**< Read size = 8 */
AnnaBridge 171:3a7713b1edbc 176 #define PMU_MOVE_READ_16_BIT 1 /**< Read size = 16 */
AnnaBridge 171:3a7713b1edbc 177 #define PMU_MOVE_READ_32_BIT 2 /**< Read size = 32 */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 #define PMU_MOVE_READ_NO_INC 0 /**< read address not incremented */
AnnaBridge 171:3a7713b1edbc 180 #define PMU_MOVE_READ_INC 1 /**< Auto-Increment read address */
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 #define PMU_MOVE_WRITE_8_BIT 0 /**< Write Size = 8 */
AnnaBridge 171:3a7713b1edbc 183 #define PMU_MOVE_WRITE_16_BIT 1 /**< Write Size = 16 */
AnnaBridge 171:3a7713b1edbc 184 #define PMU_MOVE_WRITE_32_BIT 2 /**< Write Size = 32 */
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 #define PMU_MOVE_WRITE_NO_INC 0 /**< Write address not incremented */
AnnaBridge 171:3a7713b1edbc 187 #define PMU_MOVE_WRITE_INC 1 /**< Auto_Increment write address */
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 #define PMU_MOVE_NO_CONT 0 /**< MOVE does not rely on previous MOVE */
AnnaBridge 171:3a7713b1edbc 190 #define PMU_MOVE_CONT 1 /**< MOVE continues from read/write address and INC values defined in previous MOVE */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 /* MOVE bit positions */
AnnaBridge 171:3a7713b1edbc 193 #define PMU_MOVE_READS_POS 5
AnnaBridge 171:3a7713b1edbc 194 #define PMU_MOVE_READI_POS 7
AnnaBridge 171:3a7713b1edbc 195 #define PMU_MOVE_WRITES_POS 8
AnnaBridge 171:3a7713b1edbc 196 #define PMU_MOVE_WRITEI_POS 10
AnnaBridge 171:3a7713b1edbc 197 #define PMU_MOVE_CONT_POS 11
AnnaBridge 171:3a7713b1edbc 198 #define PMU_MOVE_LEN_POS 12
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /* WRITE descriptor bit values */
AnnaBridge 171:3a7713b1edbc 201 #define PMU_WRITE_MASKED_WRITE_VALUE 0 /**< Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */
AnnaBridge 171:3a7713b1edbc 202 #define PMU_WRITE_PLUS_1 1 /**< Value = READ_VALUE + 1 */
AnnaBridge 171:3a7713b1edbc 203 #define PMU_WRITE_MINUS_1 2 /**< Value = READ_VALUE - 1 */
AnnaBridge 171:3a7713b1edbc 204 #define PMU_WRITE_SHIFT_RT_1 3 /**< Value = READ_VALUE >> 1 */
AnnaBridge 171:3a7713b1edbc 205 #define PMU_WRITE_SHIFT_LT_1 4 /**< Value = READ_VALUE << 1 */
AnnaBridge 171:3a7713b1edbc 206 #define PMU_WRITE_ROTATE_RT_1 5 /**< Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */
AnnaBridge 171:3a7713b1edbc 207 #define PMU_WRITE_ROTATE_LT_1 6 /**< Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */
AnnaBridge 171:3a7713b1edbc 208 #define PMU_WRITE_NOT_READ_VAL 7 /**< Value = ~READ_VALUE */
AnnaBridge 171:3a7713b1edbc 209 #define PMU_WRITE_XOR_MASK 8 /**< Value = READ_VALUE XOR WRITE_MASK */
AnnaBridge 171:3a7713b1edbc 210 #define PMU_WRITE_OR_MASK 9 /**< Value = READ_VALUE | WRITE_MASK */
AnnaBridge 171:3a7713b1edbc 211 #define PMU_WRITE_AND_MASK 10 /**< Value = READ_VALUE & WRITE_MASK */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /* WRITE bit positions */
AnnaBridge 171:3a7713b1edbc 214 #define PMU_WRITE_METHOD_POS 8
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /* WAIT descriptor bit values */
AnnaBridge 171:3a7713b1edbc 217 #define PMU_WAIT_SEL_0 0 /**< Select the interrupt source */
AnnaBridge 171:3a7713b1edbc 218 #define PMU_WAIT_SEL_1 1
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /* WAIT bit positions */
AnnaBridge 171:3a7713b1edbc 221 #define PMU_WAIT_WAIT_POS 5
AnnaBridge 171:3a7713b1edbc 222 #define PMU_WAIT_SEL_POS 6
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /* LOOP descriptor bit values */
AnnaBridge 171:3a7713b1edbc 225 #define PMU_LOOP_SEL_COUNTER0 0 /**< select Counter0 to count down from */
AnnaBridge 171:3a7713b1edbc 226 #define PMU_LOOP_SEL_COUNTER1 1 /**< select Counter1 to count down from */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 /* LOOP bit positions */
AnnaBridge 171:3a7713b1edbc 229 #define PMU_LOOP_SEL_COUNTER_POS 5
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /* POLL descriptor bit values */
AnnaBridge 171:3a7713b1edbc 232 #define PMU_POLL_OR 0 /**< polling ends when at least one mask bit matches expected data */
AnnaBridge 171:3a7713b1edbc 233 #define PMU_POLL_AND 1 /**< polling ends when all mask bits matches expected data */
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 /* POLL bit positions */
AnnaBridge 171:3a7713b1edbc 236 #define PMU_POLL_AND_POS 7
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 /* BRANCH descriptor bit values */
AnnaBridge 171:3a7713b1edbc 239 #define PMU_BRANCH_OR 0 /**< branch when any mask bit = or != expected data (based on = or != branch type) */
AnnaBridge 171:3a7713b1edbc 240 #define PMU_BRANCH_AND 1 /**< branch when all mask bit = or != expected data (based on = or != branch type) */
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 #define PMU_BRANCH_TYPE_NOT_EQUAL 0 /**< Branch when polled data != expected data */
AnnaBridge 171:3a7713b1edbc 243 #define PMU_BRANCH_TYPE_EQUAL 1 /**< Branch when polled data = expected data */
AnnaBridge 171:3a7713b1edbc 244 #define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /**< Branch when polled data <= expected data */
AnnaBridge 171:3a7713b1edbc 245 #define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /**< Branch when polled data >= expected data */
AnnaBridge 171:3a7713b1edbc 246 #define PMU_BRANCH_TYPE_LESSER 4 /**< Branch when polled data < expected data */
AnnaBridge 171:3a7713b1edbc 247 #define PMU_BRANCH_TYPE_GREATER 5 /**< Branch when polled data > expected data */
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /* BRANCH bit positions */
AnnaBridge 171:3a7713b1edbc 250 #define PMU_BRANCH_AND_POS 7
AnnaBridge 171:3a7713b1edbc 251 #define PMU_BRANCH_TYPE_POS 8
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /* TRANSFER descriptor bit values */
AnnaBridge 171:3a7713b1edbc 254 #define PMU_TX_READ_8_BIT 0 /**< Read size = 8 */
AnnaBridge 171:3a7713b1edbc 255 #define PMU_TX_READ_16_BIT 1 /**< Read size = 16 */
AnnaBridge 171:3a7713b1edbc 256 #define PMU_TX_READ_32_BIT 2 /**< Read size = 32 */
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 #define PMU_TX_READ_NO_INC 0 /**< read address not incremented */
AnnaBridge 171:3a7713b1edbc 259 #define PMU_TX_READ_INC 1 /**< Auto-Increment read address */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 #define PMU_TX_WRITE_8_BIT 0 /**< Write Size = 8 */
AnnaBridge 171:3a7713b1edbc 262 #define PMU_TX_WRITE_16_BIT 1 /**< Write Size = 16 */
AnnaBridge 171:3a7713b1edbc 263 #define PMU_TX_WRITE_32_BIT 2 /**< Write Size = 32 */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 #define PMU_TX_WRITE_NO_INC 0 /**< Write address not incremented */
AnnaBridge 171:3a7713b1edbc 266 #define PMU_TX_WRITE_INC 1 /**< Auto_Increment write address */
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /* TRANSFER bit positions */
AnnaBridge 171:3a7713b1edbc 269 #define PMU_TX_READS_POS 5
AnnaBridge 171:3a7713b1edbc 270 #define PMU_TX_READI_POS 7
AnnaBridge 171:3a7713b1edbc 271 #define PMU_TX_WRITES_POS 8
AnnaBridge 171:3a7713b1edbc 272 #define PMU_TX_WRITEI_POS 10
AnnaBridge 171:3a7713b1edbc 273 #define PMU_TX_LEN_POS 12
AnnaBridge 171:3a7713b1edbc 274 #define PMU_TX_BS_POS 26
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 /* PMU interrupt sources for the WAIT opcode */
AnnaBridge 171:3a7713b1edbc 277 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
AnnaBridge 171:3a7713b1edbc 278 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
AnnaBridge 171:3a7713b1edbc 279 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
AnnaBridge 171:3a7713b1edbc 280 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
AnnaBridge 171:3a7713b1edbc 281 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
AnnaBridge 171:3a7713b1edbc 282 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
AnnaBridge 171:3a7713b1edbc 283 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
AnnaBridge 171:3a7713b1edbc 284 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
AnnaBridge 171:3a7713b1edbc 285 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
AnnaBridge 171:3a7713b1edbc 286 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
AnnaBridge 171:3a7713b1edbc 287 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
AnnaBridge 171:3a7713b1edbc 288 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
AnnaBridge 171:3a7713b1edbc 289 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
AnnaBridge 171:3a7713b1edbc 290 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
AnnaBridge 171:3a7713b1edbc 291 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
AnnaBridge 171:3a7713b1edbc 292 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
AnnaBridge 171:3a7713b1edbc 293 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16))
AnnaBridge 171:3a7713b1edbc 294 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17))
AnnaBridge 171:3a7713b1edbc 295 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18))
AnnaBridge 171:3a7713b1edbc 296 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19))
AnnaBridge 171:3a7713b1edbc 297 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20))
AnnaBridge 171:3a7713b1edbc 298 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21))
AnnaBridge 171:3a7713b1edbc 299 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22))
AnnaBridge 171:3a7713b1edbc 300 #define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23))
AnnaBridge 171:3a7713b1edbc 301 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24))
AnnaBridge 171:3a7713b1edbc 302 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25))
AnnaBridge 171:3a7713b1edbc 303 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26))
AnnaBridge 171:3a7713b1edbc 304 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27))
AnnaBridge 171:3a7713b1edbc 305 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28))
AnnaBridge 171:3a7713b1edbc 306 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29))
AnnaBridge 171:3a7713b1edbc 307 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30))
AnnaBridge 171:3a7713b1edbc 308 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31))
AnnaBridge 171:3a7713b1edbc 309 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0))
AnnaBridge 171:3a7713b1edbc 310 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1))
AnnaBridge 171:3a7713b1edbc 311 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2))
AnnaBridge 171:3a7713b1edbc 312 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3))
AnnaBridge 171:3a7713b1edbc 313 #define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4))
AnnaBridge 171:3a7713b1edbc 314 #define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5))
AnnaBridge 171:3a7713b1edbc 315 #define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6))
AnnaBridge 171:3a7713b1edbc 316 #define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7))
AnnaBridge 171:3a7713b1edbc 317 #define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8))
AnnaBridge 171:3a7713b1edbc 318 #define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9))
AnnaBridge 171:3a7713b1edbc 319 #define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10))
AnnaBridge 171:3a7713b1edbc 320 #define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11))
AnnaBridge 171:3a7713b1edbc 321 #define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12))
AnnaBridge 171:3a7713b1edbc 322 #define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13))
AnnaBridge 171:3a7713b1edbc 323 #define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14))
AnnaBridge 171:3a7713b1edbc 324 #define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15))
AnnaBridge 171:3a7713b1edbc 325 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16))
AnnaBridge 171:3a7713b1edbc 326 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17))
AnnaBridge 171:3a7713b1edbc 327 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18))
AnnaBridge 171:3a7713b1edbc 328 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19))
AnnaBridge 171:3a7713b1edbc 329 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20))
AnnaBridge 171:3a7713b1edbc 330 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21))
AnnaBridge 171:3a7713b1edbc 331 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22))
AnnaBridge 171:3a7713b1edbc 332 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23))
AnnaBridge 171:3a7713b1edbc 333 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24))
AnnaBridge 171:3a7713b1edbc 334 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25))
AnnaBridge 171:3a7713b1edbc 335 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26))
AnnaBridge 171:3a7713b1edbc 336 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27))
AnnaBridge 171:3a7713b1edbc 337 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28))
AnnaBridge 171:3a7713b1edbc 338 #define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29))
AnnaBridge 171:3a7713b1edbc 339 #define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30))
AnnaBridge 171:3a7713b1edbc 340 #define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31))
AnnaBridge 171:3a7713b1edbc 341 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0))
AnnaBridge 171:3a7713b1edbc 342 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1))
AnnaBridge 171:3a7713b1edbc 343 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2))
AnnaBridge 171:3a7713b1edbc 344 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3))
AnnaBridge 171:3a7713b1edbc 345 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4))
AnnaBridge 171:3a7713b1edbc 346 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5))
AnnaBridge 171:3a7713b1edbc 347 #define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6))
AnnaBridge 171:3a7713b1edbc 348 #define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7))
AnnaBridge 171:3a7713b1edbc 349 #define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8))
AnnaBridge 171:3a7713b1edbc 350 #define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9))
AnnaBridge 171:3a7713b1edbc 351 #define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10))
AnnaBridge 171:3a7713b1edbc 352 #define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11))
AnnaBridge 171:3a7713b1edbc 353 #define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12))
AnnaBridge 171:3a7713b1edbc 354 #define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13))
AnnaBridge 171:3a7713b1edbc 355 #define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14))
AnnaBridge 171:3a7713b1edbc 356 #define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15))
AnnaBridge 171:3a7713b1edbc 357 #define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16))
AnnaBridge 171:3a7713b1edbc 358 #define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17))
AnnaBridge 171:3a7713b1edbc 359 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18))
AnnaBridge 171:3a7713b1edbc 360 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19))
AnnaBridge 171:3a7713b1edbc 361 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20))
AnnaBridge 171:3a7713b1edbc 362 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21))
AnnaBridge 171:3a7713b1edbc 363 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22))
AnnaBridge 171:3a7713b1edbc 364 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23))
AnnaBridge 171:3a7713b1edbc 365 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24))
AnnaBridge 171:3a7713b1edbc 366 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25))
AnnaBridge 171:3a7713b1edbc 367 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26))
AnnaBridge 171:3a7713b1edbc 368 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27))
AnnaBridge 171:3a7713b1edbc 369 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28))
AnnaBridge 171:3a7713b1edbc 370 #define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29))
AnnaBridge 171:3a7713b1edbc 371 #define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30))
AnnaBridge 171:3a7713b1edbc 372 #define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31))
AnnaBridge 171:3a7713b1edbc 373 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0))
AnnaBridge 171:3a7713b1edbc 374 #define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1))
AnnaBridge 171:3a7713b1edbc 375 #define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2))
AnnaBridge 171:3a7713b1edbc 376 #define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3))
AnnaBridge 171:3a7713b1edbc 377 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4))
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /* PMU interrupt sources for the TRANSFER opcode */
AnnaBridge 171:3a7713b1edbc 380 #define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
AnnaBridge 171:3a7713b1edbc 381 #define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
AnnaBridge 171:3a7713b1edbc 382 #define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
AnnaBridge 171:3a7713b1edbc 383 #define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
AnnaBridge 171:3a7713b1edbc 384 #define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
AnnaBridge 171:3a7713b1edbc 385 #define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
AnnaBridge 171:3a7713b1edbc 386 #define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
AnnaBridge 171:3a7713b1edbc 387 #define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
AnnaBridge 171:3a7713b1edbc 388 #define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
AnnaBridge 171:3a7713b1edbc 389 #define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
AnnaBridge 171:3a7713b1edbc 390 #define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
AnnaBridge 171:3a7713b1edbc 391 #define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
AnnaBridge 171:3a7713b1edbc 392 #define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
AnnaBridge 171:3a7713b1edbc 393 #define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
AnnaBridge 171:3a7713b1edbc 394 #define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
AnnaBridge 171:3a7713b1edbc 395 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
AnnaBridge 171:3a7713b1edbc 396 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16))
AnnaBridge 171:3a7713b1edbc 397 #define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17))
AnnaBridge 171:3a7713b1edbc 398 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18))
AnnaBridge 171:3a7713b1edbc 399 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19))
AnnaBridge 171:3a7713b1edbc 400 #define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20))
AnnaBridge 171:3a7713b1edbc 401 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21))
AnnaBridge 171:3a7713b1edbc 402 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22))
AnnaBridge 171:3a7713b1edbc 403 #define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23))
AnnaBridge 171:3a7713b1edbc 404 #define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24))
AnnaBridge 171:3a7713b1edbc 405 ///@endcond
AnnaBridge 171:3a7713b1edbc 406 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 407 }
AnnaBridge 171:3a7713b1edbc 408 #endif
AnnaBridge 171:3a7713b1edbc 409
AnnaBridge 171:3a7713b1edbc 410 #endif /* _MXC_PMU_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 411