mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/adc_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-09-30 19:43:43 -0500 (Fri, 30 Sep 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24540 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_ADC_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_ADC_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /// @cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 /// @endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* **** Definitions **** */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @ingroup adc
AnnaBridge 171:3a7713b1edbc 75 * @defgroup adc_registers Registers
AnnaBridge 171:3a7713b1edbc 76 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
AnnaBridge 171:3a7713b1edbc 77 */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 81 * Structure type to access the ADC Registers.
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> ADC CTRL Register */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t status; /**< <tt>\b 0x004:</tt> ADC STATUS Register */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t data; /**< <tt>\b 0x008:</tt> ADC DATA Register */
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t intr; /**< <tt>\b 0x00C:</tt> ADC INTR Register */
AnnaBridge 171:3a7713b1edbc 88 __IO uint32_t limit[4]; /**< <tt>\b 0x010:</tt> ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t afe_ctrl; /**< <tt>\b 0x020:</tt> ADC AFE_CTRL Register */
AnnaBridge 171:3a7713b1edbc 90 __IO uint32_t ro_cal0; /**< <tt>\b 0x024:</tt> ADC RO_CAL0 Register */
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t ro_cal1; /**< <tt>\b 0x028:</tt> ADC RO_CAL1 Register */
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t ro_cal2; /**< <tt>\b 0x02C:</tt> ADC RO_CAL2 Register */
AnnaBridge 171:3a7713b1edbc 93 } mxc_adc_regs_t;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 /* Register offsets for module ADC. */
AnnaBridge 171:3a7713b1edbc 97 /**
AnnaBridge 171:3a7713b1edbc 98 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 99 * @defgroup ADC_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 100 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 101 * @{
AnnaBridge 171:3a7713b1edbc 102 */
AnnaBridge 171:3a7713b1edbc 103 #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt>\b 0x000</tt> */
AnnaBridge 171:3a7713b1edbc 104 #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt>\b 0x004</tt> */
AnnaBridge 171:3a7713b1edbc 105 #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt>\b 0x008</tt> */
AnnaBridge 171:3a7713b1edbc 106 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt>\b 0x00C</tt> */
AnnaBridge 171:3a7713b1edbc 107 #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt>\b 0x010</tt> */
AnnaBridge 171:3a7713b1edbc 108 #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt>\b 0x014</tt> */
AnnaBridge 171:3a7713b1edbc 109 #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt>\b 0x018</tt> */
AnnaBridge 171:3a7713b1edbc 110 #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt>\b 0x01C</tt> */
AnnaBridge 171:3a7713b1edbc 111 #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt>\b 0x020</tt> */
AnnaBridge 171:3a7713b1edbc 112 #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt>\b 0x024</tt> */
AnnaBridge 171:3a7713b1edbc 113 #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt>\b 0x028</tt> */
AnnaBridge 171:3a7713b1edbc 114 #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt>\b 0x02C</tt> */
AnnaBridge 171:3a7713b1edbc 115 /**@} end of group adc_registers */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 /**
AnnaBridge 171:3a7713b1edbc 118 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 119 * @defgroup ADC_CTRL_Register ADC_CTRL
AnnaBridge 171:3a7713b1edbc 120 * @brief Field Positions and Bit Masks for the ADC_CTRL register
AnnaBridge 171:3a7713b1edbc 121 * @{
AnnaBridge 171:3a7713b1edbc 122 */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 #if (MXC_ADC_REV == 0)
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */
AnnaBridge 171:3a7713b1edbc 153 #endif
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /**@} end of group adc_ctrl_register */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /**
AnnaBridge 171:3a7713b1edbc 162 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 163 * @defgroup ADC_STATUS_Register ADC_STATUS
AnnaBridge 171:3a7713b1edbc 164 * @brief Field Positions and Bit Masks for the ADC_STATUS register
AnnaBridge 171:3a7713b1edbc 165 * @{
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */
AnnaBridge 171:3a7713b1edbc 175 /**@} end of group ADC_STATUS_register */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /**
AnnaBridge 171:3a7713b1edbc 178 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 179 * @defgroup ADC_DATA_Register ADC_DATA
AnnaBridge 171:3a7713b1edbc 180 * @brief Field Positions and Bit Masks for the ADC_DATA register
AnnaBridge 171:3a7713b1edbc 181 * @{
AnnaBridge 171:3a7713b1edbc 182 */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */
AnnaBridge 171:3a7713b1edbc 185 /**@} end of group ADC_DATA_register */
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 /**
AnnaBridge 171:3a7713b1edbc 188 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 189 * @defgroup ADC_INTR_Register ADC_INTR Register
AnnaBridge 171:3a7713b1edbc 190 * @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 /**
AnnaBridge 171:3a7713b1edbc 193 * @ingroup ADC_INTR_Register
AnnaBridge 171:3a7713b1edbc 194 * @defgroup ADC_INTR_IE_Register Interrupt Enable Bits
AnnaBridge 171:3a7713b1edbc 195 * @brief Interrupt Enable Bit Positions and Masks
AnnaBridge 171:3a7713b1edbc 196 * @{
AnnaBridge 171:3a7713b1edbc 197 */
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */
AnnaBridge 171:3a7713b1edbc 201 #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */
AnnaBridge 171:3a7713b1edbc 202 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */
AnnaBridge 171:3a7713b1edbc 210 /**@} end of group ADC_INTR_IE_Register */
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /**
AnnaBridge 171:3a7713b1edbc 214 * @ingroup ADC_INTR_Register
AnnaBridge 171:3a7713b1edbc 215 * @defgroup ADC_INTR_IF_Register Interrupt Flag Bits
AnnaBridge 171:3a7713b1edbc 216 * @brief Interrupt Flag Bit Positions and Masks
AnnaBridge 171:3a7713b1edbc 217 * @{
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */
AnnaBridge 171:3a7713b1edbc 225 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */
AnnaBridge 171:3a7713b1edbc 233 /**@} end of group ADC_INTR_IF_Register */
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 /**
AnnaBridge 171:3a7713b1edbc 236 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 237 * @defgroup ADC_LIMIT0_Register ADC_LIMIT0
AnnaBridge 171:3a7713b1edbc 238 * @brief Field Positions and Bit Masks for the ADC_LIMIT0 register
AnnaBridge 171:3a7713b1edbc 239 * @{
AnnaBridge 171:3a7713b1edbc 240 */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */
AnnaBridge 171:3a7713b1edbc 247 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 248 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 249 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 250 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 251 /**@} end of group ADC_LIMIT0_register */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /**
AnnaBridge 171:3a7713b1edbc 254 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 255 * @defgroup ADC_LIMIT1_Register ADC_LIMIT1
AnnaBridge 171:3a7713b1edbc 256 * @brief Field Positions and Bit Masks for the ADC_LIMIT1 register
AnnaBridge 171:3a7713b1edbc 257 * @{
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */
AnnaBridge 171:3a7713b1edbc 264 #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 269 /**@} end of group ADC_LIMIT1_register */
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 /**
AnnaBridge 171:3a7713b1edbc 272 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 273 * @defgroup ADC_LIMIT2_Register ADC_LIMIT2
AnnaBridge 171:3a7713b1edbc 274 * @brief Field Positions and Bit Masks for the ADC_LIMIT2 register
AnnaBridge 171:3a7713b1edbc 275 * @{
AnnaBridge 171:3a7713b1edbc 276 */
AnnaBridge 171:3a7713b1edbc 277 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 278 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 280 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 287 /**@} end of group ADC_LIMIT2_register */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /**
AnnaBridge 171:3a7713b1edbc 290 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 291 * @defgroup ADC_LIMIT3_Register ADC_LIMIT3
AnnaBridge 171:3a7713b1edbc 292 * @brief Field Positions and Bit Masks for the ADC_LIMIT3 register
AnnaBridge 171:3a7713b1edbc 293 * @{
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 296 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 297 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
AnnaBridge 171:3a7713b1edbc 298 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 299 #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */
AnnaBridge 171:3a7713b1edbc 300 #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
AnnaBridge 171:3a7713b1edbc 305 /**@} end of group ADC_LIMIT3_register */
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /**
AnnaBridge 171:3a7713b1edbc 308 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 309 * @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL
AnnaBridge 171:3a7713b1edbc 310 * @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register
AnnaBridge 171:3a7713b1edbc 311 * @{
AnnaBridge 171:3a7713b1edbc 312 */
AnnaBridge 171:3a7713b1edbc 313 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */
AnnaBridge 171:3a7713b1edbc 314 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */
AnnaBridge 171:3a7713b1edbc 315 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */
AnnaBridge 171:3a7713b1edbc 316 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */
AnnaBridge 171:3a7713b1edbc 317 /**@} end of group ADC_AFE_CTRL_register */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /**
AnnaBridge 171:3a7713b1edbc 320 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 321 * @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0
AnnaBridge 171:3a7713b1edbc 322 * @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register
AnnaBridge 171:3a7713b1edbc 323 * @{
AnnaBridge 171:3a7713b1edbc 324 */
AnnaBridge 171:3a7713b1edbc 325 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */
AnnaBridge 171:3a7713b1edbc 326 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */
AnnaBridge 171:3a7713b1edbc 327 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */
AnnaBridge 171:3a7713b1edbc 328 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */
AnnaBridge 171:3a7713b1edbc 329 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */
AnnaBridge 171:3a7713b1edbc 330 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */
AnnaBridge 171:3a7713b1edbc 331 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */
AnnaBridge 171:3a7713b1edbc 332 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */
AnnaBridge 171:3a7713b1edbc 333 #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */
AnnaBridge 171:3a7713b1edbc 334 #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */
AnnaBridge 171:3a7713b1edbc 335 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */
AnnaBridge 171:3a7713b1edbc 336 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */
AnnaBridge 171:3a7713b1edbc 337 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */
AnnaBridge 171:3a7713b1edbc 338 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */
AnnaBridge 171:3a7713b1edbc 339 /**@} end of group ADC_RO_CAL0_register */
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /**
AnnaBridge 171:3a7713b1edbc 342 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 343 * @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1
AnnaBridge 171:3a7713b1edbc 344 * @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register
AnnaBridge 171:3a7713b1edbc 345 * @{
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */
AnnaBridge 171:3a7713b1edbc 348 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */
AnnaBridge 171:3a7713b1edbc 349 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */
AnnaBridge 171:3a7713b1edbc 350 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */
AnnaBridge 171:3a7713b1edbc 351 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */
AnnaBridge 171:3a7713b1edbc 352 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */
AnnaBridge 171:3a7713b1edbc 353 /**@} end of group RO_CAL1_register */
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 /**
AnnaBridge 171:3a7713b1edbc 356 * @ingroup adc_registers
AnnaBridge 171:3a7713b1edbc 357 * @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2
AnnaBridge 171:3a7713b1edbc 358 * @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register
AnnaBridge 171:3a7713b1edbc 359 * @{
AnnaBridge 171:3a7713b1edbc 360 */
AnnaBridge 171:3a7713b1edbc 361 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */
AnnaBridge 171:3a7713b1edbc 362 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */
AnnaBridge 171:3a7713b1edbc 363 /**@} end of group RO_CAL2_register */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 /**
AnnaBridge 171:3a7713b1edbc 366 * @ingroup ADC_CTRL_Register
AnnaBridge 171:3a7713b1edbc 367 * @defgroup ADC_CHSEL_values ADC Channel Select Values
AnnaBridge 171:3a7713b1edbc 368 * @brief Channel Select Values
AnnaBridge 171:3a7713b1edbc 369 * @{
AnnaBridge 171:3a7713b1edbc 370 */
AnnaBridge 171:3a7713b1edbc 371 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */
AnnaBridge 171:3a7713b1edbc 372 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */
AnnaBridge 171:3a7713b1edbc 373 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */
AnnaBridge 171:3a7713b1edbc 374 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */
AnnaBridge 171:3a7713b1edbc 375 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */
AnnaBridge 171:3a7713b1edbc 376 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */
AnnaBridge 171:3a7713b1edbc 377 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */
AnnaBridge 171:3a7713b1edbc 378 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */
AnnaBridge 171:3a7713b1edbc 379 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */
AnnaBridge 171:3a7713b1edbc 380 #define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */
AnnaBridge 171:3a7713b1edbc 381 #define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 #if(MXC_ADC_REV > 0)
AnnaBridge 171:3a7713b1edbc 384 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */
AnnaBridge 171:3a7713b1edbc 385 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */
AnnaBridge 171:3a7713b1edbc 386 #endif
AnnaBridge 171:3a7713b1edbc 387 /**@} end of group ADC_CHSEL_values */
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 390 }
AnnaBridge 171:3a7713b1edbc 391 #endif
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 #endif /* _MXC_ADC_REGS_H_ */