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TARGET_MAX32600MBED/TOOLCHAIN_IAR/uart_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_UART_REGS_H_
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_UART_REGS_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file uart_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup uart UART
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 50 ====== ============================================== */
AnnaBridge 171:3a7713b1edbc 51 typedef struct {
AnnaBridge 171:3a7713b1edbc 52 __IO uint32_t ctrl; /* 0x0000 UART Control Register */
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t status; /* 0x0004 UART Status Register */
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t intfl; /* 0x000C Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */
AnnaBridge 171:3a7713b1edbc 61 } mxc_uart_regs_t;
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /*
AnnaBridge 171:3a7713b1edbc 65 Register offsets for module UART.
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67 #define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 68 #define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 69 #define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 70 #define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 71 #define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 72 #define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 73 #define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 74 #define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL)
AnnaBridge 171:3a7713b1edbc 75 #define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL)
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /*
AnnaBridge 171:3a7713b1edbc 78 Field positions and masks for module UART.
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 #define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0
AnnaBridge 171:3a7713b1edbc 81 #define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS))
AnnaBridge 171:3a7713b1edbc 82 #define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4
AnnaBridge 171:3a7713b1edbc 83 #define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 84 #define MXC_F_UART_CTRL_PARITY_MODE_POS 5
AnnaBridge 171:3a7713b1edbc 85 #define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS))
AnnaBridge 171:3a7713b1edbc 86 #define MXC_F_UART_CTRL_PARITY_BIAS_POS 6
AnnaBridge 171:3a7713b1edbc 87 #define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS))
AnnaBridge 171:3a7713b1edbc 88 #define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8
AnnaBridge 171:3a7713b1edbc 89 #define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS))
AnnaBridge 171:3a7713b1edbc 90 #define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9
AnnaBridge 171:3a7713b1edbc 91 #define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS))
AnnaBridge 171:3a7713b1edbc 92 #define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10
AnnaBridge 171:3a7713b1edbc 93 #define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS))
AnnaBridge 171:3a7713b1edbc 94 #define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12
AnnaBridge 171:3a7713b1edbc 95 #define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS))
AnnaBridge 171:3a7713b1edbc 96 #define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13
AnnaBridge 171:3a7713b1edbc 97 #define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS))
AnnaBridge 171:3a7713b1edbc 98 #define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14
AnnaBridge 171:3a7713b1edbc 99 #define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS))
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 #define MXC_F_UART_STATUS_TX_BUSY_POS 0
AnnaBridge 171:3a7713b1edbc 102 #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS))
AnnaBridge 171:3a7713b1edbc 103 #define MXC_F_UART_STATUS_RX_BUSY_POS 1
AnnaBridge 171:3a7713b1edbc 104 #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS))
AnnaBridge 171:3a7713b1edbc 105 #define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4
AnnaBridge 171:3a7713b1edbc 106 #define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 107 #define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5
AnnaBridge 171:3a7713b1edbc 108 #define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS))
AnnaBridge 171:3a7713b1edbc 109 #define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6
AnnaBridge 171:3a7713b1edbc 110 #define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS))
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS))
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS))
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS))
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS))
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_UART_INTEN_CTS_CHANGE_POS 2
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS))
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_UART_INTEN_RX_OVERRUN_POS 3
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS))
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS))
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS))
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_UART_INTFL_CTS_CHANGE_POS 2
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS))
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_UART_INTFL_RX_OVERRUN_POS 3
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS))
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS))
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_UART_BAUD_INT_FBAUD_POS 0
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS))
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_UART_BAUD_DIV_128_DIV_POS 0
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS))
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS))
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS))
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS))
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS))
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS))
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 168 }
AnnaBridge 171:3a7713b1edbc 169 #endif
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /**
AnnaBridge 171:3a7713b1edbc 172 * @}
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 #endif /* _MXC_UART_REGS_H_ */