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TARGET_KW41Z/TOOLCHAIN_GCC_ARM/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 32 #define _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /*! @addtogroup clock */
AnnaBridge 171:3a7713b1edbc 37 /*! @{ */
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /*! @file */
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 42 * Definitions
AnnaBridge 171:3a7713b1edbc 43 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 46 /*@{*/
AnnaBridge 171:3a7713b1edbc 47 /*! @brief CLOCK driver version 2.2.0. */
AnnaBridge 171:3a7713b1edbc 48 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
AnnaBridge 171:3a7713b1edbc 49 /*@}*/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge 171:3a7713b1edbc 52 *
AnnaBridge 171:3a7713b1edbc 53 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
AnnaBridge 171:3a7713b1edbc 54 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
AnnaBridge 171:3a7713b1edbc 55 * if XTAL0 is 8 MHz:
AnnaBridge 171:3a7713b1edbc 56 * @code
AnnaBridge 171:3a7713b1edbc 57 * CLOCK_InitOsc0(...); // Set up the OSC0
AnnaBridge 171:3a7713b1edbc 58 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
AnnaBridge 171:3a7713b1edbc 59 * @endcode
AnnaBridge 171:3a7713b1edbc 60 *
AnnaBridge 171:3a7713b1edbc 61 * This is important for the multicore platforms where only one core needs to set up the
AnnaBridge 171:3a7713b1edbc 62 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
AnnaBridge 171:3a7713b1edbc 63 * to get a valid clock frequency.
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 extern uint32_t g_xtal0Freq;
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge 171:3a7713b1edbc 68 *
AnnaBridge 171:3a7713b1edbc 69 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
AnnaBridge 171:3a7713b1edbc 70 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
AnnaBridge 171:3a7713b1edbc 71 *
AnnaBridge 171:3a7713b1edbc 72 * This is important for the multicore platforms where only one core needs to set up
AnnaBridge 171:3a7713b1edbc 73 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
AnnaBridge 171:3a7713b1edbc 74 * to get a valid clock frequency.
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 extern uint32_t g_xtal32Freq;
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 #if (defined(OSC) && !(defined(OSC0)))
AnnaBridge 171:3a7713b1edbc 79 #define OSC0 OSC
AnnaBridge 171:3a7713b1edbc 80 #endif
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /*! @brief Clock ip name array for DMAMUX. */
AnnaBridge 171:3a7713b1edbc 83 #define DMAMUX_CLOCKS \
AnnaBridge 171:3a7713b1edbc 84 { \
AnnaBridge 171:3a7713b1edbc 85 kCLOCK_Dmamux0 \
AnnaBridge 171:3a7713b1edbc 86 }
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 /*! @brief Clock ip name array for RTC. */
AnnaBridge 171:3a7713b1edbc 89 #define RTC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 90 { \
AnnaBridge 171:3a7713b1edbc 91 kCLOCK_Rtc0 \
AnnaBridge 171:3a7713b1edbc 92 }
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 /*! @brief Clock ip name array for PIT. */
AnnaBridge 171:3a7713b1edbc 95 #define PIT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 96 { \
AnnaBridge 171:3a7713b1edbc 97 kCLOCK_Pit0 \
AnnaBridge 171:3a7713b1edbc 98 }
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /*! @brief Clock ip name array for PORT. */
AnnaBridge 171:3a7713b1edbc 101 #define PORT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 102 { \
AnnaBridge 171:3a7713b1edbc 103 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC \
AnnaBridge 171:3a7713b1edbc 104 }
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /*! @brief Clock ip name array for TSI. */
AnnaBridge 171:3a7713b1edbc 107 #define TSI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 108 { \
AnnaBridge 171:3a7713b1edbc 109 kCLOCK_Tsi0 \
AnnaBridge 171:3a7713b1edbc 110 }
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /*! @brief Clock ip name array for DSPI. */
AnnaBridge 171:3a7713b1edbc 113 #define DSPI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 114 { \
AnnaBridge 171:3a7713b1edbc 115 kCLOCK_Spi0, kCLOCK_Spi1 \
AnnaBridge 171:3a7713b1edbc 116 }
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /*! @brief Clock ip name array for LPUART. */
AnnaBridge 171:3a7713b1edbc 119 #define LPUART_CLOCKS \
AnnaBridge 171:3a7713b1edbc 120 { \
AnnaBridge 171:3a7713b1edbc 121 kCLOCK_Lpuart0 \
AnnaBridge 171:3a7713b1edbc 122 }
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /*! @brief Clock ip name array for DAC. */
AnnaBridge 171:3a7713b1edbc 125 #define DAC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 126 { \
AnnaBridge 171:3a7713b1edbc 127 kCLOCK_Dac0 \
AnnaBridge 171:3a7713b1edbc 128 }
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /*! @brief Clock ip name array for LPTMR. */
AnnaBridge 171:3a7713b1edbc 131 #define LPTMR_CLOCKS \
AnnaBridge 171:3a7713b1edbc 132 { \
AnnaBridge 171:3a7713b1edbc 133 kCLOCK_Lptmr0 \
AnnaBridge 171:3a7713b1edbc 134 }
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /*! @brief Clock ip name array for ADC16. */
AnnaBridge 171:3a7713b1edbc 137 #define ADC16_CLOCKS \
AnnaBridge 171:3a7713b1edbc 138 { \
AnnaBridge 171:3a7713b1edbc 139 kCLOCK_Adc0 \
AnnaBridge 171:3a7713b1edbc 140 }
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 /*! @brief Clock ip name array for TRNG. */
AnnaBridge 171:3a7713b1edbc 143 #define TRNG_CLOCKS \
AnnaBridge 171:3a7713b1edbc 144 { \
AnnaBridge 171:3a7713b1edbc 145 kCLOCK_Trng0 \
AnnaBridge 171:3a7713b1edbc 146 }
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /*! @brief Clock ip name array for DMA. */
AnnaBridge 171:3a7713b1edbc 149 #define EDMA_CLOCKS \
AnnaBridge 171:3a7713b1edbc 150 { \
AnnaBridge 171:3a7713b1edbc 151 kCLOCK_Dma0 \
AnnaBridge 171:3a7713b1edbc 152 }
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /*! @brief Clock ip name array for CMT. */
AnnaBridge 171:3a7713b1edbc 155 #define CMT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 156 { \
AnnaBridge 171:3a7713b1edbc 157 kCLOCK_Cmt0 \
AnnaBridge 171:3a7713b1edbc 158 }
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /*! @brief Clock ip name array for TPM. */
AnnaBridge 171:3a7713b1edbc 161 #define TPM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 162 { \
AnnaBridge 171:3a7713b1edbc 163 kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
AnnaBridge 171:3a7713b1edbc 164 }
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /*! @brief Clock ip name array for LTC. */
AnnaBridge 171:3a7713b1edbc 167 #define LTC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 168 { \
AnnaBridge 171:3a7713b1edbc 169 kCLOCK_Ltc0 \
AnnaBridge 171:3a7713b1edbc 170 }
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /*! @brief Clock ip name array for I2C. */
AnnaBridge 171:3a7713b1edbc 173 #define I2C_CLOCKS \
AnnaBridge 171:3a7713b1edbc 174 { \
AnnaBridge 171:3a7713b1edbc 175 kCLOCK_I2c0, kCLOCK_I2c1 \
AnnaBridge 171:3a7713b1edbc 176 }
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /*! @brief Clock ip name array for CMP. */
AnnaBridge 171:3a7713b1edbc 179 #define CMP_CLOCKS \
AnnaBridge 171:3a7713b1edbc 180 { \
AnnaBridge 171:3a7713b1edbc 181 kCLOCK_Cmp0 \
AnnaBridge 171:3a7713b1edbc 182 }
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /*! @brief Clock ip name array for VREF. */
AnnaBridge 171:3a7713b1edbc 185 #define VREF_CLOCKS \
AnnaBridge 171:3a7713b1edbc 186 { \
AnnaBridge 171:3a7713b1edbc 187 kCLOCK_Vref0 \
AnnaBridge 171:3a7713b1edbc 188 }
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /*! @brief Clock ip name array for DCDC. */
AnnaBridge 171:3a7713b1edbc 191 #define DCDC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 192 { \
AnnaBridge 171:3a7713b1edbc 193 kCLOCK_Dcdc0 \
AnnaBridge 171:3a7713b1edbc 194 }
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /*!
AnnaBridge 171:3a7713b1edbc 197 * @brief LPO clock frequency.
AnnaBridge 171:3a7713b1edbc 198 */
AnnaBridge 171:3a7713b1edbc 199 #define LPO_CLK_FREQ 1000U
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 /*! @brief Prepherials clock source definition. */
AnnaBridge 171:3a7713b1edbc 202 #define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge 171:3a7713b1edbc 203 #define BUS_CLK kCLOCK_BusClk
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 #define I2C0_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 206 #define I2C1_CLK_SRC SYS_CLK
AnnaBridge 171:3a7713b1edbc 207 #define DSPI0_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 208 #define DSPI1_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 /*! @brief Clock name used to get clock frequency. */
AnnaBridge 171:3a7713b1edbc 211 typedef enum _clock_name
AnnaBridge 171:3a7713b1edbc 212 {
AnnaBridge 171:3a7713b1edbc 213 /* ----------------------------- System layer clock -------------------------------*/
AnnaBridge 171:3a7713b1edbc 214 kCLOCK_CoreSysClk, /*!< Core/system clock */
AnnaBridge 171:3a7713b1edbc 215 kCLOCK_PlatClk, /*!< Platform clock */
AnnaBridge 171:3a7713b1edbc 216 kCLOCK_BusClk, /*!< Bus clock */
AnnaBridge 171:3a7713b1edbc 217 kCLOCK_FlashClk, /*!< Flash clock */
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 220 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
AnnaBridge 171:3a7713b1edbc 221 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge 171:3a7713b1edbc 224 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
AnnaBridge 171:3a7713b1edbc 225 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
AnnaBridge 171:3a7713b1edbc 226 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
AnnaBridge 171:3a7713b1edbc 227 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /* --------------------------------- Other clock ----------------------------------*/
AnnaBridge 171:3a7713b1edbc 230 kCLOCK_LpoClk, /*!< LPO clock */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 } clock_name_t;
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 /*------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 clock_gate_t definition:
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 31 16 0
AnnaBridge 171:3a7713b1edbc 239 -----------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 240 | SIM_SCGC register offset | control bit offset in SCGC |
AnnaBridge 171:3a7713b1edbc 241 -----------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge 171:3a7713b1edbc 244 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 kClockGateSdhc0 = (0x1030 << 16) | 17;
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 ------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 #define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge 171:3a7713b1edbc 251 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge 171:3a7713b1edbc 252 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge 171:3a7713b1edbc 253 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge 171:3a7713b1edbc 256 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
AnnaBridge 171:3a7713b1edbc 257 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge 171:3a7713b1edbc 260 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
AnnaBridge 171:3a7713b1edbc 263 typedef enum _clock_ip_name
AnnaBridge 171:3a7713b1edbc 264 {
AnnaBridge 171:3a7713b1edbc 265 kCLOCK_IpInvalid = 0U,
AnnaBridge 171:3a7713b1edbc 266
AnnaBridge 171:3a7713b1edbc 267 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
AnnaBridge 171:3a7713b1edbc 268 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge 171:3a7713b1edbc 269 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge 171:3a7713b1edbc 270 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 171:3a7713b1edbc 271 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge 171:3a7713b1edbc 274 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
AnnaBridge 171:3a7713b1edbc 275 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge 171:3a7713b1edbc 276 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge 171:3a7713b1edbc 277 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge 171:3a7713b1edbc 278 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
AnnaBridge 171:3a7713b1edbc 279 kCLOCK_Aesa = CLK_GATE_DEFINE(0x1038U, 24U),
AnnaBridge 171:3a7713b1edbc 280 kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x1038U, 24U),
AnnaBridge 171:3a7713b1edbc 281 kCLOCK_Rsim = CLK_GATE_DEFINE(0x1038U, 25U),
AnnaBridge 171:3a7713b1edbc 282 kCLOCK_Dcdc0 = CLK_GATE_DEFINE(0x1038U, 26U),
AnnaBridge 171:3a7713b1edbc 283 kCLOCK_Btll = CLK_GATE_DEFINE(0x1038U, 27U),
AnnaBridge 171:3a7713b1edbc 284 kCLOCK_PhyDig = CLK_GATE_DEFINE(0x1038U, 28U),
AnnaBridge 171:3a7713b1edbc 285 kCLOCK_ZigBee = CLK_GATE_DEFINE(0x1038U, 29U),
AnnaBridge 171:3a7713b1edbc 286 kCLOCK_GenFsk = CLK_GATE_DEFINE(0x1038U, 31U),
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge 171:3a7713b1edbc 289 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge 171:3a7713b1edbc 290 kCLOCK_Trng0 = CLK_GATE_DEFINE(0x103CU, 9U),
AnnaBridge 171:3a7713b1edbc 291 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
AnnaBridge 171:3a7713b1edbc 292 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
AnnaBridge 171:3a7713b1edbc 293 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge 171:3a7713b1edbc 294 kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge 171:3a7713b1edbc 295 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge 171:3a7713b1edbc 296 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge 171:3a7713b1edbc 297 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge 171:3a7713b1edbc 298 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge 171:3a7713b1edbc 299 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
AnnaBridge 171:3a7713b1edbc 302 } clock_ip_name_t;
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /*!@brief SIM configuration structure for clock setting. */
AnnaBridge 171:3a7713b1edbc 305 typedef struct _sim_clock_config
AnnaBridge 171:3a7713b1edbc 306 {
AnnaBridge 171:3a7713b1edbc 307 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
AnnaBridge 171:3a7713b1edbc 308 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
AnnaBridge 171:3a7713b1edbc 309 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
AnnaBridge 171:3a7713b1edbc 310 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
AnnaBridge 171:3a7713b1edbc 311 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
AnnaBridge 171:3a7713b1edbc 312 } sim_clock_config_t;
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 /*! @brief OSC work mode. */
AnnaBridge 171:3a7713b1edbc 315 typedef enum _osc_mode
AnnaBridge 171:3a7713b1edbc 316 {
AnnaBridge 171:3a7713b1edbc 317 kOSC_ModeExt = 0U, /*!< Use an external clock. */
AnnaBridge 171:3a7713b1edbc 318 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge 171:3a7713b1edbc 319 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
AnnaBridge 171:3a7713b1edbc 320 #else
AnnaBridge 171:3a7713b1edbc 321 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
AnnaBridge 171:3a7713b1edbc 322 #endif
AnnaBridge 171:3a7713b1edbc 323 kOSC_ModeOscHighGain = 0U
AnnaBridge 171:3a7713b1edbc 324 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge 171:3a7713b1edbc 325 |
AnnaBridge 171:3a7713b1edbc 326 MCG_C2_EREFS_MASK
AnnaBridge 171:3a7713b1edbc 327 #else
AnnaBridge 171:3a7713b1edbc 328 |
AnnaBridge 171:3a7713b1edbc 329 MCG_C2_EREFS0_MASK
AnnaBridge 171:3a7713b1edbc 330 #endif
AnnaBridge 171:3a7713b1edbc 331 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
AnnaBridge 171:3a7713b1edbc 332 |
AnnaBridge 171:3a7713b1edbc 333 MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
AnnaBridge 171:3a7713b1edbc 334 #else
AnnaBridge 171:3a7713b1edbc 335 |
AnnaBridge 171:3a7713b1edbc 336 MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
AnnaBridge 171:3a7713b1edbc 337 #endif
AnnaBridge 171:3a7713b1edbc 338 } osc_mode_t;
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340 /*!
AnnaBridge 171:3a7713b1edbc 341 * @brief OSC Initialization Configuration Structure
AnnaBridge 171:3a7713b1edbc 342 *
AnnaBridge 171:3a7713b1edbc 343 * Defines the configuration data structure to initialize the OSC.
AnnaBridge 171:3a7713b1edbc 344 * When porting to a new board, set the following members
AnnaBridge 171:3a7713b1edbc 345 * according to the board setting:
AnnaBridge 171:3a7713b1edbc 346 * 1. freq: The external frequency.
AnnaBridge 171:3a7713b1edbc 347 * 2. workMode: The OSC module mode.
AnnaBridge 171:3a7713b1edbc 348 */
AnnaBridge 171:3a7713b1edbc 349 typedef struct _osc_config
AnnaBridge 171:3a7713b1edbc 350 {
AnnaBridge 171:3a7713b1edbc 351 uint32_t freq; /*!< External clock frequency. */
AnnaBridge 171:3a7713b1edbc 352 osc_mode_t workMode; /*!< OSC work mode setting. */
AnnaBridge 171:3a7713b1edbc 353 } osc_config_t;
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 /*! @brief MCG FLL reference clock source select. */
AnnaBridge 171:3a7713b1edbc 356 typedef enum _mcg_fll_src
AnnaBridge 171:3a7713b1edbc 357 {
AnnaBridge 171:3a7713b1edbc 358 kMCG_FllSrcExternal, /*!< External reference clock is selected */
AnnaBridge 171:3a7713b1edbc 359 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
AnnaBridge 171:3a7713b1edbc 360 } mcg_fll_src_t;
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /*! @brief MCG internal reference clock select */
AnnaBridge 171:3a7713b1edbc 363 typedef enum _mcg_irc_mode
AnnaBridge 171:3a7713b1edbc 364 {
AnnaBridge 171:3a7713b1edbc 365 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
AnnaBridge 171:3a7713b1edbc 366 kMCG_IrcFast /*!< Fast internal reference clock selected */
AnnaBridge 171:3a7713b1edbc 367 } mcg_irc_mode_t;
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
AnnaBridge 171:3a7713b1edbc 370 typedef enum _mcg_dmx32
AnnaBridge 171:3a7713b1edbc 371 {
AnnaBridge 171:3a7713b1edbc 372 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
AnnaBridge 171:3a7713b1edbc 373 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
AnnaBridge 171:3a7713b1edbc 374 } mcg_dmx32_t;
AnnaBridge 171:3a7713b1edbc 375
AnnaBridge 171:3a7713b1edbc 376 /*! @brief MCG DCO range select */
AnnaBridge 171:3a7713b1edbc 377 typedef enum _mcg_drs
AnnaBridge 171:3a7713b1edbc 378 {
AnnaBridge 171:3a7713b1edbc 379 kMCG_DrsLow, /*!< Low frequency range */
AnnaBridge 171:3a7713b1edbc 380 kMCG_DrsMid, /*!< Mid frequency range */
AnnaBridge 171:3a7713b1edbc 381 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
AnnaBridge 171:3a7713b1edbc 382 kMCG_DrsHigh /*!< High frequency range */
AnnaBridge 171:3a7713b1edbc 383 } mcg_drs_t;
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /*! @brief MCG PLL reference clock select */
AnnaBridge 171:3a7713b1edbc 386 typedef enum _mcg_pll_ref_src
AnnaBridge 171:3a7713b1edbc 387 {
AnnaBridge 171:3a7713b1edbc 388 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
AnnaBridge 171:3a7713b1edbc 389 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
AnnaBridge 171:3a7713b1edbc 390 } mcg_pll_ref_src_t;
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 /*! @brief MCGOUT clock source. */
AnnaBridge 171:3a7713b1edbc 393 typedef enum _mcg_clkout_src
AnnaBridge 171:3a7713b1edbc 394 {
AnnaBridge 171:3a7713b1edbc 395 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
AnnaBridge 171:3a7713b1edbc 396 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
AnnaBridge 171:3a7713b1edbc 397 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
AnnaBridge 171:3a7713b1edbc 398 } mcg_clkout_src_t;
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /*! @brief MCG Automatic Trim Machine Select */
AnnaBridge 171:3a7713b1edbc 401 typedef enum _mcg_atm_select
AnnaBridge 171:3a7713b1edbc 402 {
AnnaBridge 171:3a7713b1edbc 403 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
AnnaBridge 171:3a7713b1edbc 404 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
AnnaBridge 171:3a7713b1edbc 405 } mcg_atm_select_t;
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /*! @brief MCG OSC Clock Select */
AnnaBridge 171:3a7713b1edbc 408 typedef enum _mcg_oscsel
AnnaBridge 171:3a7713b1edbc 409 {
AnnaBridge 171:3a7713b1edbc 410 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
AnnaBridge 171:3a7713b1edbc 411 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
AnnaBridge 171:3a7713b1edbc 412 } mcg_oscsel_t;
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 /*! @brief MCG PLLCS select */
AnnaBridge 171:3a7713b1edbc 415 typedef enum _mcg_pll_clk_select
AnnaBridge 171:3a7713b1edbc 416 {
AnnaBridge 171:3a7713b1edbc 417 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
AnnaBridge 171:3a7713b1edbc 418 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
AnnaBridge 171:3a7713b1edbc 419 } mcg_pll_clk_select_t;
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421 /*! @brief MCG clock monitor mode. */
AnnaBridge 171:3a7713b1edbc 422 typedef enum _mcg_monitor_mode
AnnaBridge 171:3a7713b1edbc 423 {
AnnaBridge 171:3a7713b1edbc 424 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
AnnaBridge 171:3a7713b1edbc 425 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
AnnaBridge 171:3a7713b1edbc 426 kMCG_MonitorReset /*!< System reset when clock lost. */
AnnaBridge 171:3a7713b1edbc 427 } mcg_monitor_mode_t;
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /*! @brief MCG status. */
AnnaBridge 171:3a7713b1edbc 430 enum _mcg_status
AnnaBridge 171:3a7713b1edbc 431 {
AnnaBridge 171:3a7713b1edbc 432 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
AnnaBridge 171:3a7713b1edbc 433 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
AnnaBridge 171:3a7713b1edbc 434 function. */
AnnaBridge 171:3a7713b1edbc 435 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
AnnaBridge 171:3a7713b1edbc 436 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
AnnaBridge 171:3a7713b1edbc 437 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
AnnaBridge 171:3a7713b1edbc 438 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
AnnaBridge 171:3a7713b1edbc 439 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
AnnaBridge 171:3a7713b1edbc 440 it is in use. */
AnnaBridge 171:3a7713b1edbc 441 };
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 /*! @brief MCG status flags. */
AnnaBridge 171:3a7713b1edbc 444 enum _mcg_status_flags_t
AnnaBridge 171:3a7713b1edbc 445 {
AnnaBridge 171:3a7713b1edbc 446 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
AnnaBridge 171:3a7713b1edbc 447 };
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
AnnaBridge 171:3a7713b1edbc 450 enum _mcg_irclk_enable_mode
AnnaBridge 171:3a7713b1edbc 451 {
AnnaBridge 171:3a7713b1edbc 452 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
AnnaBridge 171:3a7713b1edbc 453 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
AnnaBridge 171:3a7713b1edbc 454 };
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /*! @brief MCG mode definitions */
AnnaBridge 171:3a7713b1edbc 457 typedef enum _mcg_mode
AnnaBridge 171:3a7713b1edbc 458 {
AnnaBridge 171:3a7713b1edbc 459 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
AnnaBridge 171:3a7713b1edbc 460 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
AnnaBridge 171:3a7713b1edbc 461 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
AnnaBridge 171:3a7713b1edbc 462 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
AnnaBridge 171:3a7713b1edbc 463 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
AnnaBridge 171:3a7713b1edbc 464 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
AnnaBridge 171:3a7713b1edbc 465 kMCG_ModeError /*!< Unknown mode */
AnnaBridge 171:3a7713b1edbc 466 } mcg_mode_t;
AnnaBridge 171:3a7713b1edbc 467
AnnaBridge 171:3a7713b1edbc 468 /*! @brief MCG mode change configuration structure
AnnaBridge 171:3a7713b1edbc 469 *
AnnaBridge 171:3a7713b1edbc 470 * When porting to a new board, set the following members
AnnaBridge 171:3a7713b1edbc 471 * according to the board setting:
AnnaBridge 171:3a7713b1edbc 472 * 1. frdiv: If the FLL uses the external reference clock, set this
AnnaBridge 171:3a7713b1edbc 473 * value to ensure that the external reference clock divided by frdiv is
AnnaBridge 171:3a7713b1edbc 474 * in the 31.25 kHz to 39.0625 kHz range.
AnnaBridge 171:3a7713b1edbc 475 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
AnnaBridge 171:3a7713b1edbc 476 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
AnnaBridge 171:3a7713b1edbc 477 * FSL_FEATURE_MCG_PLL_REF_MAX range.
AnnaBridge 171:3a7713b1edbc 478 */
AnnaBridge 171:3a7713b1edbc 479 typedef struct _mcg_config
AnnaBridge 171:3a7713b1edbc 480 {
AnnaBridge 171:3a7713b1edbc 481 mcg_mode_t mcgMode; /*!< MCG mode. */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /* ----------------------- MCGIRCCLK settings ------------------------ */
AnnaBridge 171:3a7713b1edbc 484 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
AnnaBridge 171:3a7713b1edbc 485 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
AnnaBridge 171:3a7713b1edbc 486 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
AnnaBridge 171:3a7713b1edbc 487
AnnaBridge 171:3a7713b1edbc 488 /* ------------------------ MCG FLL settings ------------------------- */
AnnaBridge 171:3a7713b1edbc 489 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
AnnaBridge 171:3a7713b1edbc 490 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
AnnaBridge 171:3a7713b1edbc 491 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
AnnaBridge 171:3a7713b1edbc 492 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /* ------------------------ MCG PLL settings ------------------------- */
AnnaBridge 171:3a7713b1edbc 495 } mcg_config_t;
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 498 * API
AnnaBridge 171:3a7713b1edbc 499 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 502 extern "C" {
AnnaBridge 171:3a7713b1edbc 503 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /*!
AnnaBridge 171:3a7713b1edbc 506 * @brief Enable the clock for specific IP.
AnnaBridge 171:3a7713b1edbc 507 *
AnnaBridge 171:3a7713b1edbc 508 * @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge 171:3a7713b1edbc 509 */
AnnaBridge 171:3a7713b1edbc 510 static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge 171:3a7713b1edbc 511 {
AnnaBridge 171:3a7713b1edbc 512 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 171:3a7713b1edbc 513 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 171:3a7713b1edbc 514 }
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /*!
AnnaBridge 171:3a7713b1edbc 517 * @brief Disable the clock for specific IP.
AnnaBridge 171:3a7713b1edbc 518 *
AnnaBridge 171:3a7713b1edbc 519 * @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge 171:3a7713b1edbc 520 */
AnnaBridge 171:3a7713b1edbc 521 static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge 171:3a7713b1edbc 522 {
AnnaBridge 171:3a7713b1edbc 523 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 171:3a7713b1edbc 524 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 171:3a7713b1edbc 525 }
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /*!
AnnaBridge 171:3a7713b1edbc 528 * @brief Set ERCLK32K source.
AnnaBridge 171:3a7713b1edbc 529 *
AnnaBridge 171:3a7713b1edbc 530 * @param src The value to set ERCLK32K clock source.
AnnaBridge 171:3a7713b1edbc 531 */
AnnaBridge 171:3a7713b1edbc 532 static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 533 {
AnnaBridge 171:3a7713b1edbc 534 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
AnnaBridge 171:3a7713b1edbc 535 }
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /*!
AnnaBridge 171:3a7713b1edbc 538 * @brief Set LPUART clock source.
AnnaBridge 171:3a7713b1edbc 539 *
AnnaBridge 171:3a7713b1edbc 540 * @param src The value to set LPUART clock source.
AnnaBridge 171:3a7713b1edbc 541 */
AnnaBridge 171:3a7713b1edbc 542 static inline void CLOCK_SetLpuartClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 543 {
AnnaBridge 171:3a7713b1edbc 544 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src));
AnnaBridge 171:3a7713b1edbc 545 }
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /*!
AnnaBridge 171:3a7713b1edbc 548 * @brief Set TPM clock source.
AnnaBridge 171:3a7713b1edbc 549 *
AnnaBridge 171:3a7713b1edbc 550 * @param src The value to set TPM clock source.
AnnaBridge 171:3a7713b1edbc 551 */
AnnaBridge 171:3a7713b1edbc 552 static inline void CLOCK_SetTpmClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 553 {
AnnaBridge 171:3a7713b1edbc 554 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
AnnaBridge 171:3a7713b1edbc 555 }
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 /*!
AnnaBridge 171:3a7713b1edbc 558 * @brief Set CLKOUT source.
AnnaBridge 171:3a7713b1edbc 559 *
AnnaBridge 171:3a7713b1edbc 560 * @param src The value to set CLKOUT source.
AnnaBridge 171:3a7713b1edbc 561 */
AnnaBridge 171:3a7713b1edbc 562 static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 563 {
AnnaBridge 171:3a7713b1edbc 564 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
AnnaBridge 171:3a7713b1edbc 565 }
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 /*!
AnnaBridge 171:3a7713b1edbc 568 * @brief System clock divider
AnnaBridge 171:3a7713b1edbc 569 *
AnnaBridge 171:3a7713b1edbc 570 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4].
AnnaBridge 171:3a7713b1edbc 571 *
AnnaBridge 171:3a7713b1edbc 572 * @param outdiv1 Clock 1 output divider value.
AnnaBridge 171:3a7713b1edbc 573 *
AnnaBridge 171:3a7713b1edbc 574 * @param outdiv4 Clock 4 output divider value.
AnnaBridge 171:3a7713b1edbc 575 */
AnnaBridge 171:3a7713b1edbc 576 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4)
AnnaBridge 171:3a7713b1edbc 577 {
AnnaBridge 171:3a7713b1edbc 578 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4);
AnnaBridge 171:3a7713b1edbc 579 }
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 /*!
AnnaBridge 171:3a7713b1edbc 582 * @brief Gets the clock frequency for a specific clock name.
AnnaBridge 171:3a7713b1edbc 583 *
AnnaBridge 171:3a7713b1edbc 584 * This function checks the current clock configurations and then calculates
AnnaBridge 171:3a7713b1edbc 585 * the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge 171:3a7713b1edbc 586 * The MCG must be properly configured before using this function.
AnnaBridge 171:3a7713b1edbc 587 *
AnnaBridge 171:3a7713b1edbc 588 * @param clockName Clock names defined in clock_name_t
AnnaBridge 171:3a7713b1edbc 589 * @return Clock frequency value in Hertz
AnnaBridge 171:3a7713b1edbc 590 */
AnnaBridge 171:3a7713b1edbc 591 uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 /*!
AnnaBridge 171:3a7713b1edbc 594 * @brief Get the core clock or system clock frequency.
AnnaBridge 171:3a7713b1edbc 595 *
AnnaBridge 171:3a7713b1edbc 596 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 597 */
AnnaBridge 171:3a7713b1edbc 598 uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /*!
AnnaBridge 171:3a7713b1edbc 601 * @brief Get the platform clock frequency.
AnnaBridge 171:3a7713b1edbc 602 *
AnnaBridge 171:3a7713b1edbc 603 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 604 */
AnnaBridge 171:3a7713b1edbc 605 uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 /*!
AnnaBridge 171:3a7713b1edbc 608 * @brief Get the bus clock frequency.
AnnaBridge 171:3a7713b1edbc 609 *
AnnaBridge 171:3a7713b1edbc 610 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 611 */
AnnaBridge 171:3a7713b1edbc 612 uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /*!
AnnaBridge 171:3a7713b1edbc 615 * @brief Get the flash clock frequency.
AnnaBridge 171:3a7713b1edbc 616 *
AnnaBridge 171:3a7713b1edbc 617 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 618 */
AnnaBridge 171:3a7713b1edbc 619 uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 /*!
AnnaBridge 171:3a7713b1edbc 622 * @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge 171:3a7713b1edbc 623 *
AnnaBridge 171:3a7713b1edbc 624 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 625 */
AnnaBridge 171:3a7713b1edbc 626 uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge 171:3a7713b1edbc 627
AnnaBridge 171:3a7713b1edbc 628 /*!
AnnaBridge 171:3a7713b1edbc 629 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge 171:3a7713b1edbc 630 *
AnnaBridge 171:3a7713b1edbc 631 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 632 */
AnnaBridge 171:3a7713b1edbc 633 uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635 /*!
AnnaBridge 171:3a7713b1edbc 636 * @brief Set the clock configure in SIM module.
AnnaBridge 171:3a7713b1edbc 637 *
AnnaBridge 171:3a7713b1edbc 638 * This function sets system layer clock settings in SIM module.
AnnaBridge 171:3a7713b1edbc 639 *
AnnaBridge 171:3a7713b1edbc 640 * @param config Pointer to the configure structure.
AnnaBridge 171:3a7713b1edbc 641 */
AnnaBridge 171:3a7713b1edbc 642 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge 171:3a7713b1edbc 643
AnnaBridge 171:3a7713b1edbc 644 /*!
AnnaBridge 171:3a7713b1edbc 645 * @brief Set the system clock dividers in SIM to safe value.
AnnaBridge 171:3a7713b1edbc 646 *
AnnaBridge 171:3a7713b1edbc 647 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge 171:3a7713b1edbc 648 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge 171:3a7713b1edbc 649 * changes then the system level clocks may be out of range. This function could
AnnaBridge 171:3a7713b1edbc 650 * be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge 171:3a7713b1edbc 651 * range.
AnnaBridge 171:3a7713b1edbc 652 *
AnnaBridge 171:3a7713b1edbc 653 * @param config Pointer to the configure structure.
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655 static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge 171:3a7713b1edbc 656 {
AnnaBridge 171:3a7713b1edbc 657 SIM->CLKDIV1 = 0x00040000U;
AnnaBridge 171:3a7713b1edbc 658 }
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660 /*! @name MCG frequency functions. */
AnnaBridge 171:3a7713b1edbc 661 /*@{*/
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 /*!
AnnaBridge 171:3a7713b1edbc 664 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
AnnaBridge 171:3a7713b1edbc 665 *
AnnaBridge 171:3a7713b1edbc 666 * This function gets the MCG output clock frequency in Hz based on the current MCG
AnnaBridge 171:3a7713b1edbc 667 * register value.
AnnaBridge 171:3a7713b1edbc 668 *
AnnaBridge 171:3a7713b1edbc 669 * @return The frequency of MCGOUTCLK.
AnnaBridge 171:3a7713b1edbc 670 */
AnnaBridge 171:3a7713b1edbc 671 uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /*!
AnnaBridge 171:3a7713b1edbc 674 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
AnnaBridge 171:3a7713b1edbc 675 *
AnnaBridge 171:3a7713b1edbc 676 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
AnnaBridge 171:3a7713b1edbc 677 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
AnnaBridge 171:3a7713b1edbc 678 * disabled in low power state in other modes.
AnnaBridge 171:3a7713b1edbc 679 *
AnnaBridge 171:3a7713b1edbc 680 * @return The frequency of MCGFLLCLK.
AnnaBridge 171:3a7713b1edbc 681 */
AnnaBridge 171:3a7713b1edbc 682 uint32_t CLOCK_GetFllFreq(void);
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /*!
AnnaBridge 171:3a7713b1edbc 685 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge 171:3a7713b1edbc 686 *
AnnaBridge 171:3a7713b1edbc 687 * This function gets the MCG internal reference clock frequency in Hz based
AnnaBridge 171:3a7713b1edbc 688 * on the current MCG register value.
AnnaBridge 171:3a7713b1edbc 689 *
AnnaBridge 171:3a7713b1edbc 690 * @return The frequency of MCGIRCLK.
AnnaBridge 171:3a7713b1edbc 691 */
AnnaBridge 171:3a7713b1edbc 692 uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /*!
AnnaBridge 171:3a7713b1edbc 695 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
AnnaBridge 171:3a7713b1edbc 696 *
AnnaBridge 171:3a7713b1edbc 697 * This function gets the MCG fixed frequency clock frequency in Hz based
AnnaBridge 171:3a7713b1edbc 698 * on the current MCG register value.
AnnaBridge 171:3a7713b1edbc 699 *
AnnaBridge 171:3a7713b1edbc 700 * @return The frequency of MCGFFCLK.
AnnaBridge 171:3a7713b1edbc 701 */
AnnaBridge 171:3a7713b1edbc 702 uint32_t CLOCK_GetFixedFreqClkFreq(void);
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704 /*@}*/
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 /*! @name MCG clock configuration. */
AnnaBridge 171:3a7713b1edbc 707 /*@{*/
AnnaBridge 171:3a7713b1edbc 708
AnnaBridge 171:3a7713b1edbc 709 /*!
AnnaBridge 171:3a7713b1edbc 710 * @brief Enables or disables the MCG low power.
AnnaBridge 171:3a7713b1edbc 711 *
AnnaBridge 171:3a7713b1edbc 712 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
AnnaBridge 171:3a7713b1edbc 713 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
AnnaBridge 171:3a7713b1edbc 714 * PBI modes, enabling low power sets the MCG to BLPI mode.
AnnaBridge 171:3a7713b1edbc 715 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
AnnaBridge 171:3a7713b1edbc 716 *
AnnaBridge 171:3a7713b1edbc 717 * @param enable True to enable MCG low power, false to disable MCG low power.
AnnaBridge 171:3a7713b1edbc 718 */
AnnaBridge 171:3a7713b1edbc 719 static inline void CLOCK_SetLowPowerEnable(bool enable)
AnnaBridge 171:3a7713b1edbc 720 {
AnnaBridge 171:3a7713b1edbc 721 if (enable)
AnnaBridge 171:3a7713b1edbc 722 {
AnnaBridge 171:3a7713b1edbc 723 MCG->C2 |= MCG_C2_LP_MASK;
AnnaBridge 171:3a7713b1edbc 724 }
AnnaBridge 171:3a7713b1edbc 725 else
AnnaBridge 171:3a7713b1edbc 726 {
AnnaBridge 171:3a7713b1edbc 727 MCG->C2 &= ~MCG_C2_LP_MASK;
AnnaBridge 171:3a7713b1edbc 728 }
AnnaBridge 171:3a7713b1edbc 729 }
AnnaBridge 171:3a7713b1edbc 730
AnnaBridge 171:3a7713b1edbc 731 /*!
AnnaBridge 171:3a7713b1edbc 732 * @brief Configures the Internal Reference clock (MCGIRCLK).
AnnaBridge 171:3a7713b1edbc 733 *
AnnaBridge 171:3a7713b1edbc 734 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
AnnaBridge 171:3a7713b1edbc 735 * source. If the fast IRC is used, this function sets the fast IRC divider.
AnnaBridge 171:3a7713b1edbc 736 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
AnnaBridge 171:3a7713b1edbc 737 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
AnnaBridge 171:3a7713b1edbc 738 * using the function in these modes it is not allowed.
AnnaBridge 171:3a7713b1edbc 739 *
AnnaBridge 171:3a7713b1edbc 740 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge 171:3a7713b1edbc 741 * @param ircs MCGIRCLK clock source, choose fast or slow.
AnnaBridge 171:3a7713b1edbc 742 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
AnnaBridge 171:3a7713b1edbc 743 * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
AnnaBridge 171:3a7713b1edbc 744 * the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge 171:3a7713b1edbc 745 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
AnnaBridge 171:3a7713b1edbc 746 */
AnnaBridge 171:3a7713b1edbc 747 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
AnnaBridge 171:3a7713b1edbc 748
AnnaBridge 171:3a7713b1edbc 749 /*!
AnnaBridge 171:3a7713b1edbc 750 * @brief Selects the MCG external reference clock.
AnnaBridge 171:3a7713b1edbc 751 *
AnnaBridge 171:3a7713b1edbc 752 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
AnnaBridge 171:3a7713b1edbc 753 * and waits for the clock source to be stable. Because the external reference
AnnaBridge 171:3a7713b1edbc 754 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
AnnaBridge 171:3a7713b1edbc 755 *
AnnaBridge 171:3a7713b1edbc 756 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
AnnaBridge 171:3a7713b1edbc 757 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
AnnaBridge 171:3a7713b1edbc 758 * the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge 171:3a7713b1edbc 759 * @retval kStatus_Success External reference clock set successfully.
AnnaBridge 171:3a7713b1edbc 760 */
AnnaBridge 171:3a7713b1edbc 761 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 /*!
AnnaBridge 171:3a7713b1edbc 764 * @brief Set the FLL external reference clock divider value.
AnnaBridge 171:3a7713b1edbc 765 *
AnnaBridge 171:3a7713b1edbc 766 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
AnnaBridge 171:3a7713b1edbc 767 *
AnnaBridge 171:3a7713b1edbc 768 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
AnnaBridge 171:3a7713b1edbc 769 */
AnnaBridge 171:3a7713b1edbc 770 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
AnnaBridge 171:3a7713b1edbc 771 {
AnnaBridge 171:3a7713b1edbc 772 MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv);
AnnaBridge 171:3a7713b1edbc 773 }
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775 /*@}*/
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 /*! @name MCG clock lock monitor functions. */
AnnaBridge 171:3a7713b1edbc 778 /*@{*/
AnnaBridge 171:3a7713b1edbc 779
AnnaBridge 171:3a7713b1edbc 780 /*!
AnnaBridge 171:3a7713b1edbc 781 * @brief Sets the RTC OSC clock monitor mode.
AnnaBridge 171:3a7713b1edbc 782 *
AnnaBridge 171:3a7713b1edbc 783 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge 171:3a7713b1edbc 784 *
AnnaBridge 171:3a7713b1edbc 785 * @param mode Monitor mode to set.
AnnaBridge 171:3a7713b1edbc 786 */
AnnaBridge 171:3a7713b1edbc 787 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
AnnaBridge 171:3a7713b1edbc 788
AnnaBridge 171:3a7713b1edbc 789 /*!
AnnaBridge 171:3a7713b1edbc 790 * @brief Gets the MCG status flags.
AnnaBridge 171:3a7713b1edbc 791 *
AnnaBridge 171:3a7713b1edbc 792 * This function gets the MCG clock status flags. All status flags are
AnnaBridge 171:3a7713b1edbc 793 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
AnnaBridge 171:3a7713b1edbc 794 * check a specific flag, compare the return value with the flag.
AnnaBridge 171:3a7713b1edbc 795 *
AnnaBridge 171:3a7713b1edbc 796 * Example:
AnnaBridge 171:3a7713b1edbc 797 * @code
AnnaBridge 171:3a7713b1edbc 798 // To check the clock lost lock status of OSC0 and PLL0.
AnnaBridge 171:3a7713b1edbc 799 uint32_t mcgFlags;
AnnaBridge 171:3a7713b1edbc 800
AnnaBridge 171:3a7713b1edbc 801 mcgFlags = CLOCK_GetStatusFlags();
AnnaBridge 171:3a7713b1edbc 802
AnnaBridge 171:3a7713b1edbc 803 if (mcgFlags & kMCG_Osc0LostFlag)
AnnaBridge 171:3a7713b1edbc 804 {
AnnaBridge 171:3a7713b1edbc 805 // OSC0 clock lock lost. Do something.
AnnaBridge 171:3a7713b1edbc 806 }
AnnaBridge 171:3a7713b1edbc 807 if (mcgFlags & kMCG_Pll0LostFlag)
AnnaBridge 171:3a7713b1edbc 808 {
AnnaBridge 171:3a7713b1edbc 809 // PLL0 clock lock lost. Do something.
AnnaBridge 171:3a7713b1edbc 810 }
AnnaBridge 171:3a7713b1edbc 811 @endcode
AnnaBridge 171:3a7713b1edbc 812 *
AnnaBridge 171:3a7713b1edbc 813 * @return Logical OR value of the @ref _mcg_status_flags_t.
AnnaBridge 171:3a7713b1edbc 814 */
AnnaBridge 171:3a7713b1edbc 815 uint32_t CLOCK_GetStatusFlags(void);
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817 /*!
AnnaBridge 171:3a7713b1edbc 818 * @brief Clears the MCG status flags.
AnnaBridge 171:3a7713b1edbc 819 *
AnnaBridge 171:3a7713b1edbc 820 * This function clears the MCG clock lock lost status. The parameter is a logical
AnnaBridge 171:3a7713b1edbc 821 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
AnnaBridge 171:3a7713b1edbc 822 *
AnnaBridge 171:3a7713b1edbc 823 * Example:
AnnaBridge 171:3a7713b1edbc 824 * @code
AnnaBridge 171:3a7713b1edbc 825 // To clear the clock lost lock status flags of OSC0 and PLL0.
AnnaBridge 171:3a7713b1edbc 826
AnnaBridge 171:3a7713b1edbc 827 CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
AnnaBridge 171:3a7713b1edbc 828 @endcode
AnnaBridge 171:3a7713b1edbc 829 *
AnnaBridge 171:3a7713b1edbc 830 * @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 831 * enumeration @ref _mcg_status_flags_t.
AnnaBridge 171:3a7713b1edbc 832 */
AnnaBridge 171:3a7713b1edbc 833 void CLOCK_ClearStatusFlags(uint32_t mask);
AnnaBridge 171:3a7713b1edbc 834
AnnaBridge 171:3a7713b1edbc 835 /*@}*/
AnnaBridge 171:3a7713b1edbc 836
AnnaBridge 171:3a7713b1edbc 837 /*!
AnnaBridge 171:3a7713b1edbc 838 * @name OSC configuration
AnnaBridge 171:3a7713b1edbc 839 * @{
AnnaBridge 171:3a7713b1edbc 840 */
AnnaBridge 171:3a7713b1edbc 841
AnnaBridge 171:3a7713b1edbc 842 /*!
AnnaBridge 171:3a7713b1edbc 843 * @brief Initializes the OSC0.
AnnaBridge 171:3a7713b1edbc 844 *
AnnaBridge 171:3a7713b1edbc 845 * This function initializes the OSC0 according to the board configuration.
AnnaBridge 171:3a7713b1edbc 846 *
AnnaBridge 171:3a7713b1edbc 847 * @param config Pointer to the OSC0 configuration structure.
AnnaBridge 171:3a7713b1edbc 848 */
AnnaBridge 171:3a7713b1edbc 849 void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge 171:3a7713b1edbc 850
AnnaBridge 171:3a7713b1edbc 851 /*!
AnnaBridge 171:3a7713b1edbc 852 * @brief Deinitializes the OSC0.
AnnaBridge 171:3a7713b1edbc 853 *
AnnaBridge 171:3a7713b1edbc 854 * This function deinitializes the OSC0.
AnnaBridge 171:3a7713b1edbc 855 */
AnnaBridge 171:3a7713b1edbc 856 void CLOCK_DeinitOsc0(void);
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /* @} */
AnnaBridge 171:3a7713b1edbc 859
AnnaBridge 171:3a7713b1edbc 860 /*!
AnnaBridge 171:3a7713b1edbc 861 * @name External clock frequency
AnnaBridge 171:3a7713b1edbc 862 * @{
AnnaBridge 171:3a7713b1edbc 863 */
AnnaBridge 171:3a7713b1edbc 864
AnnaBridge 171:3a7713b1edbc 865 /*!
AnnaBridge 171:3a7713b1edbc 866 * @brief Sets the XTAL0 frequency based on board settings.
AnnaBridge 171:3a7713b1edbc 867 *
AnnaBridge 171:3a7713b1edbc 868 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 869 */
AnnaBridge 171:3a7713b1edbc 870 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge 171:3a7713b1edbc 871 {
AnnaBridge 171:3a7713b1edbc 872 g_xtal0Freq = freq;
AnnaBridge 171:3a7713b1edbc 873 }
AnnaBridge 171:3a7713b1edbc 874
AnnaBridge 171:3a7713b1edbc 875 /*!
AnnaBridge 171:3a7713b1edbc 876 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
AnnaBridge 171:3a7713b1edbc 877 *
AnnaBridge 171:3a7713b1edbc 878 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 879 */
AnnaBridge 171:3a7713b1edbc 880 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge 171:3a7713b1edbc 881 {
AnnaBridge 171:3a7713b1edbc 882 g_xtal32Freq = freq;
AnnaBridge 171:3a7713b1edbc 883 }
AnnaBridge 171:3a7713b1edbc 884 /* @} */
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 /*!
AnnaBridge 171:3a7713b1edbc 887 * @name MCG auto-trim machine.
AnnaBridge 171:3a7713b1edbc 888 * @{
AnnaBridge 171:3a7713b1edbc 889 */
AnnaBridge 171:3a7713b1edbc 890
AnnaBridge 171:3a7713b1edbc 891 /*!
AnnaBridge 171:3a7713b1edbc 892 * @brief Auto trims the internal reference clock.
AnnaBridge 171:3a7713b1edbc 893 *
AnnaBridge 171:3a7713b1edbc 894 * This function trims the internal reference clock by using the external clock. If
AnnaBridge 171:3a7713b1edbc 895 * successful, it returns the kStatus_Success and the frequency after
AnnaBridge 171:3a7713b1edbc 896 * trimming is received in the parameter @p actualFreq. If an error occurs,
AnnaBridge 171:3a7713b1edbc 897 * the error code is returned.
AnnaBridge 171:3a7713b1edbc 898 *
AnnaBridge 171:3a7713b1edbc 899 * @param extFreq External clock frequency, which should be a bus clock.
AnnaBridge 171:3a7713b1edbc 900 * @param desireFreq Frequency to trim to.
AnnaBridge 171:3a7713b1edbc 901 * @param actualFreq Actual frequency after trimming.
AnnaBridge 171:3a7713b1edbc 902 * @param atms Trim fast or slow internal reference clock.
AnnaBridge 171:3a7713b1edbc 903 * @retval kStatus_Success ATM success.
AnnaBridge 171:3a7713b1edbc 904 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
AnnaBridge 171:3a7713b1edbc 905 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
AnnaBridge 171:3a7713b1edbc 906 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
AnnaBridge 171:3a7713b1edbc 907 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
AnnaBridge 171:3a7713b1edbc 908 */
AnnaBridge 171:3a7713b1edbc 909 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
AnnaBridge 171:3a7713b1edbc 910 /* @} */
AnnaBridge 171:3a7713b1edbc 911
AnnaBridge 171:3a7713b1edbc 912 /*! @name MCG mode functions. */
AnnaBridge 171:3a7713b1edbc 913 /*@{*/
AnnaBridge 171:3a7713b1edbc 914
AnnaBridge 171:3a7713b1edbc 915 /*!
AnnaBridge 171:3a7713b1edbc 916 * @brief Gets the current MCG mode.
AnnaBridge 171:3a7713b1edbc 917 *
AnnaBridge 171:3a7713b1edbc 918 * This function checks the MCG registers and determines the current MCG mode.
AnnaBridge 171:3a7713b1edbc 919 *
AnnaBridge 171:3a7713b1edbc 920 * @return Current MCG mode or error code; See @ref mcg_mode_t.
AnnaBridge 171:3a7713b1edbc 921 */
AnnaBridge 171:3a7713b1edbc 922 mcg_mode_t CLOCK_GetMode(void);
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924 /*!
AnnaBridge 171:3a7713b1edbc 925 * @brief Sets the MCG to FEI mode.
AnnaBridge 171:3a7713b1edbc 926 *
AnnaBridge 171:3a7713b1edbc 927 * This function sets the MCG to FEI mode. If setting to FEI mode fails
AnnaBridge 171:3a7713b1edbc 928 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 929 *
AnnaBridge 171:3a7713b1edbc 930 * @param dmx32 DMX32 in FEI mode.
AnnaBridge 171:3a7713b1edbc 931 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 932 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
AnnaBridge 171:3a7713b1edbc 933 * NULL does not cause a delay.
AnnaBridge 171:3a7713b1edbc 934 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 935 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 936 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 171:3a7713b1edbc 937 * to a frequency above 32768 Hz.
AnnaBridge 171:3a7713b1edbc 938 */
AnnaBridge 171:3a7713b1edbc 939 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 /*!
AnnaBridge 171:3a7713b1edbc 942 * @brief Sets the MCG to FEE mode.
AnnaBridge 171:3a7713b1edbc 943 *
AnnaBridge 171:3a7713b1edbc 944 * This function sets the MCG to FEE mode. If setting to FEE mode fails
AnnaBridge 171:3a7713b1edbc 945 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 946 *
AnnaBridge 171:3a7713b1edbc 947 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 171:3a7713b1edbc 948 * @param dmx32 DMX32 in FEE mode.
AnnaBridge 171:3a7713b1edbc 949 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 950 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
AnnaBridge 171:3a7713b1edbc 951 * NULL does not cause a delay.
AnnaBridge 171:3a7713b1edbc 952 *
AnnaBridge 171:3a7713b1edbc 953 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 954 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 955 */
AnnaBridge 171:3a7713b1edbc 956 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 957
AnnaBridge 171:3a7713b1edbc 958 /*!
AnnaBridge 171:3a7713b1edbc 959 * @brief Sets the MCG to FBI mode.
AnnaBridge 171:3a7713b1edbc 960 *
AnnaBridge 171:3a7713b1edbc 961 * This function sets the MCG to FBI mode. If setting to FBI mode fails
AnnaBridge 171:3a7713b1edbc 962 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 963 *
AnnaBridge 171:3a7713b1edbc 964 * @param dmx32 DMX32 in FBI mode.
AnnaBridge 171:3a7713b1edbc 965 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 966 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge 171:3a7713b1edbc 967 * is not used in FBI mode, this parameter can be NULL. Passing
AnnaBridge 171:3a7713b1edbc 968 * NULL does not cause a delay.
AnnaBridge 171:3a7713b1edbc 969 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 970 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 971 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 171:3a7713b1edbc 972 * to frequency above 32768 Hz.
AnnaBridge 171:3a7713b1edbc 973 */
AnnaBridge 171:3a7713b1edbc 974 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /*!
AnnaBridge 171:3a7713b1edbc 977 * @brief Sets the MCG to FBE mode.
AnnaBridge 171:3a7713b1edbc 978 *
AnnaBridge 171:3a7713b1edbc 979 * This function sets the MCG to FBE mode. If setting to FBE mode fails
AnnaBridge 171:3a7713b1edbc 980 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 981 *
AnnaBridge 171:3a7713b1edbc 982 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 171:3a7713b1edbc 983 * @param dmx32 DMX32 in FBE mode.
AnnaBridge 171:3a7713b1edbc 984 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 985 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge 171:3a7713b1edbc 986 * is not used in FBE mode, this parameter can be NULL. Passing NULL
AnnaBridge 171:3a7713b1edbc 987 * does not cause a delay.
AnnaBridge 171:3a7713b1edbc 988 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 989 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 990 */
AnnaBridge 171:3a7713b1edbc 991 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 992
AnnaBridge 171:3a7713b1edbc 993 /*!
AnnaBridge 171:3a7713b1edbc 994 * @brief Sets the MCG to BLPI mode.
AnnaBridge 171:3a7713b1edbc 995 *
AnnaBridge 171:3a7713b1edbc 996 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
AnnaBridge 171:3a7713b1edbc 997 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 998 *
AnnaBridge 171:3a7713b1edbc 999 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1000 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1001 */
AnnaBridge 171:3a7713b1edbc 1002 status_t CLOCK_SetBlpiMode(void);
AnnaBridge 171:3a7713b1edbc 1003
AnnaBridge 171:3a7713b1edbc 1004 /*!
AnnaBridge 171:3a7713b1edbc 1005 * @brief Sets the MCG to BLPE mode.
AnnaBridge 171:3a7713b1edbc 1006 *
AnnaBridge 171:3a7713b1edbc 1007 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
AnnaBridge 171:3a7713b1edbc 1008 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1009 *
AnnaBridge 171:3a7713b1edbc 1010 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1011 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1012 */
AnnaBridge 171:3a7713b1edbc 1013 status_t CLOCK_SetBlpeMode(void);
AnnaBridge 171:3a7713b1edbc 1014
AnnaBridge 171:3a7713b1edbc 1015 /*!
AnnaBridge 171:3a7713b1edbc 1016 * @brief Switches the MCG to FBE mode from the external mode.
AnnaBridge 171:3a7713b1edbc 1017 *
AnnaBridge 171:3a7713b1edbc 1018 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
AnnaBridge 171:3a7713b1edbc 1019 * The external clock is used as the system clock souce and PLL is disabled. However,
AnnaBridge 171:3a7713b1edbc 1020 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge 171:3a7713b1edbc 1021 * during the mode switch. For example, to switch from PEE mode to FEI mode:
AnnaBridge 171:3a7713b1edbc 1022 *
AnnaBridge 171:3a7713b1edbc 1023 * @code
AnnaBridge 171:3a7713b1edbc 1024 * CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge 171:3a7713b1edbc 1025 * CLOCK_SetFeiMode(...);
AnnaBridge 171:3a7713b1edbc 1026 * @endcode
AnnaBridge 171:3a7713b1edbc 1027 *
AnnaBridge 171:3a7713b1edbc 1028 * @retval kStatus_Success Switched successfully.
AnnaBridge 171:3a7713b1edbc 1029 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
AnnaBridge 171:3a7713b1edbc 1030 */
AnnaBridge 171:3a7713b1edbc 1031 status_t CLOCK_ExternalModeToFbeModeQuick(void);
AnnaBridge 171:3a7713b1edbc 1032
AnnaBridge 171:3a7713b1edbc 1033 /*!
AnnaBridge 171:3a7713b1edbc 1034 * @brief Switches the MCG to FBI mode from internal modes.
AnnaBridge 171:3a7713b1edbc 1035 *
AnnaBridge 171:3a7713b1edbc 1036 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
AnnaBridge 171:3a7713b1edbc 1037 * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
AnnaBridge 171:3a7713b1edbc 1038 * FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge 171:3a7713b1edbc 1039 * during the mode switch. For example, to switch from PEI mode to FEE mode:
AnnaBridge 171:3a7713b1edbc 1040 *
AnnaBridge 171:3a7713b1edbc 1041 * @code
AnnaBridge 171:3a7713b1edbc 1042 * CLOCK_InternalModeToFbiModeQuick();
AnnaBridge 171:3a7713b1edbc 1043 * CLOCK_SetFeeMode(...);
AnnaBridge 171:3a7713b1edbc 1044 * @endcode
AnnaBridge 171:3a7713b1edbc 1045 *
AnnaBridge 171:3a7713b1edbc 1046 * @retval kStatus_Success Switched successfully.
AnnaBridge 171:3a7713b1edbc 1047 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
AnnaBridge 171:3a7713b1edbc 1048 */
AnnaBridge 171:3a7713b1edbc 1049 status_t CLOCK_InternalModeToFbiModeQuick(void);
AnnaBridge 171:3a7713b1edbc 1050
AnnaBridge 171:3a7713b1edbc 1051 /*!
AnnaBridge 171:3a7713b1edbc 1052 * @brief Sets the MCG to FEI mode during system boot up.
AnnaBridge 171:3a7713b1edbc 1053 *
AnnaBridge 171:3a7713b1edbc 1054 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1055 * set up MCG during system boot up.
AnnaBridge 171:3a7713b1edbc 1056 *
AnnaBridge 171:3a7713b1edbc 1057 * @param dmx32 DMX32 in FEI mode.
AnnaBridge 171:3a7713b1edbc 1058 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1059 * @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge 171:3a7713b1edbc 1060 *
AnnaBridge 171:3a7713b1edbc 1061 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1062 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1063 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 171:3a7713b1edbc 1064 * to frequency above 32768 Hz.
AnnaBridge 171:3a7713b1edbc 1065 */
AnnaBridge 171:3a7713b1edbc 1066 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1067
AnnaBridge 171:3a7713b1edbc 1068 /*!
AnnaBridge 171:3a7713b1edbc 1069 * @brief Sets the MCG to FEE mode during system bootup.
AnnaBridge 171:3a7713b1edbc 1070 *
AnnaBridge 171:3a7713b1edbc 1071 * This function sets MCG to FEE mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1072 * set up the MCG during system boot up.
AnnaBridge 171:3a7713b1edbc 1073 *
AnnaBridge 171:3a7713b1edbc 1074 * @param oscsel OSC clock select, OSCSEL.
AnnaBridge 171:3a7713b1edbc 1075 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 171:3a7713b1edbc 1076 * @param dmx32 DMX32 in FEE mode.
AnnaBridge 171:3a7713b1edbc 1077 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1078 * @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge 171:3a7713b1edbc 1079 *
AnnaBridge 171:3a7713b1edbc 1080 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1081 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1082 */
AnnaBridge 171:3a7713b1edbc 1083 status_t CLOCK_BootToFeeMode(
AnnaBridge 171:3a7713b1edbc 1084 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086 /*!
AnnaBridge 171:3a7713b1edbc 1087 * @brief Sets the MCG to BLPI mode during system boot up.
AnnaBridge 171:3a7713b1edbc 1088 *
AnnaBridge 171:3a7713b1edbc 1089 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1090 * set up the MCG during sytem boot up.
AnnaBridge 171:3a7713b1edbc 1091 *
AnnaBridge 171:3a7713b1edbc 1092 * @param fcrdiv Fast IRC divider, FCRDIV.
AnnaBridge 171:3a7713b1edbc 1093 * @param ircs The internal reference clock to select, IRCS.
AnnaBridge 171:3a7713b1edbc 1094 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge 171:3a7713b1edbc 1095 *
AnnaBridge 171:3a7713b1edbc 1096 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
AnnaBridge 171:3a7713b1edbc 1097 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1098 */
AnnaBridge 171:3a7713b1edbc 1099 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
AnnaBridge 171:3a7713b1edbc 1100
AnnaBridge 171:3a7713b1edbc 1101 /*!
AnnaBridge 171:3a7713b1edbc 1102 * @brief Sets the MCG to BLPE mode during sytem boot up.
AnnaBridge 171:3a7713b1edbc 1103 *
AnnaBridge 171:3a7713b1edbc 1104 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1105 * set up the MCG during sytem boot up.
AnnaBridge 171:3a7713b1edbc 1106 *
AnnaBridge 171:3a7713b1edbc 1107 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge 171:3a7713b1edbc 1108 *
AnnaBridge 171:3a7713b1edbc 1109 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1110 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1111 */
AnnaBridge 171:3a7713b1edbc 1112 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
AnnaBridge 171:3a7713b1edbc 1113
AnnaBridge 171:3a7713b1edbc 1114 /*!
AnnaBridge 171:3a7713b1edbc 1115 * @brief Sets the MCG to a target mode.
AnnaBridge 171:3a7713b1edbc 1116 *
AnnaBridge 171:3a7713b1edbc 1117 * This function sets MCG to a target mode defined by the configuration
AnnaBridge 171:3a7713b1edbc 1118 * structure. If switching to the target mode fails, this function
AnnaBridge 171:3a7713b1edbc 1119 * chooses the correct path.
AnnaBridge 171:3a7713b1edbc 1120 *
AnnaBridge 171:3a7713b1edbc 1121 * @param config Pointer to the target MCG mode configuration structure.
AnnaBridge 171:3a7713b1edbc 1122 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
AnnaBridge 171:3a7713b1edbc 1123 *
AnnaBridge 171:3a7713b1edbc 1124 * @note If the external clock is used in the target mode, ensure that it is
AnnaBridge 171:3a7713b1edbc 1125 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
AnnaBridge 171:3a7713b1edbc 1126 * function.
AnnaBridge 171:3a7713b1edbc 1127 */
AnnaBridge 171:3a7713b1edbc 1128 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
AnnaBridge 171:3a7713b1edbc 1129
AnnaBridge 171:3a7713b1edbc 1130 /*@}*/
AnnaBridge 171:3a7713b1edbc 1131
AnnaBridge 171:3a7713b1edbc 1132 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 1133 }
AnnaBridge 171:3a7713b1edbc 1134 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 1135
AnnaBridge 171:3a7713b1edbc 1136 /*! @} */
AnnaBridge 171:3a7713b1edbc 1137
AnnaBridge 171:3a7713b1edbc 1138 #endif /* _FSL_CLOCK_H_ */