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TARGET_K82F/TOOLCHAIN_GCC_ARM/fsl_dspi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/*
AnnaBridge	145:64910690c574	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	145:64910690c574	3	* All rights reserved.
AnnaBridge	145:64910690c574	4	*
AnnaBridge	145:64910690c574	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	6	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	7	*
AnnaBridge	145:64910690c574	8	* o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	145:64910690c574	9	* of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	145:64910690c574	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	145:64910690c574	13	* other materials provided with the distribution.
AnnaBridge	145:64910690c574	14	*
AnnaBridge	145:64910690c574	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	145:64910690c574	16	* contributors may be used to endorse or promote products derived from this
AnnaBridge	145:64910690c574	17	* software without specific prior written permission.
AnnaBridge	145:64910690c574	18	*
AnnaBridge	145:64910690c574	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	145:64910690c574	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	145:64910690c574	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	145:64910690c574	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	145:64910690c574	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	145:64910690c574	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	145:64910690c574	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	145:64910690c574	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	145:64910690c574	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	29	*/
AnnaBridge	145:64910690c574	30	#ifndef _FSL_DSPI_H_
AnnaBridge	145:64910690c574	31	#define _FSL_DSPI_H_
AnnaBridge	145:64910690c574	32
AnnaBridge	145:64910690c574	33	#include "fsl_common.h"
AnnaBridge	145:64910690c574	34
AnnaBridge	145:64910690c574	35	/*!
AnnaBridge	145:64910690c574	36	* @addtogroup dspi_driver
AnnaBridge	145:64910690c574	37	* @{
AnnaBridge	145:64910690c574	38	*/
AnnaBridge	145:64910690c574	39
AnnaBridge	145:64910690c574	40
AnnaBridge	145:64910690c574	41	/**********************************************************************************************************************
AnnaBridge	145:64910690c574	42	* Definitions
AnnaBridge	145:64910690c574	43	*********************************************************************************************************************/
AnnaBridge	145:64910690c574	44
AnnaBridge	145:64910690c574	45	/! @name Driver version /
AnnaBridge	145:64910690c574	46	/@{/
AnnaBridge	145:64910690c574	47	/! @brief DSPI driver version 2.1.3. /
AnnaBridge	145:64910690c574	48	#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
AnnaBridge	145:64910690c574	49	/@}/
AnnaBridge	145:64910690c574	50
AnnaBridge	145:64910690c574	51	#ifndef DSPI_DUMMY_DATA
AnnaBridge	145:64910690c574	52	/! @brief DSPI dummy data if there is no Tx data./
AnnaBridge	145:64910690c574	53	#define DSPI_DUMMY_DATA (0x00U) /!< Dummy data used for Tx if there is no txData. /
AnnaBridge	145:64910690c574	54	#endif
AnnaBridge	145:64910690c574	55
AnnaBridge	145:64910690c574	56	/! @brief Status for the DSPI driver./
AnnaBridge	145:64910690c574	57	enum _dspi_status
AnnaBridge	145:64910690c574	58	{
AnnaBridge	145:64910690c574	59	kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /!< DSPI transfer is busy./
AnnaBridge	145:64910690c574	60	kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /!< DSPI driver error. /
AnnaBridge	145:64910690c574	61	kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /!< DSPI is idle./
AnnaBridge	145:64910690c574	62	kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /!< DSPI transfer out of range. /
AnnaBridge	145:64910690c574	63	};
AnnaBridge	145:64910690c574	64
AnnaBridge	145:64910690c574	65	/! @brief DSPI status flags in SPIx_SR register./
AnnaBridge	145:64910690c574	66	enum _dspi_flags
AnnaBridge	145:64910690c574	67	{
AnnaBridge	145:64910690c574	68	kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /!< Transfer Complete Flag. /
AnnaBridge	145:64910690c574	69	kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /!< End of Queue Flag./
AnnaBridge	145:64910690c574	70	kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /!< Transmit FIFO Underflow Flag./
AnnaBridge	145:64910690c574	71	kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /!< Transmit FIFO Fill Flag./
AnnaBridge	145:64910690c574	72	kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /!< Receive FIFO Overflow Flag./
AnnaBridge	145:64910690c574	73	kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /!< Receive FIFO Drain Flag./
AnnaBridge	145:64910690c574	74	kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /!< The module is in Stopped/Running state./
AnnaBridge	145:64910690c574	75	kDSPI_AllStatusFlag = SPI_SR_TCF_MASK \| SPI_SR_EOQF_MASK \| SPI_SR_TFUF_MASK \| SPI_SR_TFFF_MASK \| SPI_SR_RFOF_MASK \|
AnnaBridge	145:64910690c574	76	SPI_SR_RFDF_MASK \| SPI_SR_TXRXS_MASK /!< All statuses above./
AnnaBridge	145:64910690c574	77	};
AnnaBridge	145:64910690c574	78
AnnaBridge	145:64910690c574	79	/! @brief DSPI interrupt source./
AnnaBridge	145:64910690c574	80	enum _dspi_interrupt_enable
AnnaBridge	145:64910690c574	81	{
AnnaBridge	145:64910690c574	82	kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /!< TCF interrupt enable./
AnnaBridge	145:64910690c574	83	kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /!< EOQF interrupt enable./
AnnaBridge	145:64910690c574	84	kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /!< TFUF interrupt enable./
AnnaBridge	145:64910690c574	85	kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /!< TFFF interrupt enable, DMA disable./
AnnaBridge	145:64910690c574	86	kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /!< RFOF interrupt enable./
AnnaBridge	145:64910690c574	87	kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /!< RFDF interrupt enable, DMA disable./
AnnaBridge	145:64910690c574	88	kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK \| SPI_RSER_EOQF_RE_MASK \| SPI_RSER_TFUF_RE_MASK \|
AnnaBridge	145:64910690c574	89	SPI_RSER_TFFF_RE_MASK \| SPI_RSER_RFOF_RE_MASK \| SPI_RSER_RFDF_RE_MASK
AnnaBridge	145:64910690c574	90	/!< All above interrupts enable./
AnnaBridge	145:64910690c574	91	};
AnnaBridge	145:64910690c574	92
AnnaBridge	145:64910690c574	93	/! @brief DSPI DMA source./
AnnaBridge	145:64910690c574	94	enum _dspi_dma_enable
AnnaBridge	145:64910690c574	95	{
AnnaBridge	145:64910690c574	96	kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK \| SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests.
AnnaBridge	145:64910690c574	97	No Tx interrupt request. */
AnnaBridge	145:64910690c574	98	kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK \| SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests.
AnnaBridge	145:64910690c574	99	No Rx interrupt request. */
AnnaBridge	145:64910690c574	100	};
AnnaBridge	145:64910690c574	101
AnnaBridge	145:64910690c574	102	/! @brief DSPI master or slave mode configuration./
AnnaBridge	145:64910690c574	103	typedef enum _dspi_master_slave_mode
AnnaBridge	145:64910690c574	104	{
AnnaBridge	145:64910690c574	105	kDSPI_Master = 1U, /!< DSPI peripheral operates in master mode./
AnnaBridge	145:64910690c574	106	kDSPI_Slave = 0U /!< DSPI peripheral operates in slave mode./
AnnaBridge	145:64910690c574	107	} dspi_master_slave_mode_t;
AnnaBridge	145:64910690c574	108
AnnaBridge	145:64910690c574	109	/*!
AnnaBridge	145:64910690c574	110	* @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid
AnnaBridge	145:64910690c574	111	* only when the CPHA bit in the CTAR register is 0.
AnnaBridge	145:64910690c574	112	*/
AnnaBridge	145:64910690c574	113	typedef enum _dspi_master_sample_point
AnnaBridge	145:64910690c574	114	{
AnnaBridge	145:64910690c574	115	kDSPI_SckToSin0Clock = 0U, /!< 0 system clocks between SCK edge and SIN sample./
AnnaBridge	145:64910690c574	116	kDSPI_SckToSin1Clock = 1U, /!< 1 system clock between SCK edge and SIN sample./
AnnaBridge	145:64910690c574	117	kDSPI_SckToSin2Clock = 2U /!< 2 system clocks between SCK edge and SIN sample./
AnnaBridge	145:64910690c574	118	} dspi_master_sample_point_t;
AnnaBridge	145:64910690c574	119
AnnaBridge	145:64910690c574	120	/! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure)./
AnnaBridge	145:64910690c574	121	typedef enum _dspi_which_pcs_config
AnnaBridge	145:64910690c574	122	{
AnnaBridge	145:64910690c574	123	kDSPI_Pcs0 = 1U << 0, /!< Pcs[0] /
AnnaBridge	145:64910690c574	124	kDSPI_Pcs1 = 1U << 1, /!< Pcs[1] /
AnnaBridge	145:64910690c574	125	kDSPI_Pcs2 = 1U << 2, /!< Pcs[2] /
AnnaBridge	145:64910690c574	126	kDSPI_Pcs3 = 1U << 3, /!< Pcs[3] /
AnnaBridge	145:64910690c574	127	kDSPI_Pcs4 = 1U << 4, /!< Pcs[4] /
AnnaBridge	145:64910690c574	128	kDSPI_Pcs5 = 1U << 5 /!< Pcs[5] /
AnnaBridge	145:64910690c574	129	} dspi_which_pcs_t;
AnnaBridge	145:64910690c574	130
AnnaBridge	145:64910690c574	131	/! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration./
AnnaBridge	145:64910690c574	132	typedef enum _dspi_pcs_polarity_config
AnnaBridge	145:64910690c574	133	{
AnnaBridge	145:64910690c574	134	kDSPI_PcsActiveHigh = 0U, /!< Pcs Active High (idles low). /
AnnaBridge	145:64910690c574	135	kDSPI_PcsActiveLow = 1U /!< Pcs Active Low (idles high). /
AnnaBridge	145:64910690c574	136	} dspi_pcs_polarity_config_t;
AnnaBridge	145:64910690c574	137
AnnaBridge	145:64910690c574	138	/! @brief DSPI Peripheral Chip Select (Pcs) Polarity./
AnnaBridge	145:64910690c574	139	enum _dspi_pcs_polarity
AnnaBridge	145:64910690c574	140	{
AnnaBridge	145:64910690c574	141	kDSPI_Pcs0ActiveLow = 1U << 0, /!< Pcs0 Active Low (idles high). /
AnnaBridge	145:64910690c574	142	kDSPI_Pcs1ActiveLow = 1U << 1, /!< Pcs1 Active Low (idles high). /
AnnaBridge	145:64910690c574	143	kDSPI_Pcs2ActiveLow = 1U << 2, /!< Pcs2 Active Low (idles high). /
AnnaBridge	145:64910690c574	144	kDSPI_Pcs3ActiveLow = 1U << 3, /!< Pcs3 Active Low (idles high). /
AnnaBridge	145:64910690c574	145	kDSPI_Pcs4ActiveLow = 1U << 4, /!< Pcs4 Active Low (idles high). /
AnnaBridge	145:64910690c574	146	kDSPI_Pcs5ActiveLow = 1U << 5, /!< Pcs5 Active Low (idles high). /
AnnaBridge	145:64910690c574	147	kDSPI_PcsAllActiveLow = 0xFFU /!< Pcs0 to Pcs5 Active Low (idles high). /
AnnaBridge	145:64910690c574	148	};
AnnaBridge	145:64910690c574	149
AnnaBridge	145:64910690c574	150	/! @brief DSPI clock polarity configuration for a given CTAR./
AnnaBridge	145:64910690c574	151	typedef enum _dspi_clock_polarity
AnnaBridge	145:64910690c574	152	{
AnnaBridge	145:64910690c574	153	kDSPI_ClockPolarityActiveHigh = 0U, /!< CPOL=0. Active-high DSPI clock (idles low)./
AnnaBridge	145:64910690c574	154	kDSPI_ClockPolarityActiveLow = 1U /!< CPOL=1. Active-low DSPI clock (idles high)./
AnnaBridge	145:64910690c574	155	} dspi_clock_polarity_t;
AnnaBridge	145:64910690c574	156
AnnaBridge	145:64910690c574	157	/! @brief DSPI clock phase configuration for a given CTAR./
AnnaBridge	145:64910690c574	158	typedef enum _dspi_clock_phase
AnnaBridge	145:64910690c574	159	{
AnnaBridge	145:64910690c574	160	kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
AnnaBridge	145:64910690c574	161	following edge.*/
AnnaBridge	145:64910690c574	162	kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
AnnaBridge	145:64910690c574	163	following edge.*/
AnnaBridge	145:64910690c574	164	} dspi_clock_phase_t;
AnnaBridge	145:64910690c574	165
AnnaBridge	145:64910690c574	166	/! @brief DSPI data shifter direction options for a given CTAR./
AnnaBridge	145:64910690c574	167	typedef enum _dspi_shift_direction
AnnaBridge	145:64910690c574	168	{
AnnaBridge	145:64910690c574	169	kDSPI_MsbFirst = 0U, /!< Data transfers start with most significant bit./
AnnaBridge	145:64910690c574	170	kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.
AnnaBridge	145:64910690c574	171	Shifting out of LSB is not supported for slave */
AnnaBridge	145:64910690c574	172	} dspi_shift_direction_t;
AnnaBridge	145:64910690c574	173
AnnaBridge	145:64910690c574	174	/! @brief DSPI delay type selection./
AnnaBridge	145:64910690c574	175	typedef enum _dspi_delay_type
AnnaBridge	145:64910690c574	176	{
AnnaBridge	145:64910690c574	177	kDSPI_PcsToSck = 1U, /!< Pcs-to-SCK delay. /
AnnaBridge	145:64910690c574	178	kDSPI_LastSckToPcs, /!< The last SCK edge to Pcs delay. /
AnnaBridge	145:64910690c574	179	kDSPI_BetweenTransfer /!< Delay between transfers. /
AnnaBridge	145:64910690c574	180	} dspi_delay_type_t;
AnnaBridge	145:64910690c574	181
AnnaBridge	145:64910690c574	182	/! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection./
AnnaBridge	145:64910690c574	183	typedef enum _dspi_ctar_selection
AnnaBridge	145:64910690c574	184	{
AnnaBridge	145:64910690c574	185	kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the
AnnaBridge	145:64910690c574	186	same register address. */
AnnaBridge	145:64910690c574	187	kDSPI_Ctar1 = 1U, /!< CTAR1 selection option for master mode only. /
AnnaBridge	145:64910690c574	188	kDSPI_Ctar2 = 2U, /!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. /
AnnaBridge	145:64910690c574	189	kDSPI_Ctar3 = 3U, /!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. /
AnnaBridge	145:64910690c574	190	kDSPI_Ctar4 = 4U, /!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. /
AnnaBridge	145:64910690c574	191	kDSPI_Ctar5 = 5U, /!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. /
AnnaBridge	145:64910690c574	192	kDSPI_Ctar6 = 6U, /!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. /
AnnaBridge	145:64910690c574	193	kDSPI_Ctar7 = 7U /!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. /
AnnaBridge	145:64910690c574	194	} dspi_ctar_selection_t;
AnnaBridge	145:64910690c574	195
AnnaBridge	145:64910690c574	196	#define DSPI_MASTER_CTAR_SHIFT (0U) /!< DSPI master CTAR shift macro; used internally. /
AnnaBridge	145:64910690c574	197	#define DSPI_MASTER_CTAR_MASK (0x0FU) /!< DSPI master CTAR mask macro; used internally. /
AnnaBridge	145:64910690c574	198	#define DSPI_MASTER_PCS_SHIFT (4U) /!< DSPI master PCS shift macro; used internally. /
AnnaBridge	145:64910690c574	199	#define DSPI_MASTER_PCS_MASK (0xF0U) /!< DSPI master PCS mask macro; used internally. /
AnnaBridge	145:64910690c574	200	/! @brief Use this enumeration for the DSPI master transfer configFlags. /
AnnaBridge	145:64910690c574	201	enum _dspi_transfer_config_flag_for_master
AnnaBridge	145:64910690c574	202	{
AnnaBridge	145:64910690c574	203	kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR0 setting. /
AnnaBridge	145:64910690c574	204	kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR1 setting. /
AnnaBridge	145:64910690c574	205	kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR2 setting. /
AnnaBridge	145:64910690c574	206	kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR3 setting. /
AnnaBridge	145:64910690c574	207	kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR4 setting. /
AnnaBridge	145:64910690c574	208	kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR5 setting. /
AnnaBridge	145:64910690c574	209	kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR6 setting. /
AnnaBridge	145:64910690c574	210	kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR7 setting. /
AnnaBridge	145:64910690c574	211
AnnaBridge	145:64910690c574	212	kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS0 signal. /
AnnaBridge	145:64910690c574	213	kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS1 signal. /
AnnaBridge	145:64910690c574	214	kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS2 signal./
AnnaBridge	145:64910690c574	215	kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS3 signal. /
AnnaBridge	145:64910690c574	216	kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS4 signal. /
AnnaBridge	145:64910690c574	217	kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS5 signal. /
AnnaBridge	145:64910690c574	218
AnnaBridge	145:64910690c574	219	kDSPI_MasterPcsContinuous = 1U << 20, /!< Indicates whether the PCS signal is continuous. /
AnnaBridge	145:64910690c574	220	kDSPI_MasterActiveAfterTransfer = 1U << 21, /!< Indicates whether the PCS signal is active after the last frame transfer./
AnnaBridge	145:64910690c574	221	};
AnnaBridge	145:64910690c574	222
AnnaBridge	145:64910690c574	223	#define DSPI_SLAVE_CTAR_SHIFT (0U) /!< DSPI slave CTAR shift macro; used internally. /
AnnaBridge	145:64910690c574	224	#define DSPI_SLAVE_CTAR_MASK (0x07U) /!< DSPI slave CTAR mask macro; used internally. /
AnnaBridge	145:64910690c574	225	/! @brief Use this enumeration for the DSPI slave transfer configFlags. /
AnnaBridge	145:64910690c574	226	enum _dspi_transfer_config_flag_for_slave
AnnaBridge	145:64910690c574	227	{
AnnaBridge	145:64910690c574	228	kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /!< DSPI slave transfer use CTAR0 setting. /
AnnaBridge	145:64910690c574	229	/!< DSPI slave can only use PCS0. /
AnnaBridge	145:64910690c574	230	};
AnnaBridge	145:64910690c574	231
AnnaBridge	145:64910690c574	232	/! @brief DSPI transfer state, which is used for DSPI transactional API state machine. /
AnnaBridge	145:64910690c574	233	enum _dspi_transfer_state
AnnaBridge	145:64910690c574	234	{
AnnaBridge	145:64910690c574	235	kDSPI_Idle = 0x0U, /!< Nothing in the transmitter/receiver. /
AnnaBridge	145:64910690c574	236	kDSPI_Busy, /!< Transfer queue is not finished. /
AnnaBridge	145:64910690c574	237	kDSPI_Error /!< Transfer error. /
AnnaBridge	145:64910690c574	238	};
AnnaBridge	145:64910690c574	239
AnnaBridge	145:64910690c574	240	/! @brief DSPI master command date configuration used for the SPIx_PUSHR./
AnnaBridge	145:64910690c574	241	typedef struct _dspi_command_data_config
AnnaBridge	145:64910690c574	242	{
AnnaBridge	145:64910690c574	243	bool isPcsContinuous; /!< Option to enable the continuous assertion of the chip select between transfers./
AnnaBridge	145:64910690c574	244	dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
AnnaBridge	145:64910690c574	245	Register (CTAR) to use for CTAS.*/
AnnaBridge	145:64910690c574	246	dspi_which_pcs_t whichPcs; /!< The desired PCS signal to use for the data transfer./
AnnaBridge	145:64910690c574	247	bool isEndOfQueue; /!< Signals that the current transfer is the last in the queue./
AnnaBridge	145:64910690c574	248	bool clearTransferCount; /!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts./
AnnaBridge	145:64910690c574	249	} dspi_command_data_config_t;
AnnaBridge	145:64910690c574	250
AnnaBridge	145:64910690c574	251	/! @brief DSPI master ctar configuration structure./
AnnaBridge	145:64910690c574	252	typedef struct _dspi_master_ctar_config
AnnaBridge	145:64910690c574	253	{
AnnaBridge	145:64910690c574	254	uint32_t baudRate; /!< Baud Rate for DSPI. /
AnnaBridge	145:64910690c574	255	uint32_t bitsPerFrame; /!< Bits per frame, minimum 4, maximum 16./
AnnaBridge	145:64910690c574	256	dspi_clock_polarity_t cpol; /!< Clock polarity. /
AnnaBridge	145:64910690c574	257	dspi_clock_phase_t cpha; /!< Clock phase. /
AnnaBridge	145:64910690c574	258	dspi_shift_direction_t direction; /!< MSB or LSB data shift direction. /
AnnaBridge	145:64910690c574	259
AnnaBridge	145:64910690c574	260	uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
AnnaBridge	145:64910690c574	261	delay. It also sets the boundary value if out of range.*/
AnnaBridge	145:64910690c574	262	uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
AnnaBridge	145:64910690c574	263	minimum delay. It also sets the boundary value if out of range.*/
AnnaBridge	145:64910690c574	264
AnnaBridge	145:64910690c574	265	uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
AnnaBridge	145:64910690c574	266	delay. It also sets the boundary value if out of range.*/
AnnaBridge	145:64910690c574	267	} dspi_master_ctar_config_t;
AnnaBridge	145:64910690c574	268
AnnaBridge	145:64910690c574	269	/! @brief DSPI master configuration structure./
AnnaBridge	145:64910690c574	270	typedef struct _dspi_master_config
AnnaBridge	145:64910690c574	271	{
AnnaBridge	145:64910690c574	272	dspi_ctar_selection_t whichCtar; /!< The desired CTAR to use. /
AnnaBridge	145:64910690c574	273	dspi_master_ctar_config_t ctarConfig; /!< Set the ctarConfig to the desired CTAR. /
AnnaBridge	145:64910690c574	274
AnnaBridge	145:64910690c574	275	dspi_which_pcs_t whichPcs; /!< The desired Peripheral Chip Select (pcs). /
AnnaBridge	145:64910690c574	276	dspi_pcs_polarity_config_t pcsActiveHighOrLow; /!< The desired PCS active high or low. /
AnnaBridge	145:64910690c574	277
AnnaBridge	145:64910690c574	278	bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
AnnaBridge	145:64910690c574	279	supported for CPHA = 1.*/
AnnaBridge	145:64910690c574	280	bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
AnnaBridge	145:64910690c574	281	data is ignored and the data from the transfer that generated the overflow
AnnaBridge	145:64910690c574	282	is also ignored. If ROOE = 1, the incoming data is shifted to the
AnnaBridge	145:64910690c574	283	shift register. */
AnnaBridge	145:64910690c574	284
AnnaBridge	145:64910690c574	285	bool enableModifiedTimingFormat; /!< Enables a modified transfer format to be used if true./
AnnaBridge	145:64910690c574	286	dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
AnnaBridge	145:64910690c574	287	Format. It's valid only when CPHA=0. */
AnnaBridge	145:64910690c574	288	} dspi_master_config_t;
AnnaBridge	145:64910690c574	289
AnnaBridge	145:64910690c574	290	/! @brief DSPI slave ctar configuration structure./
AnnaBridge	145:64910690c574	291	typedef struct _dspi_slave_ctar_config
AnnaBridge	145:64910690c574	292	{
AnnaBridge	145:64910690c574	293	uint32_t bitsPerFrame; /!< Bits per frame, minimum 4, maximum 16./
AnnaBridge	145:64910690c574	294	dspi_clock_polarity_t cpol; /!< Clock polarity. /
AnnaBridge	145:64910690c574	295	dspi_clock_phase_t cpha; /!< Clock phase. /
AnnaBridge	145:64910690c574	296	/!< Slave only supports MSB and does not support LSB./
AnnaBridge	145:64910690c574	297	} dspi_slave_ctar_config_t;
AnnaBridge	145:64910690c574	298
AnnaBridge	145:64910690c574	299	/! @brief DSPI slave configuration structure./
AnnaBridge	145:64910690c574	300	typedef struct _dspi_slave_config
AnnaBridge	145:64910690c574	301	{
AnnaBridge	145:64910690c574	302	dspi_ctar_selection_t whichCtar; /!< The desired CTAR to use. /
AnnaBridge	145:64910690c574	303	dspi_slave_ctar_config_t ctarConfig; /!< Set the ctarConfig to the desired CTAR. /
AnnaBridge	145:64910690c574	304
AnnaBridge	145:64910690c574	305	bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
AnnaBridge	145:64910690c574	306	supported for CPHA = 1.*/
AnnaBridge	145:64910690c574	307	bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
AnnaBridge	145:64910690c574	308	data is ignored and the data from the transfer that generated the overflow
AnnaBridge	145:64910690c574	309	is also ignored. If ROOE = 1, the incoming data is shifted to the
AnnaBridge	145:64910690c574	310	shift register. */
AnnaBridge	145:64910690c574	311	bool enableModifiedTimingFormat; /!< Enables a modified transfer format to be used if true./
AnnaBridge	145:64910690c574	312	dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
AnnaBridge	145:64910690c574	313	Format. It's valid only when CPHA=0. */
AnnaBridge	145:64910690c574	314	} dspi_slave_config_t;
AnnaBridge	145:64910690c574	315
AnnaBridge	145:64910690c574	316	/*!
AnnaBridge	145:64910690c574	317	* @brief Forward declaration of the _dspi_master_handle typedefs.
AnnaBridge	145:64910690c574	318	*/
AnnaBridge	145:64910690c574	319	typedef struct _dspi_master_handle dspi_master_handle_t;
AnnaBridge	145:64910690c574	320
AnnaBridge	145:64910690c574	321	/*!
AnnaBridge	145:64910690c574	322	* @brief Forward declaration of the _dspi_slave_handle typedefs.
AnnaBridge	145:64910690c574	323	*/
AnnaBridge	145:64910690c574	324	typedef struct _dspi_slave_handle dspi_slave_handle_t;
AnnaBridge	145:64910690c574	325
AnnaBridge	145:64910690c574	326	/*!
AnnaBridge	145:64910690c574	327	* @brief Completion callback function pointer type.
AnnaBridge	145:64910690c574	328	*
AnnaBridge	145:64910690c574	329	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	330	* @param handle Pointer to the handle for the DSPI master.
AnnaBridge	145:64910690c574	331	* @param status Success or error code describing whether the transfer completed.
AnnaBridge	145:64910690c574	332	* @param userData Arbitrary pointer-dataSized value passed from the application.
AnnaBridge	145:64910690c574	333	*/
AnnaBridge	145:64910690c574	334	typedef void (dspi_master_transfer_callback_t)(SPI_Type base,
AnnaBridge	145:64910690c574	335	dspi_master_handle_t *handle,
AnnaBridge	145:64910690c574	336	status_t status,
AnnaBridge	145:64910690c574	337	void *userData);
AnnaBridge	145:64910690c574	338	/*!
AnnaBridge	145:64910690c574	339	* @brief Completion callback function pointer type.
AnnaBridge	145:64910690c574	340	*
AnnaBridge	145:64910690c574	341	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	342	* @param handle Pointer to the handle for the DSPI slave.
AnnaBridge	145:64910690c574	343	* @param status Success or error code describing whether the transfer completed.
AnnaBridge	145:64910690c574	344	* @param userData Arbitrary pointer-dataSized value passed from the application.
AnnaBridge	145:64910690c574	345	*/
AnnaBridge	145:64910690c574	346	typedef void (dspi_slave_transfer_callback_t)(SPI_Type base,
AnnaBridge	145:64910690c574	347	dspi_slave_handle_t *handle,
AnnaBridge	145:64910690c574	348	status_t status,
AnnaBridge	145:64910690c574	349	void *userData);
AnnaBridge	145:64910690c574	350
AnnaBridge	145:64910690c574	351	/! @brief DSPI master/slave transfer structure./
AnnaBridge	145:64910690c574	352	typedef struct _dspi_transfer
AnnaBridge	145:64910690c574	353	{
AnnaBridge	145:64910690c574	354	uint8_t txData; /!< Send buffer. */
AnnaBridge	145:64910690c574	355	uint8_t rxData; /!< Receive buffer. */
AnnaBridge	145:64910690c574	356	volatile size_t dataSize; /!< Transfer bytes. /
AnnaBridge	145:64910690c574	357
AnnaBridge	145:64910690c574	358	uint32_t
AnnaBridge	145:64910690c574	359	configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the
AnnaBridge	145:64910690c574	360	transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
AnnaBridge	145:64910690c574	361	is used for slave.*/
AnnaBridge	145:64910690c574	362	} dspi_transfer_t;
AnnaBridge	145:64910690c574	363
AnnaBridge	145:64910690c574	364	/! @brief DSPI master transfer handle structure used for transactional API. /
AnnaBridge	145:64910690c574	365	struct _dspi_master_handle
AnnaBridge	145:64910690c574	366	{
AnnaBridge	145:64910690c574	367	uint32_t bitsPerFrame; /!< The desired number of bits per frame. /
AnnaBridge	145:64910690c574	368	volatile uint32_t command; /!< The desired data command. /
AnnaBridge	145:64910690c574	369	volatile uint32_t lastCommand; /!< The desired last data command. /
AnnaBridge	145:64910690c574	370
AnnaBridge	145:64910690c574	371	uint8_t fifoSize; /!< FIFO dataSize. /
AnnaBridge	145:64910690c574	372
AnnaBridge	145:64910690c574	373	volatile bool isPcsActiveAfterTransfer; /!< Indicates whether the PCS signal is active after the last frame transfer./
AnnaBridge	145:64910690c574	374	volatile bool isThereExtraByte; /!< Indicates whether there are extra bytes./
AnnaBridge	145:64910690c574	375
AnnaBridge	145:64910690c574	376	uint8_t volatile txData; /!< Send buffer. */
AnnaBridge	145:64910690c574	377	uint8_t volatile rxData; /!< Receive buffer. */
AnnaBridge	145:64910690c574	378	volatile size_t remainingSendByteCount; /!< A number of bytes remaining to send./
AnnaBridge	145:64910690c574	379	volatile size_t remainingReceiveByteCount; /!< A number of bytes remaining to receive./
AnnaBridge	145:64910690c574	380	size_t totalByteCount; /!< A number of transfer bytes/
AnnaBridge	145:64910690c574	381
AnnaBridge	145:64910690c574	382	volatile uint8_t state; /!< DSPI transfer state, see _dspi_transfer_state./
AnnaBridge	145:64910690c574	383
AnnaBridge	145:64910690c574	384	dspi_master_transfer_callback_t callback; /!< Completion callback. /
AnnaBridge	145:64910690c574	385	void userData; /!< Callback user data. */
AnnaBridge	145:64910690c574	386	};
AnnaBridge	145:64910690c574	387
AnnaBridge	145:64910690c574	388	/! @brief DSPI slave transfer handle structure used for the transactional API. /
AnnaBridge	145:64910690c574	389	struct _dspi_slave_handle
AnnaBridge	145:64910690c574	390	{
AnnaBridge	145:64910690c574	391	uint32_t bitsPerFrame; /!< The desired number of bits per frame. /
AnnaBridge	145:64910690c574	392	volatile bool isThereExtraByte; /!< Indicates whether there are extra bytes./
AnnaBridge	145:64910690c574	393
AnnaBridge	145:64910690c574	394	uint8_t volatile txData; /!< Send buffer. */
AnnaBridge	145:64910690c574	395	uint8_t volatile rxData; /!< Receive buffer. */
AnnaBridge	145:64910690c574	396	volatile size_t remainingSendByteCount; /!< A number of bytes remaining to send./
AnnaBridge	145:64910690c574	397	volatile size_t remainingReceiveByteCount; /!< A number of bytes remaining to receive./
AnnaBridge	145:64910690c574	398	size_t totalByteCount; /!< A number of transfer bytes/
AnnaBridge	145:64910690c574	399
AnnaBridge	145:64910690c574	400	volatile uint8_t state; /!< DSPI transfer state./
AnnaBridge	145:64910690c574	401
AnnaBridge	145:64910690c574	402	volatile uint32_t errorCount; /!< Error count for slave transfer./
AnnaBridge	145:64910690c574	403
AnnaBridge	145:64910690c574	404	dspi_slave_transfer_callback_t callback; /!< Completion callback. /
AnnaBridge	145:64910690c574	405	void userData; /!< Callback user data. */
AnnaBridge	145:64910690c574	406	};
AnnaBridge	145:64910690c574	407
AnnaBridge	145:64910690c574	408	/**********************************************************************************************************************
AnnaBridge	145:64910690c574	409	* API
AnnaBridge	145:64910690c574	410	*********************************************************************************************************************/
AnnaBridge	145:64910690c574	411	#if defined(__cplusplus)
AnnaBridge	145:64910690c574	412	extern "C" {
AnnaBridge	145:64910690c574	413	#endif /_cplusplus/
AnnaBridge	145:64910690c574	414
AnnaBridge	145:64910690c574	415	/*!
AnnaBridge	145:64910690c574	416	* @name Initialization and deinitialization
AnnaBridge	145:64910690c574	417	* @{
AnnaBridge	145:64910690c574	418	*/
AnnaBridge	145:64910690c574	419
AnnaBridge	145:64910690c574	420	/*!
AnnaBridge	145:64910690c574	421	* @brief Initializes the DSPI master.
AnnaBridge	145:64910690c574	422	*
AnnaBridge	145:64910690c574	423	* This function initializes the DSPI master configuration. This is an example use case.
AnnaBridge	145:64910690c574	424	* @code
AnnaBridge	145:64910690c574	425	* dspi_master_config_t masterConfig;
AnnaBridge	145:64910690c574	426	* masterConfig.whichCtar = kDSPI_Ctar0;
AnnaBridge	145:64910690c574	427	* masterConfig.ctarConfig.baudRate = 500000000U;
AnnaBridge	145:64910690c574	428	* masterConfig.ctarConfig.bitsPerFrame = 8;
AnnaBridge	145:64910690c574	429	* masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
AnnaBridge	145:64910690c574	430	* masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
AnnaBridge	145:64910690c574	431	* masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
AnnaBridge	145:64910690c574	432	* masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
AnnaBridge	145:64910690c574	433	* masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
AnnaBridge	145:64910690c574	434	* masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
AnnaBridge	145:64910690c574	435	* masterConfig.whichPcs = kDSPI_Pcs0;
AnnaBridge	145:64910690c574	436	* masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
AnnaBridge	145:64910690c574	437	* masterConfig.enableContinuousSCK = false;
AnnaBridge	145:64910690c574	438	* masterConfig.enableRxFifoOverWrite = false;
AnnaBridge	145:64910690c574	439	* masterConfig.enableModifiedTimingFormat = false;
AnnaBridge	145:64910690c574	440	* masterConfig.samplePoint = kDSPI_SckToSin0Clock;
AnnaBridge	145:64910690c574	441	* DSPI_MasterInit(base, &masterConfig, srcClock_Hz);
AnnaBridge	145:64910690c574	442	* @endcode
AnnaBridge	145:64910690c574	443	*
AnnaBridge	145:64910690c574	444	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	445	* @param masterConfig Pointer to the structure dspi_master_config_t.
AnnaBridge	145:64910690c574	446	* @param srcClock_Hz Module source input clock in Hertz.
AnnaBridge	145:64910690c574	447	*/
AnnaBridge	145:64910690c574	448	void DSPI_MasterInit(SPI_Type base, const dspi_master_config_t masterConfig, uint32_t srcClock_Hz);
AnnaBridge	145:64910690c574	449
AnnaBridge	145:64910690c574	450	/*!
AnnaBridge	145:64910690c574	451	* @brief Sets the dspi_master_config_t structure to default values.
AnnaBridge	145:64910690c574	452	*
AnnaBridge	145:64910690c574	453	* The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
AnnaBridge	145:64910690c574	454	* Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure
AnnaBridge	145:64910690c574	455	* before calling the DSPI_MasterInit().
AnnaBridge	145:64910690c574	456	* Example:
AnnaBridge	145:64910690c574	457	* @code
AnnaBridge	145:64910690c574	458	* dspi_master_config_t masterConfig;
AnnaBridge	145:64910690c574	459	* DSPI_MasterGetDefaultConfig(&masterConfig);
AnnaBridge	145:64910690c574	460	* @endcode
AnnaBridge	145:64910690c574	461	* @param masterConfig pointer to dspi_master_config_t structure
AnnaBridge	145:64910690c574	462	*/
AnnaBridge	145:64910690c574	463	void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
AnnaBridge	145:64910690c574	464
AnnaBridge	145:64910690c574	465	/*!
AnnaBridge	145:64910690c574	466	* @brief DSPI slave configuration.
AnnaBridge	145:64910690c574	467	*
AnnaBridge	145:64910690c574	468	* This function initializes the DSPI slave configuration. This is an example use case.
AnnaBridge	145:64910690c574	469	* @code
AnnaBridge	145:64910690c574	470	* dspi_slave_config_t slaveConfig;
AnnaBridge	145:64910690c574	471	* slaveConfig->whichCtar = kDSPI_Ctar0;
AnnaBridge	145:64910690c574	472	* slaveConfig->ctarConfig.bitsPerFrame = 8;
AnnaBridge	145:64910690c574	473	* slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
AnnaBridge	145:64910690c574	474	* slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
AnnaBridge	145:64910690c574	475	* slaveConfig->enableContinuousSCK = false;
AnnaBridge	145:64910690c574	476	* slaveConfig->enableRxFifoOverWrite = false;
AnnaBridge	145:64910690c574	477	* slaveConfig->enableModifiedTimingFormat = false;
AnnaBridge	145:64910690c574	478	* slaveConfig->samplePoint = kDSPI_SckToSin0Clock;
AnnaBridge	145:64910690c574	479	* DSPI_SlaveInit(base, &slaveConfig);
AnnaBridge	145:64910690c574	480	* @endcode
AnnaBridge	145:64910690c574	481	*
AnnaBridge	145:64910690c574	482	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	483	* @param slaveConfig Pointer to the structure dspi_master_config_t.
AnnaBridge	145:64910690c574	484	*/
AnnaBridge	145:64910690c574	485	void DSPI_SlaveInit(SPI_Type base, const dspi_slave_config_t slaveConfig);
AnnaBridge	145:64910690c574	486
AnnaBridge	145:64910690c574	487	/*!
AnnaBridge	145:64910690c574	488	* @brief Sets the dspi_slave_config_t structure to a default value.
AnnaBridge	145:64910690c574	489	*
AnnaBridge	145:64910690c574	490	* The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
AnnaBridge	145:64910690c574	491	* Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure
AnnaBridge	145:64910690c574	492	* before calling the DSPI_SlaveInit().
AnnaBridge	145:64910690c574	493	* This is an example.
AnnaBridge	145:64910690c574	494	* @code
AnnaBridge	145:64910690c574	495	* dspi_slave_config_t slaveConfig;
AnnaBridge	145:64910690c574	496	* DSPI_SlaveGetDefaultConfig(&slaveConfig);
AnnaBridge	145:64910690c574	497	* @endcode
AnnaBridge	145:64910690c574	498	* @param slaveConfig Pointer to the dspi_slave_config_t structure.
AnnaBridge	145:64910690c574	499	*/
AnnaBridge	145:64910690c574	500	void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
AnnaBridge	145:64910690c574	501
AnnaBridge	145:64910690c574	502	/*!
AnnaBridge	145:64910690c574	503	* @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
AnnaBridge	145:64910690c574	504	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	505	*/
AnnaBridge	145:64910690c574	506	void DSPI_Deinit(SPI_Type *base);
AnnaBridge	145:64910690c574	507
AnnaBridge	145:64910690c574	508	/*!
AnnaBridge	145:64910690c574	509	* @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
AnnaBridge	145:64910690c574	510	*
AnnaBridge	145:64910690c574	511	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	512	* @param enable Pass true to enable module, false to disable module.
AnnaBridge	145:64910690c574	513	*/
AnnaBridge	145:64910690c574	514	static inline void DSPI_Enable(SPI_Type *base, bool enable)
AnnaBridge	145:64910690c574	515	{
AnnaBridge	145:64910690c574	516	if (enable)
AnnaBridge	145:64910690c574	517	{
AnnaBridge	145:64910690c574	518	base->MCR &= ~SPI_MCR_MDIS_MASK;
AnnaBridge	145:64910690c574	519	}
AnnaBridge	145:64910690c574	520	else
AnnaBridge	145:64910690c574	521	{
AnnaBridge	145:64910690c574	522	base->MCR \|= SPI_MCR_MDIS_MASK;
AnnaBridge	145:64910690c574	523	}
AnnaBridge	145:64910690c574	524	}
AnnaBridge	145:64910690c574	525
AnnaBridge	145:64910690c574	526	/*!
AnnaBridge	145:64910690c574	527	*@}
AnnaBridge	145:64910690c574	528	*/
AnnaBridge	145:64910690c574	529
AnnaBridge	145:64910690c574	530	/*!
AnnaBridge	145:64910690c574	531	* @name Status
AnnaBridge	145:64910690c574	532	* @{
AnnaBridge	145:64910690c574	533	*/
AnnaBridge	145:64910690c574	534
AnnaBridge	145:64910690c574	535	/*!
AnnaBridge	145:64910690c574	536	* @brief Gets the DSPI status flag state.
AnnaBridge	145:64910690c574	537	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	538	* @return DSPI status (in SR register).
AnnaBridge	145:64910690c574	539	*/
AnnaBridge	145:64910690c574	540	static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
AnnaBridge	145:64910690c574	541	{
AnnaBridge	145:64910690c574	542	return (base->SR);
AnnaBridge	145:64910690c574	543	}
AnnaBridge	145:64910690c574	544
AnnaBridge	145:64910690c574	545	/*!
AnnaBridge	145:64910690c574	546	* @brief Clears the DSPI status flag.
AnnaBridge	145:64910690c574	547	*
AnnaBridge	145:64910690c574	548	* This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
AnnaBridge	145:64910690c574	549	* desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
AnnaBridge	145:64910690c574	550	* function uses these bit positions in its algorithm to clear the desired flag state.
AnnaBridge	145:64910690c574	551	* This is an example.
AnnaBridge	145:64910690c574	552	* @code
AnnaBridge	145:64910690c574	553	* DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag\|kDSPI_EndOfQueueFlag);
AnnaBridge	145:64910690c574	554	* @endcode
AnnaBridge	145:64910690c574	555	*
AnnaBridge	145:64910690c574	556	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	557	* @param statusFlags The status flag used from the type dspi_flags.
AnnaBridge	145:64910690c574	558	*/
AnnaBridge	145:64910690c574	559	static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
AnnaBridge	145:64910690c574	560	{
AnnaBridge	145:64910690c574	561	base->SR = statusFlags; /!< The status flags are cleared by writing 1 (w1c)./
AnnaBridge	145:64910690c574	562	}
AnnaBridge	145:64910690c574	563
AnnaBridge	145:64910690c574	564	/*!
AnnaBridge	145:64910690c574	565	*@}
AnnaBridge	145:64910690c574	566	*/
AnnaBridge	145:64910690c574	567
AnnaBridge	145:64910690c574	568	/*!
AnnaBridge	145:64910690c574	569	* @name Interrupts
AnnaBridge	145:64910690c574	570	* @{
AnnaBridge	145:64910690c574	571	*/
AnnaBridge	145:64910690c574	572
AnnaBridge	145:64910690c574	573	/*!
AnnaBridge	145:64910690c574	574	* @brief Enables the DSPI interrupts.
AnnaBridge	145:64910690c574	575	*
AnnaBridge	145:64910690c574	576	* This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask.
AnnaBridge	145:64910690c574	577	* Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
AnnaBridge	145:64910690c574	578	*
AnnaBridge	145:64910690c574	579	* @code
AnnaBridge	145:64910690c574	580	* DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable \| kDSPI_EndOfQueueInterruptEnable );
AnnaBridge	145:64910690c574	581	* @endcode
AnnaBridge	145:64910690c574	582	*
AnnaBridge	145:64910690c574	583	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	584	* @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
AnnaBridge	145:64910690c574	585	*/
AnnaBridge	145:64910690c574	586	void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
AnnaBridge	145:64910690c574	587
AnnaBridge	145:64910690c574	588	/*!
AnnaBridge	145:64910690c574	589	* @brief Disables the DSPI interrupts.
AnnaBridge	145:64910690c574	590	*
AnnaBridge	145:64910690c574	591	* @code
AnnaBridge	145:64910690c574	592	* DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable \| kDSPI_EndOfQueueInterruptEnable );
AnnaBridge	145:64910690c574	593	* @endcode
AnnaBridge	145:64910690c574	594	*
AnnaBridge	145:64910690c574	595	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	596	* @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
AnnaBridge	145:64910690c574	597	*/
AnnaBridge	145:64910690c574	598	static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
AnnaBridge	145:64910690c574	599	{
AnnaBridge	145:64910690c574	600	base->RSER &= ~mask;
AnnaBridge	145:64910690c574	601	}
AnnaBridge	145:64910690c574	602
AnnaBridge	145:64910690c574	603	/*!
AnnaBridge	145:64910690c574	604	*@}
AnnaBridge	145:64910690c574	605	*/
AnnaBridge	145:64910690c574	606
AnnaBridge	145:64910690c574	607	/*!
AnnaBridge	145:64910690c574	608	* @name DMA Control
AnnaBridge	145:64910690c574	609	* @{
AnnaBridge	145:64910690c574	610	*/
AnnaBridge	145:64910690c574	611
AnnaBridge	145:64910690c574	612	/*!
AnnaBridge	145:64910690c574	613	* @brief Enables the DSPI DMA request.
AnnaBridge	145:64910690c574	614	*
AnnaBridge	145:64910690c574	615	* This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask.
AnnaBridge	145:64910690c574	616	* @code
AnnaBridge	145:64910690c574	617	* DSPI_EnableDMA(base, kDSPI_TxDmaEnable \| kDSPI_RxDmaEnable);
AnnaBridge	145:64910690c574	618	* @endcode
AnnaBridge	145:64910690c574	619	*
AnnaBridge	145:64910690c574	620	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	621	* @param mask The interrupt mask; use the enum dspi_dma_enable.
AnnaBridge	145:64910690c574	622	*/
AnnaBridge	145:64910690c574	623	static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
AnnaBridge	145:64910690c574	624	{
AnnaBridge	145:64910690c574	625	base->RSER \|= mask;
AnnaBridge	145:64910690c574	626	}
AnnaBridge	145:64910690c574	627
AnnaBridge	145:64910690c574	628	/*!
AnnaBridge	145:64910690c574	629	* @brief Disables the DSPI DMA request.
AnnaBridge	145:64910690c574	630	*
AnnaBridge	145:64910690c574	631	* This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask.
AnnaBridge	145:64910690c574	632	* @code
AnnaBridge	145:64910690c574	633	* SPI_DisableDMA(base, kDSPI_TxDmaEnable \| kDSPI_RxDmaEnable);
AnnaBridge	145:64910690c574	634	* @endcode
AnnaBridge	145:64910690c574	635	*
AnnaBridge	145:64910690c574	636	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	637	* @param mask The interrupt mask; use the enum dspi_dma_enable.
AnnaBridge	145:64910690c574	638	*/
AnnaBridge	145:64910690c574	639	static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
AnnaBridge	145:64910690c574	640	{
AnnaBridge	145:64910690c574	641	base->RSER &= ~mask;
AnnaBridge	145:64910690c574	642	}
AnnaBridge	145:64910690c574	643
AnnaBridge	145:64910690c574	644	/*!
AnnaBridge	145:64910690c574	645	* @brief Gets the DSPI master PUSHR data register address for the DMA operation.
AnnaBridge	145:64910690c574	646	*
AnnaBridge	145:64910690c574	647	* This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.
AnnaBridge	145:64910690c574	648	*
AnnaBridge	145:64910690c574	649	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	650	* @return The DSPI master PUSHR data register address.
AnnaBridge	145:64910690c574	651	*/
AnnaBridge	145:64910690c574	652	static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
AnnaBridge	145:64910690c574	653	{
AnnaBridge	145:64910690c574	654	return (uint32_t) & (base->PUSHR);
AnnaBridge	145:64910690c574	655	}
AnnaBridge	145:64910690c574	656
AnnaBridge	145:64910690c574	657	/*!
AnnaBridge	145:64910690c574	658	* @brief Gets the DSPI slave PUSHR data register address for the DMA operation.
AnnaBridge	145:64910690c574	659	*
AnnaBridge	145:64910690c574	660	* This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.
AnnaBridge	145:64910690c574	661	*
AnnaBridge	145:64910690c574	662	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	663	* @return The DSPI slave PUSHR data register address.
AnnaBridge	145:64910690c574	664	*/
AnnaBridge	145:64910690c574	665	static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
AnnaBridge	145:64910690c574	666	{
AnnaBridge	145:64910690c574	667	return (uint32_t) & (base->PUSHR_SLAVE);
AnnaBridge	145:64910690c574	668	}
AnnaBridge	145:64910690c574	669
AnnaBridge	145:64910690c574	670	/*!
AnnaBridge	145:64910690c574	671	* @brief Gets the DSPI POPR data register address for the DMA operation.
AnnaBridge	145:64910690c574	672	*
AnnaBridge	145:64910690c574	673	* This function gets the DSPI POPR data register address as this value is needed for the DMA operation.
AnnaBridge	145:64910690c574	674	*
AnnaBridge	145:64910690c574	675	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	676	* @return The DSPI POPR data register address.
AnnaBridge	145:64910690c574	677	*/
AnnaBridge	145:64910690c574	678	static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
AnnaBridge	145:64910690c574	679	{
AnnaBridge	145:64910690c574	680	return (uint32_t) & (base->POPR);
AnnaBridge	145:64910690c574	681	}
AnnaBridge	145:64910690c574	682
AnnaBridge	145:64910690c574	683	/*!
AnnaBridge	145:64910690c574	684	*@}
AnnaBridge	145:64910690c574	685	*/
AnnaBridge	145:64910690c574	686
AnnaBridge	145:64910690c574	687	/*!
AnnaBridge	145:64910690c574	688	* @name Bus Operations
AnnaBridge	145:64910690c574	689	* @{
AnnaBridge	145:64910690c574	690	*/
AnnaBridge	145:64910690c574	691
AnnaBridge	145:64910690c574	692	/*!
AnnaBridge	145:64910690c574	693	* @brief Configures the DSPI for master or slave.
AnnaBridge	145:64910690c574	694	*
AnnaBridge	145:64910690c574	695	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	696	* @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t.
AnnaBridge	145:64910690c574	697	*/
AnnaBridge	145:64910690c574	698	static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
AnnaBridge	145:64910690c574	699	{
AnnaBridge	145:64910690c574	700	base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) \| SPI_MCR_MSTR(mode);
AnnaBridge	145:64910690c574	701	}
AnnaBridge	145:64910690c574	702
AnnaBridge	145:64910690c574	703	/*!
AnnaBridge	145:64910690c574	704	* @brief Returns whether the DSPI module is in master mode.
AnnaBridge	145:64910690c574	705	*
AnnaBridge	145:64910690c574	706	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	707	* @return Returns true if the module is in master mode or false if the module is in slave mode.
AnnaBridge	145:64910690c574	708	*/
AnnaBridge	145:64910690c574	709	static inline bool DSPI_IsMaster(SPI_Type *base)
AnnaBridge	145:64910690c574	710	{
AnnaBridge	145:64910690c574	711	return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
AnnaBridge	145:64910690c574	712	}
AnnaBridge	145:64910690c574	713	/*!
AnnaBridge	145:64910690c574	714	* @brief Starts the DSPI transfers and clears HALT bit in MCR.
AnnaBridge	145:64910690c574	715	*
AnnaBridge	145:64910690c574	716	* This function sets the module to start data transfer in either master or slave mode.
AnnaBridge	145:64910690c574	717	*
AnnaBridge	145:64910690c574	718	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	719	*/
AnnaBridge	145:64910690c574	720	static inline void DSPI_StartTransfer(SPI_Type *base)
AnnaBridge	145:64910690c574	721	{
AnnaBridge	145:64910690c574	722	base->MCR &= ~SPI_MCR_HALT_MASK;
AnnaBridge	145:64910690c574	723	}
AnnaBridge	145:64910690c574	724	/*!
AnnaBridge	145:64910690c574	725	* @brief Stops DSPI transfers and sets the HALT bit in MCR.
AnnaBridge	145:64910690c574	726	*
AnnaBridge	145:64910690c574	727	* This function stops data transfers in either master or slave modes.
AnnaBridge	145:64910690c574	728	*
AnnaBridge	145:64910690c574	729	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	730	*/
AnnaBridge	145:64910690c574	731	static inline void DSPI_StopTransfer(SPI_Type *base)
AnnaBridge	145:64910690c574	732	{
AnnaBridge	145:64910690c574	733	base->MCR \|= SPI_MCR_HALT_MASK;
AnnaBridge	145:64910690c574	734	}
AnnaBridge	145:64910690c574	735
AnnaBridge	145:64910690c574	736	/*!
AnnaBridge	145:64910690c574	737	* @brief Enables or disables the DSPI FIFOs.
AnnaBridge	145:64910690c574	738	*
AnnaBridge	145:64910690c574	739	* This function allows the caller to disable/enable the Tx and Rx FIFOs independently.
AnnaBridge	145:64910690c574	740	* Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable,
AnnaBridge	145:64910690c574	741	* pass in a logic 1 (true).
AnnaBridge	145:64910690c574	742	*
AnnaBridge	145:64910690c574	743	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	744	* @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO
AnnaBridge	145:64910690c574	745	* @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO
AnnaBridge	145:64910690c574	746	*/
AnnaBridge	145:64910690c574	747	static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
AnnaBridge	145:64910690c574	748	{
AnnaBridge	145:64910690c574	749	base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK \| SPI_MCR_DIS_TXF_MASK))) \| SPI_MCR_DIS_TXF(!enableTxFifo) \|
AnnaBridge	145:64910690c574	750	SPI_MCR_DIS_RXF(!enableRxFifo);
AnnaBridge	145:64910690c574	751	}
AnnaBridge	145:64910690c574	752
AnnaBridge	145:64910690c574	753	/*!
AnnaBridge	145:64910690c574	754	* @brief Flushes the DSPI FIFOs.
AnnaBridge	145:64910690c574	755	*
AnnaBridge	145:64910690c574	756	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	757	* @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO
AnnaBridge	145:64910690c574	758	* @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO
AnnaBridge	145:64910690c574	759	*/
AnnaBridge	145:64910690c574	760	static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
AnnaBridge	145:64910690c574	761	{
AnnaBridge	145:64910690c574	762	base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK \| SPI_MCR_CLR_RXF_MASK))) \| SPI_MCR_CLR_TXF(flushTxFifo) \|
AnnaBridge	145:64910690c574	763	SPI_MCR_CLR_RXF(flushRxFifo);
AnnaBridge	145:64910690c574	764	}
AnnaBridge	145:64910690c574	765
AnnaBridge	145:64910690c574	766	/*!
AnnaBridge	145:64910690c574	767	* @brief Configures the DSPI peripheral chip select polarity simultaneously.
AnnaBridge	145:64910690c574	768	* For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of
AnnaBridge	145:64910690c574	769	* PCSs is specific to the device.
AnnaBridge	145:64910690c574	770	* @code
AnnaBridge	145:64910690c574	771	* DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow \| kDSPI_Pcs1ActiveLow);
AnnaBridge	145:64910690c574	772	@endcode
AnnaBridge	145:64910690c574	773	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	774	* @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity.
AnnaBridge	145:64910690c574	775	*/
AnnaBridge	145:64910690c574	776	static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
AnnaBridge	145:64910690c574	777	{
AnnaBridge	145:64910690c574	778	base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) \| SPI_MCR_PCSIS(mask);
AnnaBridge	145:64910690c574	779	}
AnnaBridge	145:64910690c574	780
AnnaBridge	145:64910690c574	781	/*!
AnnaBridge	145:64910690c574	782	* @brief Sets the DSPI baud rate in bits per second.
AnnaBridge	145:64910690c574	783	*
AnnaBridge	145:64910690c574	784	* This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without
AnnaBridge	145:64910690c574	785	* exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the
AnnaBridge	145:64910690c574	786	* caller also provide the frequency of the module source clock (in Hertz).
AnnaBridge	145:64910690c574	787	*
AnnaBridge	145:64910690c574	788	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	789	* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t
AnnaBridge	145:64910690c574	790	* @param baudRate_Bps The desired baud rate in bits per second
AnnaBridge	145:64910690c574	791	* @param srcClock_Hz Module source input clock in Hertz
AnnaBridge	145:64910690c574	792	* @return The actual calculated baud rate
AnnaBridge	145:64910690c574	793	*/
AnnaBridge	145:64910690c574	794	uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
AnnaBridge	145:64910690c574	795	dspi_ctar_selection_t whichCtar,
AnnaBridge	145:64910690c574	796	uint32_t baudRate_Bps,
AnnaBridge	145:64910690c574	797	uint32_t srcClock_Hz);
AnnaBridge	145:64910690c574	798
AnnaBridge	145:64910690c574	799	/*!
AnnaBridge	145:64910690c574	800	* @brief Manually configures the delay prescaler and scaler for a particular CTAR.
AnnaBridge	145:64910690c574	801	*
AnnaBridge	145:64910690c574	802	* This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
AnnaBridge	145:64910690c574	803	* (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT).
AnnaBridge	145:64910690c574	804	*
AnnaBridge	145:64910690c574	805	* These delay names are available in the type dspi_delay_type_t.
AnnaBridge	145:64910690c574	806	*
AnnaBridge	145:64910690c574	807	* The user passes the delay to the configuration along with the prescaler and scaler value.
AnnaBridge	145:64910690c574	808	* This allows the user to directly set the prescaler/scaler values if pre-calculated or
AnnaBridge	145:64910690c574	809	* to manually increment either value.
AnnaBridge	145:64910690c574	810	*
AnnaBridge	145:64910690c574	811	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	812	* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
AnnaBridge	145:64910690c574	813	* @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
AnnaBridge	145:64910690c574	814	* @param scaler The scaler delay value (can be any integer between 0 to 15).
AnnaBridge	145:64910690c574	815	* @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t
AnnaBridge	145:64910690c574	816	*/
AnnaBridge	145:64910690c574	817	void DSPI_MasterSetDelayScaler(
AnnaBridge	145:64910690c574	818	SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
AnnaBridge	145:64910690c574	819
AnnaBridge	145:64910690c574	820	/*!
AnnaBridge	145:64910690c574	821	* @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
AnnaBridge	145:64910690c574	822	*
AnnaBridge	145:64910690c574	823	* This function calculates the values for the following.
AnnaBridge	145:64910690c574	824	* PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
AnnaBridge	145:64910690c574	825	* After SCK delay pre-scalar (PASC) and scalar (ASC), or
AnnaBridge	145:64910690c574	826	* Delay after transfer pre-scalar (PDT) and scalar (DT).
AnnaBridge	145:64910690c574	827	*
AnnaBridge	145:64910690c574	828	* These delay names are available in the type dspi_delay_type_t.
AnnaBridge	145:64910690c574	829	*
AnnaBridge	145:64910690c574	830	* The user passes which delay to configure along with the desired delay value in nanoseconds. The function
AnnaBridge	145:64910690c574	831	* calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact
AnnaBridge	145:64910690c574	832	* delay match may not be possible. In this case, the closest match is calculated without going below the desired
AnnaBridge	145:64910690c574	833	* delay value input.
AnnaBridge	145:64910690c574	834	* It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
AnnaBridge	145:64910690c574	835	* supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
AnnaBridge	145:64910690c574	836	* input.
AnnaBridge	145:64910690c574	837	*
AnnaBridge	145:64910690c574	838	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	839	* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
AnnaBridge	145:64910690c574	840	* @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
AnnaBridge	145:64910690c574	841	* @param srcClock_Hz Module source input clock in Hertz
AnnaBridge	145:64910690c574	842	* @param delayTimeInNanoSec The desired delay value in nanoseconds.
AnnaBridge	145:64910690c574	843	* @return The actual calculated delay value.
AnnaBridge	145:64910690c574	844	*/
AnnaBridge	145:64910690c574	845	uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
AnnaBridge	145:64910690c574	846	dspi_ctar_selection_t whichCtar,
AnnaBridge	145:64910690c574	847	dspi_delay_type_t whichDelay,
AnnaBridge	145:64910690c574	848	uint32_t srcClock_Hz,
AnnaBridge	145:64910690c574	849	uint32_t delayTimeInNanoSec);
AnnaBridge	145:64910690c574	850
AnnaBridge	145:64910690c574	851	/*!
AnnaBridge	145:64910690c574	852	* @brief Writes data into the data buffer for master mode.
AnnaBridge	145:64910690c574	853	*
AnnaBridge	145:64910690c574	854	* In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
AnnaBridge	145:64910690c574	855	* provides characteristics of the data, such as the optional continuous chip select
AnnaBridge	145:64910690c574	856	* operation between transfers, the desired Clock and Transfer Attributes register to use for the
AnnaBridge	145:64910690c574	857	* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
AnnaBridge	145:64910690c574	858	* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
AnnaBridge	145:64910690c574	859	* sending the first frame of a data packet). This is an example.
AnnaBridge	145:64910690c574	860	* @code
AnnaBridge	145:64910690c574	861	* dspi_command_data_config_t commandConfig;
AnnaBridge	145:64910690c574	862	* commandConfig.isPcsContinuous = true;
AnnaBridge	145:64910690c574	863	* commandConfig.whichCtar = kDSPICtar0;
AnnaBridge	145:64910690c574	864	* commandConfig.whichPcs = kDSPIPcs0;
AnnaBridge	145:64910690c574	865	* commandConfig.clearTransferCount = false;
AnnaBridge	145:64910690c574	866	* commandConfig.isEndOfQueue = false;
AnnaBridge	145:64910690c574	867	* DSPI_MasterWriteData(base, &commandConfig, dataWord);
AnnaBridge	145:64910690c574	868	@endcode
AnnaBridge	145:64910690c574	869	*
AnnaBridge	145:64910690c574	870	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	871	* @param command Pointer to the command structure.
AnnaBridge	145:64910690c574	872	* @param data The data word to be sent.
AnnaBridge	145:64910690c574	873	*/
AnnaBridge	145:64910690c574	874	static inline void DSPI_MasterWriteData(SPI_Type base, dspi_command_data_config_t command, uint16_t data)
AnnaBridge	145:64910690c574	875	{
AnnaBridge	145:64910690c574	876	base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) \| SPI_PUSHR_CTAS(command->whichCtar) \|
AnnaBridge	145:64910690c574	877	SPI_PUSHR_PCS(command->whichPcs) \| SPI_PUSHR_EOQ(command->isEndOfQueue) \|
AnnaBridge	145:64910690c574	878	SPI_PUSHR_CTCNT(command->clearTransferCount) \| SPI_PUSHR_TXDATA(data);
AnnaBridge	145:64910690c574	879	}
AnnaBridge	145:64910690c574	880
AnnaBridge	145:64910690c574	881	/*!
AnnaBridge	145:64910690c574	882	* @brief Sets the dspi_command_data_config_t structure to default values.
AnnaBridge	145:64910690c574	883	*
AnnaBridge	145:64910690c574	884	* The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
AnnaBridge	145:64910690c574	885	* Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure
AnnaBridge	145:64910690c574	886	* before calling the DSPI_MasterWrite_xx().
AnnaBridge	145:64910690c574	887	* This is an example.
AnnaBridge	145:64910690c574	888	* @code
AnnaBridge	145:64910690c574	889	* dspi_command_data_config_t command;
AnnaBridge	145:64910690c574	890	* DSPI_GetDefaultDataCommandConfig(&command);
AnnaBridge	145:64910690c574	891	* @endcode
AnnaBridge	145:64910690c574	892	* @param command Pointer to the dspi_command_data_config_t structure.
AnnaBridge	145:64910690c574	893	*/
AnnaBridge	145:64910690c574	894	void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
AnnaBridge	145:64910690c574	895
AnnaBridge	145:64910690c574	896	/*!
AnnaBridge	145:64910690c574	897	* @brief Writes data into the data buffer master mode and waits till complete to return.
AnnaBridge	145:64910690c574	898	*
AnnaBridge	145:64910690c574	899	* In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
AnnaBridge	145:64910690c574	900	* provides characteristics of the data, such as the optional continuous chip select
AnnaBridge	145:64910690c574	901	* operation between transfers, the desired Clock and Transfer Attributes register to use for the
AnnaBridge	145:64910690c574	902	* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
AnnaBridge	145:64910690c574	903	* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
AnnaBridge	145:64910690c574	904	* sending the first frame of a data packet). This is an example.
AnnaBridge	145:64910690c574	905	* @code
AnnaBridge	145:64910690c574	906	* dspi_command_config_t commandConfig;
AnnaBridge	145:64910690c574	907	* commandConfig.isPcsContinuous = true;
AnnaBridge	145:64910690c574	908	* commandConfig.whichCtar = kDSPICtar0;
AnnaBridge	145:64910690c574	909	* commandConfig.whichPcs = kDSPIPcs1;
AnnaBridge	145:64910690c574	910	* commandConfig.clearTransferCount = false;
AnnaBridge	145:64910690c574	911	* commandConfig.isEndOfQueue = false;
AnnaBridge	145:64910690c574	912	* DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord);
AnnaBridge	145:64910690c574	913	* @endcode
AnnaBridge	145:64910690c574	914	*
AnnaBridge	145:64910690c574	915	* Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
AnnaBridge	145:64910690c574	916	* enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
AnnaBridge	145:64910690c574	917	* the received data is available when the transmit completes.
AnnaBridge	145:64910690c574	918	*
AnnaBridge	145:64910690c574	919	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	920	* @param command Pointer to the command structure.
AnnaBridge	145:64910690c574	921	* @param data The data word to be sent.
AnnaBridge	145:64910690c574	922	*/
AnnaBridge	145:64910690c574	923	void DSPI_MasterWriteDataBlocking(SPI_Type base, dspi_command_data_config_t command, uint16_t data);
AnnaBridge	145:64910690c574	924
AnnaBridge	145:64910690c574	925	/*!
AnnaBridge	145:64910690c574	926	* @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
AnnaBridge	145:64910690c574	927	*
AnnaBridge	145:64910690c574	928	* This function allows the caller to pass in the data command structure and returns the command word formatted
AnnaBridge	145:64910690c574	929	* according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the
AnnaBridge	145:64910690c574	930	* desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or
AnnaBridge	145:64910690c574	931	* DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps
AnnaBridge	145:64910690c574	932	* improve performance in cases where the command structure is constant. For example, the user calls this function
AnnaBridge	145:64910690c574	933	* before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
AnnaBridge	145:64910690c574	934	* this formatted command word with the desired data to transmit. This process increases transmit performance when
AnnaBridge	145:64910690c574	935	* compared to calling send functions, such as DSPI_HAL_WriteDataMastermode, which format the command word each time a
AnnaBridge	145:64910690c574	936	* data word is to be sent.
AnnaBridge	145:64910690c574	937	*
AnnaBridge	145:64910690c574	938	* @param command Pointer to the command structure.
AnnaBridge	145:64910690c574	939	* @return The command word formatted to the PUSHR data register bit field.
AnnaBridge	145:64910690c574	940	*/
AnnaBridge	145:64910690c574	941	static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
AnnaBridge	145:64910690c574	942	{
AnnaBridge	145:64910690c574	943	/* Format the 16-bit command word according to the PUSHR data register bit field*/
AnnaBridge	145:64910690c574	944	return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) \| SPI_PUSHR_CTAS(command->whichCtar) \|
AnnaBridge	145:64910690c574	945	SPI_PUSHR_PCS(command->whichPcs) \| SPI_PUSHR_EOQ(command->isEndOfQueue) \|
AnnaBridge	145:64910690c574	946	SPI_PUSHR_CTCNT(command->clearTransferCount));
AnnaBridge	145:64910690c574	947	}
AnnaBridge	145:64910690c574	948
AnnaBridge	145:64910690c574	949	/*!
AnnaBridge	145:64910690c574	950	* @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
AnnaBridge	145:64910690c574	951	* buffer master mode and waits till complete to return.
AnnaBridge	145:64910690c574	952	*
AnnaBridge	145:64910690c574	953	* In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word
AnnaBridge	145:64910690c574	954	* as the data to send.
AnnaBridge	145:64910690c574	955	* The command portion provides characteristics of the data, such as the optional continuous chip select operation
AnnaBridge	145:64910690c574	956	* between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
AnnaBridge	145:64910690c574	957	* signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
AnnaBridge	145:64910690c574	958	* transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
AnnaBridge	145:64910690c574	959	* appending this command with the data to send. This is an example:
AnnaBridge	145:64910690c574	960	* @code
AnnaBridge	145:64910690c574	961	* dataWord = <16-bit command> \| <16-bit data>;
AnnaBridge	145:64910690c574	962	* DSPI_MasterWriteCommandDataBlocking(base, dataWord);
AnnaBridge	145:64910690c574	963	* @endcode
AnnaBridge	145:64910690c574	964	*
AnnaBridge	145:64910690c574	965	* Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
AnnaBridge	145:64910690c574	966	* enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
AnnaBridge	145:64910690c574	967	* Because the SPI is a synchronous protocol, the received data is available when the transmit completes.
AnnaBridge	145:64910690c574	968	*
AnnaBridge	145:64910690c574	969	* For a blocking polling transfer, see methods below.
AnnaBridge	145:64910690c574	970	* Option 1:
AnnaBridge	145:64910690c574	971	* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command);
AnnaBridge	145:64910690c574	972	* uint32_t data0 = command_to_send \| data_need_to_send_0;
AnnaBridge	145:64910690c574	973	* uint32_t data1 = command_to_send \| data_need_to_send_1;
AnnaBridge	145:64910690c574	974	* uint32_t data2 = command_to_send \| data_need_to_send_2;
AnnaBridge	145:64910690c574	975	*
AnnaBridge	145:64910690c574	976	* DSPI_MasterWriteCommandDataBlocking(base,data0);
AnnaBridge	145:64910690c574	977	* DSPI_MasterWriteCommandDataBlocking(base,data1);
AnnaBridge	145:64910690c574	978	* DSPI_MasterWriteCommandDataBlocking(base,data2);
AnnaBridge	145:64910690c574	979	*
AnnaBridge	145:64910690c574	980	* Option 2:
AnnaBridge	145:64910690c574	981	* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0);
AnnaBridge	145:64910690c574	982	* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1);
AnnaBridge	145:64910690c574	983	* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
AnnaBridge	145:64910690c574	984	*
AnnaBridge	145:64910690c574	985	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	986	* @param data The data word (command and data combined) to be sent.
AnnaBridge	145:64910690c574	987	*/
AnnaBridge	145:64910690c574	988	void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
AnnaBridge	145:64910690c574	989
AnnaBridge	145:64910690c574	990	/*!
AnnaBridge	145:64910690c574	991	* @brief Writes data into the data buffer in slave mode.
AnnaBridge	145:64910690c574	992	*
AnnaBridge	145:64910690c574	993	* In slave mode, up to 16-bit words may be written.
AnnaBridge	145:64910690c574	994	*
AnnaBridge	145:64910690c574	995	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	996	* @param data The data to send.
AnnaBridge	145:64910690c574	997	*/
AnnaBridge	145:64910690c574	998	static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
AnnaBridge	145:64910690c574	999	{
AnnaBridge	145:64910690c574	1000	base->PUSHR_SLAVE = data;
AnnaBridge	145:64910690c574	1001	}
AnnaBridge	145:64910690c574	1002
AnnaBridge	145:64910690c574	1003	/*!
AnnaBridge	145:64910690c574	1004	* @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns.
AnnaBridge	145:64910690c574	1005	*
AnnaBridge	145:64910690c574	1006	* In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data
AnnaBridge	145:64910690c574	1007	* into data register, and finally waits until the data is transmitted.
AnnaBridge	145:64910690c574	1008	*
AnnaBridge	145:64910690c574	1009	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	1010	* @param data The data to send.
AnnaBridge	145:64910690c574	1011	*/
AnnaBridge	145:64910690c574	1012	void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
AnnaBridge	145:64910690c574	1013
AnnaBridge	145:64910690c574	1014	/*!
AnnaBridge	145:64910690c574	1015	* @brief Reads data from the data buffer.
AnnaBridge	145:64910690c574	1016	*
AnnaBridge	145:64910690c574	1017	* @param base DSPI peripheral address.
AnnaBridge	145:64910690c574	1018	* @return The data from the read data buffer.
AnnaBridge	145:64910690c574	1019	*/
AnnaBridge	145:64910690c574	1020	static inline uint32_t DSPI_ReadData(SPI_Type *base)
AnnaBridge	145:64910690c574	1021	{
AnnaBridge	145:64910690c574	1022	return (base->POPR);
AnnaBridge	145:64910690c574	1023	}
AnnaBridge	145:64910690c574	1024
AnnaBridge	145:64910690c574	1025	/*!
AnnaBridge	145:64910690c574	1026	*@}
AnnaBridge	145:64910690c574	1027	*/
AnnaBridge	145:64910690c574	1028
AnnaBridge	145:64910690c574	1029	/*!
AnnaBridge	145:64910690c574	1030	* @name Transactional
AnnaBridge	145:64910690c574	1031	* @{
AnnaBridge	145:64910690c574	1032	*/
AnnaBridge	145:64910690c574	1033	/Transactional APIs/
AnnaBridge	145:64910690c574	1034
AnnaBridge	145:64910690c574	1035	/*!
AnnaBridge	145:64910690c574	1036	* @brief Initializes the DSPI master handle.
AnnaBridge	145:64910690c574	1037	*
AnnaBridge	145:64910690c574	1038	* This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
AnnaBridge	145:64910690c574	1039	* specified DSPI instance, call this API once to get the initialized handle.
AnnaBridge	145:64910690c574	1040	*
AnnaBridge	145:64910690c574	1041	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1042	* @param handle DSPI handle pointer to dspi_master_handle_t.
AnnaBridge	145:64910690c574	1043	* @param callback DSPI callback.
AnnaBridge	145:64910690c574	1044	* @param userData Callback function parameter.
AnnaBridge	145:64910690c574	1045	*/
AnnaBridge	145:64910690c574	1046	void DSPI_MasterTransferCreateHandle(SPI_Type *base,
AnnaBridge	145:64910690c574	1047	dspi_master_handle_t *handle,
AnnaBridge	145:64910690c574	1048	dspi_master_transfer_callback_t callback,
AnnaBridge	145:64910690c574	1049	void *userData);
AnnaBridge	145:64910690c574	1050
AnnaBridge	145:64910690c574	1051	/*!
AnnaBridge	145:64910690c574	1052	* @brief DSPI master transfer data using polling.
AnnaBridge	145:64910690c574	1053	*
AnnaBridge	145:64910690c574	1054	* This function transfers data using polling. This is a blocking function, which does not return until all transfers
AnnaBridge	145:64910690c574	1055	* have been completed.
AnnaBridge	145:64910690c574	1056	*
AnnaBridge	145:64910690c574	1057	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1058	* @param transfer Pointer to the dspi_transfer_t structure.
AnnaBridge	145:64910690c574	1059	* @return status of status_t.
AnnaBridge	145:64910690c574	1060	*/
AnnaBridge	145:64910690c574	1061	status_t DSPI_MasterTransferBlocking(SPI_Type base, dspi_transfer_t transfer);
AnnaBridge	145:64910690c574	1062
AnnaBridge	145:64910690c574	1063	/*!
AnnaBridge	145:64910690c574	1064	* @brief DSPI master transfer data using interrupts.
AnnaBridge	145:64910690c574	1065	*
AnnaBridge	145:64910690c574	1066	* This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
AnnaBridge	145:64910690c574	1067	* data is transferred, the callback function is called.
AnnaBridge	145:64910690c574	1068
AnnaBridge	145:64910690c574	1069	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1070	* @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1071	* @param transfer Pointer to the dspi_transfer_t structure.
AnnaBridge	145:64910690c574	1072	* @return status of status_t.
AnnaBridge	145:64910690c574	1073	*/
AnnaBridge	145:64910690c574	1074	status_t DSPI_MasterTransferNonBlocking(SPI_Type base, dspi_master_handle_t handle, dspi_transfer_t *transfer);
AnnaBridge	145:64910690c574	1075
AnnaBridge	145:64910690c574	1076	/*!
AnnaBridge	145:64910690c574	1077	* @brief Gets the master transfer count.
AnnaBridge	145:64910690c574	1078	*
AnnaBridge	145:64910690c574	1079	* This function gets the master transfer count.
AnnaBridge	145:64910690c574	1080	*
AnnaBridge	145:64910690c574	1081	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1082	* @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1083	* @param count The number of bytes transferred by using the non-blocking transaction.
AnnaBridge	145:64910690c574	1084	* @return status of status_t.
AnnaBridge	145:64910690c574	1085	*/
AnnaBridge	145:64910690c574	1086	status_t DSPI_MasterTransferGetCount(SPI_Type base, dspi_master_handle_t handle, size_t *count);
AnnaBridge	145:64910690c574	1087
AnnaBridge	145:64910690c574	1088	/*!
AnnaBridge	145:64910690c574	1089	* @brief DSPI master aborts a transfer using an interrupt.
AnnaBridge	145:64910690c574	1090	*
AnnaBridge	145:64910690c574	1091	* This function aborts a transfer using an interrupt.
AnnaBridge	145:64910690c574	1092	*
AnnaBridge	145:64910690c574	1093	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1094	* @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1095	*/
AnnaBridge	145:64910690c574	1096	void DSPI_MasterTransferAbort(SPI_Type base, dspi_master_handle_t handle);
AnnaBridge	145:64910690c574	1097
AnnaBridge	145:64910690c574	1098	/*!
AnnaBridge	145:64910690c574	1099	* @brief DSPI Master IRQ handler function.
AnnaBridge	145:64910690c574	1100	*
AnnaBridge	145:64910690c574	1101	* This function processes the DSPI transmit and receive IRQ.
AnnaBridge	145:64910690c574	1102
AnnaBridge	145:64910690c574	1103	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1104	* @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1105	*/
AnnaBridge	145:64910690c574	1106	void DSPI_MasterTransferHandleIRQ(SPI_Type base, dspi_master_handle_t handle);
AnnaBridge	145:64910690c574	1107
AnnaBridge	145:64910690c574	1108	/*!
AnnaBridge	145:64910690c574	1109	* @brief Initializes the DSPI slave handle.
AnnaBridge	145:64910690c574	1110	*
AnnaBridge	145:64910690c574	1111	* This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
AnnaBridge	145:64910690c574	1112	* specified DSPI instance, call this API once to get the initialized handle.
AnnaBridge	145:64910690c574	1113	*
AnnaBridge	145:64910690c574	1114	* @param handle DSPI handle pointer to the dspi_slave_handle_t.
AnnaBridge	145:64910690c574	1115	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1116	* @param callback DSPI callback.
AnnaBridge	145:64910690c574	1117	* @param userData Callback function parameter.
AnnaBridge	145:64910690c574	1118	*/
AnnaBridge	145:64910690c574	1119	void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
AnnaBridge	145:64910690c574	1120	dspi_slave_handle_t *handle,
AnnaBridge	145:64910690c574	1121	dspi_slave_transfer_callback_t callback,
AnnaBridge	145:64910690c574	1122	void *userData);
AnnaBridge	145:64910690c574	1123
AnnaBridge	145:64910690c574	1124	/*!
AnnaBridge	145:64910690c574	1125	* @brief DSPI slave transfers data using an interrupt.
AnnaBridge	145:64910690c574	1126	*
AnnaBridge	145:64910690c574	1127	* This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
AnnaBridge	145:64910690c574	1128	* data is transferred, the callback function is called.
AnnaBridge	145:64910690c574	1129	*
AnnaBridge	145:64910690c574	1130	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1131	* @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1132	* @param transfer Pointer to the dspi_transfer_t structure.
AnnaBridge	145:64910690c574	1133	* @return status of status_t.
AnnaBridge	145:64910690c574	1134	*/
AnnaBridge	145:64910690c574	1135	status_t DSPI_SlaveTransferNonBlocking(SPI_Type base, dspi_slave_handle_t handle, dspi_transfer_t *transfer);
AnnaBridge	145:64910690c574	1136
AnnaBridge	145:64910690c574	1137	/*!
AnnaBridge	145:64910690c574	1138	* @brief Gets the slave transfer count.
AnnaBridge	145:64910690c574	1139	*
AnnaBridge	145:64910690c574	1140	* This function gets the slave transfer count.
AnnaBridge	145:64910690c574	1141	*
AnnaBridge	145:64910690c574	1142	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1143	* @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1144	* @param count The number of bytes transferred by using the non-blocking transaction.
AnnaBridge	145:64910690c574	1145	* @return status of status_t.
AnnaBridge	145:64910690c574	1146	*/
AnnaBridge	145:64910690c574	1147	status_t DSPI_SlaveTransferGetCount(SPI_Type base, dspi_slave_handle_t handle, size_t *count);
AnnaBridge	145:64910690c574	1148
AnnaBridge	145:64910690c574	1149	/*!
AnnaBridge	145:64910690c574	1150	* @brief DSPI slave aborts a transfer using an interrupt.
AnnaBridge	145:64910690c574	1151	*
AnnaBridge	145:64910690c574	1152	* This function aborts a transfer using an interrupt.
AnnaBridge	145:64910690c574	1153	*
AnnaBridge	145:64910690c574	1154	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1155	* @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1156	*/
AnnaBridge	145:64910690c574	1157	void DSPI_SlaveTransferAbort(SPI_Type base, dspi_slave_handle_t handle);
AnnaBridge	145:64910690c574	1158
AnnaBridge	145:64910690c574	1159	/*!
AnnaBridge	145:64910690c574	1160	* @brief DSPI Master IRQ handler function.
AnnaBridge	145:64910690c574	1161	*
AnnaBridge	145:64910690c574	1162	* This function processes the DSPI transmit and receive IRQ.
AnnaBridge	145:64910690c574	1163	*
AnnaBridge	145:64910690c574	1164	* @param base DSPI peripheral base address.
AnnaBridge	145:64910690c574	1165	* @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge	145:64910690c574	1166	*/
AnnaBridge	145:64910690c574	1167	void DSPI_SlaveTransferHandleIRQ(SPI_Type base, dspi_slave_handle_t handle);
AnnaBridge	145:64910690c574	1168
AnnaBridge	145:64910690c574	1169	/*!
AnnaBridge	145:64910690c574	1170	*@}
AnnaBridge	145:64910690c574	1171	*/
AnnaBridge	145:64910690c574	1172
AnnaBridge	145:64910690c574	1173	#if defined(__cplusplus)
AnnaBridge	145:64910690c574	1174	}
AnnaBridge	145:64910690c574	1175	#endif /_cplusplus/
AnnaBridge	145:64910690c574	1176	/*!
AnnaBridge	145:64910690c574	1177	*@}
AnnaBridge	145:64910690c574	1178	*/
AnnaBridge	145:64910690c574	1179
AnnaBridge	145:64910690c574	1180	#endif /_FSL_DSPI_H_/